# Patent

## Title
Logic circuits using carbon nanotube transistors

## Abstract

In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.

## Background
RELATED APPLICATIONS
This application is a continuation of and claims priority to and incorporates by reference, the corresponding U.S. patent application Ser. No. 11/613,134 filed Dec. 19, 2005, and entitled, “LOGIC CIRCUITS USING CARBON NANOTUBE TRANSISTORS”, and issued as U.S. Pat. No. 8,004,043 on Aug. 23, 2011.


BACKGROUND
The present invention relates generally to carbon nanotube field effect transistors (CNTFETs) and their associated integrated circuits.



BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
FIG. 1 is a cross-sectional diagram of a CNTFET in accordance with some embodiments.
FIG. 2A is an energy band diagram showing hole conduction for a mid-gap Schottky Barrier CNTFET in accordance with some embodiments.
FIG. 2B is an energy band diagram showing electron conduction for a mid-gap Schotky Barrier CNTFET in accordance with some embodiments.
FIG. 2C is a diagram showing the conduction characteristics of a Schottky Barrier CNTFET in accordance with some embodiments.
FIG. 3 is a diagram showing conduction characteristics of a mid-gap Schottky Barrier CNTFET with its flat band VGS shifted in accordance with some embodiments.
FIG. 4 is a schematic diagram of an inverter using Schottky Barrier CNTFETs in accordance with some embodiments.
FIG. 5 is a schematic diagram of a NAND gate using Schottky Barrier CNTFETs in accordance with some embodiments.
FIG. 6 is a schematic diagram of a NOR gate using Schottky Barrier CNTFETs in accordance with some embodiments.
FIG. 7 is a diagram showing conduction characteristics of a Schottky Barrier CNTFET configured to conduct holes more strongly than electrons in accordance with some embodiments.
FIG. 8 is an energy band diagram for a band-edged Schottky Barrier CNTFET with source and drain terminals favoring hole conduction in accordance with some embodiments.
FIG. 9 is a block diagram of a computer system having a microprocessor with one or more logic circuits using CNTFET devices in accordance with some embodiments.



DETAILED DESCRIPTION
A CNTFET (carbon nanotube field effect transistor) is akin to a silicon MOSFET (metal oxide semiconductor field effect transistor) but with one or more carbon nanotubes in place of the silicon channel. CNTs may be well-suited for complementary logic traditionally implemented using CMOS circuits, among other things, because of their relatively high conduction mobility, for both holes and electrons.
FIG. 1 shows a cross-sectional view of a carbon nanotube field effect transistor (CNTFET) in accordance with some embodiments. The depicted CNTFET has a carbon nanotube (CNT) 101, functioning as a channel, with a gate insulator 103 sandwiched between the CNT and a gate electrode 102. It also has a drain 104 and source 106 (which are interchangeable, typically with no distinction between which can be a source and witch can be a drain) mounted at opposite ends. It is mounted atop a substrate 105, which typically has an oxide insulator on top of it. It should be appreciated that these components may be implemented with any suitable materials in a variety of different configurations. However, in the following sections, some specific examples will be given for illustrative purposes.
As compared with MOSFET silicon channels, nanotubes have minimal (if any) dangling surface bonds. Accordingly, silicon dioxide (SiO2) as a gate insulator, while suitable, is not required. Other crystalline or amorphous insulators (e.g., HfO2, ZrO2, or other materials including non-oxide insulators) with higher dielectric constants could be used instead. This can allow for higher performance in CNTFETs without having to use ultra-thin SiO2 gate insulating films.
In some embodiments, a top gated structure with a Hafnium Oxide (HfO2) gate insulator having a thickness of 2 nm may be used. A self-aligned geometry may also be implemented to reduce parasitic and/or fringe capacitance. On the other hand, sufficient gate capacitance is typically needed. Gate capacitance increases with increased gate electrode width. In some embodiments, it may be desired to have a gate electrode with a width of about 3 times the thickness of the gate insulator for sufficient gate capacitance.
The electrodes for the drain 104 and source 106 may be implemented with any suitable material. However, as discussed further below, selecting materials with a desired work function to position their Fermi energy levels appropriately for relative hole/electron conduction strengths (e.g., for complementary devices and circuits like CMOS and for a multi-stack configuration) may be sought for example, in some embodiments, it may be desirable to use a metal such as Palladium (Pd) for source/drain with Fermi band levels generally leaning toward typical CNT valence bands for better hole conduction. (This is addressed again below.) With regard to dimensions, drain and source terminal widths should be chosen for making the transistor footprint very small while minimizing the parasitic resistance and capacitance relative to their lengths for desired performance. In an exemplary CNTFET, the drain and source electrodes have dimensions of 15 nm by 15 nm for a transistor channel (CNT) length of 50 nm.
With reference to FIGS. 2A-2C, electrical characteristics for an exemplary CNT channel are shown. Because the CNT channels are implemented with mid-gap SB carbon nanotubes, they are ambipolar, i.e., depending on how they are biased, they can conduct both holes and electrons. FIGS. 2A and 2B show conduction (EC) and valence (EV) band levels, relative to the drain and source Fermi levels (EF) for hole conduction and electron conduction, respectively. As the gate is biased toward “negative” voltages (less than half of supply voltage and applied drain bias to the transistor), the energy bands are bent and shifted (relative to the drain/source Fermi levels) enabling holes to conduct through by tunneling through the Schottky barrier to the CNT channel, as is represented in FIG. 2A and further being collected by the terminal (i.e. injected by tunneling to the channel from source and being collected by the drain that holds a negative bias as shown in FIG. 2A). Alternatively, as the gate voltage goes toward positive voltages (more than half of supply voltage and applied drain bias to the transistor), the energy bands are bent and shifted (relative to the drain/source Fermi levels) enabling electrons to conduct through by tunneling to the CNT channel, as is represented in FIG. 2B.
FIG. 2C shows ID/VGS curves for exemplary nanotubes having diameters of 0.6, 1.0, and 1.5 nm. As is shown in the curves, a channel conducts minimal current when its gate-source voltage is at a “flatband” level (around VDD/2 for the curves in this example). If VGS is above this level, electrons conduct, with the electron current increasing as VGS increases. On the other hand, if VGS is below this minimal-current level, then holes conduct instead of electrons, with the hole current increasing as VGS decreases. A minimal current point is achieved when hole and electron currents balance each other out.
As indicated by these curves, channel current is affected by the diameter of the fabricated nanotube. As the diameter increases, the difference between minimum and maximum channel current (ID) for a given drain/source voltage decreases. In most digital applications, a sufficient difference between on and off currents is desired, so a small CNT diameter may be sought. On the other hand, if the diameter is too small, the “ON” or charging current of the transistor reduces, which is not desirable. For example, one might have low “OFF” current and a good ON-to-OFF current ratio, but may not have a high enough “ON” current for desired digital applications. Accordingly, a suitable compromise between these competing factors may be sought. In some embodiments, a CNT with a diameter of between 0.5 and 2.0 nm may be suitable for implementation in digital circuits. In an example discussed below, a diameter of about 1 nm is used.
FIG. 3 shows an ID/VGS curve for an ambipolar SB CNT whose flatband voltage has been shifted resulting in a shift of its ID/VGS curve along the VGS axis so that its minimum current conduction occurs at VGS=0 V. In some embodiments, this may be achieved by applying a negative bias to the low supply side of the CNT transistor. With a flat band VGS of 0, the CNT can be better used as a digital device with a Low input voltage of 0 V and a High at VDD (or thereabouts for maximum voltage swing in circuit operation). In other embodiments, one could change the choice of gate electrode material, for example, using Pd (Palladium) or Al (Aluminum) to engineer a desired work function and provide a suitable shift in the transistor ID/VGS curve, as shown in FIG. 3.
FIG. 4 shows an exemplary logic gate (inverter) comprising first and second CNTFETs (CFET1, CFET2). They are coupled in series between a high supply voltage (VDD) and a low supply reference (VSS). (Note that they have a diamond at their gates to indicate that they are not necessarily physically configured, e.g., doped, to function as N-type or P-type devices, so the transistors themselves can function as N or P type devices depending on how they are biased.) The first CNTFET (CFET1), which is biased to conduct holes, functions as a driver transistor with its gate providing an inverter input (Vin). The second transistor (CFET2), which is biased to conduct electrons, functions to facilitate an active load with its gate coupled to a supply (VGG) for appropriately biasing it so that the output (Vout) provides suitable High and Low output values when Vin is Low and High, respectively. Note that one can adjust VGG and VSS to achieve desired output swing. For example, it is commonly desirable for VGG to approach (if not equal) VDD and for VSS to be at ground, but these voltages would depend on the behavior of a given CNTFET.
In accordance with some embodiments, the gate/source flatband levels for the CNTFETs (CFET1, CFET2) are shifted to the left by using a negative, low side supply (VSS) relative to a logical Low level of about 0 V and a logical High value of VDD (e.g., about 1.0 V). Moreover, the ID/VGS characteristics of the transistors are made to be similar to that shown in FIG. 7. This figure shows a desired P type transistor behavior. In this case, hole current is enhanced over electron current in an ambipolar CNTFET.
This can be achieved in several ways. It may be achieved by changing the work function of the source/drain material and hence the Schottky barrier, as illustrated in FIG. 8. For example, Pd (Palladium) could be used to favor hole conduction. Another way is to implement differently sized transistors (using different numbers of carbon nanotubes in each transistor's channel). For example, with the circuit of FIG. 4, CFET 1 could have a higher number of tubes than CFET 2 and hence be stronger than CFET2. It should be appreciated, however, that when packing multiple nanotubes in a single channel, a trade-off exists between the number of nanotubes per unit width and the capacitance (and current) per nanotube.
FIG. 5 shows an exemplary NAND gate comprising CNTFETs as discussed herein in accordance with some embodiments. It comprises driver CNTFETs (CFET1, CFET2) coupled together in parallel between a high supply reference (VDD) and an active load transistor CFET3, which is coupled to a low supply reference VSS, as shown. The gates of the drive transistors (CFET1, CFET2) provide first and second NAND gate inputs (Vin—A, Vin—B) respectively, and a gate output is provided at the drain of CFET3 as shown. If either input is Low (e.g., 0 V), then the output is High (approaching VDD. Conversely, if both inputs are High (approaching VDD), then the output will be Low.
FIG. 6 shows an exemplary NOR gate comprising CNTFETs as discussed herein in accordance with some embodiments. It comprises driver CNTFETs (CFET1, CFET2) coupled together in series between a high supply reference (VDD) and an active load transistor CFET3, which is coupled to a low supply reference VSS, as shown. The gates of the drive transistors (CFET1, CFET2) provide first and second NOR gate inputs (Vin—A, Vin—B) respectively, and a gate output is provided at the drain of CFET3 as shown. If both inputs are Low (e.g., 0 V), then the output is High (approaching VDD. Conversely, if either or both inputs are High (approaching VDD), then the output will be Low.
Other types of digital devices such as gates, memory devices, clocked logic, and the like could be implemented using CNTFETs as described herein. For example, persons of skill will appreciate that inverters, NOR and NAND gates can be building blocks for many types of more complex circuits. Along these lines, some integrated circuits could comprise both MOSFETs and CNTFETs, in separate circuit blocks or combined in hybrid circuits. For example, currently, in many CMOS applications, P type devices can limit the performance of circuits because they conduct more slowly (slower mobility) than their NMOS counterparts. Accordingly, circuits could use, for example, CNTFETs configure to conduct holes to function as P type devices, and NMOS devices (in Silicon or in other compound semiconductors such as III-V or II-VI materials) could be used for the N-type transistors.
With reference to FIG. 9, one example of a computer system is shown. The depicted system generally comprises a processor 902 that is coupled to a power supply 904, a wireless interface 906, and memory 908. It is coupled to the power supply 904 to receive from it power when in operation. The wireless interface 906 is coupled to an antenna 910 to communicatively link the processor through the wireless interface chip 906 to a wireless network (not shown). Microprocessor 902 comprises one or more logic circuits 903 using CNTFET inverters, as disclosed herein.
It should be noted that the depicted system could be implemented in different forms. That is, it could be implemented in a single chip module, a circuit board, or a chassis having multiple circuit boards. Similarly, it could constitute one or more complete computers or alternatively, it could constitute a component useful within a computing system.
The invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. For example, it should be appreciated that the present invention is applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chip set components, programmable logic arrays (PLA), memory chips, network chips, and the like.
Moreover, it should be appreciated that example sizes/models/values/ranges may have been given, although the present invention is not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the FIGS. for simplicity of illustration and discussion, and so as not to obscure the invention. Further, arrangements may be shown in block diagram form in order to avoid obscuring the invention, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present invention is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that the invention can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

## Claims

1. A NAND logic gate comprising:
a first CNTFET to receive a first logic input, the first CNTFET coupled between a high power supply reference and an output node;
a second CNTFET to receive a second logic input, the second CNTFET coupled in parallel to the first CNTFET; and
a third CNTFET having a gate coupled to a bias supply so that the third CNTFET provides an active load for the first and second CNTFETs.

2. The NAND logic gate of claim 1, wherein the bias supply is different from the first and second logic inputs.

3. The NAND logic gate of claim 1, wherein the third CNTFET is coupled in series with the first and second CNTFETs and a low supply reference.

4. The NAND logic gate of claim 1, wherein the first, second, and third CNTFETs have channels formed from intrinsic carbon nanotubes.

5. The NAND logic gate of claim 1, wherein the high supply reference is greater than the low supply reference.

6. The NAND logic gate of claim 1, wherein the first, second, and third CNTFETs have channels comprising one or more carbon nanotubes, wherein the first and second CNTFETs channels having more carbon nanotubes than the third CNTFET channel so that the first and second CNTFETs conduct more strongly than the third CNTFET.

7. The NAND logic gate of claim 1, wherein when either the first or second logic inputs approach low power supply reference, then the first and second CNTFETs cause voltage on the output node to approach the high power supply reference.

8. The NAND logic gate of claim 1, wherein when both the first and second logic inputs approach the high power supply reference, then the third CNTFET causes voltage on the output node to approach low power supply reference.

9. The NAND logic gate of claim 1, wherein the first, second, and third CNTFETs comprise drain and source electrodes formed from a material with Fermi energy level that is closer to a valence band than to a conduction band.

10. A system comprising:
a processor having an inverter and a NAND logic gate formed from CNTFET devices;
a memory unit coupled to the processor; and
an antenna coupled to the processor to communicatively link it with a wireless network.

11. The system of claim 10, wherein the NAND logic gate comprises: a first CNTFET to receive a first logic input, the first CNTFET coupled between a high power supply reference and an output node; a second CNTFET to receive a second logic input, the second CNTFET coupled in parallel to the first CNTFET; and a third CNTFET having a gate coupled to a bias supply so that the third CNTFET provides an active load for the first and second CNTFETs.

12. The system of claim 11, wherein the third CNTFET is coupled in series with the first and second CNTFETs and a low supply reference.

13. The system of claim 11, wherein the first, second, and third CNTFETs have channels formed from intrinsic carbon nanotubes.

14. The system of claim 10, wherein the inverter comprises: a first CNTFET coupled between a high power supply reference and an output node for the inverter circuit; and
a second CNTFET coupled between the output node and a low power supply reference, the first CNTFET to provide an input to receive high and low logical values for the inverter, the second CNTFET biased to provide an active load for the
first CNTFET, wherein the high power supply reference is higher than the low power supply reference.

15. A system comprising: a processor having an inverter including: a first CNTFET coupled between a high power supply reference and an output node for the inverter circuit; and a second CNTFET coupled between the output node and a low power supply reference, the first CNTFET to provide an input to receive high and low logical values for the inverter, the second CNTFET biased to provide an active load for the first CNTFET, wherein the high power supply reference is higher than the low power supply reference;
a memory unit coupled to the processor; and an antenna coupled to the processor to communicatively link it with a wireless network.

16. The system of claim 15, wherein the first and second CNTFET have channels comprising one or more carbon nanotubes, the first CNTFET channel having more carbon nanotubes than the second CNTFET channel so that the first CNTFET conducts more strongly than the second CNTFET.

17. A system comprising: a processor having a NAND logic gate including:
a first CNTFET to receive a first logic input, the first CNTFET coupled between a high power supply reference and an output node;
a second CNTFET to receive a second logic input, the second CNTFET coupled in parallel to the first CNTFET; and
a third CNTFET having a gate coupled to a bias supply so that the third CNTFET provides an active load for the first and second CNTFETs;
a memory unit coupled to the processor; and
an antenna coupled to the processor to communicatively link it with a wireless network.

18. The system of claim 17, wherein the third CNTFET is coupled in series with the first and second CNTFETs and a low supply reference.

19. The system of claim 7, wherein the first, second, and third CNTFETs have channels formed from intrinsic carbon nanotubes.

20. The system of claim 17, wherein the first, second, and third CNTFETs have channels comprising one or more carbon nanotubes, wherein the first and second CNTFETs channels having more carbon nanotubes than the third CNTFET channel so that the first and second CNTFETs conduct more strongly than the third CNTFET.