# Patent

## Title
Receiver of multiplexed binary offset carrier (MBOC) modulated signals

## Abstract

A receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which arc different to the code rate, the receiver comprising processing means arranged to: generate a first estimate of delay based on the code modulation only; generate a second estimate of delay based on the first component of the sub-carrier modulation only; and generate a third estimate of delay based on the second component of the sub-carrier modulation only; and determine a further delay estimate from the first second and third delay estimates.

## Background
FIELD OF THE INVENTION
The present invention relates to the reception of Multiplexed Binary Offset Carrier (MBOC) modulated signals and similar such signals. One particular application of the invention is the reception of MBOC modulated navigation signals in a Global Navigation Satellite System (GNSS).
BACKGROUND TO THE INVENTION
In a GNSS, a receiver estimates delays τ in the navigation signals received from different satellites and uses this information, combined with information on the position of the satellites, to estimate its position. The more accurate the estimation of the delays τ, the more accurately the receiver can estimate its position.
The United States led Global Positioning System (GPS) is presently the GNSS in most common use. Navigation signals transmitted by GPS satellites are modulated using a Phase Shift Keying (PSK) modulation of a code onto a carrier signal having a designated carrier frequency. The modulation involves altering the phase of the carrier signal by fixed amounts (0 or π) at a code rate fC, each symbol of the code having duration TC=1/fC and the code being repeated with time period TG. A navigation signal received at a receiver from a satellite can therefore be represented by an equivalent bi-modal amplitude modulation function α(t−τ)ε(−1,+1) with period TG, as shown in FIG. 1.
The receiver estimates the delay τ by comparing the received signal to a locally generated reference signal. The reference signal consists of an in-phase and quadrature-phase (I and Q) carrier modulated with the same code as the input signal. The reference modulation can be represented mathematically as a(t−{circumflex over (τ)}) where {circumflex over (τ)} is a trial delay. The comparison typically consists in multiplying the received signal by the I and Q reference to yield a demodulated signal. The demodulated signal is then integrated over a given time, usually the same as the period TG of the code, to output a value known as a correlation. The correlation depends on the difference between the trial delay {circumflex over (τ)} of the reference signal and the true delay τ of the received signal and can be expressed as a correlation function Λ({circumflex over (τ)}−τ). As shown in FIG. 2, this correlation function for a PSK modulated signal is triangular and peaks when the trial delay {circumflex over (τ)} matches the true delay τ The width of the correlation function is twice the symbol duration TC, i.e. 2TC.
Calculating the entire correlation function Λ({circumflex over (τ)}−τ) over all {circumflex over (τ)} and analysing it to determine its peak and hence identify the delay τ of the received signal is a computationally time-consuming task. Most conventional GPS receivers therefore compute just three sampled correlations simultaneously, using three reference signals offset in time from one another. The three correlations are usually referred to as gate values of Early (E), Prompt (P) and Late (L) gates. The E and L gates are offset from one another by a time separation TDC, so that they can be considered to have trial delays




  
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respectively. The P gate can then be considered to have trial delay {circumflex over (τ)} half way between these trial delays of the E and L gates. So, as illustrated in FIG. 2, when the E and L gate values are equal, the P gate value yields the peak value of the correlation function Λ({circumflex over (τ)}−τ) and the trial delay {circumflex over (τ)} is equal to the true delay τ.

An iterative algorithm can be used to arrive at this state. When the trial delay {circumflex over (τ)} is not equal to the true delay, the P gate will be offset from the peak of the correlation function Λ( ) and there will be a difference in the values of the E and L gates. So, an error signal proportional to the difference between the trial delay {circumflex over (τ)} and the true delay τ can be generated by subtracting the E gate value from the L gate value. This can be used to iteratively adjust the trial delay {circumflex over (τ)} toward the true delay τ. A best estimate of the true delay is then deemed to be the value of the trial delay (of the P gate) when the E gate value is equal to the L gate value (as shown in FIG. 2).
It is presently intended to improve the American GPS by adding new navigation signals to the system. The independent European Galileo system will use similar new navigation signals in both the same and new frequency bands. While some of the new navigation signals will continue to use PSK modulation, most of them will be modulated using the new Binary Offset Carrier (BOC) modulation which is described first. An important sub-set of BOC is called Multiplexed binary offset carrier and is described next.
BOC Modulation.
BOC modulation is like PSK in that it involves modulating a code onto a carrier. The code is similar to that used in PSK modulation, and the code in the received signal can again be represented by an equivalent bi-modal amplitude modulation function a(t−τ) having code rate fC, symbol duration TC and periodicity TG. However, BOC involves further modulating the signal by a sub-carrier, which can be represented by a sub-carrier modulation function s(t−τ) having sub-carrier rate fs and sub-symbol duration equivalent to a half-cycle TS=1/(2fS). As seen in FIG. 3, the sub-carrier modulation function s(t−τ) is a simple periodic square waveform. The sub-carrier rate fs is an integer multiple, or an integer-and-a-half multiple of the code rate fC. The standard notation for BOC modulation reads BOC(fs, fC). This figure shows what can be called ‘sine-BOC’ where the sub carrier has 0 deg phase shift relative to the code zero crossings. Also there is ‘cosine-BOC’ where the sub-carrier is phase shifted 90 deg relative to the code zero-crossings (not shown).
When a received BOC signal is correlated using a matching locally generated BOC reference signal the resulting correlation function ({circumflex over (τ)}−τ) has multiple peaks. For example, referring to FIG. 4a, this correlation function of a sine-BOC signal modulated using BOC(2f, f) has three positive peaks and four negative peaks. The central positive peak corresponds to a match of the true delay τ of the received signal with the trial delay of the reference signal. The other, secondary peaks are separated at intervals of the sub-symbol duration Ts. Importantly, the envelope (dashed line) of this correlation function ({circumflex over (τ)}−τ) is the same as the correlation function Λ({circumflex over (τ)}−τ) of a PSK modulated signal having the same code rate fC.
Because the central peak of the BOC correlation function ({circumflex over (τ)}−τ) has steeper sides than the peak of the equivalent PSK correlation function Λ({circumflex over (τ)}−τ), BOC modulation has the potential to allow more accurate delay estimation. Specifically, when the E and L gates are located on either side of the central peak then the error signal generated from the difference between the L gate value and the E gate value can steer the P gate to the top of the central peak and hence the trial delay {circumflex over (τ)} to the true delay τ, as illustrated in the top part of FIG. 4a. There is however an inherent ambiguity in the delay estimate for a BOC signal provided by the conventional delay estimation technique, as described above. When the E and L gates reside on either side of one of the secondary peaks, the error signal will steer the P gate to the secondary peak (which can be negative). In that situation, the error signal will be zero, just as it is when the P gate is at the top of the central peak, and the iteration will have converged to a value of the trial delay {circumflex over (τ)} that does not correspond to the true delay τ. This is known as ‘false lock’ or ‘slip’, or ‘false node tracking’.
A number of techniques have been proposed for overcoming this problem with pure BOC. One such technique, commonly referred to as ‘bump jumping’, is described in the paper “Tracking Algorithm for GPS Offset Carrier Signals”, P. Fine et al, Proceedings of ION 1999 National Technical Meeting, January 1999. This technique takes advantage of the knowledge that adjacent peaks of the BOC correlation function ({circumflex over (τ)}−τ) are separated from one another by the known sub-carrier symbol duration Ts. Specifically, the technique tests for correct location of the P gate using a pair of gates, called Very Early (VE) and Very Late (VL) gates, having trial delays {circumflex over (τ)}−TS and {circumflex over (τ)}+TS respectively. These are offset from the trial delay {circumflex over (τ)} of the P gate by the sub-carrier symbol duration TS. So, if the P gate has converged to the top of one of the peaks, e.g. the receiver is in lock, the VE, P and VL gates are located on three adjacent peaks. At this stage, the VE, P and VL gate values are compared. If the VE and VL gate amplitudes are less than the P gate amplitude, the P gate is known to lie on the central peak and the trial delay {circumflex over (τ)} corresponds to the true delay. However, if the VE or VL gate amplitude is higher than the P gate value, the P gate is on a secondary peak. In this event, the trial delay {circumflex over (τ)} is incremented by the sub-symbol duration Ts in the direction of whichever of the VE and VL gates has the higher (modulus) value. This action should cause the P gate to jump to the next peak toward the central peak. The comparison is then repeated to verify that the P gate is on the central peak or to cause repeated incrementing of the trial delay {circumflex over (τ)} until the P gate is located on the central peak.
Bump jumping allows a receiver to fully exploit the potential accuracy of BOC. However, there can be a significant waiting time before the delay estimate can be relied on. There is an elapsed time required to decide whether there is a false lock or not. This is longer for a low C/N0, when the VE, P and VL gate values must also be averaged over a significant time in order to be sure which of the three tested adjacent peaks has the highest amplitude. The required time to detect false lock also increases proportionally with the ratio of the sub-carrier rate to the code rate fS/fC, because the difference of amplitude between adjacent peaks relatively decreases. It may also be necessary to correct false lock several times over successive secondary peaks before the central peak is found, a problem which is exacerbated as the ratio of the sub-carrier rate to the code rate fS/fC increases, because the number of secondary peaks increases. Overall, the waiting time may range upwards to several seconds, which is certainly enough to have potentially disastrous consequences for a plane landing, ship docking or such like. Worse, the receiver does not know that it has been in a false lock state until it actually jumps out of it. The bump jumping system therefore is not fail safe.
A further difficulty has now been realised since the launch of the first test satellite GIOVE-A transmitting BOC signals in December 2005. Non-linear and linear distortion in the transmitting chain can easily cause appreciable asymmetry in the actual correlation function ({circumflex over (τ)}−τ)—where the corresponding secondary peaks on either side of the main peak are no longer equal in amplitude. This inevitably degrades performance, and in a worst case, the bump-jumping receiver simply does not work. Recent practical tests are described in “GIOVE-A in orbit testing results” M. Falcone, M. Lugert, M. Malik, M. Crisic, C. Jackson, E. Rooney, M. Trethey ION GNSS FortWorth Tex., September 2006.
FIG. 4b is a simulation of the effect of extreme phase distortion (90 deg). It shows that the later (negative) secondary peak has the same amplitude as the (positive) primary peak. In such a case the VEVL receiver must fail. For less extreme phase distortion—the unbalancing must degrade signal to noise performance, simply because it brings the amplitude of one of the secondary peaks closer to the amplitude of the primary peak.
The paper “Unambiguous Tracker for GPS Binary-Offset-Carrier Signals”, Fante R., ION 59th Annual Meeting/CIGTF 22nd Guidance Test Symposium, 23-25 Jun. 2003, Albuquerque, N. Mex., describes another technique involving multiple sampling (gating) of the correlation function and then linear combination of these samples to synthesise a monotonic approximation to the PSK correlation function Λ({circumflex over (τ)}−τ) having no multiple peaks. This solution certainly eliminates false locks. However, this technique relies on a very complex receiver design. More fundamentally, it fails to realise the potential accuracy conferred by BOC modulation, because the shallower PSK correlation peak is relied on to resolve the delay estimate. Similarly, the paper “BOC(x, y) signal acquisition techniques and performances”, Martin et al., Proceedings of ION GPS 2003, September 2003, Portland, Oreg., describes a technique that exploits the fact that the BOC modulated signal has a mathematical equivalence to two PSK modulated signals centred on two separate carrier frequencies; where the higher frequency fH is equal to the carrier frequency plus the sub-carrier frequency fS while the lower frequency fL is equal to the carrier frequency minus the sub-carrier frequency fS. With appropriate processing the actual monotonic PSK correlation function) Λ({circumflex over (τ)}−τ) can be recovered. But this method is again complex to implement and more fundamentally fails to realise the potential accuracy conferred by BOC modulation.
The solution—described in detail in patent application GB0624516.1—is to eliminate the problem by eliminating the correlation ( ). Instead, a two dimensional correlation is tracked independently to realise a dual estimate. An unambiguous lower accuracy estimate derived from the code phase is used to make an integer correction to a higher accuracy but ambiguous independent estimate based on the sub-carrier phase. The actual receiver may adopt a triple loop, instead of the usual double loop, where carrier phase, sub-carrier phase and code phase are tracked independently but interactively.

MBOC Modulation.

Multiplexed binary offset carrier (MBOC) has been proposed in an important modification of BOC. See “MBOC—the new optimized spreading modulation recommended for L1 O and GP L1C” published May/June 2006 Inside GNSS. The proposal is authored and agreed by international experts G. W. Hein, J-Avial Rodriguez, S Wallner, J. W. Betz, C. J. Hegarty, J. J. Rushanan A. L. Kraay, A. R. Pratt, S. Lenahan, J. Owen, J-L Issler and T. Stansell. When adopted it will add a further layer of complexity to reception of GNSS signals compared to ordinary BOC modulation, which is in turn more complicated than PSK modulation. It offers improved accuracy and better rejection of multi-path.
The basis is to make the sub-carrier modulation a linear superposition of BOC(1,1) and BOC(6,1). A common agreed code is described as MBOC(6,1,1/11). The notation implies that 1/11 of the total power is the BOC(6,1) component—and 10/11 of the power is the BOC(1,1) component. The linear superposition can be done by time domain multiplexing where 1/11 of the BOC(1,1) symbols are replaced by BOC(6,1) symbols (same chip width TC=1 μs) having same amplitude (TMBOC). The currently favoured alternative is in the frequency domain multiplexing where there is continuous modulation with unequal amplitudes of the two components (CBOC). Whichever form is adopted makes no difference to the invention. Current proposals divide power into data channel and pilot channel. One current proposal assumes a 50-50 division of power and with no BOC(6,1) component in the data channel, putting it all in the pilot channel. On that basis then the relative proportions of the two components in the pilot channel is 9/11 of BOC(1,1) and 2/11 of BOC(6,1) for which an example is shown in FIG. 5. Whatever proportions are finally decided makes no difference to the invention.
The difference from BOC is clearly seen in the form of a doubly periodic modulation with half periods described by two different sub-chip widths TS1 and TS2. When recovered in the conventional single estimate receiver an even more complicated correlation function as in FIG. 6a is the result. We shall adopt the notation ( ) for the correlation function. Not only are there two secondary (negative) peaks but there are also multiple tertiary peaks. In comparison with the ordinary correlation function for BOC(1,1)—shown as dotted—the slope magnitudes either side of the main peak are higher—which quantifies as an improved accuracy if tracking is correct. But clearly the new modulation offers many more opportunities for false tracking on the ‘ripples’ in the correlation function—for example as in FIG. 6b, when the gate width is narrow, as it has to be for potentially accurate tracking. These figures are for ideal shapes with no phase distortion. As might be expected the new MBOC is more sensitive to phase distortion than BOC. The synthesised effect of phase distortion is shown in FIG. 6c (with 50 deg distortion on BOC(6,1,1/11) where it is clear that the correlation function cannot be tracked because there is a secondary peak equal in amplitude to the primary peak. The complexities of equalization will be needed therefore in order to realize an adequately symmetrical function. At the present time MBOC is so new that no proposals have been published on how to design a receiver to overcome the problems that this complex modulation will entail.
The present invention overcomes the problem of tracking MBOC. The solution is to eliminate the problem by eliminating the correlation function ( ). Instead, a three dimensional correlation is tracked independently to realise a triple estimate. An unambiguous lower accuracy estimate derived from the code phase is used to make an integer correction to a higher accuracy but ambiguous independent estimate based on the lower frequency sub-carrier phase which in turn is used to make an integer correction to even higher accuracy but ambiguous independent estimate based on the higher frequency sub-carrier phase. The actual receiver may adopt a quadruple loop, instead of the usual double loop, where carrier phase, sub-carrier2 phase, sub-carrier1 phase and code phase are tracked independently but interactively.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite modulation function which is the sum of two different sub-carriers with unequal rates and which rates are different to the code rate the receiver comprising processing means arranged to:
generate a first estimate of delay based on the code modulation only;
generate a second estimate of delay based on the lower frequency component of the sub-carrier modulation only
generate a third estimate of delay based on the higher frequency component of the sub-carrier modulation only, and
determine a single delay estimate from the first, second and third delay estimates.
The present invention further provides a receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which are different to the code rate, the receiver comprising processing means arranged to:

    
    
        generate a first estimate of delay based on the code modulation;
        generate a second estimate of delay based on the first component of the sub-carrier modulation; and
        generate a third estimate of delay based on the second component of the sub-carrier modulation; and
        determine a further delay estimate from the first second and third delay estimates.

The present invention still further provides a receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which are different to the code rate, the receiver comprising processing means arranged to:

        generate independently first, second and third estimates of delay based on the code modulation, the first component of the sub-carrier modulation, and the second component of the sub-carrier modulation respectively; and
        determine a further delay estimate from the first second and third delay estimates.
    
    


The essence of some embodiments of the invention is that it estimates the signal delay in three independent ways and then combines all three estimates to arrive at one overall signal delay estimate. If prior art is applied to MBOC the receiver would correlate the modulation in the received signal with only a single modulation function, which is the combination of the code modulation and the composite sub-carrier modulation. Up to now dealing with the correlation function ( ), as in FIG. 6 which results from this action, has been considered unavoidable, because the combined modulation has been perceived to be intrinsic and inseparable. Some embodiments of the invention contradict this perception. They recognise that correlating the received signal with the component sub-carrier modulation function and code modulation function can be done separately, so avoiding the need to contemplate the conventional correlation function. They further recognise that the two components in the composite sub-carrier can be tracked separately.
In some embodiments of the invention the delay in the MBOC signal is estimated in three different and independent ways—in a triple estimate. A first non-ambiguous lower accuracy estimate is used to resolve the ambiguities in a second higher accuracy estimate. This first estimate is derived only from the phase of the code modulation in the BOC signal; it treats the BOC modulation as a ‘virtual’PSK and ignores the two sub carrier components. A second estimate is derived only from the phase of low frequency component sub carrier modulation in the MBOC signal and ignores the code and the high frequency component sub carrier. A third estimate is derived only from the phase of high frequency component sub carrier modulation in the MBOC signal and ignores both the code and the lower frequency sub-carrier. The code estimate resolves the ambiguity in the second estimate which in turn resolves the ambiguity in the third even higher accuracy estimate.
A four-loop receiver can be used for the optimal triple estimate of the delay in a selected MBOC transmission. In some embodiments an inner delay-locked loop (DLL) tracks the delay as embodied in the code phase; a lower frequency sub-carrier locked loop (SLL1) independently tracks the same delay as embodied in the first component sub-carrier phase, while a higher frequency sub-carrier locked loop (SLL2) independently tracks the same delay as embodied in the second component sub-carrier phase. Thus three independent delay estimates are calculated. A fourth outer loop may track and lock to the carrier phase and/or frequency of the particular satellite signal. All four loops may operate simultaneously, independently yet co-operatively. This implementation may be contrasted with a conventional receiver which uses only two loops, where the single delay estimate is derived from the tracking of the correlation function in a delay-locked loop (DLL) while in parallel and simultaneously the carrier phase and/or frequency is tracked by a second phase locked loop (PLL) or frequency locked loop (FLL).
By virtue of the triple estimate principle in some embodiments of this invention the MBOC correlation function ( ) with its secondary and tertiary peaks does not exist and there are no secondary peaks or triple peaks on which a false lock would occur.
In some embodiments of a four-loop receiver the DLL locks to the peak of the same Λ( )-shaped function as the standard GPS, so ensuring a smooth and non-ambiguous acquisition of a delay estimate. The SLL1 however locks to the nearest peak of the continuous first sub-carrier correlation function—which is a triangular function of periodicity of the low frequency sub-carrier component. This loop estimate has higher accuracy but has an inherent ambiguity in integer multiples of first sub-carrier half cycles. There is no ‘wrong peak’ in this concept however and this ambiguity is acceptable. For, in a further step, the ambiguity in this SLL1 estimate is automatically and instantly resolved by comparison with the DLL estimate.
The SLL2 however, in some embodiments, locks to the nearest peak of the continuous second sub-carrier correlation function—which is a triangular function of periodicity of the high frequency sub-carrier component. This loop estimate has higher accuracy but has an inherent ambiguity in integer multiples of second sub-carrier half cycles. There is no ‘wrong peak’ in this concept however and this ambiguity is acceptable. For, in a further step, the ambiguity in this SLL2 estimate is automatically and instantly resolved by comparison with the corrected SLL1 estimate.
The combination of SLL2, SLL1 and DLL estimates can now provide the inherently higher accuracy due to MBOC modulation on the signal (comparing with PSK on the basis of the same chip rate), with the ambiguity now resolved.
Because the allocated power to the lower frequency sub-carrier is much higher than allocated to the higher frequency sub-carrier an optimal linear combination may be made of the two SLL estimates to generate a fourth estimate with even higher accuracy.
Simulations show smooth consistent operation of this joint estimation process even in conditions of poor signal to noise.
The four-loop receiver can be implemented with the same variety of options that are available to two loop receivers. The standard option is to track the phase of the carrier—as in so-called ‘coherent DLL’ where the outer loop is phase locked to the carrier, using a phase discriminator. An alternative is to track the frequency of the carrier—as in so-called ‘incoherent DLL’ where the outer loop is frequency locked to the carrier, using a frequency discriminator. Various possible phase and frequency discriminators can be used.
Various possible discriminators for the two SLLs can also be used. A variety of standard discriminators for the DLL loop can also be used. In particular the options between coherent early late processing (CELP) and non-coherent early late processing (NELP) continue to be available not only to the code discriminator on the DLL, but also for the sub-carrier tracking on the SLLs. Known technologies and variants, including methods for reducing effect of multipath and currently used in two-loop system will transfer to the new four loop system without complication.
In some embodiments the received signal could more than two, for example three sub-carrier modulation components, in which case a quadruple estimate could be made
Preferred embodiments of the invention are now described, by way of example only, with reference to the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a graphical illustration of a PSK modulated signal according to the prior art;
FIG. 2 is a graphical illustration of a correlation function for the PSK modulated signal shown in FIG. 1 according to the prior art;
FIG. 3 is a graphical illustration of a basic sine-BOC modulated signal according to the prior art;
FIG. 4a is a graphical illustration of an ideal correlation function for the BOC modulated signal shown in FIG. 3 according to the prior art, showing examples of both correct tracking and false tracking;
FIG. 4b is a graphical illustration of a correlation function for filtered and phase distorted correlation function for the BOC example of FIG. 3, showing deleterious effect on relative amplitudes of primary and nearest secondary peak;
FIG. 5 is a graphical illustration of a basic sine-MBOC modulated signal according to the prior art;
FIG. 6a is a graphical illustration of a correlation function for the MBOC modulated signal shown in FIG. 5 according to the prior art, showing examples of correct tracking;
FIG. 6b is a graphical illustration of a correlation function for the MBOC modulated signal shown in FIG. 5 according to the prior art, showing examples of false tracking;
FIG. 6c is a graphical illustration of a correlation function for filtered and phase distorted correlation function for the MBOC example of FIG. 5, showing deleterious effect on relative amplitudes of primary and nearest secondary peak;
FIG. 7 is a schematic illustration of the overall MBOC receiver according to a first preferred embodiment of the invention;
FIG. 8 is a functional expansion of the correlation part 9 of a receiver;
FIG. 9 shows the continuous triangular correlation in either of the sub-carrier component trial delay dimensions only;
FIG. 10 is the nominal correlation in the code delay dimension only;
FIG. 11 is a CELP discriminator function in either of the component sub-carrier delay dimensions only;
FIG. 12 is a CELP discriminator function in the code delay dimension only;
FIGS. 13, 14 and 15 are computer-generated syntheses illustrating operation of the MBOC receiver; and
FIG. 16 shows an example of the top-level operations and tasks of a GNSS software receiver.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 7, an MBOC receiver 1 according to a first preferred embodiment of the present invention is arranged to receive a MBOC modulated signal via a right-hand circularly polarised antenna 2. The antenna 2 feeds the received signal to a pre-amplifier 3, which includes a filter for filtering the received signal, a circuit for blocking strong interfering signals and a Low Noise Amplifier (LNA) for amplifying the received signal. The LNA effectively sets the receiver's noise figure, normally around 2 dB, and provides around 30 dB gain. The pre-amplifier 3 feeds the filtered, amplified signal to a down-converter 4 for a first stage down-conversion of the signal to a suitable intermediate frequency (IF). The signal is down-converted in multiple stages and filtered to eliminate unwanted image signals.
The down-converter 4 feeds the down-converted signal to an Analogue to Digital Converter (ADC) 5 for converting the signal to the digital domain. The ADC 5 can quantise the signal to one, two or more bits. In this embodiment, because the ADC 5 uses multi-bit quantisation, the receiver 1 incorporates an automatic gain control (AGC) circuit 6 to maintain proper distribution of the signal across the quantisation levels. The output of the AGC circuit 6 feeds back to the down-converter 4 to enable control of the signal level input to the ADC 5 and hence maintain proper amplitude distribution of the signal output by the ADC 5. The ADC 5 is arranged to output the digital signal u(t) to the triple-estimator 8. This has a correlator stage 9 and a processing stage 10. In this embodiment, the triple estimator 8 is implemented in hardware. So, the correlator stage 9 comprises an Application Specific Integrated Circuit/Field Programmable Gate-Array (ASIC/FPGA) and the processing stage 10 is a microprocessor. The triple estimator 8 estimates the delay τ between transmission and reception of the received signal and outputs the delay estimate via output 11. A clock signal c(t) from reference oscillator at 7 is provided to the down-converter 4, ADC 6 and the triple estimator 8.
FIG. 8 shows a detailed functional description to the correlator 9. The input signal u(t) splits into an upper in-phase and lower quadrature arm and is processed through four stages. The incoming signal is mixed with replica carrier, sub carrier 2, and sub carrier 1 and code waveforms, each generated by separate digitally controlled oscillators (DCO) 12, 172, 171 18 respectively. First there is multiplication by a phase or quadrature reference signal from the carrier DCO; then multiplication by a ‘prompt’ linear combination of the two sub-carriers, by early or late reference signal from the sub-carrier DCO2, by early or late reference signal from the sub-carrier DCO1, finally multiplication by a prompt, early or late reference signal from the C/A code generator. The resulting signal combinations are accumulated over the code period and eight correlation results formed. The extreme right of the diagram shows the interaction through a data bus to the microprocessor 10.
The input signal u(t) at 5 can be described (neglecting additive noise and other (M)BOC signals simultaneously present) as

u(t)=A×cos(ω0t+φ)×(√{square root over (x1)}s1(t−τ)+√{square root over (x2)}s2(t−τ))×a(t−τ)×d  (1)

where A is amplitude, cos(ω0t+φ) represents the carrier signal after down conversion to an intermediate frequency (IF) ω0 with phase φ, s1(t−τ) and s2(t−τ) are the sub-carrier modulations in the received signal at delay τ, x1 and x2 describe the relative apportionment of power, a(t−τ) is the code modulation in the received signal at delay τ and d is a polarity with dε(−1,+1). Here s1( ) is the BOC(1,1) component while s2( ) is the BOC(6,1) component.

The invention depends on the fact that sub-carrier1 is half-periodic over a relatively short sub-chip width TS1, and sub-carrier2 which is half periodic over an even shorter time of a sub-chip width TS2 and that expression (1) is mathematically identical to

u(t)=A×cos(ω0t+φ)×(√{square root over (x1)}s1(t−τ*1)+√{square root over (x2)}s2(t−τ*2))×a(t−τ)×d*  (2)

where values

τ*1=τ+n1TS1 

τ*2=τ+n2TS2  (3)

are multi-valued shifted offset delays depending on an arbitrary integer multiple n1 of the sub-chip width TS1 and integer multiple n2 of the sub-chip width TS2. It is necessary to note a restriction on the integers. Comparing (1) with (2) it is evident that if n1 is an odd number then n2 must be an odd number; or if n1 is an even number then n2 must be an even number, otherwise the correct shape of the composite modulation is not preserved.

Irrespective of these offset delays it should be understood that the actual sub-carrier delay and the code delay for any actually received signal are still the same as in (1). The receiver must always estimate this actual non-ambiguous delay τ in the code function a( ). It is however only necessary for the same receiver to seek to estimate the ambiguous and offsets τ*1 and τ*2 in the sub-carrier functions s1( ) and s2( ) respectively and still maintain signal to noise optimality. This result is entirely different from present art implementations of BOC/MBOC where these ambiguities must be prevented, and correlations need to be reset if they occur. Therefore the offset delays τ*1 and τ*2 relative to the true delay τ can be treated as if they were independent quantities as in (2), without regard to (1), and three independent estimates are thereby generated. Only in a final correction stage is it admitted that all three estimates of the true delay τ are related, and their values arithmetically combined according to a vernier principle (see from eqs. 35).
Referring to FIG. 8, the correlator stage 9 of the triple estimator 8 receives the digital signal u(t) from the ADC 5 and the clock signal c(t) from the reference oscillator 7. A carrier Digital Controlled Oscillator (DCO) 12 of the correlator stage uses the clock signal c(t) to generate In-phase (I) and Quadrature (Q) reference signals rI(t), rQ(t) at the IF ω0 with trial phase {circumflex over (φ)}, e.g.

r1(t)=+cos(ω0t+{circumflex over (φ)})  (4)

and

rQ(t)=sin(ω0t+{circumflex over (φ)})  (5)

The multiplier 13 then multiplies the digital signal u(t) with reference rI(t) and the I signal filter 14 filters the result to output an in-phase signal vI(t) in the I channel; while the Q signal multiplier 15 multiplies the digital signal u(t) with reference rQ(t) and the Q signal filter 16 filters the result to output quadrature signal vQ(t) in the Q channel. The I and Q signals can be described (neglecting additive noise and other (M)BOC signals simultaneously present) as

vI(t)=cos(φ−{circumflex over (φ)})×(A1×s1(t−τ*1)+A2×s2(τ*2))×a(t−τ)×d  (6)

vQ(t)=sin(φ−{circumflex over (φ)})×(A1×s1(t−τ*1)+A2×s2(t−τ*2))×a(t−τ)×d  (7)

where identity is made that

A1=√{square root over (x1)}×A 

A2=√{square root over (x2)}×A  (8)

To simplify the maths instead of (6) and (7) one can write

vI(t)=A×cos(φ−{circumflex over (φ)})×s(t,τ*1τ*2)×a(t−τ)×d  (9)

vQ(t)=A×sin(φ−{circumflex over (φ)})×s(t,τ*1,τ*2)×a(t−τ)×d  (10)

where the composite modulation is described

s(t,τ*1,τ*2)=√{square root over (x1)}s1(t−τ*1)+√{square root over (x2)}s2(t−τ*2)  (11)

A lower frequency sub-carrier DCO 171 uses the clock signal c(t) input at 7 and the sub-carrier modulation function s1( ) to generate Prompt (P1), Early (E1) and Late (L1) gate sub-carrier reference signals s1(t−{circumflex over (τ)}*1), s1(t−{circumflex over (τ)}*1+TD1/2), and s1(t−{circumflex over (τ)}*1−TD1/2) respectively, where {circumflex over (τ)}*1 is a trial sub-carrier delay and TD1 is the total separation between E1 and L1 gates. The separation or gate width TD1 can be selected freely in the range TS2≦TD1≦TS1.
Similarly a higher frequency sub-carrier DCO 172 uses the clock signal c(t) and the sub-carrier modulation function s2( ) to generate Prompt (P2), Early (E2) and Late (L2) gate sub-carrier reference signals s2(t−{circumflex over (τ)}*2),s2(t−{circumflex over (τ)}*2+TD2/2), and s2(t−{circumflex over (τ)}*2−TD2/2) respectively, where {circumflex over (τ)}*2 is a trial sub-carrier delay and TD2 is the total separation between E2 and L2 gates. The separation or gate width TD2 is conventionally fixed at TD2=TS2, although if the transmitted bandwidth can support it, lower values will give improved accuracy.
Similarly, a code DCO 18 uses the clock signal c(t) and the code modulation function a(t) to generate P, E and L gate code reference signal a(t−{circumflex over (τ)}), a(t−{circumflex over (τ)}+TDC/2), a(t−{circumflex over (τ)}TDC/2) respectively, where {circumflex over (τ)} is a trial code delay and TDC is the total separation between E and L gates. The separation TDC can be selected freely in the range TS1≦TDC≦TC.
The overall correlator stage 8 multiplies the I and Q signals vI(i), vQ(t) by appropriate combinations of the P, E and L gate sub-carrier reference signals s1(t−τ*1), s1(t−{circumflex over (τ)}1+TD1/2), and s1(t−{circumflex over (τ)}*1−TD1/2), the P, E and L gate sub-carrier reference signals s2(t−τ*1), s2(t−{circumflex over (τ)}*2+TD2/2), and s2(t−{circumflex over (τ)}*2−TD2/2) along with the P, E and L gate code reference signals a(t−{circumflex over (τ)}), a(t−{circumflex over (τ)}+TDC/2), a(t−{circumflex over (τ)}−TDC/2). Eight demodulated signals are generated: I channel sum sub carrier P gate code P gate signal vIII(t); I channel sub carrier1 E1 gate code P gate signal vIE1I(t); I channel sub carrier1 L1 gate code P gate signal vIL1I(t), I channel sub carrier2 E2 gate code P gate signal vIE2I(t), I channel sub carrier2 L2 gate code P gate signal vIL2I(t); I channel sum sub carrier P gate code E gate signal vIIE(t); I channel sum sub carrier P gate code L gate signal vIIL(t); Q channel sum sub carrier P gate code P gate signal vQII(t). Algebraically

vIII(t)=vI(t)×s(t,{circumflex over (τ)}*1,{circumflex over (τ)}*2)×a(t−{circumflex over (τ)})  (12)

vIE1I(t)=vI(t)×s1(t−{circumflex over (τ)}*1+TD1/2)×a(t−{circumflex over (τ)})  (13)

vIL1I(t)=vI(t)×s1(t−{circumflex over (τ)}*1+TD1/2)×a(t−{circumflex over (τ)})  (14)

vIE2I(t)=vI(t)×s2(t−{circumflex over (τ)}*2+TD2/2)×a(t−{circumflex over (τ)})  (15)

vIL2I(t)=vI(t)×s2(t−{circumflex over (τ)}*2+TD2/2)×a(t−{circumflex over (τ)})  (16)

vIIE(t)=vI(t)×s(t,{circumflex over (τ)}*1,{circumflex over (τ)}*2)×a(t−{circumflex over (τ)}+TDC/2)  (17)

vIIL(t)=vI(t)×s(t,{circumflex over (τ)}*1,{circumflex over (τ)}*2)×a(t−{circumflex over (τ)}−TDC/2)  (18)

vQII(t)=vQ(t)×s(t,{circumflex over (τ)}*1,{circumflex over (τ)}*2)×a(t−{circumflex over (τ)})  (19)

where the composite trial modulation above

s(t,{circumflex over (τ)}*1,τ*2)=√{square root over (x1)}s1(t−{circumflex over (τ)}*1)+√{square root over (x2)}s2(t−{circumflex over (t)}*2)  (20)

These multiplications are implemented by: first and second multipliers 19, 20 multiplying the I signal vI(t) with P gate sum sub-carrier s(t,{circumflex over (τ)}*1,{circumflex over (τ)}*2) and P gate code to output demodulated, signal vIII(t); third1 and fourth1 multipliers 211, 221 multiplying the I signal vI(t) with E1 gate sub-carrier and P gate code to output second1 demodulated signal vIE1I(t); fifth1 and sixth1 multipliers 231, 241 multiplying the I signal vI(t) with L1 gate sub-carrier and P gate code to output third1 demodulated signal vIL1I(t); third2 and fourth2 multipliers 212, 222 multiplying the I signal vI(t) with E2 gate sub-carrier and P gate code to output secondB demodulated signal vIE2I(t); fifth2 and sixth2 multipliers 232, 242 multiplying the I signal vI(t) with L2 gate sub-carrier and P gate code to output thirdB demodulated signal vIL2I(t); first and seventh multipliers 19, 25 multiplying the I signal vI(t) with P gate composite sub-carrier and E gate code to output fourth demodulated signal vIIE(t); first and eighth multipliers 19, 26 multiplying the I signal vI(t) with P gate composite sub-carrier and L gate code to output fifth demodulated signal vIIL(t); and ninth and tenth multipliers 27, 28 for multiplying the Q signal vQ(t) with P gate composite sub-carrier and P gate code to output sixth demodulated signal vQII(t).

The demodulated signals vIII(t), vIE1I(t), vIL1I(t), vIE2I(t), vIL2I(t), vIIE(t), vIIL(t) and vQII(t), are then integrated by integrators 29 to 34 respectively. The integrators 29 to 34 perform the integration over a fixed time, which in this embodiment is the same as the code period TG. In other embodiments, the integration time can be an integer multiple of the code period TG, so that the integration time is typically of the order of a few milliseconds in total.
The output of each of the integrators 29 to 34 is sampled by the processing stage 10 at the end of each fixed time and the integrators 29 to 34 reset to zero. The outputs of the integrators 29 to 34 can be described by a set of eight correlations wIII[k], wIE1I[k], wIL1I[k], wIE2I[k], wIL2I[k], wIIE[k], wIIL[k] and wQII[k] for each sample k=1, 2, 3 . . . . The purpose of introducing this index k is to clarify the nature of a time series being generated—the actual practical software does not need to implement a count notation. The values of these correlations depend of the difference between the trial phase {circumflex over (φ)} and the true phase φ the difference between the trial sub-carrier delay {circumflex over (τ)}*1 and the offset sub-carrier delay τ*1, the difference between the trial sub-carrier delay {circumflex over (τ)}*2 and the offset sub-carrier delay τ*2, and the difference between the trial code delay {circumflex over (τ)} and the true code delay τ. The I sub-carrier P gate and code P gate correlation wIII[k] can be expressed exactly

wIII[k]=A×cos(φ−{circumflex over (φ)})×χ({circumflex over (τ)}*1−{circumflex over (τ)}*1,{circumflex over (τ)}*2−{circumflex over (τ)}*2,{circumflex over (τ)}−τ)×d*  (21)

where χ( . . . ) is a three-dimensional correlation function. This function is not easily displayed. The three-dimensional correlation function χ( . . . ) has multiple ‘peaks’ when the trial code delay {circumflex over (τ)} equals the true code delay τ i.e.

{circumflex over (τ)}=τ  (22)

and the trial sub-carrier delay {circumflex over (τ)}*1 is equal to any of the multiple values of the sub-carrier code delay τ1*, i.e. the true code delay τ plus a positive or negative integer n multiple of the sub-carrier symbol duration TS1 i.e.

{circumflex over (τ)}*1=τ+n1TS1  (23)

while the trial sub-carrier delay {circumflex over (τ)}*2 is equal to any of the multiple values of the sub-carrier code delay τ*2, i.e. the true code delay τ plus a positive or negative integer n multiple of twice the sub-carrier symbol duration TS2 i.e.

{circumflex over (τ)}2*=τ+n2TS2  (24)

The discriminator action meets the requirement that integer n2 must be odd if n1 is odd and even if n1 is even. In consequence while the {circumflex over (τ)}*1 estimate can shift by arbitrary integer multiple of TS1 the {circumflex over (τ)}*2 estimate will shift by integer multiples of 2TS2.

For explanatory purposes, the I sub-carrier P gate and code P gate correlation wIII[k] can be approximated by the expression

wIII[k]=A×cos(φ−{circumflex over (φ)})×(x1trc1(τ−{circumflex over (τ)}*1)+x2trc1(τ−{circumflex over (τ)}2*))×Λ({circumflex over (τ)}−τ)×d*  (25)

where trc1( ) is a continuous triangular cosine of periodicity 2TS1, trc2( ) is a continuous triangular cosine of periodicity 2TS2. FIG. 9 sketches the general shape; while Λ( . . . ) is the correlation function of a PSK modulated signal having the same code rate as the received signal. This is shown in FIG. 10

The other correlations wIE1I[k], wIE1I[k], wIE2I[k], wIL2I[k], wIIE[k], wIIL[k] and wQII[k] are likewise sufficiently well approximated mathematically by

wIE1I[k]≈A1×cos(φ−{circumflex over (φ)})×trc1({circumflex over (τ)}*1−τ1*−TD1/2)×Λ({circumflex over (τ)}−τ)×d*  (26)

wIL1I[k]≈A1×cos(φ−{circumflex over (φ)})×trc1({circumflex over (τ)}*1−τ1*−TD1/2)×Λ({circumflex over (τ)}−τ)×d*  (27)

wIE2I[k]≈A2×cos(φ−{circumflex over (φ)})×trc2({circumflex over (τ)}*2−τ2*−TD2/2)×Λ({circumflex over (τ)}−τ)×d*  (28)

wIL2I[k]≈A2×cos(φ−{circumflex over (φ)})×trc2({circumflex over (τ)}*2−τ2*−TD2/2)×Λ({circumflex over (τ)}−τ)×d*  (29)

wIIE[k]≈A×cos(φ−{circumflex over (φ)})××Λ({circumflex over (τ)}−τ−TDC/2)×d*  (30)

wIIL[k]≈A×cos(φ−{circumflex over (φ)})×s(τ,{circumflex over (τ)}*1,{circumflex over (τ)}2*)×Λ({circumflex over (τ)}−τ+TDC/2)×d*  (31)

wQII[k]≈A×sin(φ−{circumflex over (φ)})×s(τ,{circumflex over (τ)}*1,{circumflex over (τ)}2*)×Λ({circumflex over (τ)}−τ)×d*  (32)

It can be appreciated that, when the I channel sub carrier1 E1 gate code P gate correlation wIE1I[k] has the same value as the I channel sub-carrier1 L1 gate of code P gate the correlation wIL1I[k], i.e. wIE1I[k]=wIL1I[k], this because the E1 and L1 gates for the sub-carrier1 reference signal have the same value.
Similarly, when the I channel sub carrier2 E2 gate code P gate correlation wIE2I[k] has the same value as the I channel sub carrier2 L2 gate code P gate correlation wIL2I[k] i.e. wIE2I[k]=wIL2I[k] this is because the E2 and L2 gates for the sub-carrier2 reference signals have the same value.
Similarly, when the I channel sum sub carrier P gate code E gate correlation wIIE[k] has the same value the I channel sum sub carrier P gate code L gate correlation wIIL[k], i.e. wIIE[k]=wIIL[k], this because the E and L gates for the code have the same value.
Similarly when phase lock has been achieved the Q channel correlation wQII[k] is zero, i.e. wQII[k]=0, because the phase estimate {circumflex over (φ)} is the same as the true phase φ plus or minus an integer number of carrier half cycles, and the sine function in expression ( ) is zero.
Any difference between the correlation wIE1I[k] and the correlation wIL1I[k] is proportional to the difference between the sub-carrier trial delay {circumflex over (τ)}*1 and the nearest multi-value of the sub-carrier delay τ*1. Consequently, the processing stage 10 carries out a subtraction step 351 that subtracts correlation wIE1I[k] from the correlation wIL1I[k] to give a sub-carrier1 difference correlation wIQ1I[k]. This can be expressed mathematically as

wIQ1I[k]≈A1×cos(φ−{circumflex over (φ)})×Trs1(τ*1−{circumflex over (τ)}*1)×trc2({circumflex over (τ)}*2−{circumflex over (τ)}*2)×Λ({circumflex over (τ)}−τ)×d*  (33-1)

where Trs1( ) is a trapezium sine discriminator function of periodicity 2TS1 depending on the difference between the trial sub-carrier delay {circumflex over (τ)}*1 and the multivalued sub-carrier delay τ*1. FIG. 11 shows this general function.

Any difference between the correlation wIE2I[k] and the correlation wIL2I[k] is proportional to the difference between the sub-carrier trial delay {circumflex over (τ)}*2 and the nearest multi-value of the sub-carrier delay τ*2.
CELP
According to one embodiment the principle of coherent early-late processing (CELP) may be adopted. Consequently, the processing stage 10 carries out a subtraction step 352 that subtracts correlation wIE2I[k] from the correlation wIL2I[k] to give a sub-carrier2 difference correlation wIQ2I[k]. This can be expressed as

wIQ2I[k]≈A1×cos(φ−{circumflex over (φ)})×trc1({circumflex over (τ)}*1−{circumflex over (τ)}*1)×Trs2({circumflex over (τ)}*2−{circumflex over (τ)}*2)×Λ({circumflex over (τ)}−τ)×d*  (33-2)

where Trs2( ) is a trapezium sine discriminator function of periodicity 2TS2 depending on the difference between the trial sub-carrier delay {circumflex over (τ)}*2 and the multivalued sub-carrier delay τ*2, again as shown in FIG. 11.

Similarly, any difference between the I sub-carrier P gate and I code E gate correlation wIIE[k], and the correlation wIIL[k] is proportional to the difference between the trial code delay {circumflex over (τ)} and the true code delay τ. Consequently, the processing stage 10 carries out a subtraction step 36 that subtracts correlation wIIE[k] from the correlation wIIL[k] to give a code difference correlation wIIQ[k]. This can then be expressed as

wIIQ[k]A×cos(φ−{circumflex over (φ)})×(x1trc1(τ−{circumflex over (τ)}*1)+x2trc1(τ−{circumflex over (τ)}*2))×VΛ(τ−{circumflex over (τ)})×d*  (34)

where VΛ( ) is a discriminator function and is shown in FIG. 12.

Finally, any non-zero value of the Q sub-carrier P gate and Q sub-carrier P gate correlation wQII[k] is approximately proportional to the difference between the trial phase {circumflex over (φ)} and the true phase φ within an arbitrary number of carrier half cycles.
It should be noted that in this account an E gate is subtracted from an L gate in order to ensure correct polarity of loop correction in terms of a code and sub-carrier delay estimate. In an equivalent description an L gate is subtracted from an E gate, in order to ensure correct polarity of loop correction as expressed in terms of a code and sub-carrier phase estimate. This is because conventionally ‘phase’ and ‘delay’ which are equivalent ways of describing shifts in periodic waveforms are generally perceived as having opposite signs.
Finally, any non-zero value of the Q sub-carrier P gate and Q sub-carrier P gate correlation wQII[k] is approximately proportional to the difference between the trial phase {circumflex over (φ)} and the true phase φ.
NELP
An alternative embodiment according to the principle of non-coherent early late processing (NELP) may be adopted and is described below in ‘alternative embodiments of error discriminators’
From the overall structure of the equations and with the quadruple loop action ideally in the absence of noise the carrier phase {circumflex over (φ)}→φ+nπ where n is an odd or even integer, while the three time estimates {circumflex over (τ)}, {circumflex over (τ)}*1, and {circumflex over (τ)}*2 converge ideally and independently to the values given as in (22), (23) and (24) respectively. The {circumflex over (τ)} estimate is any unambiguous estimator of the true delay τ but can be shown to be the least accurate, in the presence of noise. The {circumflex over (τ)}*1 is more accurate since it exploits the sub-carrier modulation but is offset by an arbitrary integer multiple n1 of sub-chip width TS1. A simplest procedure to derive a corrected estimate combines the two




  
    
      
        
          
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This estimate corrected can then be used to correct the even better estimate based on the faster sub-carrier component





  
    
      
        
          
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finally, and recognising that the MBOC proposal puts considerably less power in the higher sub-carrier component, an optimal linear combination may be formed

{circumflex over (τ)}+=w1{circumflex over (τ)}1++w2{circumflex over (τ)}2+  (35-3)

where coefficient w1 and w2 can be established from standard theory of least square estimation.

Rather than a double rounding procedure the preferred embodiment enables automatic integer correction within the loops operation so that {circumflex over (τ)}*1→{circumflex over (τ)}1+ and {circumflex over (τ)}*2→{circumflex over (τ)}2+ and there is no proliferation of different variable names

Code Processing Description (CELP Implementation)

All processing actions will be described and also summarised in pseudo code. Execution of this block of computer code is synchronised to every correlation and is updated here according to a count k.
Correlations wIII[k], wIQ1I[k], wIQ2I[k], wIIQ[k] and wQII[k] are input to this processing block. Timing errors eτ1*[k], et2*[k] and eτ[k] and phase error eφ[k] are generated from the correlations in order to steer the trial phase {circumflex over (φ)}[k], trial delays {circumflex over (τ)}*1[k], {circumflex over (τ)}*2[k] and {circumflex over (τ)}[k] towards true phase φ and true delays τ*1, τ*2 and τ respectively. Also responsive DLL gate widths TDC[k] and SLL1 gate width TD1[k] are output—which vary in response to conditions. An optimal linear combination {circumflex over (τ)}+ of the SLL estimates is also computed.
The block of computer pseudo-code may be summarised as follows












→ wIII wIQ1I wIQ2I wIIQ wQII Δ{circumflex over (τ)}1 Δ{circumflex over (τ)}2 {circumflex over (τ)}1* {circumflex over (τ)}2* {circumflex over (τ)} {circumflex over (φ)} TD1 TDC









{circumflex over (d)} ← sgn(wIII)
compute sign
36-1


eφ ← wQII × {circumflex over (d)}
PLL error
36-2


eτ1* ← wIQ1I × {circumflex over (d)}
SLL1 error
36-31


eτ2* ← wIQ2I × {circumflex over (d)}
SLL2 error
36-32


eτ ← wIIQ × {circumflex over (d)}
DLL error
36-4


fφ ← fφ + eφ
update phase estimate
36-5


{circumflex over (φ)} ← {circumflex over (φ)} + k1fφ + k2eφ


{circumflex over (τ)}2* ← {circumflex over (τ)}2* + kτ2*eτ2*
update SLL2 estimate
36-62


{circumflex over (τ)}1* ← {circumflex over (τ)}1* + kτ1*eτ1*
update SLL1 estimate
36-61


{circumflex over (τ)} ← {circumflex over (τ)} + kτeτ
update DLL estimate
36-7


{circumflex over (τ)}+ ← w1{circumflex over (τ)}1* + w2{circumflex over (τ)}2*
update optimal joint
36-8



estimate


If |Δ{circumflex over (τ)}1| > TS1/2
test tracking of SLL1
36-91



against DLL


{circumflex over (τ)}1* ← {circumflex over (τ)}1* + sign(Δ{circumflex over (τ)}1) × TS1
boot SLL1 estimate
36-101


Δ{circumflex over (τ)}1 ← 0
reset filter1 output
36-111


TDC ← TC
raise gate width DLL
36-121


otherwise


Δ{circumflex over (τ)}1 ← KF × ({circumflex over (τ)} − {circumflex over (τ)}1* − Δ{circumflex over (τ)}1) + Δ{circumflex over (τ)}1
filter estimate1 difference
36-131


TDC ← KD × (TS1 − TDC) + TDC
relax gate width DLL
36-141


If |Δ{circumflex over (τ)}2| > TS2/2
test tracking of SLL2
36-92



against SLL1


{circumflex over (τ)}2* ← {circumflex over (τ)}2* + sign(Δ{circumflex over (τ)}2) × TS2
boot SLL2 estimate
36-102


Δ{circumflex over (τ)}2 ← 0
reset filter2 output
36-112


TD1 ← TS1
raise gate width of SLL1
36-122


otherwise


Δ{circumflex over (τ)}2 ← KF × ({circumflex over (τ)}1* − {circumflex over (τ)}2* − Δ{circumflex over (τ)}2) + Δ{circumflex over (τ)}2
filter estimate2 difference
36-132


TD1 ← KD × (TS2 − TD1) + TD1
relax gate width SLL1
36-142


← Δ{circumflex over (τ)}1 Δ{circumflex over (τ)}2 {circumflex over (τ)}+ {circumflex over (τ)}1* {circumflex over (τ)}2* {circumflex over (τ)} {circumflex over (φ)} TD1 TDC









DETAILED DESCRIPTION
The processing stage 1 is a limiter to estimate the sign of the I sub-carrier P gate and code P gate correlation wIII[k] (which may be either positive or negative). The ‘sgn’ function delivers either +1 or −1 depending on the polarity of the correlation.
Every Ts, notated here as an event by a unit increment in count k, the processing stage 10 then computes the three feed-back error signals eφ[k] eτ1*[k] et2*[k] eτ[k] at 2, 31 32, and 4 respectively by multiplying the respective Q sub-carrier P gate and Q code P gate correlation wQII[k], sub-carrier difference correlations wIQ1I[k] and wIQ2I[k] and code difference correlation wIIQ[k] by the sgn( ) signal {circumflex over (d)}[k].
The count notation ‘[k]’ is deliberately omitted since in the actual algorithm this count need not be recorded.
The processing stage then filters the error signals in order to increment or decrement the trial phase {circumflex over (φ)}, sub-carrier trial delays {circumflex over (τ)}*1 {circumflex over (τ)}*2 and code trial delay {circumflex over (τ)} as in 5, 61, 62 and 7 respectively.
Of the three timing estimates, {circumflex over (τ)}*2 with which SLL2 tracks the sub carrier component at f2=6 MHz is the most accurate but potentially ambiguous by multiples of TS2=1/12 μs, while {circumflex over (τ)}*1 with which SLL1 tracks the sub carrier component at f2=1 MHz is the less accurate but potentially ambiguous by multiples of TS1=1/2 μs, and {circumflex over (τ)} with which DLL tracks the code component is the least accurate but quite unambiguous.
But because of the lower power in the MBOC component the difference in accuracy between the SLL1 and SLL2 estimates is not so large. Consequently it is worth while to form an optimal linear mix of the two estimates, after the values have been corrected, as is shown in line 8 to get an estimate which is the best of all.
Again, the count notation ‘[k]’ is deliberately omitted since in the actual algorithm this count need not be recorded.
In this embodiment the carrier phase correction is implemented by a second order loop, where phase error eφ, increments an integrated phase error fφ, which direct and integrated errors update a current phase estimate via two gain constants k1 and k2. The SLL time estimates implement a first order loops via a gain constants kτ1* and kτ2* respectively and the DLL time estimate implements a first order loop via a gain constant kτ.
With increasing count and in the realistic presence of noise these errors go to zero on average i.e. eφ[k]→0, eτ[k]→0 and eτ1*[k]→0 eτ2*[k]→0
The remainder of the processing block is concerned with corrections when needed to the potentially ambiguous estimates.
In line 91 the filtered difference Δ{circumflex over (τ)}1 between SLL1 estimate {circumflex over (τ)}*1[k] and the DLL estimate {circumflex over (τ)}[k] was evaluated on previous iteration (previous k value).
If the difference Δ{circumflex over (τ)}1 is now found to have exceeded half a sub-chip width TS1 then the SLL1 estimate is deemed to have slipped. This estimate is therefore booted, i.e. appropriately incremented or decremented as in 101 and the difference Δ{circumflex over (τ)}1 reset to zero at 111. Further, the DLL gate width is expanded from whatever is its current narrower width (TDC) to a full chip width TC as in 121. The purpose of this manoeuvre is to speed up acquisition because it is likely that the DLL is in the process of acquiring lock.
Otherwise it may be that the filtered difference between the two estimates has not exceeded half a sub-chip width. In which case a first order difference filter updates Δ{circumflex over (τ)}1 using the newly available updates {circumflex over (τ)}*1 and {circumflex over (τ)} as in 131. A gain term KF controls the response time of this difference filter. Further, the code gate width TDC decrements exponentially, and in due course, over sufficient number of iterations this width will settle asymptotically on a minimum value—made here to be equal to the sub-chip width TS1 as in 141. The settling time of this is determined by a controller gain KD.
The point of controlling the DLL gate downwards to this minimum is in order to minimise the noise in the DLL loop, which if excessive could trigger a false decision in line 91. In this way the operating range of the receiver is extended downwards to the lowest possible carrier to noise density ratio C/N0. for a given loop bandwidth BL. In this embodiment the DLL gate width TDC[k] therefore becomes a dynamic variable over the range TS1≦TDC≦TC.
A similar action takes place with respect to the filtered difference Δ{circumflex over (τ)}2. The test for the SLL2 estimate deemed to have slipped if it has exceeded a half sub-chip width TS2/2—see line 92. Alignment of the adjusted estimates preserves the correct shape of the multiplexed subcarriers as in FIG. 5 The reason is that in the Costas loop action respond only to the sign of estimate {circumflex over (d)}[k] as determined by the state of {circumflex over (φ)}[k] {circumflex over (τ)}*1 and {circumflex over (τ)}. It will not respond to the value of {circumflex over (τ)}*2 since in the two components of the sum modulation s(t,{circumflex over (τ)}*1, {circumflex over (τ)}*2) the s1( ) component is dominating. Consequently, while the time discriminator characteristic of error eτ1* is periodic over TS1 the time discriminator characteristic of error eτ2* is periodic over 2TS2. In the event of a detected slip the SLL1 gate width is augmented, anticipating an acquisition state. If no slip is detected this gate width is allowed to relax back to the steady state value.
If the difference Δ{circumflex over (τ)}2 is now found to have exceeded a half sub-chip width TS2/2 as at 92 then the SLL2 estimate is deemed to have slipped. This is therefore booted, i.e. appropriately incremented or decremented and the difference Δ{circumflex over (τ)}e is reset to zero in 102 and 112. Further, the SLL1 gate width is expanded from whatever is its current narrower width (TD1) to a full sub-chip width TS1 in 122. The purpose of this manoeuvre is to speed up acquisition because it is likely that the SLL1 is in the process of acquiring lock.
Otherwise it may be that the filtered difference between the two estimates has not exceeded a full sub-chip width. In which case a first order difference filter updates Δ{circumflex over (τ)}2 using the newly available updates {circumflex over (τ)}*1 and {circumflex over (τ)}*2 as in 132. A gain term KF controls the response time of this difference filter. Further, the gate width TD1 decrements exponentially, and in due course, over sufficient number of iterations this width will settle asymptotically on a minimum value—made here to be equal to the sub-chip width TS2. The settling time of this is determined by a controller gain KD.
The point of controlling the SLL1 gate downwards to some minimum is in order to minimise the noise in the SLL1 loop, which if excessive could trigger a false decision at 92. In this way the receiver may operate in the lowest possible carrier to noise density ratio
C/N0. for a given loop bandwidth BL.
In these correction stages it is admitted that the estimates {circumflex over (τ)}*1[k] {circumflex over (τ)}*2[k] and {circumflex over (τ)}[k] are necessarily linked, because the difference between them, after rounding, should be an integer multiple of the sub chip width TS1 and an integer multiple of the sub chip width TS2, respectively, and assuming that all three loops are locked (converged) and the input C/N0 is sufficiently high. This best combination of the three estimates which finally yield an optimal linear combination {circumflex over (τ)}+[k] is updated every correlation interval.
The system as described above with reference to FIGS. 7-12 eliminates the possibility of slip or false node tracking in an MBOC receiver while fully exploiting the potential of MBOC modulation.
As an essential qualification is noted that the system fails if the loops lose lock. But this is true of all loop-based systems. The system also fails if the filtered difference of estimates falls randomly outside the bounds

|Δ{circumflex over (τ)}1|>TS1/2  (37)

|Δ{circumflex over (τ)}2|>TS2/2  (38)

which in principle can occur because of excessive noise in the various estimates, even if the loops are in lock, for too low an input carrier to noise density ratio (CNDR) and/or too high a loop bandwidth BL. Theory finds however that this restriction on the allowed range of CNDR and BL. is not practically onerous. The value of the DLL gate width TDC, which controls the DLL discriminator action is an automatic compromise. To maximise speed of acquisition it is switched to the highest value which is the chip width TC This gives the fastest response of the DLL in the initial acquisition. In a detected steady state the relaxation of TDC down to sub-chip width TS1 will however minimise the noise in the DLL estimate and extend the basic performance envelope. Similarly the value of the SLL1 gate width TD1, which controls the SLL1 discriminator action is an automatic compromise. To maximize speed of acquisition it is switched to the highest value which is the sub-chip width TS1. This gives the fastest response of the SLL1 in the initial acquisition. In a detected steady state the relaxation of TD1 down to the smaller sub-chip width TS2 will however minimise the noise in the SLL1 estimate and extend the basic performance envelope.

The failure condition are however fail safe since the receiver can always measure for itself when this condition has arisen.
Allowing for Phase Distortion
It was claimed that the prior art receiver designed according to the VEVL, amongst other problems, is vulnerable to phase distortion (see FIG. 6c). The same effect manifests itself here as non integer shifts to the two SLL estimates. Now (2) is literally true and instead of (3) one must write

τ*1=τ+n1TS1+ε1 

τ*2=τ+n2TS2+ε2  3*

where non-integer errors ε1 and ε2 are due to group delay distortion. The corresponding modifications needed in the pseudo code can be done in a number of ways. The simplest is to modify 36-8 to

{circumflex over (τ)}+←w1×({circumflex over (τ)}*1−{circumflex over (ε)}1)+w2×({circumflex over (τ)}*2−{circumflex over (ε)}1)  36-8*

and modify (36-131) and (36-132) accordingly so that

Δ{circumflex over (τ)}1←KF×({circumflex over (τ)}−{circumflex over (τ)}*1+{circumflex over (ε)}1−Δ{circumflex over (τ)}1)+Δ{circumflex over (τ)}1  36-13*1 

Δ{circumflex over (τ)}2←KF×({circumflex over (τ)}−{circumflex over (ε)}1−{circumflex over (τ)}*2+{circumflex over (ε)}2−Δ{circumflex over (τ)}2)+Δ{circumflex over (τ)}2  36-13*2 

where corrections {circumflex over (ε)}1 and {circumflex over (ε)}2 are supplied most simply in a preliminary calibration.

Practical Implementation

The correlator architecture of a GNSS BOC receiver requires relatively few changes compared to a GNSS PSK receiver in order to implement the triple estimate in a quadruple loop technique. This process is equivalent in both hardware and software receivers.

FIG. 16 shows an example of the top-level operations and tasks of a GNSS software receiver according to a further embodiment of the invention. The initialisation involves setting up the software and starting the correlator channels running. After initialisation the software enables the software interrupts. Typically two types of interrupt are used; a fast rate (≈1 ms) interrupt for the tracking task which takes the highest priority and a slower rate (≈100 ms) interrupt for the measurement task which is given a lower priority. The tracking task reads the accumulator values, estimates the navigational data state and updates all four loops with new estimates of carrier1, sub carrier, sub carrier2 and code phase. The measurement task provides the detailed measurements required to form the navigation solution such as reading the carrier, the two sub carriers and code DCO values and necessary counters in the correlator. Under these essential tasks priority can be given to the various navigational tasks.
Table T1 shows the hardware requirements of each correlator channel based on receiver architecture designed to operate at an intermediate frequency IF of 11.38 MHz, with a 50 MHz sampling rate, 100 ms measurement interval (TIC period) and 2-bit quantisation. The hardware requirements of the quadruple loop receiver as detailed in Table 1 are easily achievable (12 channels or more) with most modern ASIC and FPGA designs. Two levels of complexity are distinguished—the minimum components needed for the outer loop embodying a DLL—as given in the detailed description and FIG. 8 plus the detailed pseudo-code listing of Eqs (36). A further level of complexity requires the additional components as shown in extreme right columns for the purposes described in the next section.







TABLE 1







Hardware requirements of triple loop architecture per channel.









Number required



per channel










Components
Size
basic
extended













Multipliers
4 × 1
14
+14










2 × 2
2


Digitally Controlled
31 bits
4 (Carrier,


Oscillators (DCO)
(frequency resolution =
Sub carrier and



23.03 mHz)
Code DCOs)










Accumulators
19 bits
8
+14









Counters
21 bits
1



(carrier cycles in 100 ms)



20 bits
2



(sub carrier cycles up to



10.23 MHz)



20 bits
1



(code chips up to 10.23 Mcps)



11 bits
1



(epoch counter 1 ms epochs)


Registers
31 bits
3 (Carrier,



(phase register)
Sub carrier and




Code DCO phase)









Extensions and Improvements

In the standard literature numerous improvements and alternatives are described to enable double loop implementation of standard PSK-CDMA. Without exception, after appropriate modification these may be applied to the quadruple loop receiver of MBOC.
Additional Correlations
Not shown in FIG. 8 are potential improvements and alternatives, obtainable from computing further processing the down converted signals. These by natural extension for n=1 and n=2

vIEnE(t)=vI(t)×sn(t−{circumflex over (τ)}*+TDn/2)×a(t−{circumflex over (τ)}+TDC/2)  (39)

vILnE(t)=vI(t)×sn(t−{circumflex over (τ)}*−TDn/2)×a(t−{circumflex over (τ)}+TDC/2)  (40)

vIEnL(t)=vI(t)×sn(t−{circumflex over (τ)}*+TDn/2)×a(t−{circumflex over (τ)}+TDC/2)  (41)

vILnL(t)=vI(t)×sn(t−{circumflex over (τ)}*−TDn/2)×a(t−{circumflex over (τ)}+TDC/2)  (42)

vQEnI(t)=vQ(t)×sn(t−{circumflex over (τ)}*+TDn/2)×a(t−{circumflex over (τ)})  (43)

vQLnI(t)=vQ(t)×sn(t−{circumflex over (τ)}*−TDn/2)×a(t−{circumflex over (τ)})  (44)

vQIE(t)=vQ(t)×s(t,{circumflex over (τ)}*1,{circumflex over (τ)}*2)×a(t−{circumflex over (τ)}+TDC/2)  (45)

vQIL(t)=vQ(t)×s(t,{circumflex over (τ)}*1,{circumflex over (τ)}*2)×a(t−{circumflex over (τ)}+TDC/2)  (46)

where again the composite trial modulation above

s(t,{circumflex over (τ)}*1,τ*2)=√{square root over (x1)}s1(t−{circumflex over (τ)}*1)+√{square root over (x2)}s2(t−{circumflex over (τ)}*2)  (11)

From these may be integrated to corresponding correlations every T seconds to wIEnE[k], wILnE[k], wIEnL[k], wILnL[k], wQEnI[k], wQLnI[k], wQIE[k], wQIL[k] respectively. Further, there may be extracted correlation differences

wIQnQ=(wILnL−wIEnL)−(wILnE−wIEnE)  (47)

wQQnI=wQLnI−wQEnI  (48)

wQIQ=wQIL−wQIE  (49)

These correlations may be used to enhance and generalise operation of the invention in many different ways.
Improvement from Carrier Aiding
The invention admits the standard technique of carrier aiding—the technique of importing into the delay estimate a correction proportional to the Doppler frequency. The equations (36-6) can be modified accordingly to read

{circumflex over (τ)}*2←{circumflex over (τ)}*2+kφ2*fφ+kτ2*eτ2*  (50)

{circumflex over (τ)}*1←{circumflex over (τ)}*1+kφ1*fφ+kτ1*eτ1*  (51)

{circumflex over (τ)}←{circumflex over (τ)}+kφfφ+kτeτ  (52)

Term fφ is the same as in the PLL equations (36-5) and is interpreted as a scaled Doppler shift estimate (either positive or negative depending on the sign of the relative motion). Constants kφ, kφ2* and kφ1* are pre-calculated to provide the necessary open loop correction of Doppler shift appropriately scaled down to the code rate and sub-carrier rate respectively.
Alternative Embodiments of Error Discriminators
The computation to error sequences according to (36-2), (36-3), and (36-4) utilised only one of many possible discriminators. The standard alternatives available in the dual-loop single-estimate conventional PSK receivers may be adopted here, after appropriate modification, and in particular non-coherent early late processors (NELP).

PLL Discriminators

From (36-1) and (36-2) the equivalent formulation is

eφ←wQII[k]×sgn(wIII)  (53)

Dispensing with sgn( ) operation gives

eφ←wQII[k]×wIII  (54)

Expressing this as a ratio gives





  
    
      
        
          e
          φ
        
        ←
        
          
            w
            QII
          
          
            w
            III
          
        
      
    
    
      
        (
        55
        )
      
    
  




To improve tracking when SLL is not yet in lock one can adopt

eφ←wQII×sgn(wIII)+wQQI×sgn(wIQI)  (56)

from which removing sgn( ) gives

eφ←wQII×wIII+wQQI×wIQI  (57)

SLLn Discriminators

From (36-1) and (36-3) the equivalent formulation is

eτn*←wIQnI×sgn(wIII)  (58)

Dispensing with the sgn( ) operation gives

eτn*←wIQnI×wIII  (59)

Expressing this as a ratio gives





  
    
      
        
          e
          
            τ
            ⁢
            
              
            
            ⁢
            
              n
              *
            
          
        
        ←
        
          
            w
            IQnI
          
          
            w
            III
          
        
      
    
    
      
        (
        60
        )
      
    
  




DLL Discriminator

From (36-1) and (36-4) the equivalent formulation is

eτ←wIIQ×sgn(wIII)  (61)

Removing the sgn( ) operation gives

eτ←wIIQ×wIII  (62)

Incoherent DLL Embodiment

It has been claimed that an ‘incoherent DLL’ receiver is more effective than ‘coherent DLL’. A representative paper is “Theory and Performance of narrow correlation spacing in a GPS receiver”, A. J. Van Dierendonck et al ION National Technical Meeting San Diego Calif. January 1992. This concept requires a frequency locked loop (FLL) instead of a PLL in the outer loop. This type of system is readily incorporated into the triple estimate concept for MBOC-GNSS requiring however some of the additional correlations identified from (39) to (46).
The implementation of an FLL requires only that the difference between the phase and the phase estimate

Δφ=φ−{circumflex over (φ)}  (63)

be made to settle at some arbitrary constant rather than zero. The aim however with the control of the time estimates in the two loops is again that {circumflex over (τ)}*1→τ+n1TS1, {circumflex over (τ)}*2→T+n2Ts2 and {circumflex over (τ)}→τ. But effective tracking of the SLL1 sub carrier phase and SLL2 (to yield estimates {circumflex over (τ)}*1 and {circumflex over (τ)}*2 respectively) and the DLL (to yield estimate {circumflex over (τ)}) must generate an error signal which is indifferent to an arbitrary constant offset between {circumflex over (φ)} and φ.

It is necessary then to realise a frequency discriminator from the correlations and/or correlation differences, and to ensure that the SLL1,SLL2 and DLL discriminators are indifferent to carrier phase error.
FLL Discriminators
First we can compute a frequency error from current and previous correlations and correlation differences

eωQI←wQIIsgn(wIII−)−wIIIsgn(wQII−)  (64)

where the notation wIII− and wQII− stands for correlation in the previous correlation (earlier by T) One can also form

eωII←wIIIsgn(wIII−)+wQIIsgn(wQII−)  (65)

which allows a 2-quadrant computation





  
    
      
        
          e
          ω
        
        =
        
          
            
              〈
              
                e
                
                  ω
                  ⁢
                  
                    
                  
                  ⁢
                  QI
                
              
              〉
            
            
              〈
              
                e
                
                  ω
                  ⁢
                  
                    
                  
                  ⁢
                  II
                
              
              〉
            
          
          ≈
          
            tan
            ⁡
            
              (
              Δω
              )
            
          
        
      
    
    
      
        (
        66
        )
      
    
  




Alternatively a 4 quadrant computation

eω=arctan 2eωQIeωII  (67)

Another alternative is to dispense with sgn functions as in (64) so that

eωQI←wQIIwIII−−wIIIwQII−  (68)

and one can also form

eωII←wIIIwIII−+wQIIwQII−  (69)

which again allows a 2-quadrant computation or a 4 quadrant comparison.

SLL Discriminators (NELP)

The discriminator must work for an arbitrary phase difference Δφ Discriminator (36-3) does not work in this case, so we need to extend to

eτn*←wIQnIsgn(wIII)+wQQnIsgn(wQII)  (70)

One can dispense with sgn( ) to obtain

eτn*←wIQnIwIII+wQQnIwQII  (71)

DLL Discriminator (NELP)

The discriminator must work for an arbitrary phase difference Δφ Discriminator (36-4) does not work in this case, so we need to extend to

eτ←wIIQsgn(wIII)+wQIQsgn(wQII)  (72)

One can dispense with sgn( ) to obtain

eτ←wIIQwIII+wQIQwQII  (73)

Computing the difference of power direct from early and late correlations gives

eτ←wIIL2+wQIL2−wIIE2−wQIE2  (74)

which one may enhance with further correlations to obtain

eτ←(wIIL2+wQIL2+wIQL2+wQQL2)−(wIIE2+wQIE2+wIQE2+wQQE2)  (75)

Computing the difference of amplitude direct from early and late correlations gives

eτ←√{square root over (wIIL2−wQIL2)}−√{square root over (wIIE2+wQIE2)}  (76)

and computing the normalised difference gives





  
    
      
        
          e
          τ
        
        ←
        
          
            
              
                
                  w
                  IIL
                  2
                
                -
                
                  w
                  QIL
                  2
                
              
            
            -
            
              
                
                  w
                  IIE
                  2
                
                +
                
                  w
                  QIE
                  2
                
              
            
          
          
            
              
                
                  w
                  IIL
                  2
                
                -
                
                  w
                  QIL
                  2
                
              
            
            -
            
              
                
                  w
                  IIE
                  2
                
                +
                
                  w
                  QIE
                  2
                
              
            
          
        
      
    
    
      
        (
        77
        )
      
    
  




Loop Operations

An appropriate modification for ‘incoherent DLL’ can be expressed in pseudo code as:

êφ←êφ+eωI 

{circumflex over (f)}φ←{circumflex over (f)}φ+êφFLL  (78

{circumflex over (φ)}←{circumflex over (φ)}+k1{circumflex over (f)}φ+k2êφ

{circumflex over (τ)}*1←{circumflex over (τ)}*1+kτ1*eτ1*SLL1  (79)

{circumflex over (τ)}*2←{circumflex over (τ)}*2+kτ2*eτ2*SLL2  (80)

{circumflex over (τ)}←{circumflex over (τ)}+kτeτDLL  (81)

which can be extended by carrier aiding.

Computer Generated Simulation

FIGS. 13, 14 and 15 show a simulation of the quadruple loop-dual estimator in action according to the embodiment of FIG. 8, and as described earlier, according to the CELP principle. The chosen parameters are exactly the same in the two FIGS. 13 and 14 but without and with additive noise respectively. The aim here is not only to demonstrate the anti-slip fail safe nature of the quadruple loop but also to show a typical acquisition process. There is assumed to have been an initial search—just as in standard PSK-CDMA—which brings the code delay estimate within ±TC of the actual input delay and therefore within range of the DLL discriminator.
Simulation values are deliberately chosen for the most stringent test of possible operation. The C/N0±250 Hz is equivalent to 24 dBHz and is the very low value chosen in the already cited paper by Fine and Wilson. This carrier to noise density ratio is significantly lower than usual test conditions for GNSS signals. The MBOC modulation is the one actually proposed where the high rate component BOC(6,1) is 2/11 of the low rate component BOC(1,1). This composite modulation confined to the pilot channel which is 50% of the whole power. Correlation interval T=20 ms gives 10 dB signal to I channel noise ratio Normalised chip width TC=1. Normalised sub-chip width TS1=1/2. Normalised sub-chip width TS2=1/12. The loop bandwidth of BL=2 Hz which is close to the highest allowed for this low value of C/N0. The test here shows that the algorithm will simultaneously acquire all three estimates and instantaneously correct the SLL1 estimate from the DLL estimate and the SLL2 estimate from the SLL1 estimate, even during the dynamic process when the loops are locking up. Tracking performance depends on the difference between the actual code delay and the initial setting of the loop estimates after an initial search. The example has a synthesised actual delay τ=τ0=9.5/12 which is bad start up condition with the DLL and SLL loops originally initialised in this example with {circumflex over (τ)}*1=0, {circumflex over (τ)}*2=0 and {circumflex over (τ)}=0, because the initial search result is presumed to be a poor one. Filter gains KF=0.5 and KD=0.02 were chosen empirically as a result of these tests.
The rising dotted curve in the upper graph is the DLL estimate. Acquisition by the DLL responds immediately but the other loops hardly move until count 21 (420 msec); then SLL1 is booted into action and immediately after SLL2. The long dashed curve for SLL1 shows that it requires only two steps to get to the final estimate; while the continuous curve for SLL2 shows the expected smaller increments.
The whole point and purpose of the invention is demonstrated here: namely when the loops are active (and the signal to noise is high enough) it is impossible for the higher-accuracy SLL2 estimate to slip more than ±TS2/2 out of alignment with the lower accuracy SLL1 estimate which in turn cannot slip more than ±TS1/2 with respect to the lowest accuracy DLL estimate. Acquisition is complete on a step at around 50 counts or 1 s. The simulation also monitors the tracking of the third carrier tracking loop which here is a 2nd order PLL. An input true carrier phase of φ=30 deg was adopted arbitrarily for this example. The continuous track on the lower graph of FIG. 13 is the phase estimate and shows the characteristic overshoot of a under-damped second order loop. The dotted and dashed curves on the lower graph show the dynamic response of the gate widths TDC and TD1—opening out when there is a perceived need for rapid acquisition and then settling down to lower levels TS1 and TS2 respectively in due time.
Similar results with additive electrical noise actually present are shown in example from FIG. 14. The acquisition time is accordingly a random variable. It can take longer; or it can be shorter. The quasi-random nature of the acquisition process is evident. Yet there is a definite acquisition.
FIG. 15 shows the relative noise levels in steady measurements. The widely fluctuating dotted curve is the DLL estimate. The broken curve is the SLL1 estimate. The continuous curve is the joint optimal linear estimate computed as described. The much lower timing error in the optimal estimate is evident.
The advantage of some embodiments of the present invention over the prior art may include the following: the method can realise the potential accuracy of MBOC Discounting loop settling time (common to all systems) the correct estimate is essentially instantaneous. The present invention avoids locking on a wrong peak (false node), provided uncritical requirements on input carrier to noise density ratio and loop bandwidth are met, since there is no multi-peaked one-dimensional correlation function in the first place. More specifically, while the DLL estimate {circumflex over (τ)} must converge on the true delay, the two SLL estimates {circumflex over (τ)}*1 and {circumflex over (τ)}*2 may converge on arbitrary offsets from this true delay and only instantaneous arithmetic corrections according to Eqs. 35 need be implemented, without loss of optimality. Equivalently the more complicated routines of Esq. 36 allows for arithmetic corrections without need for re-setting the corresponding correlations. The receiver is therefore fail safe, in the sense that after loop convergence the highest quality estimate is immediately and continuously available thereafter. This is a unique feature to the present invention It is also insensitive to non-linear amplitude/frequency conversion that may be present in the transmission chain.
The described embodiments of the invention are only examples of how the invention may be implemented. Modifications, variations and changes to the described embodiments will occur to those having appropriate skills and knowledge. These modifications, variations and changes may be made without departure from the scope of the invention defined in the claims and its equivalents.

## Claims

1. A receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which are different to the code rate, the receiver comprising a processor arranged to:
generate a first estimate of delay based on the code modulation only;
generate a second estimate of delay based on the first component of the sub-carrier modulation only; and
generate a third estimate of delay based on the second component of the sub-carrier modulation only; and
determine a further delay estimate from the first, second and third delay estimates; and
wherein the rate of the second component is higher than the rate of the first component and the processor is arranged in determining the further delay estimate, to recalculate the second estimate by an integer number of half cycles at the lower sub-carrier frequency to bring it towards the first estimate, and to recalculate the third estimate by an integer number of half cycles at the higher sub-carrier frequency to bring it towards the second estimate.

2. A receiver according to claim 1 wherein the processor is arranged to make a correction to at least one of the second and third estimates of delay to correct for phase distortion.

3. A receiver according to claim 2 wherein the correction is a non-integer multiple of the sub-chip width.

4. A receiver according to claim 1 wherein a control means is arranged to determine a combined estimate of delay from the third delay estimate and the further delay estimate.

5. A receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which are different to the code rate, the receiver comprising a processor arranged to:
generate a first estimate of delay based on the code modulation only;
generate a second estimate of delay based on the first component of the sub-carrier modulation only; and
generate a third estimate of delay based on the second component of the sub-carrier modulation only; and
determine a further delay estimate from the first, second and third delay estimates; and
wherein the processor is arranged in determining the further delay estimate, to calculate a first delay difference as the difference between the first and second estimates rounded to an integer number of first sub-carrier half cycles, and a second delay difference as the difference between the second and third estimates rounded to an integer number of second sub-carrier half cycles.

6. A receiver according to claim 5 wherein the processor is arranged, in determining the further delay estimate, to add the first delay difference to the second estimate of delay and the second delay difference to the third estimate.

7. A receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which are different to the code rate, the receiver comprising a processor arranged to:
generate a first estimate of delay based on the code modulation only
generate a second estimate of delay based on the first component of the sub-carrier modulation only; and
generate a third estimate of delay based on the second component of the sub-carrier modulation only; and
determine a further delay estimate from the first, second and third delay estimates; and
wherein the processor is arranged to update the first and second estimates iteratively and to calculate the first delay difference and add it to the second estimate repeatedly; and to update the second and third estimates iteratively and to calculate the second delay difference and add it to the third estimate repeatedly.

8. A receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which are different to the code rate, the receiver comprising a processor arranged to:
generate a first estimate of delay based on the code modulation only;
generate a second estimate of delay based on the first component of the sub-carrier modulation only; and
generate a third estimate of delay based on the second component of the sub-carrier modulation only; and
determine a further delay estimate from the first, second and third delay estimates; and
wherein the processor is arranged to update the first and second estimates iteratively until they converge towards respective final values, to update the second and third estimates iteratively until they converge towards respective final values, and to calculate the further delay estimate from the final values.

9. A receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which are different to the code rate, the receiver comprising a processor arranged to:
generate a first estimate of delay based on the code modulation only;
generate a second estimate of delay based on the first component of the sub-carrier modulation only; and
generate a third estimate of delay based on the second component of the sub-carrier modulation only; and
determine a further delay estimate from the first, second and third delay estimates;

wherein the processor includes:
a reference code signal generator arranged to generate at least one reference code signal using the first estimate of delay;
a reference lower frequency sub-carrier signal generator arranged to generate at least one lower frequency reference sub-carrier signal using the second estimate of delay; and
a reference higher frequency sub-carrier signal generator arranged to generate at least one higher frequency reference sub-carrier signal using the third estimate of delay; and
a correlation generator arranged to generate correlations based on the reference signals and at least one component of the received signal;

wherein
the at least one lower frequency reference sub-carrier signal includes an early reference lower frequency sub-carrier signal and a late reference lower frequency sub-carrier signal separated by a gate width time difference; and at least one higher frequency reference sub-carrier signal includes an early reference higher frequency sub-carrier signal and a late reference higher frequency sub-carrier signal separated by a gate width time difference wherein the gate width time differences are variable;
the processor being arranged to vary the gate width time difference as the trial sub-carrier delay is updated;
wherein the processor is arranged in determining the further delay estimate, to calculate a first delay difference as the difference between the first and second estimates rounded to an integer number of first sub-carrier half cycles, and a second delay difference as the difference between the second and third estimates rounded to an integer number of second sub-carrier half cycles, and

the processor is arranged to detect a slip condition in the updating of one of the trial sub-carrier delays corresponding to a change in the estimated value of the associated integral number, and to increase the gate width time difference in response to the slip condition.

10. A receiver according to claim 9 wherein the processor is arranged to use the correlations to generate error estimations for the delay estimates, and to update the delay estimates based on the error estimations.

11. A receiver according to claim 9 wherein the at least one reference code signal includes an early reference code signal and a late reference code signal separated by a gate width time difference.

12. A receiver for receiving a navigation signal comprising a carrier modulated by a code modulation function of a given code rate and further modulated by a composite sub-carrier modulation function having first and second components with two different rates both of which are different to the code rate, the receiver comprising a processor arranged to:
generate a first estimate of delay based on the code modulation only;
generate a second estimate of delay based on the first component of the sub-carrier modulation only; and
generate a third estimate of delay based on the second component of the sub-carrier modulation only; and
determine a further delay estimate from the first, second and third delay estimates;

wherein the processor includes:
a reference code signal generator arranged to generate at least one reference code signal using the first estimate of delay;
a reference lower frequency sub-carrier signal generator arranged to generate at least one lower frequency reference sub-carrier signal using the second estimate of delay; and
a reference higher frequency sub-carrier signal generator arranged to generate at least one higher frequency reference sub-carrier signal using the third estimate of delay; and
a correlation generator arranged to generate correlations based on the reference signals and at least one component of the received signal; and

wherein the correlation means is arranged to generate a plurality of correlations that vary in different ways as the trial delay approaches an actual delay and to combine them to determine the error estimation.

13. A receiver according to claim 12 wherein the processor is arranged to combine the correlations in a manner which varies as the delay approaches the actual delay to determine the error estimations.