# Patent

## Title
Semiconductor device including latch circuit

## Abstract

The latch circuit includes a transistor whose channel region is formed with an oxide semiconductor (OS). Data is held in a node that is electrically connected to an output terminal and one of a source and a drain of the transistor and brought into a floating state when the transistor is turned off. Note that the oxide semiconductor has a band gap wider than silicon and an intrinsic carrier density lower than silicon. By using such an oxide semiconductor for the channel region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a latch circuit and a semiconductor device including the latch circuit. Note that the semiconductor device in this specification indicates any device that can operate by utilizing semiconductor characteristics.
2. Description of the Related Art
A latch circuit is a circuit that can temporarily hold a specific logic state (hereinafter also referred to as data), and is used in a variety of semiconductor devices. For example, a latch circuit is used as a circuit that temporarily hold data when the data is written or read to/from a storage circuit provided in a semiconductor device.
The latch circuit can be constituted by logic gates. For example, there are an SR latch circuit illustrated in FIG. 26A, an /SR latch circuit illustrated in FIG. 26C, a JK latch circuit illustrated in FIG. 26E, a gated SR latch circuit illustrated in FIG. 26G, and a D latch circuit illustrated in FIG. 26I. FIG. 26B shows the truth table of the SR latch circuit in FIG. 26A. FIG. 26D shows the truth table of the /SR latch circuit in FIG. 26C. FIG. 26F shows the truth table of the JK latch circuit in FIG. 26E. FIG. 26H shows the truth table of the gated SR latch circuit in FIG. 26G. FIG. 26J shows the truth table of the D latch circuit in FIG. 26I.
In the latch circuit constituted by logic gates as illustrated in FIGS. 26A to 26J, stored data is lost when power supply is stopped. In addition, a large number of semiconductor elements (such as transistors) are required to form the latch circuit.
Further, a latch circuit can be constituted by a non-volatile ferroelectric element (see Patent Document 1). In that case, data can be held in the ferroelectric element even when power supply is stopped. However, when the ferroelectric element is used, deterioration of data retention due to the increase in the number of rewrite operations tends to be obvious.
REFERENCE


    Patent Document 1: Japanese Published Patent Application No. 2004-212477


SUMMARY OF THE INVENTION
In view of the above, an object of one embodiment of the present invention is to provide a novel latch circuit. Specifically, an object of one embodiment of the present invention is to provide a latch circuit that can retain data even when power supply is stopped. Another object of one embodiment of the present invention is to provide a latch circuit including a smaller number of semiconductor elements than a conventional latch circuit. Another object of one embodiment of the present invention is to provide a latch circuit in which deterioration of data retention is suppressed. Note that one embodiment of the present invention aims to achieve at least one of the above objects.
The main point of one embodiment of the present invention lies in that a latch circuit is formed using a transistor whose channel region is formed with an oxide semiconductor. Note that the oxide semiconductor has a band gap wider than silicon and an intrinsic carrier density lower than silicon. By using such an oxide semiconductor for the channel region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized.
Specifically, one embodiment of the present invention is a latch circuit illustrated in FIG. 1. The latch circuit in FIG. 1 includes a transistor 10 whose channel region is formed with an oxide semiconductor (OS). Data is held in a node 11 that is electrically connected to an output terminal (terminal Q) and one of a source and a drain of the transistor 10 and brought into a floating state when the transistor 10 is turned off.
In addition, the oxide semiconductor is preferably an i-type (intrinsic) or substantially intrinsic oxide semiconductor (purified OS) in which the concentration of impurities such as moisture or hydrogen that might serve as electron donors (donors) has been reduced. Therefore, the off-state current (leakage current) of the transistor whose channel region is formed with an oxide semiconductor can be further reduced. Specifically, the oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less, preferably 5×1018 (atoms/cm3) or less, further preferably 5×1017 (atoms/cm3) or less when the hydrogen concentration is measured by secondary ion mass spectrometry (SIMS). The carrier density of the oxide semiconductor measured by Hall effect measurement is less than 1×1014/cm3, preferably less than 1×1012/cm3, further preferably less than 1×1011/cm3. The band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, further preferably 3 eV or more.
An alkali metal and an alkaline earth metal are adverse impurities for the oxide semiconductor and are preferably contained as little as possible. When an insulating layer in contact with the oxide semiconductor is an oxide, an alkali metal, in particular, sodium (Na) diffuses into the oxide and becomes Na+. In addition, sodium cuts a bond between metal and oxygen or enters the bond in the oxide semiconductor, which causes deterioration of transistor characteristics (e.g., the transistor becomes normally on (the threshold voltage shifts negatively) or the mobility is decreased). Further, this also causes variation in the characteristics. Such a problem is significant especially in the case where the hydrogen concentration in the oxide semiconductor is sufficiently low. Therefore, it is strongly required that the concentration of an alkali metal is reduced in the case where the hydrogen concentration in the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3), particularly lower than or equal to 5×1018 (atoms/cm3). Specifically, the oxide semiconductor needs to have the following lowest concentrations of sodium (Na), lithium (Li), and potassium (K), measured by secondary ion mass spectrometry: the sodium concentration is 5×1016 (atoms/cm3) or less, preferably 1×1016 (atoms/cm3) or less, further preferably 1×1015 (atoms/cm3) or less; the lithium concentration is 5×1015 (atoms/cm3) or less, preferably 1×1015 (atoms/cm3) or less; and the potassium concentration is 5×1015 (atoms/cm3) or less, preferably 1×1015 (atoms/cm3) or less.
Here, analysis of the hydrogen concentration by secondary ion mass spectrometry (SIMS) is mentioned. It is known that it is difficult to accurately obtain data in the proximity of a surface of a sample or in the proximity of an interface between stacked films formed using different materials by the SIMS analysis in principle. Thus, in the case where distributions of the hydrogen concentrations of the film in the thickness direction are analyzed by SIMS, an average value in a region of the film where the value is not greatly changed and almost the same value can be obtained is employed as the hydrogen concentration. Further, in the case where the thickness of the film to be measured is small, a region where almost the same value can be obtained cannot be found in some cases because of the influence of the hydrogen concentration of the films adjacent to each other. In that case, the maximum value or the minimum value of the hydrogen concentration of a region where the films are provided is employed as the hydrogen concentration of the film. Furthermore, in the case where a mountain-shaped peak having the maximum value and a valley-shaped peak having the minimum value do not exist in the region where the films are provided, the value of the inflection point is employed as the hydrogen concentration.
Examples of the oxide semiconductor are an In—Sn—Ga—Zn—O-based oxide semiconductor which is an oxide of four metal elements; an In—Ga—Zn—O-based oxide semiconductor, an In—Sn—Zn—O-based oxide semiconductor, an In—Al—Zn—O-based oxide semiconductor, a Sn—Ga—Zn—O-based oxide semiconductor, an Al—Ga—Zn—O-based oxide semiconductor, and a Sn—Al—Zn—O-based oxide semiconductor which are oxides of three metal elements; an In—Zn—O-based oxide semiconductor, a Sn—Zn—O-based oxide semiconductor, an Al—Zn—O-based oxide semiconductor, a Zn—Mg—O-based oxide semiconductor, a Sn—Mg—O-based oxide semiconductor, an In—Mg—O-based oxide semiconductor, and an In—Ga—O-based oxide semiconductor which are oxides of two metal elements; and an In—O-based oxide semiconductor, a Sn—O-based oxide semiconductor, and a Zn—O-based oxide semiconductor. Note that in this specification, for example, an In—Sn—Ga—Zn—O-based oxide semiconductor means a metal oxide containing indium (In), tin (Sn), gallium (Ga), and zinc (Zn). There is no particular limitation on the composition ratio. The above oxide semiconductor may contain silicon.
Further, in this specification, an oxide semiconductor can be represented by the chemical formula, InMO3(ZnO)m (m>0), for example. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co.
In the latch circuit according to one embodiment of the present invention, data is stored in a node that is electrically connected to one of a source and a drain of a transistor whose channel region is formed with an oxide semiconductor and is brought into a floating state when the transistor is turned off. Note that the off-state current (leakage current) of the transistor is extremely low. Therefore, when the potential of the node is set to a specific value and then the transistor is turned off, the potential can be kept constant or almost constant. Consequently, data can be accurately retained in the latch circuit. Furthermore, the transistor is kept off even when supply of power to the latch circuit is stopped. As a result, data can be retained in the latch circuit even when power supply is stopped.
In the latch circuit according to one embodiment of the present invention, data is retained using the transistor whose channel region is formed with an oxide semiconductor; therefore, the number of transistors can be reduced as compared to that in a latch circuit constituted by a combination of logic gates.
In addition, the latch circuit according to one embodiment of the present invention is formed without using a ferroelectric element, so that deterioration of data retention can be suppressed.



BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings:
FIG. 1 illustrates a latch circuit according to one embodiment of the present invention;
FIGS. 2A to 2H illustrate an example of a method for forming a transistor;
FIGS. 3A to 3C are diagrams for explaining a method for measuring off-state current of a transistor;
FIGS. 4A and 4B show characteristics of transistors;
FIG. 5 shows characteristics of transistors;
FIG. 6 shows characteristics of transistors;
FIG. 7 shows characteristics of transistors;
FIG. 8 shows characteristics of transistors;
FIG. 9A is a circuit diagram illustrating a specific example of an SR latch circuit, and FIG. 9B shows the truth table of the SR latch circuit;
FIG. 10 shows Vg-Id characteristics of three kinds of transistors;
FIG. 11A shows potentials input to a terminal S and a terminal R and FIG. 11B shows potentials output from a terminal Q in the circuit illustrated in FIG. 9A;
FIG. 12A is a circuit diagram illustrating a specific example of an SR latch circuit, and FIG. 12B shows the truth table of the SR latch circuit;
FIG. 13A shows potentials input to a terminal S and a terminal R and FIG. 13B shows potentials output from a terminal Q in the circuit illustrated in FIG. 12A;
FIG. 14A is a circuit diagram illustrating a specific example of an /SR latch circuit, and FIG. 14B shows the truth table of the /SR latch circuit;
FIG. 15A shows potentials input to a terminal IS and a terminal /R and FIG. 15B shows potentials output from a terminal Q in the circuit illustrated in FIG. 14A;
FIG. 16A is a circuit diagram illustrating a specific example of an /SR latch circuit, and FIG. 16B shows the truth table of the /SR latch circuit;
FIG. 17A shows potentials input to a terminal /S and a terminal /R and FIG. 17B shows potentials output from a terminal Q in the circuit illustrated in FIG. 16A;
FIG. 18A is a circuit diagram illustrating a specific example of a JK latch circuit, and FIG. 18B shows the truth table of the JK latch circuit;
FIG. 19A shows potentials input to a terminal J, a terminal K, and a terminal CK and FIG. 19B shows potentials output from a terminal Q in the circuit illustrated in FIG. 18A;
FIG. 20A is a circuit diagram illustrating a specific example of a gated SR latch circuit, and FIG. 20B shows the truth table of the gated SR latch circuit;
FIG. 21A shows potentials input to a terminal S, a terminal R, and a terminal E and FIG. 21B shows potentials output from a terminal Q in the circuit illustrated in FIG. 20A;
FIG. 22A is a circuit diagram illustrating a specific example of a gated SR latch circuit, and FIG. 22B shows the truth table of the gated SR latch circuit;
FIG. 23A shows potentials input to a terminal S, a terminal R, and a terminal E and FIG. 23B shows potentials output from a terminal Q in the circuit illustrated in FIG. 22A;
FIG. 24A is a circuit diagram illustrating a specific example of a D latch circuit, and FIG. 24B shows the truth table of the D latch circuit;
FIG. 25A shows potentials input to a terminal D and a terminal E and FIG. 25B shows potentials output from a terminal Q in the circuit illustrated in FIG. 24A;
FIG. 26A illustrates a conventional SR latch circuit, FIG. 26B shows the truth table of the SR latch circuit, FIG. 26C illustrates a conventional /SR latch circuit, FIG. 26D shows the truth table of the /SR latch circuit, FIG. 26E illustrates a conventional JK latch circuit, FIG. 26F shows the truth table of the JK latch circuit, FIG. 26G illustrates a conventional gated SR latch circuit, FIG. 26H shows the truth table of the gated SR latch circuit, FIG. 26I illustrates a conventional D latch circuit, and FIG. 26J shows the truth table of the D latch circuit;
FIG. 27 illustrates a specific example of a transistor;
FIGS. 28A to 28H illustrate an example of specific steps for forming a transistor;
FIGS. 29A to 29G illustrate an example of specific steps for forming a transistor;
FIGS. 30A to 30D illustrate an example of specific steps for forming a transistor;
FIG. 31 illustrates a variation of a transistor;
FIGS. 32A and 32B each illustrate a variation of a transistor;
FIGS. 33A and 33B each illustrate a variation of a transistor;
FIGS. 34A and 34B each illustrate a variation of a transistor;
FIG. 35 illustrates a variation of a transistor;
FIG. 36 illustrates a variation of a transistor;
FIGS. 37A to 37C illustrate a variation of steps for forming an oxide semiconductor layer;
FIG. 38A illustrates a structural example of a semiconductor device, FIG. 38B illustrates a specific example of a memory cell, and FIG. 38C illustrates another specific example of a memory cell;
FIGS. 39A to 39E each illustrate a crystal structure of an oxide material;
FIGS. 40A to 40C illustrate a crystal structure of an oxide material;
FIGS. 41A to 41C illustrate a crystal structure of an oxide material;
FIG. 42 shows gate voltage dependence of mobility obtained by calculation;
FIGS. 43A to 43C each show gate voltage dependence of drain current and mobility, obtained by calculation;
FIGS. 44A to 44C each show gate voltage dependence of drain current and mobility, obtained by calculation;
FIGS. 45A to 45C each show gate voltage dependence of drain current and mobility, obtained by calculation;
FIGS. 46A and 46B each illustrate a cross-sectional structure of a transistor used in calculation;
FIGS. 47A and 47B are a top view and a cross-sectional view of a transistor which is one embodiment of the present invention;
FIGS. 48A and 48B are a top view and a cross-sectional view of a transistor corresponding to Samples 1 to 6;
FIGS. 49A to 49C show Vgs-Ids characteristics and field-effect mobility of transistors of Samples 3 and 4;
FIGS. 50A and 50B show Vgs-Ids characteristics and field-effect mobility of a transistor of Sample 1 before and after BT tests;
FIGS. 51A and 51B show Vgs-Ids characteristics and field-effect mobility of a transistor of Sample 4 before and after BT tests;
FIG. 52 shows Vgs-Ids characteristics and field-effect mobility of a transistor of Sample 4 depending on measurement temperatures;
FIGS. 53A and 53B show relations between substrate temperature and threshold voltage or field-effect mobility of a transistor of Sample 4;
FIG. 54 shows XRD spectra of In—Sn—Zn—O films; and
FIG. 55 shows off-state current of a transistor including an In—Sn—Zn—O film.



DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be hereinafter described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the description below, and it is easily understood by those skilled in the art that a variety of changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be limited to the descriptions of the embodiments below.
<Off-State Current of Transistor Whose Channel Region is Formed with Oxide Semiconductor>
First, the results of measuring the off-state current (leakage current) of a transistor whose channel region is formed with an oxide semiconductor will be described.
First, a method for forming a transistor used for the measurement will be described with reference to FIGS. 2A to 2H.
First, a base layer 51 formed of a stack of a 100-nm-thick silicon nitride layer and a 150-nm-thick silicon oxynitride layer was formed by CVD over a glass substrate 50 (see FIG. 2A).
Next, a 100-nm-thick tungsten layer was formed by sputtering over the base layer 51. Then, the tungsten layer was selectively etched by photolithography, so that a gate layer 52 was formed (see FIG. 2B).
Next, a gate insulating layer 53 formed of a 100-nm-thick silicon oxynitride layer was formed by CVD over the base layer 51 and the gate layer 52 (see FIG. 2C).
Then, a 25-nm-thick oxide semiconductor layer was formed by sputtering over the gate insulating layer 53. A metal oxide target having a composition ratio of In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] was used for forming the oxide semiconductor layer. In addition, the oxide semiconductor layer was formed under the following conditions: the substrate temperature was 200° C., the internal pressure of the chamber was 0.6 Pa, the direct-current power was 5 kW, and the atmosphere was a mixed atmosphere of oxygen and argon (the oxygen flow rate was 50 sccm and the argon flow rate was 50 sccm). Then, the oxide semiconductor layer was selectively etched by photolithography, so that an oxide semiconductor layer 54 was formed (see FIG. 2D).
Subsequently, heat treatment was performed at 450° C. for one hour in a mixed atmosphere of nitrogen and oxygen (the percentage of nitrogen is 80% and that of oxygen is 20%).
Then, the gate insulating layer 53 was selectively etched by photolithography (not illustrated). Note that this etching is a step for forming a contact hole for connecting the gate layer 52 and a conductive layer to be formed.
Next, a stack of a 100-nm-thick titanium layer, a 200-nm-thick aluminum layer, and a 100-nm-thick titanium layer was formed by sputtering over the gate insulating layer 53 and the oxide semiconductor layer 54. Then, the stack was selectively etched by photolithography, so that a source layer 55a and a drain layer 55b were formed (see FIG. 2E).
Then, heat treatment was performed at 300° C. for one hour in a nitrogen atmosphere.
Next, a protective insulating layer 56 formed of a 300-nm-thick silicon oxide layer was formed over the gate insulating layer 53, the oxide semiconductor layer 54, the source layer 55a, and the drain layer 55b. Then, the protective insulating layer 56 was selectively etched by photolithography (see FIG. 2F). Note that this etching is a step for forming a contact hole for connecting the gate layer, the source layer, and the drain layer and the conductive layer to be formed.
Next, a 1.5-μm-thick acrylic layer was applied over the protective insulating layer 56 and selectively exposed to light, so that a planarization insulating layer 57 was formed (see FIG. 2G). Then, the planarization insulating layer 57 formed of the acrylic layer was baked with heat treatment at 250° C. for one hour in a nitrogen atmosphere.
Subsequently, a 200-nm-thick titanium layer was formed by sputtering over the planarization insulating layer 57. Then, the titanium layer was selectively etched by photolithography, thereby forming a conductive layer (not illustrated) connected to the gate layer 52, a conductive layer 58a connected to the source layer 55a, and a conductive layer 58b connected to the drain layer 55b (see FIG. 2H).
Next, heat treatment was performed at 250° C. for one hour in a nitrogen atmosphere.
Through the above steps, the transistor used for the measurement was formed.
Next, a method for calculating the value of off-state current by using a circuit for evaluating characteristics, used in the measurement, will be described below.
Current measurement using a circuit for evaluating characteristics will be described with reference to FIGS. 3A to 3C. FIGS. 3A to 3C are diagrams for explaining a circuit for evaluating characteristics.
First, a configuration of a circuit for evaluating characteristics is described with reference to FIG. 3A. FIG. 3A is a circuit diagram illustrating the configuration of the circuit for evaluating characteristics.
The circuit for evaluating characteristics illustrated in FIG. 3A includes a plurality of measurement systems 801. The plurality of measurement systems 801 are connected in parallel with each other. Here, eight measurement systems 801 are connected in parallel with each other. By using the plurality of measurement systems 801, a plurality of leakage currents can be measured at the same time.
The measurement system 801 includes a transistor 811, a transistor 812, a capacitor 813, a transistor 814, and a transistor 815.
The transistors 811, 812, 814, and 815 are n-channel field effect transistors.
A voltage V1 is input to one of a source and a drain of the transistor 811. A voltage Vext_a is input to a gate of the transistor 811. The transistor 811 is a transistor for injecting charge.
One of a source and a drain of the transistor 812 is connected to the other of the source and the drain of the transistor 811. A voltage V2 is input to the other of the source and the drain of the transistor 812. A voltage Vext_b is input to a gate of the transistor 812. The transistor 812 is a transistor for evaluating leakage current. Note that “leakage current” in this embodiment refers to a leakage current including an off-state current of the transistor.
One electrode of the capacitor 813 is connected to the other of the source and the drain of the transistor 811. The voltage V2 is input to the other electrode of the capacitor 813. Here, the voltage V2 is 0 V.
A voltage V3 is input to one of a source and a drain of the transistor 814. A gate of the transistor 814 is connected to the other of the source and the drain of the transistor 811. Note that a portion where the gate of the transistor 814, the other of the source and the drain of the transistor 811, the one of the source and the drain of the transistor 812, and the one electrode of the capacitor 813 are connected to each other is referred to as a node A. Here, the voltage V3 is 5 V.
One of a source and a drain of the transistor 815 is connected to the other of the source and the drain of the transistor 814. A voltage V4 is input to the other of the source and the drain of the transistor 815. A voltage Vext_c is input to a gate of the transistor 815. Here, the voltage Vext_c is 0.5 V.
The measurement system 801 outputs a voltage at a portion where the other of the source and the drain of the transistor 814 is connected to the one of the source and the drain of the transistor 815, as an output voltage Vout.
Here, as the transistor 811, a transistor that is formed by the formation method described with reference to FIGS. 2A to 2H and has a channel length L of 10 μm and a channel width W of 10 μm is used.
As the transistors 814 and 815, a transistor that is formed by the formation method described with reference to FIGS. 2A to 2H and has a channel length L of 3 μm and a channel width W of 100 μm is used.
At least the transistor 812 includes a 1-μm-wide offset region in which the gate layer 52 does not overlap with the source layer 55a and the drain layer 55b as illustrated in FIG. 3B. By providing the offset region, parasitic capacitance can be reduced. Further, as the transistor 812, six samples (SMP) of transistors having different channel lengths L and channel widths W are used (see Table 1).










TABLE 1







L [μm]
W [μm]




















SMP1
1.5
1 × 105



SMP2
3
1 × 105



SMP3
10
1 × 105



SMP4
1.5
1 × 106



SMP5
3
1 × 106



SMP6
10
1 × 106










The transistor for injecting charge and the transistor for evaluating leakage current are separately provided as illustrated in FIG. 3A, so that the transistor for evaluating leakage current can be always kept off while electric charge is injected.
In addition, the transistor for injecting charge and the transistor for evaluating leakage current are separately provided, whereby each transistor can have an appropriate size. When the channel width W of the transistor for evaluating leakage current is made larger than that of the transistor for injecting charge, leakage current components of the circuit for evaluating characteristics other than the leakage current of the transistor for evaluating leakage current can be made relatively small. As a result, the leakage current of the transistor for evaluating leakage current can be measured with high accuracy. In addition, since the transistor for evaluating leakage current does not need to be turned on at the time of charge injection, the measurement is not adversely affected by variation in the voltage of the node A, which is caused when part of electric charge in the channel region flows into the node A.
Next, a method for measuring a leakage current of the circuit for evaluating characteristics illustrated in FIG. 3A will be described with reference to FIG. 3C. FIG. 3C is a timing chart for explaining the method for measuring a leakage current with use of the circuit for evaluating characteristics illustrated in FIG. 3A.
In the method for measuring the leakage current with the circuit for evaluating characteristics illustrated in FIG. 3A, a write period and a hold period are provided. The operation in each period is described below.
In the write period, a voltage VL (−3 V) with which the transistor 812 is turned off is input as the voltage Vext_b. Moreover, a write voltage Vw is input as the voltage V1, and then, a voltage VH (5 V) with which the transistor 811 is turned on is input as the voltage Vext_a for a given period. Thus, electric charge is accumulated in the node A, and the voltage of the node A becomes equivalent to the write voltage Vw. Then, the voltage VL with which the transistor 811 is turned off is input as the voltage Vext_a. After that, a voltage VSS (0 V) is input as the voltage V1.
In the hold period, the amount of change in the voltage of the node A, caused by change in the amount of the electric charge held in the node A, is measured. From the amount of change in the voltage, the value of the current flowing between the source and the drain of the transistor 812 can be calculated. In the above manner, electric charge can be accumulated in the node A, and the amount of change in the voltage of the node A can be measured.
Accumulation of electric charge in the node A and measurement of the amount of change in the voltage of the node A (also referred to as an accumulation and measurement operation) are repeatedly performed. First, a first accumulation and measurement operation is repeated 15 times. In the first accumulation and measurement operation, a voltage of 5 V is input as the write voltage Vw in the write period and retained for 1 hour in the hold period. Next, a second accumulation and measurement operation is repeated twice. In the second accumulation and measurement operation, a voltage of 3.5 V is input as the write voltage Vw in the write period and retained for 50 hours in the hold period. Next, a third accumulation and measurement operation is performed once. In the third accumulation and measurement operation, a voltage of 4.5 V is input as the write voltage Vw in the write period and retained for 10 hours in the hold period. By repeating the accumulation and measurement operation, the measured current value can be confirmed to be the value in the steady state. In other words, the transient current (a current component that decreases over time after the measurement starts) can be removed from a current IA flowing through the node A. Consequently, the leakage current can be measured with higher accuracy.
In general, a voltage VA of the node A is expressed as a function of the output voltage Vout by Formula 1.

VA=F(Vout)  [Formula 1]

Electric charge QA of the node A is expressed by Formula 2, using the voltage VA of the node A, capacitance CA connected to the node A, and a constant (const). Here, the capacitance CA connected to the node A is the sum of the capacitance of the capacitor 813 and a capacitance other than that of the capacitor 813.

QA=CAVA+const  [Formula 2]

Since the current IA of the node A is the time differential of electric charge flowing into the node A (or electric charge flowing from the node A), the current IA of the node A is expressed by Formula 3.




  
    
      
        
          
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            A
          
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              t
            
          
        
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                C
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              Δ
            
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              F
              ⁡
              
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                Vout
                )
              
            
          
          
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            t
          
        
      
    
    
      
        [
        
          Formula
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          3
        
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Here, Δt is about 54000 sec. As above, the current IA of the node A, which is the leakage current, can be calculated with the capacitance CA connected to the node A and the output voltage Vout, so that the leakage current of the circuit for evaluating characteristics can be obtained.
Next, the results of measuring the output voltage by the measurement method using the above circuit for evaluating characteristics and the value of the leakage current of the circuit for evaluating characteristics, which is calculated from the measurement results, will be described with reference to FIGS. 4A and 4B.
As an example, FIG. 4A shows the relation between the elapsed time Time of the above measurement (the first accumulation and measurement operation) of the transistors SMP4, SMP5, and SMP6 and the output voltage Vout. FIG. 4B shows the relation between the elapsed time Time of the above measurement and the current IA calculated by the measurement. It is found that the output voltage Vout varies after the measurement starts and it takes 10 hours or longer to reach a steady state.
FIG. 5 shows the relation between the voltage of the node A in SMP1 to SMP6 and the leakage current estimated by the above measurement. In SMP4 in FIG. 5, for example, when the voltage of the node A is 3.0 V, the leakage current (per unit channel width (1 μm) here) is 28 yA/μm. Since the leakage current includes the off-state current of the transistor 812, the off-state current of the transistor 812 can be considered to be 28 yA/μm or less.
FIG. 6, FIG. 7, and FIG. 8 each show the relation between the voltage of the node A in SMP1 to SMP6 at 85° C., 125° C., and 150° C. and the leakage current estimated by the above measurement. As shown in FIGS. 6 to 8, the leakage current is 100 zA/μm or less even at 150° C.
As described above, the leakage current is sufficiently low in the circuit for evaluating characteristics, including the transistor whose channel region is formed with an oxide semiconductor, which means that the off-state current of the transistor is sufficiently low. In addition, the off-state current of the transistor is sufficiently low even when the temperature rises.
<Latch Circuit Disclosed in this Specification>
In the latch circuit disclosed in this specification, data is stored in a node to which one of a source and a drain of a transistor whose channel region is formed with an oxide semiconductor is electrically connected and which is brought into a floating state when the transistor is turned off. Therefore, when the potential of the node is set to a specific value and then the transistor is turned off, the potential can be kept constant or almost constant. Consequently, data can be accurately retained in the latch circuit. Furthermore, the transistor is kept off even when supply of power to the latch circuit is stopped. As a result, data can be retained in the latch circuit even when power supply is stopped. In addition, the latch circuit is formed without using a ferroelectric element, so that deterioration of data retention can be suppressed.
Specific Example
Specific examples of the latch circuit will be described with reference to FIGS. 9A and 9B, FIG. 10, FIGS. 11A and 11B, FIGS. 12A and 12B, FIGS. 13A and 13B, FIGS. 14A and 14B, FIGS. 15A and 15B, FIGS. 16A and 16B, FIGS. 17A and 17B, FIGS. 18A and 18B, FIGS. 19A and 19B, FIGS. 20A and 20B, FIGS. 21A and 21B, FIGS. 22A and 22B, FIGS. 23A and 23B, FIGS. 24A and 24B, and FIGS. 25A and 25B.
First Specific Example of SR Latch Circuit
FIG. 9A is a circuit diagram illustrating a specific example of an SR latch circuit. The SR latch circuit in FIG. 9A includes an inverter 20, a transistor 21, and a transistor 22. An input terminal of the inverter 20 is electrically connected to a reset terminal (a first input terminal of the SR latch circuit in FIG. 9A, hereinafter also referred to as a terminal R). A gate of the transistor 21 is electrically connected to the terminal R. One of a source and a drain of the transistor 21 is electrically connected to a set terminal (a second input terminal of the SR latch circuit in FIG. 9A, hereinafter also referred to as a terminal S). The other of the source and the drain of the transistor 21 is electrically connected to a terminal Q (an output terminal of the SR latch circuit in FIG. 9A). A gate of the transistor 22 is electrically connected to the terminal S. One of a source and a drain of the transistor 22 is electrically connected to an output terminal of the inverter 20. The other of the source and the drain of the transistor 22 is electrically connected to the terminal Q. Note that each of the transistors 21 and 22 is a transistor whose channel region is formed with an oxide semiconductor (OS). In the latch circuit, data is held in a node where the other of the source and the drain of the transistor 21, the other of the source and the drain of the transistor 22, and the terminal Q are electrically connected to each other. FIG. 9B shows the truth table of the SR latch circuit.
Here, the results of evaluating whether the circuit in FIG. 9A can operate as an SR latch circuit are shown. For the calculation, output signals of the terminal Q when three kinds of transistors having different Vg-Id characteristics are used as the transistors 21 and 22 are calculated. FIG. 10 shows Vg-Id characteristics of the three kinds of transistors. Here, the three kinds of transistors having different Vg-Id characteristics are assumed to be a transistor whose channel region is formed with an oxide semiconductor and which has a threshold voltage of 0.6 V (OS_Vth=0.6 V), a transistor whose channel region is formed with an oxide semiconductor and which has a threshold voltage of 1.6 V (OS_Vth=1.6 V), and a transistor whose channel region is formed with silicon (Si).
FIG. 11A shows potentials input to the terminal S and the terminal R in a given period. Note that in FIG. 11A, a voltage of 5 V corresponds to a logic “1” and a voltage of 0 V corresponds to a logic “0”. FIG. 11B shows output potentials of the terminal Q in the given period. Note that FIG. 11B shows output potentials of the terminal Q in the cases where the above three kinds of transistors are used as the transistors 21 and 22.
In the cases of using the transistors having Vg-Id characteristics which are assumed to be those of transistors whose channel region is formed with an oxide semiconductor, it is confirmed from FIG. 11B that the circuit in FIG. 9A can operate in accordance with the truth table of the SR latch circuit illustrated in FIG. 9B. On the other hand, in the case of using the transistor having Vg-Id characteristics which are assumed to be those of a transistor whose channel region is formed with silicon, it is found to be difficult to retain the logic “0”. Specifically, it is confirmed that a potential around 0 V cannot be retained in a period between 2×10−4 s and 3×10−4 s and a period between 6×10−4 s and 7×10−4 is n FIG. 11B.
These results prove that the circuit in FIG. 9A can be used as an SR latch circuit when a transistor with an extremely low off-state current, such as the transistor whose channel region is formed with an oxide semiconductor, is used as the transistors 21 and 22.
In addition, the circuit in FIG. 9A can realize an SR latch circuit with a smaller number of transistors than the SR latch circuit in FIG. 26A.
Second Specific Example of SR Latch Circuit
FIG. 12A is a circuit diagram illustrating a specific example of an SR latch circuit that is different from that in FIG. 9A. The SR latch circuit in FIG. 12A includes an OR gate 30 and a transistor 31. A first input terminal of the OR gate 30 is electrically connected to a terminal R (a first input terminal of the SR latch circuit in FIG. 12A). A second input terminal of the OR gate 30 is electrically connected to a terminal S (a second input terminal of the SR latch circuit in FIG. 12A). A gate of the transistor 31 is electrically connected to an output terminal of the OR gate 30. One of a source and a drain of the transistor 31 is electrically connected to the terminal S The other of the source and the drain of the transistor 31 is electrically connected to a terminal Q (an output terminal of the SR latch circuit in FIG. 12A). Note that the transistor 31 is a transistor whose channel region is formed with an oxide semiconductor (OS). In the latch circuit, data is held in a node where the other of the source and the drain of the transistor 31 and the terminal Q are electrically connected to each other. FIG. 12B shows the truth table of the SR latch circuit.
Here, the results of evaluating whether the circuit in FIG. 12A can operate as an SR latch circuit are shown. For the calculation, output signals of the terminal Q when the three kinds of transistors having different Vg-Id characteristics illustrated in FIG. 10 are used as the transistor 31 are calculated. Since the three kinds of transistors have been described, the above description is employed here.
FIG. 13A shows potentials input to the terminal S and the terminal R in a given period. Note that in FIG. 13A, a voltage of 5 V corresponds to a logic “1” and a voltage of 0 V corresponds to a logic “0”. FIG. 13B shows output potentials of the terminal Q in the given period. Note that FIG. 13B shows output potentials of the terminal Q in the cases where the above three kinds of transistors are used as the transistor 31.
As shown in FIG. 13B, the output potential of the terminal Q is drastically decreased when the logic “1” is held (at 4×10−4 s or 8×10−4 s) in all the cases. That is, FIG. 13B shows that it is difficult to store the logic “1” in all the cases. Note that in the case of using the transistor having Vg-Id characteristics which are assumed to be those of the transistor whose channel region is faulted with an oxide semiconductor and which has a threshold voltage of 1.6 V, the output potential of the terminal Q is kept at approximately 1 V even in a period of storing the logic “1”. It is therefore confirmed that the circuit in FIG. 12A has a possibility of operating as an SR latch circuit when the threshold for distinguishing between the logic “0” and the logic “1” is set to approximately 0.5 V and the transistor whose channel region is formed with the oxide semiconductor is used as the transistor 31.
These results prove that the circuit in FIG. 12A has a possibility of serving as an SR latch circuit when a transistor with an extremely low off-state current, such as the transistor whose channel region is formed with an oxide semiconductor, is used as the transistor 31.
In addition, the circuit in FIG. 12A has a possibility of realizing an SR latch circuit with a smaller number of transistors than the SR latch circuit in FIG. 26A.
First Specific Example of /SR Latch Circuit
FIG. 14A is a circuit diagram illustrating a specific example of an /SR latch circuit. The /SR latch circuit in FIG. 14A includes an inverter 40, an inverter 41, a transistor 42, and a transistor 43. An input terminal of the inverter 40 is electrically connected to a terminal /S (a first input terminal of the /SR latch circuit in FIG. 14A). An input terminal of the inverter 41 is electrically connected to a terminal /R (a second input terminal of the /SR latch circuit in FIG. 14A). A gate of the transistor 42 is electrically connected to an output terminal of the inverter 40. One of a source and a drain of the transistor 42 is electrically connected to the terminal /R. The other of the source and the drain of the transistor 42 is electrically connected to a terminal Q (an output terminal of the /SR latch circuit in FIG. 14A). A gate of the transistor 43 is electrically connected to an output terminal of the inverter 41. One of a source and a drain of the transistor 43 is electrically connected to the output terminal of the inverter 40 and the gate of the transistor 42. The other of the source and the drain of the transistor 43 is electrically connected to the terminal Q. Note that each of the transistors 42 and 43 is a transistor whose channel region is formed with an oxide semiconductor (OS). In the latch circuit, data is held in a node where the other of the source and the drain of the transistor 42, the other of the source and the drain of the transistor 43, and the terminal Q are electrically connected to each other. FIG. 14B shows the truth table of the /SR latch circuit.
Here, the results of evaluating whether the circuit in FIG. 14A can operate as an /SR latch circuit are shown. For the calculation, output signals of the terminal Q when the three kinds of transistors having different Vg-Id characteristics illustrated in FIG. 10 are used as the transistors 42 and 43 are calculated. Since the three kinds of transistors have been described, the above description is employed here.
FIG. 15A shows potentials input to the terminal /S and the terminal /R in a given period. Note that in FIG. 15A, a voltage of 5 V corresponds to a logic “1” and a voltage of 0 V corresponds to a logic “0”. FIG. 15B shows output potentials of the terminal Q in the given period. Note that FIG. 15B shows output potentials of the terminal Q in the cases where the above three kinds of transistors are used as the transistors 42 and 43.
In the cases of using the transistors having Vg-Id characteristics which are assumed to be those of transistors whose channel region is formed with an oxide semiconductor, it is confirmed from FIG. 15B that the circuit in FIG. 14A can operate in accordance with the truth table of the /SR latch circuit illustrated in FIG. 14B. On the other hand, in the case of using the transistor having Vg-Id characteristics which are assumed to be those of a transistor whose channel region is formed with silicon, it is found to be difficult to retain the logic “0”. Specifically, it is confirmed that a potential around 0 V cannot be retained in a period between 4×10−4 s and 5×10−4 s and a period between 8×10−4 s and 9×10−4 s in FIG. 15B.
These results prove that the circuit in FIG. 14A can be used as an /SR latch circuit when a transistor with an extremely low off-state current, such as the transistor whose channel region is formed with an oxide semiconductor, is used as the transistors 42 and 43.
In addition, the circuit in FIG. 14A can realize an /SR latch circuit with a smaller number of transistors than the /SR latch circuit in FIG. 26C.
Second Specific Example of /SR Latch Circuit
FIG. 16A is a circuit diagram illustrating a specific example of an /SR latch circuit. The /SR latch circuit in FIG. 16A includes a NAND gate 60 and a transistor 61. A first input terminal of the NAND gate 60 is electrically connected to a terminal /S (a first input terminal of the /SR latch circuit in FIG. 16A). A second input terminal of the NAND gate 60 is electrically connected to a terminal /R (a second input terminal of the /SR latch circuit in FIG. 16A). A gate of the transistor 61 is electrically connected to an output terminal of the NAND gate 60. One of a source and a drain of the transistor 61 is electrically connected to the terminal /R. The other of the source and the drain of the transistor 61 is electrically connected to a terminal Q (an output terminal of the /SR latch circuit in FIG. 16A). Note that the transistor 61 is a transistor whose channel region is formed with an oxide semiconductor (OS). In the latch circuit, data is held in a node where the other of the source and the drain of the transistor 61 and the terminal Q are electrically connected to each other. FIG. 16B shows the truth table of the /SR latch circuit.
Here, the results of evaluating whether the circuit in FIG. 16A can operate as an /SR latch circuit are shown. For the calculation, output signals of the terminal Q when the three kinds of transistors having different Vg-Id characteristics illustrated in FIG. 10 are used as the transistor 61 are calculated. Since the three kinds of transistors have been described, the above description is employed here.
FIG. 17A shows potentials input to the terminal /S and the terminal /R in a given period. Note that in FIG. 17A, a voltage of 5 V corresponds to a logic “1” and a voltage of 0 V corresponds to a logic “0”. FIG. 17B shows output potentials of the terminal Q in the given period. Note that FIG. 17B shows output potentials of the terminal Q in the cases where the above three kinds of transistors are used as the transistor 61.
In the cases of using the transistors having Vg-Id characteristics which are assumed to be those of transistors whose channel region is formed with an oxide semiconductor, it is confirmed from FIG. 17B that the circuit in FIG. 16A can operate in accordance with the truth table of the /SR latch circuit illustrated in FIG. 16B by setting the threshold for distinguishing between the logic “0” and the logic “1” to approximately 2V. On the other hand, in the case of using the transistor having Vg-Id characteristics which are assumed to be those of a transistor whose channel region is formed with silicon, it is found to be difficult to retain the logic “0”. Specifically, it is confirmed that the potential corresponding to the logic “0” cannot be retained in a period between 4×10−4 s and 5×10−4 s and a period between 8×10−4 s and 9×10−4 s in FIG. 17B.
These results prove that the circuit in FIG. 16A can be used as an /SR latch circuit when a transistor with an extremely low off-state current, such as the transistor whose channel region is formed with an oxide semiconductor, is used as the transistor 61.
In addition, the circuit in FIG. 16A can realize an /SR latch circuit with a smaller number of transistors than the /SR latch circuit in FIG. 26C.
Specific Example of JK Latch Circuit
FIG. 18A is a circuit diagram illustrating a specific example of a JK latch circuit. The JK latch circuit in FIG. 18A includes a NAND gate 70, a NAND gate 71, an inverter 72, an inverter 73, a transistor 74, a transistor 75, and an inverter 76. A first input terminal of the NAND gate 70 is electrically connected to a terminal CK (a first input terminal of the JK latch circuit in FIG. 18A). A second input terminal of the NAND gate 70 is electrically connected to a terminal J (a second input terminal of the JK latch circuit in FIG. 18A). A first input terminal of the NAND gate 71 is electrically connected to the terminal CK. A second input terminal of the NAND gate 71 is electrically connected to a terminal K (a third input terminal of the JK latch circuit in FIG. 18A). A third input terminal of the NAND gate 71 is electrically connected to a terminal Q (an output terminal of the JK latch circuit in FIG. 18A). An input terminal of the inverter 72 is electrically connected to an output terminal of the NAND gate 70. An input terminal of the inverter 73 is electrically connected to an output terminal of the NAND gate 71. A gate of the transistor 74 is electrically connected to an output terminal of the inverter 72. One of a source and a drain of the transistor 74 is electrically connected to the output terminal of the NAND gate 71. The other of the source and the drain of the transistor 74 is electrically connected to the terminal Q. A gate of the transistor 75 is electrically connected to an output terminal of the inverter 73. One of a source and a drain of the transistor 75 is electrically connected to the output terminal of the inverter 72. The other of the source and the drain of the transistor 75 is electrically connected to the terminal Q. An input terminal of the inverter 76 is electrically connected to the terminal Q. An output terminal of the inverter 76 is electrically connected to a third input terminal of the NAND gate 70. Note that each of the transistors 74 and 75 is a transistor whose channel region is formed with an oxide semiconductor (OS). In the latch circuit, data is held in a node where the other of the source and the drain of the transistor 74, the other of the source and the drain of the transistor 75, and the terminal Q are electrically connected to each other. FIG. 18B shows the truth table of the JK latch circuit.
Here, the results of evaluating whether the circuit in FIG. 18A can operate as a JK latch circuit are shown. For the calculation, output signals of the terminal Q when the three kinds of transistors having different Vg-Id characteristics illustrated in FIG. 10 are used as the transistors 74 and 75 are calculated. Since the three kinds of transistors have been described, the above description is employed here.
FIG. 19A shows potentials input to the terminal J, the terminal K, and the terminal CK in a given period. Note that in FIG. 19A, a voltage of 5 V corresponds to a logic “1” and a voltage of 0 V corresponds to a logic “0”. FIG. 19B shows output potentials of the terminal Q in the given period. Note that FIG. 19B shows output potentials of the terminal Q in the cases where the above three kinds of transistors are used as the transistors 74 and 75.
In the cases of using the transistors having Vg-Id characteristics which are assumed to be those of transistors whose channel region is formed with an oxide semiconductor, it is confirmed from FIG. 19B that the circuit in FIG. 18A can operate in accordance with the truth table of the JK latch circuit illustrated in FIG. 18B by setting the threshold for distinguishing between the logic “0” and the logic “1” to approximately 2V. On the other hand, in the case of using the transistor having Vg-Id characteristics which are assumed to be those of a transistor whose channel region is formed with silicon, it is found to be difficult to retain the logic “0”. Specifically, it is confirmed that the potential corresponding to the logic “0” cannot be retained in a period between 4×10−4 s and 5×10−4 s in FIG. 19B.
These results prove that the circuit in FIG. 18A can be used as a JK latch circuit when a transistor with an extremely low off-state current, such as the transistor whose channel region is formed with an oxide semiconductor, is used as the transistors 74 and 75.
First Specific Example of Gated SR Latch Circuit
FIG. 20A is a circuit diagram illustrating a specific example of a gated SR latch circuit. The gated SR latch circuit in FIG. 20A includes a NAND gate 80, a NAND gate 81, an inverter 82, an inverter 83, a transistor 84, and a transistor 85. A first input terminal of the NAND gate 80 is electrically connected to a terminal E (a first input terminal of the gated SR latch circuit in FIG. 20A). A second input terminal of the NAND gate 80 is electrically connected to a terminal R (a second input terminal of the gated SR latch circuit in FIG. 20A). A first input terminal of the NAND gate 81 is electrically connected to the terminal E. A second input terminal of the NAND gate 81 is electrically connected to a terminal S (a third input terminal of the gated SR latch circuit in FIG. 20A). An input terminal of the inverter 82 is electrically connected to an output terminal of the NAND gate 80. An input terminal of the inverter 83 is electrically connected to an output terminal of the NAND gate 81. A gate of the transistor 84 is electrically connected to an output terminal of the inverter 82. One of a source and a drain of the transistor 84 is electrically connected to an output terminal of the inverter 83. The other of the source and the drain of the transistor 84 is electrically connected to the terminal Q. A gate of the transistor 85 is electrically connected to the output terminal of the inverter 83. One of a source and a drain of the transistor 85 is electrically connected to the output terminal of the NAND gate 80. The other of the source and the drain of the transistor 85 is electrically connected to the terminal Q. Note that each of the transistors 84 and 85 is a transistor whose channel region is formed with an oxide semiconductor (OS). In the latch circuit, data is held in a node where the other of the source and the drain of the transistor 84, the other of the source and the drain of the transistor 85, and the terminal Q are electrically connected to each other. FIG. 20B shows the truth table of the gated SR latch circuit.
Here, the results of evaluating whether the circuit in FIG. 20A can operate as a gated SR latch circuit are shown. For the calculation, output signals of the terminal Q when the three kinds of transistors having different Vg-Id characteristics illustrated in FIG. 10 are used as the transistors 84 and 85 are calculated. Since the three kinds of transistors have been described, the above description is employed here.
FIG. 21A shows potentials input to the terminal S, the terminal R, and the terminal E in a given period. Note that in FIG. 21A, a voltage of 5 V corresponds to a logic “1” and a voltage of 0 V corresponds to a logic “0”. FIG. 21B shows output potentials of the terminal Q in the given period. Note that FIG. 21B shows output potentials of the terminal Q in the cases where the above three kinds of transistors are used as the transistors 84 and 85.
In the cases of using the transistors having Vg-Id characteristics which are assumed to be those of transistors whose channel region is formed with an oxide semiconductor, it is confirmed from FIG. 21B that the circuit in FIG. 20A can operate in accordance with the truth table of the gated SR latch circuit illustrated in FIG. 20B. On the other hand, in the case of using the transistor having Vg-Id characteristics which are assumed to be those of a transistor whose channel region is formed with silicon, it is found to be difficult to retain the logic “0”. Specifically, it is confirmed that the potential corresponding to the logic “0” cannot be retained in a period between 4×10−4 s and 5×10−4 s in FIG. 21B.
These results prove that the circuit in FIG. 20A can be used as a gated SR latch circuit when a transistor with an extremely low off-state current, such as the transistor whose channel region is formed with an oxide semiconductor, is used as the transistors 84 and 85.
In addition, the circuit in FIG. 20A can realize a gated SR latch circuit with a smaller number of transistors than the gated SR latch circuit in FIG. 26G.
Second Specific Example of Gated SR Latch Circuit
FIG. 22A is a circuit diagram illustrating a specific example of a gated SR latch circuit. The gated SR latch circuit in FIG. 22A includes a NAND gate 90, a NAND gate 91, a NAND gate 92, and a transistor 93. A first input terminal of the NAND gate 90 is electrically connected to a terminal E (a first input terminal of the gated SR latch circuit in FIG. 22A). A second input terminal of the NAND gate 90 is electrically connected to a terminal S (a second input terminal of the gated SR latch circuit in FIG. 22A). A first input terminal of the NAND gate 91 is electrically connected to the terminal E. A second input terminal of the NAND gate 91 is electrically connected to a terminal R (a third input terminal of the gated SR latch circuit in FIG. 22A). A first input terminal of the NAND gate 92 is electrically connected to an output terminal of the NAND gate 90. A second input terminal of the NAND gate 92 is electrically connected to an output terminal of the NAND gate 91. A gate of the transistor 93 is electrically connected to an output terminal of the NAND gate 92. One of a source and a drain of the transistor 93 is electrically connected to the output terminal of the NAND gate 91. The other of the source and the drain of the transistor 93 is electrically connected to a terminal Q (an output terminal of the gated SR latch circuit in FIG. 22A). Note that the transistor 93 is a transistor whose channel region is formed with an oxide semiconductor (OS). In the latch circuit, data is held in a node where the other of the source and the drain of the transistor 93 and the terminal Q are electrically connected to each other. FIG. 22B shows the truth table of the gated SR latch circuit.
Here, the results of evaluating whether the circuit in FIG. 22A can operate as a gated SR latch circuit are shown. For the calculation, output signals of the terminal Q when the three kinds of transistors having different Vg-Id characteristics illustrated in FIG. 10 are used as the transistor 93 are calculated. Since the three kinds of transistors have been described, the above description is employed here.
FIG. 23A shows potentials input to the terminal S, the terminal R, and the terminal E in a given period. Note that in FIG. 23A, a voltage of 5 V corresponds to a logic “1” and a voltage of 0 V corresponds to a logic “0”. FIG. 23B shows output potentials of the terminal Q in the given period. Note that FIG. 23B shows output potentials of the terminal Q in the cases where the above three kinds of transistors are used as the transistor 93.
In the cases of using the transistors having Vg-Id characteristics which are assumed to be those of transistors whose channel region is formed with an oxide semiconductor, it is confirmed from FIG. 23B that the circuit in FIG. 22A can operate in accordance with the truth table of the gated SR latch circuit illustrated in FIG. 22B by setting the threshold for distinguishing between the logic “0” and the logic “1” to approximately 2 V. On the other hand, in the case of using the transistor having Vg-Id characteristics which are assumed to be those of a transistor whose channel region is formed with silicon, it is found to be difficult to retain the logic “0”. Specifically, it is confirmed that the potential corresponding to the logic “0” cannot be retained in a period between 4×10−4 s and 5×10−4 s in FIG. 23B.
These results prove that the circuit in FIG. 22A can be used as a gated SR latch circuit when a transistor with an extremely low off-state current, such as the transistor whose channel region is formed with an oxide semiconductor, is used as the transistor 93.
In addition, the circuit in FIG. 22A can realize a gated SR latch circuit with a smaller number of transistors than the gated SR latch circuit in FIG. 26G.
Specific Example of D Latch Circuit
FIG. 24A is a circuit diagram illustrating a specific example of a D latch circuit. The D latch circuit in FIG. 24A only includes a transistor 99. A gate of the transistor 99 is electrically connected to a terminal E (a first input terminal of the D latch circuit in FIG. 24A). One of a source and a drain of the transistor 99 is electrically connected to a terminal D (a second input terminal of the D latch circuit in FIG. 24A). The other of the source and the drain of the transistor 99 is electrically connected to a terminal Q (an output terminal of the D latch circuit in FIG. 24A). Note that the transistor 99 is a transistor whose channel region is formed with an oxide semiconductor (OS). In the latch circuit, data is held in a node where the other of the source and the drain of the transistor 99 and the terminal Q are electrically connected to each other. FIG. 24B shows the truth table of the D latch circuit.
Here, the results of evaluating whether the circuit in FIG. 24A can operate as a D latch circuit are shown. For the calculation, output signals of the terminal Q when the three kinds of transistors having different Vg-Id characteristics illustrated in FIG. 10 are used as the transistor 99 are calculated. Since the three kinds of transistors have been described, the above description is employed here.
FIG. 25A shows potentials input to the terminal D and the terminal E in a given period. Note that in FIG. 25A, a voltage of 5 V corresponds to a logic “1” and a voltage of 0 V corresponds to a logic “0”. FIG. 25B shows output potentials of the terminal Q in the given period. Note that FIG. 25B shows output potentials of the terminal Q in the cases where the above three kinds of transistors are used as the transistor 99.
In the cases of using the transistors having Vg-Id characteristics which are assumed to be those of transistors whose channel region is formed with an oxide semiconductor, it is confirmed from FIG. 25B that the circuit in FIG. 24A can operate in accordance with the truth table of the D latch circuit illustrated in FIG. 24B. On the other hand, in the case of using the transistor having Vg-Id characteristics which are assumed to be those of a transistor whose channel region is formed with silicon, it is found to be difficult to retain the logic “1”. Specifically, it is confirmed that the potential corresponding to the logic “1” cannot be retained in a period between 2×10−4 and 3×10−4 s and a period between 6×10−4 s and 7×10−4 s in FIG. 25B.
These results prove that the circuit in FIG. 24A can be used as a D latch circuit when a transistor with an extremely low off-state current, such as the transistor whose channel region is formed with an oxide semiconductor, is used as the transistor 99.
In addition, the circuit in FIG. 24A can realize a D latch circuit with a smaller number of transistors than the D latch circuit in FIG. 26I.
Specific Example of Transistor Included in Latch Circuit
Specific examples of transistors included in the latch circuit will be described. In particular, an example of the case where a transistor constituting a logic gate is formed using a substrate containing a semiconductor material such as single crystal silicon and a transistor whose channel region is formed with an oxide semiconductor is formed over the transistor will be described.
FIG. 27 illustrates an example of transistors included in the latch circuit. A transistor 160 illustrated in FIG. 27 includes a channel region 116 provided in a substrate 100 containing a semiconductor material, a pair of impurity regions 114a and 114b and a pair of high concentration impurity regions 120a and 120b (these regions are also collectively referred to simply as impurity regions) provided so that the channel region 116 is placed therebetween, a gate insulating layer 108 provided over the channel region 116, a gate layer 110 provided over the gate insulating layer 108, a source layer 130a electrically connected to the impurity region 114a, and a drain layer 130b electrically connected to the impurity region 114b. 
Note that sidewall insulating layers 118 are provided on side surfaces of the gate layer 110. In the substrate 100 containing a semiconductor material, the pair of high concentration impurity regions 120a and 120b is placed in regions that do not overlap with the sidewall insulating layers 118. A pair of metal compound regions 124a and 124b is placed on the pair of high concentration impurity regions 120a and 120b. An element isolation insulating layer 106 is provided over the substrate 100 so as to surround the transistor 160. An interlayer insulating layer 126 and an interlayer insulating layer 128 are provided so as to cover the transistor 160. The source layer 130a and the drain layer 130b are electrically connected to the metal compound region 124a and the metal compound region 124b, respectively, through openings formed in the interlayer insulating layers 126 and 128. That is, the source layer 130a is electrically connected to the high concentration impurity region 120a and the impurity region 114a through the metal compound region 124a, and the drain layer 130b is electrically connected to the high concentration impurity region 120b and the impurity region 114b through the metal compound region 124b. 
A transistor 164 illustrated in FIG. 27 includes a gate layer 136d provided over the interlayer insulating layer 128, a gate insulating layer 138 provided over the gate layer 136d, an oxide semiconductor layer 140 provided over the gate insulating layer 138, and a source layer 142a and a drain layer 142b that are provided over the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140.
Here, the gate layer 136d is provided to be embedded in an insulating layer 132 formed over the interlayer insulating layer 128. Like the gate layer 136d, an electrode layer 136a and an electrode layer 136b that are included in the transistor 160 and are in contact with the source layer 130a and the drain layer 130b, respectively, are formed.
A protective insulating layer 144 is provided over the transistor 164 so as to be in contact with part of the oxide semiconductor layer 140. An interlayer insulating layer 146 is provided over the protective insulating layer 144. Here, openings reaching the source layer 142a and the drain layer 142b are provided in the protective insulating layer 144 and the interlayer insulating layer 146. An electrode layer 150d in contact with the source layer 142a and an electrode layer 150e in contact with the drain layer 142b are formed through the openings. Like the electrode layers 150d and 150e, an electrode layer 150a in contact with the electrode layer 136a and an electrode layer 150b in contact with the electrode layer 136b are formed through openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146.
The oxide semiconductor layer 140 is purified by sufficient removal of impurities such as hydrogen. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is 5×1019 (atoms/cm3) or lower. Note that the hydrogen concentration of the oxide semiconductor layer 140 is preferably 5×1018 (atoms/cm3) or lower, further preferably 5×1017 (atoms/cm3) or lower. The transistor 164 with excellent off-current characteristics can be obtained with the use of such an oxide semiconductor layer 140 that is highly purified by a sufficient reduction in hydrogen concentration. When the oxide semiconductor layer 140 which is highly purified by sufficiently reducing the hydrogen concentration is used, the leakage current of the transistor 164 can be reduced. Note that the hydrogen concentration of the oxide semiconductor layer 140 is measured by secondary ion mass spectrometry (SIMS).
Further, an insulating layer 152 is provided over the interlayer insulating layer 146, and an electrode layer 154a, an electrode layer 154b, and an electrode layer 154d are provided so as to be embedded in the insulating layer 152. Note that the electrode layer 154a is in contact with the electrode layer 150a, the electrode layer 154b is in contact with the electrode layer 150b and the electrode layer 150d, and the electrode layer 154d is in contact with the electrode layer 150e. 
As illustrated in FIG. 27, the drain layer 130b in the transistor 160 is electrically connected to the source layer 142a in the transistor 164 through the electrode layer 136b, the electrode layer 150b, the electrode layer 154b, and the electrode layer 150d which are provided in the upper region.
Example of Formation Process
Next, examples of methods for forming the transistor 160 and the transistor 164 will be described. A method for forming the p-channel transistor 160 is described first with reference to FIGS. 28A to 28H, and then, a method for forming the transistor 164 is described with reference to FIGS. 29A to 29G and FIGS. 30A to 30D.
First, the substrate 100 containing a semiconductor material is prepared (see FIG. 28A). As the substrate 100 containing a semiconductor material, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate of silicon, silicon carbide, or the like, a compound semiconductor substrate of silicon germanium or the like, an SOI substrate, or the like can be used. Here, an example where a single crystal silicon substrate is used as the substrate 100 containing a semiconductor material is described. Note that in general, the “SOI substrate” means a substrate in which a silicon semiconductor layer is provided on an insulating surface. In this specification and the like, the “SOI substrate” also includes a substrate in which a semiconductor layer containing a material other than silicon is provided over an insulating surface in its category. That is, a semiconductor layer included in the “SOI substrate” is not limited to a silicon semiconductor layer. Further, the “SOI substrate” includes a substrate in which a semiconductor layer is formed over an insulating substrate such as a glass substrate with an insulating layer placed therebetween.
A protective layer 102 serving as a mask for formation of an element isolation insulating layer is formed over the substrate 100 (see FIG. 28A). As the protective layer 102, an insulating layer formed using silicon oxide, silicon nitride, silicon nitride oxide, or the like can be used, for example. Note that before or after this step, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100 in order to control the threshold voltage of a transistor. When silicon is used as the semiconductor, phosphorus, arsenic, or the like can be used as the impurity imparting n-type conductivity. Boron, aluminum, gallium, or the like can be used as the impurity imparting p-type conductivity.
Next, part of the substrate 100 which is not covered with the protective layer 102 (i.e., the substrate 100 in an exposed region) is removed by etching with the use of the protective layer 102 as a mask. Thus, an isolated semiconductor region 104 is formed (see FIG. 28B). As the etching, dry etching is preferably performed, but wet etching may be performed. An etching gas or an etchant can be selected as appropriate depending on materials of layers to be etched.
Then, an insulating layer is formed to cover the semiconductor region 104, and part of the insulating layer which overlaps with the semiconductor region 104 is selectively removed, so that the element isolation insulating layers 106 are formed (see FIG. 28B). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, or the like. As a method for removing the insulating layer, any of polishing treatment such as chemical mechanical polishing (CMP), etching treatment, and the like can be employed. Note that the protective layer 102 is removed after the formation of the semiconductor region 104 or after the formation of the element isolation insulating layers 106.
Next, an insulating layer is formed over the semiconductor region 104, and a layer containing a conductive material is formed over the insulating layer.
The insulating layer serves as a gate insulating layer later, and preferably has a single-layer structure or a stacked structure using a film containing silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, or the like formed by CVD, sputtering, or the like. Alternatively, the insulating layer may be formed in such a manner that a surface of the semiconductor region 104 is oxidized or nitrided by high-density plasma treatment or thermal oxidation treatment. The high-density plasma treatment can be performed using, for example, a mixed gas of a rare gas such as He, Ar, Kr, or Xe and a gas such as oxygen, nitrogen oxide, ammonia, or nitrogen. There is no particular limitation on the thickness of the insulating layer; the insulating layer can have a thickness of 1 nm to 100 nm, for example.
The layer containing a conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, or tungsten. The layer containing a conductive material may be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. There is no particular limitation on the method for forming the layer containing a conductive material, and a variety of film formation methods such as evaporation, CVD, sputtering, and spin coating can be employed. Note that here, an example of the case where the layer containing a conductive material is formed using a metal material is described.
After that, the insulating layer and the layer containing a conductive material are selectively etched, so that the gate insulating layer 108 and the gate layer 110 are formed (see FIG. 28C).
Next, an insulating layer 112 that covers the gate layer 110 is formed (see FIG. 28C). Then, boron (B), phosphorus (P), arsenic (As), or the like is added to the semiconductor region 104, so that the pair of impurity regions 114a and 114b with a shallow junction is formed (see FIG. 28C). Note that by formation of the pair of impurity regions 114a and 114b, the channel region 116 is formed in the semiconductor region 104 below the gate insulating layer 108 (see FIG. 28C). Here, the concentration of the impurity added can be set as appropriate; the concentration is preferably increased when the size of the semiconductor element is extremely decreased. Although the pair of impurity regions 114a and 114b is formed after formation of the insulating layer 112 here, the insulating layer 112 may be formed after formation of the pair of impurity regions 114a and 114b. 
Next, the sidewall insulating layers 118 are formed (see FIG. 28D). The sidewall insulating layers 118 can be formed in a self-aligned manner by forming an insulating layer so as to cover the insulating layer 112 and then performing highly anisotropic etching on the insulating layer. At this time, by partial etching of the insulating layer 112, an upper surface of the gate layer 110 and upper surfaces of the pair of impurity regions 114a and 114b are preferably exposed.
Next, an insulating layer is formed so as to cover the gate layer 110, the pair of impurity regions 114a and 114b, the sidewall insulating layers 118, and the like. Then, boron (B), phosphorus (P), arsenic (As), or the like is added to part of the impurity regions 114a and 114b, whereby the pair of high concentration impurity regions 120a and 120b is formed (see FIG. 28E). After that, the insulating layer is removed, and a metal layer 122 is formed so as to cover the gate layer 110, the sidewall insulating layers 118, the pair of high concentration impurity regions 120a and 120b, and the like (see FIG. 28E). The metal layer 122 can be formed by a variety of film formation methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with a semiconductor material included in the semiconductor region 104 to be a low-resistance metal compound. Examples of such metal materials are titanium, tantalum, tungsten, nickel, cobalt, and platinum.
Next, heat treatment is performed so that the metal layer 122 reacts with the semiconductor material. Thus, the pair of metal compound regions 124a and 124b in contact with the pair of high concentration impurity regions 120a and 120b is formed (see FIG. 28F). Note that when the gate layer 110 is formed using polycrystalline silicon or the like, a metal compound region is also formed in a region of the gate layer 110 in contact with the metal layer 122.
As the heat treatment, irradiation with a flash lamp can be employed, for example. Although it is needless to say that another heat treatment method may be used, a method by which heat treatment for an extremely short time can be achieved is preferably used in order to improve the controllability of chemical reaction for formation of the metal compound. Note that the metal compound regions are formed by reaction of the metal material and the semiconductor material and have sufficiently high conductivity. The formation of the metal compound regions can properly reduce the electric resistance and improve element characteristics. Note that the metal layer 122 is removed after the pair of metal compound regions 124a and 124b is formed.
Next, the interlayer insulating layer 126 and the interlayer insulating layer 128 are formed so as to cover the components formed in the above steps (see FIG. 28G). The interlayer insulating layers 126 and 128 can be formed using an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Moreover, the interlayer insulating layers 126 and 128 can be formed using an organic insulating material such as polyimide or acrylic. Note that the interlayer insulating layer has a two-layer structure of the interlayer insulating layer 126 and the interlayer insulating layer 128 here; it is not limited to having this structure. After the formation of the interlayer insulating layer 128, a surface of the interlayer insulating layer 128 is preferably planarized with CMP, etching, or the like.
After that, openings reaching the pair of metal compound regions 124a and 124b are formed in the interlayer insulating layers, and the source layer 130a and the drain layer 130b are formed in the openings (see FIG. 28H). The source layer 130a and the drain layer 130b can be formed in such a manner, for example, that a conductive layer is formed in a region including the openings by PVD, CVD, or the like and then part of the conductive layer is removed by etching or CMP.
It is preferable that the source layer 130a and the drain layer 130b be formed to have a planar surface. For example, when a thin titanium film or a thin titanium nitride film is formed in a region including the openings and then a tungsten film is formed to be embedded in the openings, excess tungsten, titanium, titanium nitride, or the like is removed and the planarity of the surface can be improved by subsequent CMP. In such a manner, the surface including the source layer 130a and the drain layer 130b is planarized, whereby an electrode, a wiring, an insulating layer, a semiconductor layer, and the like can be favorably formed in later steps.
Note that here, only the source layer 130a and the drain layer 130b which are in contact with the pair of metal compound regions 124a and 124b are illustrated; an electrode layer serving as a wiring or the like can be formed together in this step. There is no particular limitation on a material used for the source layer 130a and the drain layer 130b, and a variety of conductive materials can be used. For example, a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium can be used.
Through the above steps, the transistor 160 using the substrate 100 containing a semiconductor material is formed. Note that an electrode, a wiring, an insulating layer, or the like may be further formed after the above step. When the wiring has a multilayer wiring structure which is a stacked structure including an interlayer insulating layer and a conductive layer, a highly integrated circuit can be provided.
Next, steps for forming the transistor 164 over the interlayer insulating layer 128 will be described with reference to FIGS. 29A to 29G and FIGS. 30A to 30D. Note that FIGS. 29A to 29G and FIGS. 30A to 30D illustrate steps for forming various electrode layers, the transistor 164, and the like over the interlayer insulating layer 128; therefore, the transistor 160 and the like placed below the transistor 164 are omitted.
First, the insulating layer 132 is formed over the interlayer insulating layer 128, the source layer 130a, and the drain layer 130b (see FIG. 29A). The insulating layer 132 can be formed by PVD, CVD, or the like. The insulating layer 132 can be formed using an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide.
Next, openings that reach the source layer 130a and the drain layer 130b are formed in the insulating layer 132. At this time, an opening is also formed in a region where the gate layer 136d is to be formed later. Then, a conductive layer 134 is formed so as to fill the openings (FIG. 29B). The openings can be formed by etching using a mask or the like. The mask can be formed by light exposure using a photomask or the like. Either wet etching or dry etching may be used as the etching; dry etching is preferably used in terms of micro fabrication. The conductive layer 134 can be formed by a film formation method such as PVD or CVD. The conductive layer 134 can be formed using a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium or an alloy or a compound (e.g., a nitride) of any of these materials, for example.
Specifically, it is possible to employ a method, for example, in which a thin titanium film is formed in a region including the openings by PVD and a thin titanium nitride film is formed by CVD, and then, a tungsten film is formed to fill the openings. Here, the titanium film formed by PVD has a function of deoxidizing an oxide film at an interface so as to reduce contact resistance with the lower electrode layers (here, the source layer 130a, the drain layer 130b, and the like). The titanium nitride film formed after the formation of the titanium film has a barrier function of preventing diffusion of the conductive material. A copper film may be formed by plating after the formation of the barrier film of titanium, titanium nitride, or the like.
After the conductive layer 134 is formed, part of the conductive layer 134 is removed by etching, CMP, or the like, whereby the insulating layer 132 is exposed and the electrode layers 136a and 136b and the gate layer 136d are formed (see FIG. 29C). Note that when the electrode layers 136a and 136b and the gate layer 136d are formed by removal of part of the conductive layer 134, the process is preferably performed so that the surfaces are planarized. The surfaces of the insulating layer 132, the electrode layers 136a and 136b, and the gate layer 136d are planarized in such a manner, whereby an electrode, a wiring, an insulating layer, a semiconductor layer, and the like can be favorably formed in later steps.
Next, the gate insulating layer 138 is formed so as to cover the insulating layer 132, the electrode layers 136a and 136b, and the gate layer 136d (see FIG. 29D). The gate insulating layer 138 can be formed by CVD, sputtering, or the like. It is preferable that the gate insulating layer 138 contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, gallium oxide, or the like. Note that the gate insulating layer 138 may have a single-layer structure or a stacked structure. For example, the gate insulating layer 138 made of silicon oxynitride can be formed by plasma-enhanced CVD using silane (SiH4), oxygen, and nitrogen as a source gas. There is no particular limitation on the thickness of the gate insulating layer 138; the gate insulating layer 138 can have a thickness of 10 nm to 500 nm, for example. In the case of employing a stacked structure, for example, the gate insulating layer 138 is preferably a stack of a first gate insulating layer with a thickness of 50 nm to 200 nm, and a second gate insulating layer with a thickness of 5 nm to 300 nm over the first gate insulating layer.
Then, an oxide semiconductor layer is formed over the gate insulating layer 138 and processed by etching using a mask or the like, whereby the island-shaped oxide semiconductor layer 140 is formed (see FIG. 29E).
For the oxide semiconductor layer, any of the following oxide semiconductors can be used, for example: an In—Sn—Ga—Zn—O-based oxide semiconductor which is an oxide of four metal elements; an In—Ga—Zn—O-based oxide semiconductor, an In—Sn—Zn—O-based oxide semiconductor, an In—Al—Zn—O-based oxide semiconductor, a Sn—Ga—Zn—O-based oxide semiconductor, an Al—Ga—Zn—O-based oxide semiconductor, and a Sn—Al—Zn—O-based oxide semiconductor which are oxides of three metal elements; an In—Zn—O-based oxide semiconductor, a Sn—Zn—O-based oxide semiconductor, an Al—Zn—O-based oxide semiconductor, a Zn—Mg—O-based oxide semiconductor, a Sn—Mg—O-based oxide semiconductor, an In—Mg—O-based oxide semiconductor, and an In—Ga—O-based oxide semiconductor which are oxides of two metal elements; and an In—O-based oxide semiconductor, a Sn—O-based oxide semiconductor, and a Zn—O-based oxide semiconductor. Here, as the oxide semiconductor layer, an amorphous oxide semiconductor layer is formed by sputtering using an In—Ga—Zn—O-based metal oxide target.
As a target used for forming the oxide semiconductor layer 140 by sputtering, a metal oxide target containing zinc oxide or the like as its main component can be used, for example. It is possible to use a metal oxide target containing In, Ga, and Zn (a composition ratio of In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] and In:Ga:Zn=1:1:0.5 [atomic ratio]). As the metal oxide target containing In, Ga, and Zn, it is possible to use a target having a composition ratio of In:Ga:Zn=1:1:1 [atomic ratio] or a composition ratio of In:Ga:Zn=1:1:2 [atomic ratio]. The filling factor of the metal oxide target is 90% to 100%, and preferably 95% or higher (e.g., 99.9%). With use of a metal oxide target with high filling factor, a dense oxide semiconductor layer can be formed.
In the case where an In—Sn—Zn—O-based material is used for the oxide semiconductor, an oxide target having a composition ratio of In:Sn:Zn=1:2:2, 2:1:3, 1:1:1, or 20:45:35 in an atomic ratio is used, for example. An In—Sn—Zn-based oxide can be referred to as ITZO.
The atmosphere in which the oxide semiconductor layer is formed is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically argon) and oxygen. Specifically, it is preferable to use a high-purity gas in which impurities such as hydrogen, water, a hydroxyl group, or a hydride are reduced to about several parts per million (ppm) (preferably about several parts per billion (ppb)).
At the time of forming the oxide semiconductor layer, the substrate is held in a treatment chamber that is maintained at reduced pressure, and the substrate temperature is set to 100° C. to 600° C., preferably 200° C. to 400° C. The oxide semiconductor layer is formed while the substrate is heated, so that the impurity concentration of the oxide semiconductor layer can be reduced. In addition, damage by sputtering can be reduced. Then, a sputtering gas from which hydrogen and water are removed is introduced into the treatment chamber from which remaining moisture is being removed, and the oxide semiconductor layer is formed using a metal oxide as a target. In order to remove remaining moisture in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The evacuation unit may be a turbo pump provided with a cold trap. A hydrogen atom, a compound containing a hydrogen atom, such as water (H2O) (more preferably also a compound containing a carbon atom), and the like are removed from the deposition chamber evacuated with a cryopump, so that the impurity concentration of the oxide semiconductor layer formed in the deposition chamber can be reduced.
The oxide semiconductor layer can be formed under the following conditions, for example: the distance between the substrate and the target is 100 mm; the pressure is 0.6 Pa; the direct-current (DC) power is 0.5 kW; and the atmosphere is oxygen (the flow rate ratio of oxygen is 100%). Note that the use of a pulse direct-current (DC) power source is preferably used because dust can be reduced and the film thickness can be uniform. The thickness of the oxide semiconductor layer is 2 nm to 200 nm, preferably 5 nm to 30 nm. Note that an appropriate thickness differs depending on an oxide semiconductor material, and the thickness is set as appropriate depending on the material to be used.
Note that before the oxide semiconductor layer is formed by sputtering, dust attached on the surface of the gate insulating layer 138 is preferably removed by reverse sputtering in which plasma is generated with an argon gas introduced. Here, reverse sputtering is a method by which ions collide with a surface to be processed so that the surface is modified, in contrast to normal sputtering by which ions collide with a sputtering target. An example of a method for making ions collide with a surface to be processed is a method in which high-frequency voltage is applied to the surface in an argon atmosphere so that plasma is generated near a substrate. Note that an atmosphere of nitrogen, helium, oxygen, or the like may be used instead of an argon atmosphere.
As an etching method for the oxide semiconductor layer, either dry etching or wet etching can be employed. Needless to say, dry etching and wet etching can be used in combination. The etching conditions (e.g., an etching gas or an etchant, etching time, and temperature) are set as appropriate depending on the material so that the oxide semiconductor layer can be etched into a desired shape.
An example of an etching gas used for dry etching is a gas containing chlorine (a chlorine-based gas such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), or carbon tetrachloride (CCl4)). Moreover, a gas containing fluorine (a fluorine-based gas such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3)), hydrogen bromide (HBr), oxygen (O2), any of these gases to which a rare gas such as helium (He) or argon (Ar) is added, or the like may be used.
As the dry etching method, parallel plate RIE (reactive ion etching) or ICP (inductively coupled plasma) etching can be used. In order to etch the oxide semiconductor layer into a desired shape, etching conditions (e.g., the amount of electric power applied to a coiled electrode, the amount of electric power applied to an electrode on the substrate side, and the electrode temperature on the substrate side) are set as appropriate.
As an etchant used for wet etching, a mixed solution of phosphoric acid, acetic acid, and nitric acid can be used, for example. An etchant such as ITO07N (produced by Kanto Chemical Co., Inc.) may also be used.
Then, first heat treatment is preferably performed on the oxide semiconductor layer. The oxide semiconductor layer can be dehydrated or dehydrogenated with the first heat treatment. The temperature of the first heat treatment is 300° C. or more and 750° C. or less, preferably 400° C. or more and less than the strain point of the substrate. For example, the substrate is introduced into an electric furnace in which a resistance heating element or the like is used, and the oxide semiconductor layer 140 is subjected to heat treatment at 450° C. for one hour in a nitrogen atmosphere. The oxide semiconductor layer 140 is not exposed to the air during the heat treatment so that entry of water and hydrogen can be prevented.
The heat treatment apparatus is not limited to the electric furnace and can be an apparatus for heating an object by thermal radiation or thermal conduction from a medium such as a heated gas. For example, an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus or an LRTA (lamp rapid thermal anneal) apparatus can be used. An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus is an apparatus for performing heat treatment using a high-temperature gas. As the gas, an inert gas that does not react with an object by heat treatment, for example, nitrogen or a rare gas such as argon is used.
For example, as the first heat treatment, a GRTA process may be performed as follows. The substrate is put in an inert gas that has been heated to a high temperature of 650° C. to 700° C., heated for several minutes, and taken out of the inert gas. The GRTA process enables high-temperature heat treatment for a short time. Moreover, the GRTA process can be employed even when the temperature exceeds the strain point of the substrate because it is heat treatment for a short time.
Note that the first heat treatment is preferably performed in an atmosphere that contains nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and does not contain water, hydrogen, or the like. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into a heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).
Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer is sometimes crystallized to be microcrystalline or polycrystalline. For example, the oxide semiconductor layer sometimes becomes a microcrystalline oxide semiconductor layer with a degree of crystallization of 90% or more, or 80% or more. Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor layer including no crystalline component.
Furthermore, in the oxide semiconductor layer, a microcrystal (with a grain size of 1 nm to 20 nm, typically 2 nm to 4 nm) is sometimes mixed in an amorphous oxide semiconductor (e.g., a surface of the oxide semiconductor layer).
The electrical characteristics of the oxide semiconductor layer can be changed by aligning microcrystals in an amorphous semiconductor. For example, in the case where the oxide semiconductor layer is formed using an In—Ga—Zn—O-based metal oxide target, a microcrystalline portion where crystal grains of In2Ga2ZnO7 having electrical anisotropy are aligned is formed, whereby the electric characteristics of the oxide semiconductor layer can be changed.
Specifically, for example, when the microcrystalline portion is arranged so that the c-axis of In2Ga2ZnO7 is perpendicular to a surface of the oxide semiconductor layer, the conductivity in the direction parallel to the surface of the oxide semiconductor layer can be improved and insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer can be improved. Furthermore, such a microcrystalline portion has a function of suppressing entry of impurities such as water or hydrogen into the oxide semiconductor layer.
Note that the oxide semiconductor layer including the microcrystalline portion can be formed by heating the surface of the oxide semiconductor layer by a GRTA process. In addition, the oxide semiconductor layer can be formed in a more preferred manner by using a sputtering target in which the amount of Zn is smaller than that of In or Ga.
The first heat treatment for the oxide semiconductor layer 140 can be performed on the oxide semiconductor layer that has not yet been processed into the island-shaped oxide semiconductor layer 140. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography process is performed.
Note that the first heat treatment can be called dehydration treatment or dehydrogenation treatment because it is effective in dehydrating or dehydrogenating the oxide semiconductor layer 140. It is possible to perform such dehydration treatment or dehydrogenation treatment, for example, after the oxide semiconductor layer is formed, after source and drain layers are stacked over the oxide semiconductor layer 140, or after a protective insulating layer is formed over the source and drain layers. Such dehydration treatment or dehydrogenation treatment may be conducted once or plural times.
Next, the source layer 142a and the drain layer 142b are formed so as to be in contact with the oxide semiconductor layer 140 (see FIG. 29F). The source layer 142a and the drain layer 142b can be formed in such a manner that a conductive layer is formed so as to cover the oxide semiconductor layer 140 and then is selectively etched.
The conductive layer can be formed by PVD such as sputtering or CVD such as plasma-enhanced CVD. As a material for the conductive layer, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of these elements as a component; or the like can be used. Moreover, one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium may be used. Aluminum combined with one or more of elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used. The conductive layer can have a single-layer structure or a stacked structure including two or more layers. For example, the conductive layer can have a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, or a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order.
The materials and etching conditions of the conductive layer and the oxide semiconductor layer 140 are adjusted as appropriate so that the oxide semiconductor layer 140 is not removed in etching of the conductive layer. Note that in some cases, the oxide semiconductor layer 140 is partly etched in the etching step and thus has a groove portion (a recessed portion) depending on the materials and the etching conditions.
An oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source layer 142a or between the oxide semiconductor layer 140 and the drain layer 142b. It is possible to successively form the oxide conductive layer and a metal layer that is to be the source layer 142a and the drain layer 142b (successive deposition). The oxide conductive layer can function as a source region or a drain region. The placement of such an oxide conductive layer can reduce the resistance of the source region or the drain region, so that the transistor can operate at high speed.
In order to reduce the number of masks to be used and reduce the number of steps, an etching step may be performed with the use of a resist mask formed using a multi-tone mask which is a light-exposure mask through which light is transmitted to have a plurality of intensities. A resist mask formed with the use of a multi-tone mask has a plurality of thicknesses (has a stair-like shape) and further can be changed in shape by ashing; therefore, the resist mask can be used in a plurality of etching steps for providing different patterns. That is, a resist mask corresponding to at least two kinds of different patterns can be formed by using a multi-tone mask. Thus, the number of light-exposure masks can be reduced and the number of corresponding photolithography steps can also be reduced, whereby the process can be simplified.
Note that plasma treatment is preferably performed with the use of a gas such as N2O, N2, or Ar after the above step. This plasma treatment removes water or the like attached on an exposed surface of the oxide semiconductor layer. Plasma treatment may be performed using a mixture gas of oxygen and argon.
Next, the protective insulating layer 144 that is in contact with part of the oxide semiconductor layer 140 is formed without being exposed to the air (see FIG. 29G).
The protective insulating layer 144 can be formed by employing a method by which impurities such as water or hydrogen are prevented from entering the protective insulating layer 144, such as sputtering, as appropriate. The protective insulating layer 144 has a thickness of at least 1 nm. The protective insulating layer 144 can be formed using silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. The protective insulating layer 144 can have a single-layer structure or a stacked structure. The substrate temperature at the time of forming the protective insulating layer 144 is preferably room temperature or more and 300° C. or less. The atmosphere for forming the protective insulating layer 144 is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically argon) and oxygen.
If hydrogen is contained in the protective insulating layer 144, hydrogen may enter the oxide semiconductor layer 140 or extract oxygen in the oxide semiconductor layer 140, whereby the resistance of the oxide semiconductor layer 140 on the backchannel side might be decreased and a parasitic channel might be formed. Therefore, it is important not to use hydrogen at the time of forming the protective insulating layer 144 so that the protective insulating layer 144 contains hydrogen as little as possible.
It is preferable to form the protective insulating layer 144 while removing moisture remaining in the treatment chamber, in order that hydrogen, a hydroxyl group, or moisture is not contained in the oxide semiconductor layer 140 and the protective insulating layer 144.
In order to remove remaining moisture in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. The evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber that is evacuated with a cryopump, a hydrogen atom and a compound containing a hydrogen atom, such as water (H2O), are removed, for example; thus, the concentration of impurities contained in the protective insulating layer 144 formed in the deposition chamber can be reduced.
A sputtering gas used for the deposition of the protective insulating layer 144 is preferably a high-purity gas in which the concentration of impurities such as hydrogen, water, a hydroxyl group, or a hydride is reduced to about several parts per million (ppm) (preferably about several parts per billion (ppb)).
Next, second heat treatment (at 200° C. to 400° C., for example, at 250° C. to 350° C.) is preferably performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, the second heat treatment is performed at 250° C. for one hour in a nitrogen atmosphere. The second heat treatment can reduce variation in electric characteristics of the transistor.
Furthermore, heat treatment may be performed at 100° C. to 200° C. for 1 hour to 30 hours in the air. This heat treatment may be performed at a fixed heating temperature or follow temperature cycles in which the temperature repeatedly rises from room temperature to a heating temperature of 100° C. to 200° C. and drops from the heating temperature to room temperature. This heat treatment may be performed under reduced pressure before the protective insulating layer is formed. The heat treatment time can be shortened under reduced pressure. This heat treatment may be performed instead of the second heat treatment or may be performed before or after the second heat treatment, for example.
Then, the interlayer insulating layer 146 is formed over the protective insulating layer 144 (see FIG. 30A). The interlayer insulating layer 146 can be formed by PVD, CVD, or the like. The interlayer insulating layer 146 can be formed using an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. After the formation of the interlayer insulating layer 146, a surface of the interlayer insulating layer 146 is preferably planarized with CMP, etching, or the like.
Next, openings that reach the electrode layers 136a and 136b, the source layer 142a, and the drain layer 142b are formed in the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. Then, a conductive layer 148 is formed to be embedded in the openings (see FIG. 30B). The openings can be formed by etching using a mask or the like. The mask can be formed by light exposure using a photomask or the like. Either wet etching or dry etching may be used as the etching; dry etching is preferably used in terms of microfabrication. The conductive layer 148 can be formed by a film formation method such as PVD or CVD. The conductive layer 148 can be foamed using a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium or an alloy or a compound (e.g., a nitride) of any of these materials, for example.
Specifically, it is possible to employ a method, for example, in which a thin titanium film is formed in a region including the openings by PVD and a thin titanium nitride film is formed by CVD, and then, a tungsten film is formed to be embedded in the openings. Here, the titanium film formed by PVD has a function of deoxidizing an oxide film at an interface so as to reduce contact resistance with the lower electrodes (here, the electrode layers 136a and 136b, the source layer 142a, and the drain layer 142b). The titanium nitride film formed after the formation of the titanium film has a barrier function of preventing diffusion of the conductive material. A copper film may be formed by plating after the formation of the barrier film of titanium, titanium nitride, or the like.
After the conductive layer 148 is formed, part of the conductive layer 148 is removed by etching, CMP, or the like, so that the interlayer insulating layer 146 is exposed and the electrode layers 150a, 150b, 150d, and 150e are formed (see FIG. 30C). Note that when the electrode layers 150a, 150b, 150d, and 150e are formed by removal of part of the conductive layer 148, the process is preferably performed so that the surfaces are planarized. The surfaces of the interlayer insulating layer 146 and the electrode layers 150a, 150b, 150d, and 150e are planarized in such a manner, whereby an electrode, a wiring, an insulating layer, a semiconductor layer, and the like can be favorably formed in later steps.
Then, the insulating layer 152 is formed, and openings reaching the electrode layers 150a, 150b, 150d, and 150e are formed in the insulating layer 152. Then, a conductive layer is formed so as to fill the openings. After that, part of the conductive layer is removed by etching, CMP, or the like, whereby the insulating layer 152 is exposed and the electrode layers 154a, 154b, and 154d are formed (see FIG. 30D). This step is similar to the step for forming the electrode layer 150a and the like; thus, the detailed description is omitted.
<Variations of Transistor>
FIG. 31, FIGS. 32A and 32B, FIGS. 33A and 33B, FIGS. 34A and 34B, FIG. 35, and FIG. 36 each illustrate a variation of the transistor 164.
FIG. 31 illustrates the transistor 164 in which the gate layer 136d is placed below the oxide semiconductor layer 140 and the source layer 142a and the drain layer 142b are in contact with a bottom surface of the oxide semiconductor layer 140.
A big difference between the structure in FIG. 31 and the structure in FIG. 27 is the position at which the oxide semiconductor layer 140 is connected to the source layer 142a and the drain layer 142b. That is, an upper surface of the oxide semiconductor layer 140 is in contact with the source layer 142a and the drain layer 142b in the structure in FIG. 27, whereas the bottom surface of the oxide semiconductor layer 140 is in contact with the source layer 142a and the drain layer 142b in the structure in FIG. 31. Further, the difference in the contact position results in a different arrangement of other electrodes, insulating layers, and the like. Note that the details of each component are the same as those of FIG. 27.
Specifically, the transistor 164 illustrated in FIG. 31 includes the gate layer 136d provided over the interlayer insulating layer 128, the gate insulating layer 138 provided over the gate layer 136d, the source layer 142a and the drain layer 142b provided over the gate insulating layer 138, and the oxide semiconductor layer 140 in contact with upper surfaces of the source layer 142a and the drain layer 142b. In addition, over the transistor 164, the protective insulating layer 144 is provided so as to cover the oxide semiconductor layer 140.
FIGS. 32A and 32B each illustrate the transistor 164 in which the gate layer 136d is provided over the oxide semiconductor layer 140. FIG. 32A illustrates an example of a structure in which the source layer 142a and the drain layer 142b are in contact with a bottom surface of the oxide semiconductor layer 140. FIG. 32B illustrates an example of a structure in which the source layer 142a and the drain layer 142b are in contact with an upper surface of the oxide semiconductor layer 140.
A big difference of the structures in FIGS. 32A and 32B from those in FIG. 27 and FIG. 31 is that the gate electrode layer 136d is placed over the oxide semiconductor layer 140. Furthermore, a big difference between the structure in FIG. 32A and the structure in FIG. 32B is that the source layer 142a and the drain layer 142b are in contact with either the bottom surface or the upper surface of the oxide semiconductor layer 140. These differences result in a different arrangement of other electrodes, insulating layers, and the like. The details of each component are the same as those of FIG. 27 and the like.
Specifically, the transistor 164 illustrated in FIG. 32A includes the source layer 142a and the drain layer 142b provided over the interlayer insulating layer 128, the oxide semiconductor layer 140 in contact with the upper surfaces of the source layer 142a and the drain layer 142b, the gate insulating layer 138 provided over the oxide semiconductor layer 140, and the gate layer 136d provided over the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140.
The transistor 164 illustrated in FIG. 32B includes the oxide semiconductor layer 140 provided over the interlayer insulating layer 128; the source layer 142a and the drain layer 142b provided to be in contact with the upper surface of the oxide semiconductor layer 140; the gate insulating layer 138 provided over the oxide semiconductor layer 140, the source layer 142a, and the drain layer 142b; and the gate layer 136d provided over the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140.
Note that in the structures in FIGS. 32A and 32B, a component (e.g., the electrode layer 150a or the electrode layer 154a) is sometimes omitted from the structure in FIG. 27 or the like. In that case, a secondary effect such as simplification of the fabrication process can be obtained. It is needless to say that a nonessential component can be omitted in the structure in FIG. 27 and the like.
FIGS. 33A and 33B each illustrate the transistor 164 in the case where the size of the element is relatively large and the gate layer 136d is placed below the oxide semiconductor layer 140. In that case, a demand for the planarity of a surface and the coverage is relatively moderate, so that it is not necessary to form a wiring, an electrode, and the like to be embedded in an insulating layer. For example, the gate layer 136d and the like can be formed by patterning after formation of a conductive layer.
A big difference between the structure in FIG. 33A and the structure in FIG. 33B is that the source layer 142a and the drain layer 142b are in contact with either the bottom surface or the upper surface of the oxide semiconductor layer 140. Moreover, the difference results in a different arrangement of other electrodes, insulating layers, and the like. The details of each component are the same as those of FIG. 27 and the like.
Specifically, the transistor 164 illustrated in FIG. 33A includes the gate layer 136d provided over the interlayer insulating layer 128, the gate insulating layer 138 provided over the gate layer 136d, the source layer 142a and the drain layer 142b provided over the gate insulating layer 138, and the oxide semiconductor layer 140 that is in contact with the upper surfaces of the source layer 142a and the drain layer 142b. 
The transistor 164 illustrated in FIG. 33B includes the gate layer 136d provided over the interlayer insulating layer 128, the gate insulating layer 138 provided over the gate layer 136d, the oxide semiconductor layer 140 provided over the gate insulating layer 138 in a region overlapping with the gate layer 136d, and the source layer 142a and the drain layer 142b that are in contact with the upper surface of the oxide semiconductor layer 140.
Note that also in the structures in FIGS. 33A and 33B, a component is sometimes omitted from the structure in FIG. 27 or the like. In that case, a secondary effect such as simplification of the fabrication process can be obtained.
FIGS. 34A and 34B each illustrate the transistor 164 in the case where the size of the element is relatively large and the gate layer 136d is placed over the oxide semiconductor layer 140. Also in that case, a demand for the planarity of a surface and the coverage is relatively moderate, so that it is not necessary to form a wiring, an electrode, and the like to be embedded in an insulating layer. For example, the gate layer 136d and the like can be formed by patterning after formation of a conductive layer.
A big difference between the structure in FIG. 34A and the structure in FIG. 34B is that the source layer 142a and the drain layer 142b are in contact with either the bottom surface or the upper surface of the oxide semiconductor layer 140. The difference results in a different arrangement of other electrodes, insulating layers, and the like. The details of each component are the same as those of FIG. 27 and the like.
Specifically, the transistor 164 illustrated in FIG. 34A includes the source layer 142a and the drain layer 142b provided over the interlayer insulating layer 128; the oxide semiconductor layer 140 in contact with the upper surfaces of the source layer 142a and the drain layer 142b; the gate insulating layer 138 provided over the source layer 142a, the drain layer 142b, and the oxide semiconductor layer 140; and the gate layer 136d provided over the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140.
The transistor 164 illustrated in FIG. 34B includes the oxide semiconductor layer 140 provided over the interlayer insulating layer 128; the source layer 142a and the drain layer 142b provided to be in contact with the upper surface of the oxide semiconductor layer 140; the gate insulating layer 138 provided over the source layer 142a, the drain layer 142b, and the oxide semiconductor layer 140; and the gate layer 136d provided over the gate insulating layer 138. Note that the gate layer 136d is provided in a region overlapping with the oxide semiconductor layer 140 with the gate insulating layer 138 placed therebetween.
Note that also in the structures in FIGS. 34A and 34B, a component is sometimes omitted from the structure in FIG. 27 or the like. Also in that case, a secondary effect such as simplification of the fabrication process can be obtained.
Oxide conductive layers functioning as a source region and a drain region may be provided as buffer layers between the oxide semiconductor layer 140 and the source and drain layers 142a and 142b of the transistor 164 illustrated in FIG. 27. FIG. 35 and FIG. 36 each illustrate a transistor obtained by providing the oxide conductive layers in the transistor 164 in FIG. 27.
In the transistors 164 illustrated in FIG. 35 and FIG. 36, oxide conductive layers 162a and 162b functioning as a source region and a drain region are formed between the oxide semiconductor layer 140 and the source and drain layers 142a and 142b. A difference between the transistor 164 in FIG. 35 and that in FIG. 36 is that the shape of the oxide conductive layers 162a and 162b is different depending on the formation step.
In the transistor 164 in FIG. 35, a stack of an oxide semiconductor layer and an oxide conductive layer is formed and processed by one photolithography process, so that the island-shaped oxide semiconductor layer 140 and the island-shaped oxide conductive layer are formed. Then, the source layer 142a and the drain layer 142b are formed over the oxide semiconductor layer and the oxide conductive layer. After that, the island-shaped oxide conductive layer is etched using the source layer 142a and the drain layer 142b as masks, so that the oxide conductive layers 162a and 162b serving as a source region and a drain region are formed.
In the transistor 164 in FIG. 36, an oxide conductive layer is formed over the oxide semiconductor layer 140, and a metal conductive layer is formed thereover. Then, the oxide conductive layer and the metal conductive layer are processed by one photolithography process, so that the oxide conductive layers 162a and 162b serving as a source region and a drain region, the source layer 142a, and the drain layer 142b are formed.
For etching treatment for the processing the shape of the oxide conductive layer, the etching conditions (e.g., the kind and concentration of etching gas or etchant, and etching time) are adjusted as appropriate to prevent excessive etching of the oxide semiconductor layer.
As the method for forming the oxide conductive layers 162a and 162b, sputtering, vacuum evaporation (e.g., electron beam evaporation), arc discharge ion plating, or spray coating is used. As a material for the oxide conductive layers, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, indium tin oxide, or the like can be used. In addition, the above materials may contain silicon oxide.
By providing the oxide conductive layers as the source region and the drain region between the oxide semiconductor layer 140 and the source and drain layers 142a and 142b, the resistance of the source region and the drain region can be decreased and the transistor 164 can be operated at high speed.
Further, such a structure can improve the withstand voltage of the transistor 164.
Note that FIG. 35 and FIG. 36 illustrate the structure in which the oxide conductive layers are provided between the oxide semiconductor layer 140 and the source and drain layers 142a and 142b in the transistor 164 illustrated in FIG. 27. Alternatively, the oxide conductive layers can be provided between the oxide semiconductor layer 140 and the source and drain layers 142a and 142b in the transistors 164 illustrated in FIG. 31, FIGS. 32A and 32B, FIGS. 33A and 33B, and FIGS. 34A and 34B.
Note that the example in which the transistor 164 is stacked over the transistor 160 is described here; however, the arrangement of the transistors 160 and 164 is not limited to this example. For example, the transistor 160 and the transistor 164 can be formed over one surface. Further, the transistor 160 and the transistor 164 may be provided to overlap with each other.
<Variation of Step for Forming Oxide Semiconductor Layer>
A step for forming an oxide semiconductor layer, which is different from that in the process for forming the above-described transistor, will be described with reference to FIGS. 37A to 37C.
The oxide semiconductor layer includes a first crystalline oxide semiconductor layer and a second crystalline oxide semiconductor layer that is placed over the first crystalline oxide semiconductor layer and is thicker than the first crystalline oxide semiconductor layer.
An insulating layer 437 is formed over an insulating layer 400. Here, as the insulating layer 437, an oxide insulating layer with a thickness of 50 nm to 600 nm is formed by PECVD or sputtering. For example, the oxide insulating layer can be one layer or a stack of layers selected from a silicon oxide layer, a gallium oxide layer, an aluminum oxide layer, a silicon oxynitride layer, an aluminum oxynitride layer, or a silicon nitride oxide layer.
Next, a first oxide semiconductor layer with a thickness of 1 nm to 10 nm is formed over the insulating layer 437. The first oxide semiconductor layer is formed by sputtering. The substrate temperature at the time when the first oxide semiconductor layer is deposited by sputtering is 200° C. to 400° C.
Here, a 5-nm-thick first oxide semiconductor layer is formed using a metal oxide target (an In—Ga—Zn—O-based metal oxide target with a composition ratio of In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]) under the following conditions: the distance between the substrate and the target is 170 mm, the substrate temperature is 250° C., the pressure is 0.4 Pa, the direct-current (DC) power is 0.5 kW, and the atmosphere is oxygen (the flow rate ratio of oxygen is 100%), argon (the flow rate ratio of argon is 100%), or an atmosphere containing argon and oxygen.
Next, the atmosphere in the chamber in which the substrate is put is set to a nitrogen atmosphere or dry air, and first heat treatment is performed. The temperature of the first heat treatment ranges from 400° C. to 750° C. With the first heat treatment, a first crystalline oxide semiconductor layer 450a is formed (see FIG. 37A).
Although depending on the substrate temperature at the time of deposition or the temperature of the first heat treatment, the deposition or the first heat treatment causes crystallization from the film surface and crystals grow from the surface toward the inside, so that c-axis-oriented crystals can be obtained. With the first heat treatment, large amounts of zinc and oxygen gather at the film surface, one or a plurality of layers of a graphene-like two-dimensional crystal that is made of zinc and oxygen and has a hexagonal lattice on the top plane is/are formed on the uppermost surface, and the two-dimensional crystal overlaps one another to form a stack. When the temperature of the heat treatment is raised, crystal growth progresses from the surface to the inside and from the inside to the bottom.
With the first heat treatment, oxygen in the insulating layer 437, which is an oxide insulating layer, is diffused into the interface between the first crystalline oxide semiconductor layer 450a and the insulating layer 437 or the vicinity of the interface (within the range of ±5 nm from the interface) to reduce oxygen vacancies in the first crystalline oxide semiconductor layer 450a. Therefore, in the insulating layer 437 used as a base insulating layer, oxygen that is larger in proportion than the stoichiometric proportion preferably exists at least one of in the layer (in the bulk) and at the interface between the first crystalline oxide semiconductor layer 450a and the insulating layer 437.
Next, a second oxide semiconductor layer that is thicker than 10 nm is formed over the first crystalline oxide semiconductor layer 450a. The second oxide semiconductor layer is formed by sputtering at the substrate temperature of 200° C. to 400° C., in which case precursors are aligned in the second oxide semiconductor layer deposited to be on and in contact with a surface of the first crystalline oxide semiconductor layer, and the second oxide semiconductor layer can thus have a crystalline order.
Here, a 25-nm-thick second oxide semiconductor layer is formed using a metal oxide target (an In—Ga—Zn—O-based metal oxide target with a composition ratio of In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]) under the following conditions: the distance between the substrate and the target is 170 mm, the substrate temperature is 400° C., the pressure is 0.4 Pa, the direct-current (DC) power is 0.5 kW, and the atmosphere is oxygen (the flow rate ratio of oxygen is 100%), argon (the flow rate ratio of argon is 100%), or an atmosphere containing argon and oxygen.
Next, the atmosphere in the chamber in which the substrate is put is set to a nitrogen atmosphere or dry air, and second heat treatment is performed. The temperature of the second heat treatment ranges from 400° C. to 750° C. With the second heat treatment, a second crystalline oxide semiconductor layer 450b is formed (see FIG. 37B). The second heat treatment is performed in a nitrogen atmosphere, an oxygen atmosphere, or a mixed atmosphere of nitrogen and oxygen to increase the density of the second crystalline oxide semiconductor layer and reduce defects. With the second heat treatment, crystal growth progresses in the thickness direction, that is, from the bottom to the inside, with the first crystalline oxide semiconductor layer 450a as a nucleus; thus, the second crystalline oxide semiconductor layer 450b is formed.
It is preferable to perform the steps from the formation of the insulating layer 437 to the second heat treatment successively without exposure to the air. The steps from the formation of the insulating layer 437 to the second heat treatment are preferably performed in an atmosphere that hardly contains hydrogen and moisture (e.g., an inert atmosphere, a reduced pressure atmosphere, or a dry air atmosphere). For example, a dry nitrogen atmosphere with a dew point of −40° C. or lower, preferably −50° C. or lower is used.
Next, the oxide semiconductor stack including the first crystalline oxide semiconductor layer 450a and the second crystalline oxide semiconductor layer 450b is processed so that an oxide semiconductor layer 453 made of the island-shaped oxide semiconductor stack is formed (see FIG. 37C). In FIGS. 37B and 37C, the interface between the first crystalline oxide semiconductor layer 450a and the second crystalline oxide semiconductor layer 450b is shown by doted lines to indicate the oxide semiconductor stack; a clear interface does not exist and FIGS. 37B and 37C show the interface for easy understanding.
The oxide semiconductor stack can be processed by etching after a mask with a desired shape is formed over the oxide semiconductor stack. The mask may be formed by photolithography, ink-jet printing, or the like.
For the etching of the oxide semiconductor stack, either wet etching or dry etching can be employed. Needless to say, both of them may be employed in combination.
Note that the first and second crystalline oxide semiconductor layers preferably contain at least indium (In) or zinc (Zn). In particular, the oxide semiconductor preferably contains In and Zn. As a stabilizer for reducing variation in electric characteristics of a transistor including the oxide semiconductor, the oxide semiconductor preferably contains gallium (Ga) in addition to In and Zn. Moreover, the oxide semiconductor preferably contains tin (Sn), hafnium (Hf), and/or aluminum (Al) as a stabilizer.
As another stabilizer, one or plural kinds of lanthanoid such as lantern (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) may be contained.
Examples of the oxide semiconductor to be used are an indium oxide; a tin oxide; a zinc oxide; an oxide of two metal elements, such as an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, and an In—Ga-based oxide; an oxide of three metal elements, such as an In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, and an In—Lu—Zn-based oxide; and an oxide of four metal elements, such as an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, and an In—Hf—Al—Zn-based oxide.
Note that here, for example, an “In—Ga—Zn-based oxide” means an oxide containing In, Ga, and Zn as its main components and there is no particular limitation on the composition ratio of In, Ga, and Zn. Further, a metal element in addition to In, Ga, and Zn may be contained.
In the case of using an In—Zn-based metal oxide, an oxide target having the following composition ratio can be used for forming an In—Zn-based semiconductor layer: In:Zn=50:1 to 1:2 in an atomic ratio (In2O3:ZnO=25:1 to 1:4 in a molar ratio), preferably In:Zn=20:1 to 1:1 in an atomic ratio (In2O3:ZnO=10:1 to 1:2 in a molar ratio), further preferably In:Zn=15:1 to 1.5:1 (In2O3:ZnO=15:2 to 3:4 in a molar ratio). For example, when the atomic ratio of the target used for the deposition of the In—Zn-based oxide semiconductor is expressed by In:Zn:O═P:U:R, R>1.5P+U is satisfied. An increase in the amount of indium can increase the mobility of the transistor.
Further, a material represented by InMO3(ZnO)m (m is larger than 0) may be used as the oxide semiconductor. Here, M in InMO3(ZnO)m represents one or more metal elements selected from Ga, Al, Mn, and Co.
For example, it is possible to use an In—Ga—Zn-based oxide with an atomic ratio of In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (=2/5:2/5:1/5), or an oxide whose composition is in the neighborhood of the above compositions. Alternatively, it is possible to use an In—Sn—Zn-based oxide with an atomic ratio of In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6:1/2), or In:Sn:Zn=2:1:5 (=1/4:1/8:5/8), or an oxide whose composition is in the neighborhood of the above compositions.
Without limitation to the above, an oxide semiconductor with an appropriate composition ratio can be used in accordance with desired semiconductor characteristics (e.g., mobility, threshold voltage, and variation). In order to obtain needed semiconductor characteristics, an oxide semiconductor preferably has appropriate carrier concentration, impurity concentration, defect density, atomic ratio of a metal element to oxygen, bond distance, density, or the like.
For example, high mobility can be relatively easily obtained with an In—Sn—Z-based oxide. Even when an In—Ga—Zn-based oxide is used, the mobility can be increased by a reduction in bulk defect density.
Note that the case where the composition of an oxide having an atomic ratio of In:Ga:Zn=a:b:c (a+b+c=1) is in the neighborhood of the composition of an oxide having an atomic ratio of In:Ga:Zn=A:B:C (A+B+C=1) means that a, b, and c satisfy the following relation: (a−A)2+(b−B)2+(c−C)2≦r2, and r may be 0.05, for example. The same can be applied to other oxides.
The oxide semiconductor may be single crystal or non-single-crystal. A non-single-crystal oxide semiconductor may be amorphous or polycrystalline. Further, the oxide semiconductor may have an amorphous structure including a portion having crystallinity or a non-amorphous structure.
In an oxide semiconductor in an amorphous state, a flat surface can be obtained with relative ease. When a transistor is formed using the oxide semiconductor in an amorphous state, interface scattering can be reduced, and relatively high mobility can be obtained with relative ease.
In an oxide semiconductor having crystallinity, defects in the bulk can be further reduced. When a surface flatness is improved, mobility higher than that of an oxide semiconductor in an amorphous state can be obtained. In order to improve the surface flatness, the oxide semiconductor is preferably formed on a flat surface. Specifically, it is preferable that the oxide semiconductor be formed on a surface with an average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, further preferably 0.1 nm or less.
Note that Ra is obtained by expanding centerline average roughness, which is defined by JIS B 0601, into three dimensions so as to be applicable to a surface. Moreover, Ra can be expressed as average value of the absolute values of deviations from a reference surface to a specific surface and is defined by the following formula.




  
    
      
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Note that in Formula 4, S0 represents the area of a measurement surface (a rectangular region defined by four points represented by the coordinates (x1,y1), (x1,y2), (x2,y1), and (x2,y2)), and Z0 represents average height of the measurement surface. Further, Ra can be measured with an atomic force microscope (AFM).
The first and second crystalline oxide semiconductor layers obtained by the above formation method have c-axis alignment. Note that the first and second crystalline oxide semiconductor layers includes an oxide including a crystal with c-axis alignment (also referred to as a c-axis aligned crystal (CAAC)), which has neither a single crystal structure nor an amorphous structure. Parts of the first and second crystalline oxide semiconductor layers include crystal grains.
In a broad sense, an oxide including CAAC means a non-single-crystal oxide including a phase that has a triangular, hexagonal, regular triangular, or regular hexagonal atomic arrangement when seen from the direction perpendicular to the a-b plane and in which metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis direction.
The CAAC is not a single crystal, but this does not mean that the CAAC is composed of only an amorphous component. Although the CAAC includes a crystallized portion (crystalline portion), a boundary between one crystalline portion and another crystalline portion is not clear in some cases.
In the case where oxygen is included in the CAAC, nitrogen may be substituted for part of oxygen included in the CAAC. The c-axes of individual crystalline portions included in the CAAC may be aligned in one direction (e.g., a direction perpendicular to a surface of a substrate over which the CAAC is formed or a surface of the CAAC). Alternatively, the normals of the a-b planes of the individual crystalline portions included in the CAAC may be aligned in one direction (e.g., a direction perpendicular to a surface of a substrate over which the CAAC is formed or a surface of the CAAC).
The CAAC becomes a conductor, a semiconductor, or an insulator depending on its composition or the like. The CAAC transmits or does not transmit visible light depending on its composition or the like.
An example of such a CAAC is a crystal which is formed into a film shape and has a triangular or hexagonal atomic arrangement when observed from the direction perpendicular to a surface of the film or a surface of a supporting substrate, and in which metal atoms are arranged in a layered manner or metal atoms and oxygen atoms (or nitrogen atoms) are arranged in a layered manner when a cross section of the film is observed.
Next, an example of a crystal structure of the CAAC will be described in detail with reference to FIGS. 39A to 39E, FIGS. 40A to 40C, and FIGS. 41A to 41C. In FIGS. 39A to 39E, FIGS. 40A to 40C, and FIGS. 41A to 41C, the vertical direction corresponds to the c-axis direction and a plane perpendicular to the c-axis direction corresponds to the a-b plane, unless otherwise specified. In the case where the expressions “an upper half” and “a lower half” are simply used, they refer to an upper half above the a-b plane and a lower half below the a-b plane (an upper half and a lower half with respect to the a-b plane). Furthermore, in FIGS. 39A to 39E, O surrounded by a circle represents tetracoodinate O and O surrounded by a double circle represents tricoodinate O.
FIG. 39A illustrates a structure including one hexacoordinate In atom and six tetracoordinate oxygen (hereinafter referred to as tetracoordinate O) atoms proximate to the In atom. Here, a structure including one metal atom and oxygen atoms proximate thereto is referred to as a small group. The structure in FIG. 39A is actually an octahedral structure, but is illustrated as a planar structure for simplicity. Note that three tetracoordinate O atoms exist in each of an upper half and a lower half in FIG. 39A. In the small group illustrated in FIG. 39A, electric charge is O.
FIG. 39B illustrates a structure including one pentacoordinate Ga atom, three tricoordinate oxygen (hereinafter referred to as tricoordinate O) atoms proximate to the Ga atom, and two tetracoordinate O atoms proximate to the Ga atom. All the tricoordinate O atoms exist on the a-b plane. One tetracoordinate O atom exists in each of an upper half and a lower half in FIG. 39B. An In atom can also have the structure illustrated in FIG. 39B because an In atom can have five ligands. In the small group illustrated in FIG. 39B, electric charge is 0.
FIG. 39C illustrates a structure including one tetracoordinate Zn atom and four tetracoordinate O atoms proximate to the Zn atom. In FIG. 39C, one tetracoordinate O atom exists in an upper half and three tetracoordinate O atoms exist in a lower half. Alternatively, three tetracoordinate O atoms may exist in the upper half and one tetracoordinate O atom may exist in the lower half in FIG. 39C. In the small group illustrated in FIG. 39C, electric charge is 0.
FIG. 39D illustrates a structure including one hexacoordinate Sn atom and six tetracoordinate O atoms proximate to the Sn atom. In FIG. 39D, three tetracoordinate O atoms exist in each of an upper half and a lower half. In the small group illustrated in FIG. 39D, electric charge is +1.
FIG. 39E illustrates a small group including two Zn atoms. In FIG. 39E, one tetracoordinate O atom exists in each of an upper half and a lower half. In the small group illustrated in FIG. 39E, electric charge is −1.
Here, a plurality of small groups form a medium group, and a plurality of medium groups form a large group (also referred to as a unit cell).
Now, a rule of bonding between the small groups will be described. The three O atoms in the upper half with respect to the hexacoordinate In atom in FIG. 39A each have three proximate In atoms in the downward direction, and the three O atoms in the lower half each have three proximate In atoms in the upward direction. The one O atom in the upper half with respect to the pentacoordinate Ga atom has one proximate Ga atom in the downward direction, and the one O atom in the lower half has one proximate Ga atom in the upward direction. The one O atom in the upper half with respect to the tetracoordinate Zn atom has one proximate Zn atom in the downward direction, and the three O atoms in the lower half each have three proximate Zn atoms in the upward direction. In this manner, the number of the tetracoordinate O atoms proximate to and above the metal atom is equal to the number of the metal atoms proximate to and below each of the tetracoordinate O atoms. Similarly, the number of the tetracoordinate O atoms proximate to and below the metal atom is equal to the number of the metal atoms proximate to and above each of the tetracoordinate O atoms. Since O atoms contributing the bonding between the small groups are the tetracoordinate O atoms, the sum of the number of the metal atoms proximate to and below the O atom and the number of the metal atoms proximate to and above the O atom is 4. Accordingly, when the sum of the number of tetracoordinate O atoms above a metal atom and the number of tetracoordinate O atoms below another metal atom is 4, the two kinds of small groups including the metal atoms can be bonded. For example, in the case where the hexacoordinate metal (In or Sn) atom is bonded through three tetracoordinate O atoms in the lower half, it is bonded to the pentacoordinate metal (Ga or In) atom or the tetracoordinate metal (Zn) atom.
A metal atom having the above coordination number is bonded to another metal atom having the above coordination number through a tetracoordinate O atom in the c-axis direction. In addition to the above, a medium group can be formed in a different manner by combining a plurality of small groups so that the total electric charge of the layered structure is 0.
FIG. 40A illustrates a model of a medium group included in a layered structure of an In—Sn—Zn—O-based material. FIG. 40B illustrates a large group including three medium groups. FIG. 40C illustrates an atomic arrangement in the case where the layered structure in FIG. 40B is observed from the c-axis direction.
In FIG. 40A, for simplicity, a tricoordinate O atom is omitted and tetracoordinate O atoms are shown by a circle; the number in the circle shows the number of tetracoordinate O atoms. For example, three tetracoordinate O atoms existing in each of an upper half and a lower half with respect to a Sn atom are denoted by circled 3. Similarly, in FIG. 40A, one tetracoordinate O atom existing in each of an upper half and a lower half with respect to an In atom is denoted by circled 1. FIG. 40A also illustrates a Zn atom proximate to one tetracoordinate O atom in a lower half and three tetracoordinate O atoms in an upper half, and a Zn atom proximate to one tetracoordinate O atom in an upper half and three tetracoordinate O atoms in a lower half.
In the medium group included in the layered structure of the In—Sn—Zn—O-based material in FIG. 40A, in the order starting from the top, a Sn atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half is bonded to an In atom proximate to one tetracoordinate O atom in each of an upper half and a lower half, the In atom is bonded to a Zn atom proximate to three tetracoordinate O atoms in an upper half, the Zn atom is bonded to an In atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half through one tetracoordinate O atom in a lower half with respect to the Zn atom, the In atom is bonded to a small group that includes two Zn atoms and is proximate to one tetracoordinate O atom in an upper half, and the small group is bonded to a Sn atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half through one tetracoordinate O atom in a lower half with respect to the small group. A plurality of such medium groups are bonded, so that a large group is formed.
Here, electric charge for one bond of a tricoordinate O atom and electric charge for one bond of a tetracoordinate O atom can be assumed to be −0.667 and −0.5, respectively. For example, electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate or hexacoordinate) Sn atom are +3, +2, and +4, respectively. Accordingly, electric charge in a small group including a Sn atom is +1. Therefore, electric charge of −1, which cancels +1, is needed to form a layered structure including a Sn atom. As a structure having electric charge of −1, the small group including two Zn atoms as illustrated in FIG. 39E can be given. For example, with one small group including two Zn atoms, electric charge of one small group including a Sn atom can be cancelled, so that the total electric charge of the layered structure can be 0.
When the large group illustrated in FIG. 40B is repeated, an In—Sn—Zn—O-based crystal (In2SnZn3O8) can be obtained. Note that a layered structure of the obtained In—Sn—Zn—O-based crystal can be expressed as a composition formula, In2SnZn2O7(ZnO), (m is 0 or a natural number).
The above-described rule also applies to the following oxides: an oxide of four metal elements, such as an In—Sn—Ga—Zn-based oxide; an oxide of three metal elements, such as an In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, and an In—Lu—Zn-based oxide; an oxide of two metal elements, such as an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, and an In—Ga-based oxide.
As an example, FIG. 41A illustrates a model of a medium group included in a layered structure of an In—Ga—Zn-based material.
In the medium group included in the layered structure of the In—Ga—Zn-based material in FIG. 41A, in the order starting from the top, an In atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half is bonded to a Zn atom proximate to one tetracoordinate O atom in an upper half, the Zn atom is bonded to a Ga atom proximate to one tetracoordinate O atom in each of an upper half and a lower half through three tetracoordinate O atoms in a lower half with respect to the Zn atom, and the Ga atom is bonded to an In atom proximate to three tetracoordinate O atoms in each of an upper half and a lower half through one tetracoordinate O atom in a lower half with respect to the Ga atom. A plurality of such medium groups are bonded, so that a large group is formed.
FIG. 41B illustrates a large group including three medium groups. FIG. 41C illustrates an atomic arrangement in the case where the layered structure in FIG. 41B is observed from the c-axis direction.
Here, since electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate) Ga atom are +3, +2, +3, respectively, electric charge of a small group including any of an In atom, a Zn atom, and a Ga atom is 0. As a result, the total electric charge of a medium group having a combination of such small groups is always 0.
In order to form the layered structure of the In—Ga—Zn—O-based material, a large group can be formed using not only the medium group illustrated in FIG. 41A but also a medium group in which the arrangement of the In atom, the Ga atom, and the Zn atom is different from that in FIG. 41A.
Without limitation to the two-layer structure in which the second crystalline oxide semiconductor layer is formed over the first crystalline oxide semiconductor layer, it is possible to employ a stacked structure including three or more layers, by conducting or repeating the steps of deposition and heat treatment for forming a third crystalline oxide semiconductor layer after the formation of the second crystalline oxide semiconductor layer.
A highly reliable transistor with stable electrical characteristics can be realized because the transistor includes a stack of a first crystalline oxide semiconductor layer and a second crystalline oxide semiconductor layer like the oxide semiconductor layer 453.
The actually measured field-effect mobility of an insulated gate transistor can be lower than its original mobility because of a variety of reasons; this phenomenon occurs not only in the case of using an oxide semiconductor. One of the reasons that reduce the mobility is a defect inside a semiconductor or a defect at an interface between the semiconductor and an insulating film. When a Levinson model is used, the field-effect mobility that is based on the assumption that no defect exists inside the semiconductor can be calculated theoretically.
Assuming that the original mobility and the measured field-effect mobility of a semiconductor are μ0 and μ, respectively, and a potential barrier (such as a grain boundary) exists in the semiconductor, the measured field-effect mobility μ can be expressed as the following formula.




  
    
      
        μ
        =
        
          
            μ
            0
          
          ⁢
          
            exp
            ⁡
            
              (
              
                -
                
                  E
                  kT
                
              
              )
            
          
        
      
    
    
      
        [
        
          Formula
          ⁢
          
            
          
          ⁢
          5
        
        ]
      
    
  




Here, E represents the height of the potential barrier, k represents the Boltzmann constant, and T represents the absolute temperature. When the potential barrier is assumed to be attributed to a defect, the height E of the potential barrier is expressed as the following formula according to the Levinson model.




  
    
      
        E
        =
        
          
            
              
                e
                2
              
              ⁢
              
                N
                2
              
            
            
              8
              ⁢
              ɛ
              ⁢
              
                
              
              ⁢
              n
            
          
          =
          
            
              
                e
                3
              
              ⁢
              
                N
                2
              
              ⁢
              t
            
            
              8
              ⁢
              ɛ
              ⁢
              
                
              
              ⁢
              
                C
                ox
              
              ⁢
              
                V
                g
              
            
          
        
      
    
    
      
        [
        
          Formula
          ⁢
          
            
          
          ⁢
          6
        
        ]
      
    
  




Here, e represents the elementary charge, N represents the average defect density per unit area in a channel, e represents the permittivity of the semiconductor, n represents the number of carriers per unit area in the channel, Cox represents the capacitance per unit area, Vg represents the gate voltage, and t represents the thickness of the channel. Note that in the case where the thickness of the semiconductor layer is less than or equal to 30 nm, the thickness of the channel may be regarded as being the same as the thickness of the semiconductor layer. The drain current Id in a linear region is expressed as the following formula.




  
    
      
        
          I
          d
        
        =
        
          
            
              W
              ⁢
              
                
              
              ⁢
              μ
              ⁢
              
                
              
              ⁢
              
                V
                g
              
              ⁢
              
                V
                d
              
              ⁢
              
                C
                ox
              
            
            L
          
          ⁢
          
            exp
            ⁡
            
              (
              
                -
                
                  E
                  kT
                
              
              )
            
          
        
      
    
    
      
        [
        
          Formula
          ⁢
          
            
          
          ⁢
          7
        
        ]
      
    
  




Here, L represents the channel length and W represents the channel width, and L and W are each 10 μm. In addition, Vd represents the drain voltage. When dividing both sides of the above equation by Vg and then taking logarithms of both sides, the following formula can be obtained.




  
    
      
        
          ln
          (
          
            
              I
              d
            
            
              V
              g
            
          
          )
        
        =
        
          
            
              ln
              ⁡
              
                (
                
                  
                    W
                    ⁢
                    
                      
                    
                    ⁢
                    μ
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      d
                    
                    ⁢
                    
                      C
                      ox
                    
                  
                  L
                
                )
              
            
            -
            
              E
              kT
            
          
          =
          
            
              ln
              ⁡
              
                (
                
                  
                    W
                    ⁢
                    
                      
                    
                    ⁢
                    μ
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      d
                    
                    ⁢
                    
                      C
                      ox
                    
                  
                  L
                
                )
              
            
            -
            
              
                
                  e
                  3
                
                ⁢
                
                  N
                  2
                
                ⁢
                t
              
              
                8
                ⁢
                kT
                ⁢
                
                  
                
                ⁢
                ɛ
                ⁢
                
                  
                
                ⁢
                
                  C
                  ox
                
                ⁢
                
                  V
                  g
                
              
            
          
        
      
    
    
      
        [
        
          Formula
          ⁢
          
            
          
          ⁢
          8
        
        ]
      
    
  




The right side of Formula 8 is a function of Vg. From the formula, it is found that the defect density N can be obtained from the slope of a line in a graph that is obtained by plotting actual measured values with ln(Id/Vg) as the ordinate and 1/Vg as the abscissa. That is, the defect density can be evaluated from the Id—Vg characteristics of the transistor. The defect density N of an oxide semiconductor in which the ratio of indium (In), tin (Sn), and zinc (Zn) is 1:1:1 is approximately 1×1012/cm2.
On the basis of the defect density obtained in this manner, μ0 can be calculated to be 120 cm2/Vs from Formula 5 and Formula 6. The measured mobility of an In—Sn—Zn oxide including a defect is approximately 40 cm2/Vs. However, assuming that no defect exists inside an oxide semiconductor and at the interface between the oxide semiconductor and an insulating film, the mobility μ0 of the oxide semiconductor is expected to be 120 cm2/Vs.
Note that even when no defect exists inside a semiconductor, scattering at an interface between a channel and a gate insulating layer adversely affects the transport properties of the transistor. In other words, the mobility μ1 at a position that is distance x away from the interface between the channel and the gate insulating layer can be expressed as the following formula.




  
    
      
        
          1
          
            μ
            1
          
        
        =
        
          
            1
            
              μ
              0
            
          
          +
          
            
              D
              B
            
            ⁢
            
              exp
              ⁡
              
                (
                
                  -
                  
                    x
                    l
                  
                
                )
              
            
          
        
      
    
    
      
        [
        
          Formula
          ⁢
          
            
          
          ⁢
          9
        
        ]
      
    
  




Here, D represents the electric field in the gate direction, and B and l are constants. B and l can be obtained from actual measurement results; according to the above measurement results, B is 4.75×107 cm/s and l is 10 nm (the depth to which the influence of interface scattering reaches). When D is increased (i.e., when the gate voltage is increased), the second term of Formula 9 is increased and accordingly the mobility μ1 is decreased.
FIG. 42 shows calculation results of the mobility μ2 of a transistor whose channel is formed using an ideal oxide semiconductor without a defect inside the semiconductor. For the calculation, device simulation software Sentaurus Device manufactured by Synopsys, Inc. was used, and the band gap, the electron affinity, the relative permittivity, and the thickness of the oxide semiconductor were assumed to be 2.8 eV, 4.7 eV, 15, and 15 nm, respectively. These values were obtained by measurement of a thin film that was formed by sputtering.
Further, the work functions of a gate, a source, and a drain were assumed to be 5.5 eV, 4.6 eV, and 4.6 eV, respectively. The thickness of a gate insulating layer was assumed to be 100 nm, and the relative permittivity thereof was assumed to be 4.1. The channel length and the channel width were each assumed to be 10 μm, and the drain voltage Vd was assumed to be 0.1 V.
As shown in FIG. 42, the mobility has a peak of more than 100 cm2/Vs at a gate voltage that is a little over 1 V, and is decreased as the gate voltage becomes higher because the influence of interface scattering is increased. Note that in order to reduce interface scattering, it is preferable that a surface of the semiconductor layer be flat at the atomic level (atomic layer flatness).
Calculation results of characteristics of minute transistors formed using an oxide semiconductor having such a mobility are shown in FIGS. 43A to 43C, FIGS. 44A to 44C, and FIGS. 45A to 45C. FIGS. 46A and 46B illustrate cross-sectional structures of the transistors used for the calculation. The transistors illustrated in FIGS. 46A and 46B each include a semiconductor region 703a and a semiconductor region 703c that have n+-type conductivity in an oxide semiconductor layer. The resistivity of the semiconductor regions 703a and 703c is 2×10−3 Ωcm.
The transistor in FIG. 46A is formed over a base insulating layer 701 and an embedded insulator 702 that is embedded in the base insulating layer 701 and formed of aluminum oxide. The transistor includes the semiconductor region 703a, the semiconductor region 703c, an intrinsic semiconductor region 703b that is placed between the semiconductor regions 703a and 703c and serves as a channel formation region, and a gate 705. The width of the gate 705 is 33 nm.
A gate insulating layer 704 is formed between the gate 705 and the semiconductor region 703b. A sidewall insulator 706a and a sidewall insulator 706b are formed on both side surfaces of the gate 705, and an insulator 707 is formed over the gate 705 so as to prevent a short circuit between the gate 705 and another wiring. The sidewall insulator has a width of 5 nm. A source 708a and a drain 708b are provided in contact with the semiconductor region 703a and the semiconductor region 703c, respectively. Note that the channel width of this transistor is 40 nm.
The transistor in FIG. 46B is the same as the transistor in FIG. 46A in that it is formed over the base insulating layer 701 and the embedded insulator 702 formed of aluminum oxide and that it includes the semiconductor region 703a, the semiconductor region 703c, the intrinsic semiconductor region 703b provided therebetween, the gate 705 having a width of 33 nm, the gate insulating layer 704, the sidewall insulator 706a, the sidewall insulator 706b, the insulator 707, the source 708a, and the drain 708b. 
The difference between the transistor in FIG. 46A and the transistor in FIG. 46B is the conductivity type of semiconductor regions under the sidewall insulators 706a and 706b. In the transistor in FIG. 46A, the semiconductor regions under the sidewall insulator 706a and the sidewall insulator 706b are part of the semiconductor region 703a having n+-type conductivity and part of the semiconductor region 703c having n+-type conductivity, whereas in the transistor in FIG. 46B, the semiconductor regions under the sidewall insulator 706a and the sidewall insulator 706b are part of the intrinsic semiconductor region 703b. In other words, in the semiconductor layer of FIG. 46B, a region having a width of Loff which overlaps with neither the semiconductor region 703a (the semiconductor region 703c) nor the gate 705 is provided. This region is called an offset region, and the width Loff is called an offset length. As is seen from the drawing, the offset length is equal to the width of the sidewall insulator 706a (the sidewall insulator 706b).
The other parameters used in calculation are as described above. For the calculation, device simulation software Sentaurus Device manufactured by Synopsys, Inc. was used. FIGS. 43A to 43C show the gate voltage (Vg: a potential difference between the gate and the source) dependence of the drain current (Id, a solid line) and the mobility (μ, a dotted line) of the transistor having the structure illustrated in FIG. 46A. The drain current Id is obtained by calculation under the assumption that the drain voltage (a potential difference between the drain and the source) is +1 V, and the mobility μ is obtained by calculation under the assumption that the drain voltage is +0.1 V.
FIG. 43A shows the gate voltage dependence of the transistor in the case where the thickness of the gate insulating layer is 15 nm, FIG. 43B shows that of the transistor in the case where the thickness of the gate insulating layer is 10 nm, and FIG. 43C shows that of the transistor in the case where the thickness of the gate insulating layer is 5 nm. As the gate insulating layer is thinner, the drain current Id in an off state (the off-state current) in particular is significantly decreased. In contrast, there is no noticeable change in the peak value of the mobility μ and the drain current Id in an on state (the on-state current). The graphs show that the drain current exceeds 10 μA at a gate voltage of around 1 V.
FIGS. 44A to 44C show the gate voltage Vg dependence of the drain current Id (a solid line) and the mobility μ (a dotted line) of the transistor having the structure in FIG. 46B and an offset length Loff of 5 nm. The drain current Id is obtained by calculation under the assumption that the drain voltage is +1 V and the mobility μ is obtained by calculation under the assumption that the drain voltage is +0.1 V. FIG. 44A shows the gate voltage dependence of the transistor in the case where the thickness of the gate insulating layer is 15 nm, FIG. 44B shows that of the transistor in the case where the thickness of the gate insulating layer is 10 nm, and FIG. 44C shows that of the transistor in the case where the thickness of the gate insulating layer is 5 nm.
FIGS. 45A to 45C show the gate voltage dependence of the drain current Id (a solid line) and the mobility μ (a dotted line) of the transistor having the structure in FIG. 46B and an offset length Loff of 15 nm. The drain current Id is obtained by calculation under the assumption that the drain voltage is +1 V and the mobility μ is obtained by calculation under the assumption that the drain voltage is +0.1 V. FIG. 45A shows the gate voltage dependence of the transistor in the case where the thickness of the gate insulating layer is 15 nm, FIG. 45B shows that of the transistor in the case where the thickness of the gate insulating layer is 10 nm, and FIG. 45C shows that of the transistor in the case where the thickness of the gate insulating layer is 5 nm.
In either of the structures, as the gate insulating layer is thinner, the off-state current is significantly decreased, whereas no noticeable change arises in the peak value of the mobility μ and the on-state current.
Note that the peak of the mobility μ is approximately 80 cm2/Vs in FIGS. 43A to 43C, approximately 60 cm2/Vs in FIGS. 44A to 44C, and approximately 40 cm2/Vs in FIGS. 45A to 45C; thus, the peak of the mobility μ is decreased as the offset length Loff is increased. Further, the same applies to the off-state current. The on-state current is also decreased as the offset length Loff is increased; however, the decrease in the on-state current is much more gradual than the decrease in the off-state current. Further, the graphs show that in either of the structures, the drain current exceeds 10 μA at a gate voltage of around 1 V.
A transistor in which an oxide semiconductor including In, Sn, and Zn as main components is used as a channel formation region can have favorable characteristics by depositing the oxide semiconductor while heating a substrate or by performing heat treatment after an oxide semiconductor layer is formed. Note that a main component refers to an element included in a composition at 5 atomic % or more.
By intentionally heating the substrate after formation of the oxide semiconductor layer including In, Sn, and Zn as main components, the field-effect mobility of the transistor can be improved. Further, the threshold voltage of the transistor can be positively shifted to make the transistor nominally off.
As an example, FIGS. 49A to 49C each show characteristics of a transistor that includes an oxide semiconductor layer including In, Sn, and Zn as main components and having a channel length L of 3 μm and a channel width W of 10 μm, and a gate insulating layer with a thickness of 100 nm. Note that Vd was set to 10 V.
FIG. 49A shows characteristics of a transistor whose oxide semiconductor layer including In, Sn, and Zn as main components was formed by sputtering without heating a substrate intentionally. A peak of the field-effect mobility of the transistor is 18.8 cm2/Vsec. On the other hand, when the oxide semiconductor layer including In, Sn, and Zn as main components is formed while heating the substrate intentionally, the field-effect mobility can be improved. FIG. 49B shows characteristics of a transistor whose oxide semiconductor layer including In, Sn, and Zn as main components was formed while heating a substrate at 200° C. A peak of the field-effect mobility of the transistor is 32.2 cm2/Vsec.
The field-effect mobility can be further improved by performing heat treatment after formation of the oxide semiconductor layer including In, Sn, and Zn as main components. FIG. 49C shows characteristics of a transistor whose oxide semiconductor layer including In, Sn, and Zn as main components was formed by sputtering at 200° C. and then subjected to heat treatment at 650° C. A peak of the field-effect mobility of the transistor is 34.5 cm2/Vsec.
The intentional heating of the substrate is expected to have an effect of reducing moisture taken into the oxide semiconductor layer during the formation by sputtering. Further, the heat treatment after film formation enables hydrogen, a hydroxyl group, or moisture to be released and removed from the oxide semiconductor layer. In this manner, the field-effect mobility can be improved. Such an improvement in field-effect mobility is presumed to be achieved not only by removal of impurities by dehydration or dehydrogenation but also by a reduction in interatomic distance due to an increase in density. In addition, the oxide semiconductor can be crystallized by being highly purified by removal of impurities from the oxide semiconductor. In the case of using such a highly purified non-single-crystal oxide semiconductor, ideally, a field-effect mobility exceeding 100 cm2/Vsec is expected to be realized.
The oxide semiconductor including In, Sn, and Zn as main components may be crystallized in the following manner oxygen ions are implanted into the oxide semiconductor, hydrogen, a hydroxyl group, or moisture included in the oxide semiconductor is released by heat treatment, and the oxide semiconductor is crystallized through the heat treatment or by another heat treatment performed later. By such crystallization treatment or recrystallization treatment, a non-single-crystal oxide semiconductor having favorable crystallinity can be obtained.
The intentional heating of the substrate during film formation and/or the heat treatment after the film formation contributes not only to improving field-effect mobility but also to making the transistor normally off. In a transistor in which an oxide semiconductor layer that includes In, Sn, and Zn as main components and is formed without heating a substrate intentionally is used as a channel formation region, the threshold voltage tends to be shifted negatively. In contrast, when the oxide semiconductor layer formed while heating the substrate intentionally is used, the problem of the negative shift of the threshold voltage can be solved. That is, the threshold voltage is shifted so that the transistor becomes normally off; this tendency can be confirmed by comparison between FIGS. 49A and 49B.
Note that the threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn; when the composition ratio of In, Sn, and Zn is 2:1:3, a normally-off transistor is expected to be formed. In addition, an oxide semiconductor layer having high crystallinity can be obtained by setting the composition ratio of a target as follows: In:Sn:Zn=2:1:3.
The temperature of the intentional heating of the substrate or the temperature of the heat treatment is 150° C. or higher, preferably 200° C. or higher, further preferably 400° C. or higher. When film formation or heat treatment is performed at a high temperature, the transistor can be normally off.
By intentionally heating the substrate during film formation and/or by performing heat treatment after the film formation, the stability against a gate-bias stress can be increased. For example, when a gate bias is applied with an intensity of 2 MV/cm at 150° C. for one hour, drift of the threshold voltage can be less than ±1.5 V, preferably less than ±1.0 V.
A BT test was performed on the following two transistors: Sample 1 on which heat treatment was not performed after formation of an oxide semiconductor layer, and Sample 2 on which heat treatment at 650° C. was performed after formation of an oxide semiconductor film.
First, Vgs-Ids characteristics of the transistors were measured at a substrate temperature of 25° C. and Vds of 10 V. Note that Vds refers to a drain voltage (a potential difference between the drain and the source). Then, the substrate temperature was set to 150° C. and Vds was set to 0.1 V. After that, Vgs of 20 V was applied so that the intensity of an electric field applied to a gate insulating layer 608 was 2 MV/cm, and the condition was kept for one hour. Next, Vgs was set to 0 V. Then, Vgs-Ids characteristics of the transistors were measured at a substrate temperature of 25° C. and Vds of 10 V. This process is called a positive BT test.
In a similar manner, first, Vgs-Ids characteristics of the transistors were measured at a substrate temperature of 25° C. and Vds of 10 V. Then, the substrate temperature was set at 150° C. and Vds was set to 0.1 V. After that, Vgs of −20 V was applied so that the intensity of an electric field applied to the gate insulating layers was −2 MV/cm, and the condition was kept for one hour. Next, Vgs was set to 0 V. Then, Vgs-Ids characteristics of the transistors were measured at a substrate temperature of 25° C. and Vds of 10 V. This process is called a negative BT test.
FIGS. 50A and 50B show results of the positive BT test and the negative BT test, respectively, of Sample 1. FIGS. 51A and 51B show results of the positive BT test and the negative BT test, respectively, of Sample 2.
The amount of shift in the threshold voltage of Sample 1 due to the positive BT test and that due to the negative BT test were 1.80 V and −0.42 V, respectively. The amount of shift in the threshold voltage of Sample 2 due to the positive BT test and that due to the negative BT test were 0.79 V and 0.76 V, respectively. It is found that, in each of Sample 1 and Sample 2, the amount of shift in the threshold voltage between before and after the BT tests is small and the reliability is high.
The heat treatment can be performed in an oxygen atmosphere; alternatively, the heat treatment may be performed first in an atmosphere of nitrogen or an inert gas or under reduced pressure, and then in an atmosphere including oxygen. Oxygen is supplied to the oxide semiconductor film after dehydration or dehydrogenation, whereby the effect of the heat treatment can be further increased. As a method for supplying oxygen after dehydration or dehydrogenation, a method in which oxygen ions are accelerated by an electric field and implanted into the oxide semiconductor layer may be employed.
A defect due to oxygen vacancy is easily caused in the oxide semiconductor or at an interface between the oxide semiconductor and a film in contact with the oxide semiconductor; when excess oxygen is included in the oxide semiconductor by the heat treatment, oxygen vacancy caused later can be compensated for with excess oxygen. The excess oxygen is mainly oxygen existing between lattices. When the concentration of oxygen is set in the range of 1×1016/cm3 to 2×1020/cm3, excess oxygen can be included in the oxide semiconductor without causing crystal distortion or the like.
When heat treatment is performed so that at least part of the oxide semiconductor includes crystal, a more stable oxide semiconductor layer can be obtained. For example, when an oxide semiconductor layer that is formed by sputtering using a target having a composition ratio of In:Sn:Zn=1:1:1 without heating a substrate intentionally is analyzed by X-ray diffraction (XRD), a halo pattern is observed. The formed oxide semiconductor layer can be crystallized by being subjected to heat treatment. The temperature of the heat treatment can be set as appropriate; when the heat treatment is performed at 650° C., for example, a clear diffraction peak can be observed with X-ray diffraction.
An XRD analysis of an In—Sn—Zn—O film was conducted. The XRD analysis was conducted using an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS, and measurement was performed by an out-of-plane method.
Sample A and Sample B were prepared and the XRD analysis was performed thereon. A method for forming Sample A and Sample B will be described below.
An In—Sn—Zn—O film with a thickness of 100 nm was formed over a quartz substrate that had been subjected to dehydrogenation treatment.
The In—Sn—Zn—O film was formed with a sputtering apparatus with a power of 100 W (DC) in an oxygen atmosphere. An In—Sn—Zn—O target having an atomic ratio of In:Sn:Zn=1:1:1 was used as a target. Note that the substrate heating temperature in film formation was set at 200° C. A sample formed in this manner was used as Sample A.
Next, a sample formed by a method similar to that of Sample A was subjected to heat treatment at 650° C. As the heat treatment, heat treatment in a nitrogen atmosphere was first performed for one hour and heat treatment in an oxygen atmosphere was further performed for one hour without lowering the temperature. A sample formed in this manner was used as Sample B.
FIG. 54 shows XRD spectra of Sample A and Sample B. No peak derived from crystal was observed in Sample A, whereas peaks derived from crystal were observed when 20 was around 35 deg. and at 37 deg. to 38 deg. in Sample B.
As described above, by intentionally heating a substrate during deposition of an oxide semiconductor including In, Sn, and Zn as main components and/or by performing heat treatment after the deposition, characteristics of a transistor can be improved.
These substrate heating and heat treatment have an effect of preventing hydrogen and a hydroxyl group, which are unfavorable impurities for an oxide semiconductor, from being included in the film or an effect of removing hydrogen and a hydroxyl group from the film. That is, an oxide semiconductor can be highly purified by removing hydrogen serving as a donor impurity from the oxide semiconductor, whereby a normally-off transistor can be obtained. The high purification of an oxide semiconductor enables the off-state current of the transistor to be 1 aA/μm or lower. Here, the unit of the off-state current represents current per micrometer of a channel width.
FIG. 55 shows a relation between the off-state current of a transistor and the inverse of substrate temperature (absolute temperature) at measurement. Here, for simplicity, the horizontal axis represents a value (1000/T) obtained by multiplying an inverse of substrate temperature at measurement by 1000. Specifically, as shown in FIG. 55, the off-state current can be 1 aA/μm (1×10−18 A/μm) or lower, 100 zA/μm (1×10−19 A/μm) or lower, and 1 zA/μm (1×10−21 A/μm) or lower when the substrate temperature is 125° C., 85° C., and room temperature (27° C.), respectively. Preferably, the off-state current can be 0.1 aA/μm (1×10−19 A/μm) or lower, 10 zA/μm (1×10−20 A/μm) or lower, and 0.1 zA/μm (1×10−22 A/μm) or lower at 125° C., 85° C., and room temperature, respectively.
Note that in order to prevent hydrogen and moisture from being included in the oxide semiconductor layer during formation of the film, it is preferable to increase the purity of a sputtering gas by sufficiently suppressing leakage from the outside of a deposition chamber and degasification through an inner wall of the deposition chamber. For example, a gas with a dew point of −70° C. or lower is preferably used as the sputtering gas in order to prevent moisture from being included in the film. In addition, it is preferable to use a target that is highly purified so as not to include impurities such as hydrogen and moisture. Although it is possible to remove moisture from a film of an oxide semiconductor including In, Sn, and Zn as main components by heat treatment, a film that does not include moisture originally is preferably formed because moisture is released from the oxide semiconductor including In, Sn, and Zn as main components at a higher temperature than from an oxide semiconductor including In, Ga, and Zn as main components.
The relation between the substrate temperature and electric characteristics of the transistor using Sample B, on which heat treatment at 650° C. was performed after formation of the oxide semiconductor layer, was evaluated.
The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, Lov of 3 μm on one side (total Lov of 6 μm), and dW of 0 μm. Note that Vds was set to 10 V. Note that the substrate temperature was −40° C., −25° C., 25° C., 75° C., 125° C., and 150° C. Here, in the transistor, the width of a portion where a gate electrode overlaps with one of a pair of electrodes is referred to as Lov, and the width of a portion of the pair of electrodes, which does not overlap with an oxide semiconductor layer, is referred to as dW.
FIG. 52 shows the Vgs dependence of Ids (a solid line) and field-effect mobility (a dotted line). FIG. 53A shows a relation between the substrate temperature and the threshold voltage, and FIG. 53B shows a relation between the substrate temperature and the field-effect mobility.
From FIG. 53A, it is found that the threshold voltage gets lower as the substrate temperature increases. Note that the threshold voltage is decreased from 0.38 V to −1.08 V in the range from −40° C. to 150° C.
From FIG. 53B, it is found that the field-effect mobility gets lower as the substrate temperature increases. Note that the field-effect mobility is decreased from 37.4 cm2/Vs to 33.4 cm2/Vs in the range from −40° C. to 150° C. Thus, it is found that variation in electric characteristics is small in the above temperature range.
In a transistor in which such an oxide semiconductor including In, Sn, and Zn as main components is used as a channel formation region, a field-effect mobility of 30 cm2/Vsec or higher, preferably 40 cm2/Vsec or higher, further preferably 60 cm2/Vsec or higher can be obtained with the off-state current maintained at 1 aA/μm or lower, which can achieve on-state current needed for an LSI. For example, in an FET where L/W is 33 nm/40 nm, an on-state current of 12 μA or higher can flow when the gate voltage is 2.7 V and the drain voltage is 1.0 V. In addition, sufficient electric characteristics can be ensured in a temperature range needed for operation of a transistor. With such characteristics, an integrated circuit having a novel function can be realized without decreasing the operation speed even when a transistor including an oxide semiconductor is provided in an integrated circuit formed using a Si semiconductor.
Next, an example of a transistor in which an In—Sn—Zn—O film is used as an oxide semiconductor layer will be described with reference to FIGS. 47A and 47B.
FIGS. 47A and 47B are a top view and a cross-sectional view of a coplanar transistor having a top-gate top-contact structure. FIG. 47A is the top view of the transistor. FIG. 47B illustrates cross section A-B along dashed-dotted line A-B in FIG. 47A.
The transistor illustrated in FIG. 47B includes a substrate 750; a base insulating layer 752 provided over the substrate 750; a protective insulating layer 754 provided in the periphery of the base insulating layer 752; an oxide semiconductor layer 756 that is provided over the base insulating layer 752 and the protective insulating layer 754 and includes a high-resistance region 756a and low-resistance regions 756b; a gate insulating layer 758 provided over the oxide semiconductor layer 756; a gate electrode 760 provided to overlap with the oxide semiconductor layer 756 with the gate insulating layer 758 positioned therebetween; a sidewall insulating film 762 provided in contact with a side surface of the gate electrode 760; a pair of electrodes 764 provided in contact with at least the low-resistance regions 756b; an interlayer insulating layer 766 provided to cover at least the oxide semiconductor layer 756, the gate electrode 760, and the pair of electrodes 764; and a wiring 768 provided to be connected to at least one of the pair of electrodes 764 through an opening formed in the interlayer insulating layer 766.
Although not illustrated, a protective film may be provided to cover the interlayer insulating layer 766 and the wiring 768. With the protective layer, a minute amount of leakage current generated by surface conduction of the interlayer insulating layer 766 can be reduced, so that the off-state current of the transistor can be reduced.
Next, another example of a transistor in which an In—Sn—Zn—O film is used as an oxide semiconductor layer will be described.
FIGS. 48A and 48B are a top view and a cross-sectional view illustrating a structure of a transistor. FIG. 48A is the top view of the transistor. FIG. 48B is a cross-sectional view along dashed-dotted line A-B in FIG. 48A.
The transistor illustrated in FIG. 48B includes a substrate 600; a base insulating layer 602 provided over the substrate 600; an oxide semiconductor layer 606 provided over the base insulating layer 602; a pair of electrodes 614 in contact with the oxide semiconductor layer 606; a gate insulating layer 608 provided over the oxide semiconductor layer 606 and the pair of electrodes 614; a gate electrode 610 provided to overlap with the oxide semiconductor layer 606 with the gate insulating layer 608 positioned therebetween; an interlayer insulating layer 616 provided to cover the gate insulating layer 608 and the gate electrode 610; wirings 618 connected to the pair of electrodes 614 through openings formed in the interlayer insulating layer 616; and a protective layer 620 provided to cover the interlayer insulating layer 616 and the wirings 618.
As the substrate 600, a glass substrate was used. As the base insulating layer 602, a silicon oxide film was used. As the oxide semiconductor layer 606, an In—Sn—Zn—O film was used. As the pair of electrodes 614, a tungsten film was used. As the gate insulating layer 608, a silicon oxide film was used. The gate electrode 610 had a stacked structure of a tantalum nitride film and a tungsten film. The interlayer insulating layer 616 had a stacked structure of a silicon oxynitride film and a polyimide film. The wirings 618 had a stacked structure in which a titanium film, an aluminum film, and a titanium film were formed in this order. As the protective layer 620, a polyimide film was used.
Note that in the transistor having the structure illustrated in FIG. 48A, the width of a portion where the gate electrode 610 overlaps with one of the pair of electrodes 614 is referred to as Lov. Similarly, the width of a portion of the pair of electrodes 614, which does not overlap with the oxide semiconductor layer 606, is referred to as dW.
Application Example of Latch Circuit
FIG. 38A illustrates an example of a semiconductor device including the above-described latch circuit. The semiconductor device in FIG. 38A includes a memory cell array 200 in which a plurality of memory cells are arranged; a row selection circuit 201 that selects a given row in the memory cell array 200; a column selection circuit 202 that selects a given column in the memory cell array 200; and a data latch circuit 203 that temporarily hold data to be written or read data in one of the plurality of memory cells, which is selected by the row selection circuit 201 and the column selection circuit 202. The data latch circuit 203 is constituted by a plurality of the above latch circuits. Consequently, the scale of the data latch circuit 203 can be reduced (the number of transistors can be reduced), and the circuit scale of the semiconductor device can be reduced as a result.
Further, in the semiconductor device, the plurality of memory cells included in the memory cell array 200 can be formed using transistors whose channel region is formed with an oxide semiconductor.
FIG. 38B is a circuit diagram illustrating a specific example of the memory cell. The memory cell in FIG. 38B includes a transistor 301, a transistor 303, and a capacitor 304. A gate of the transistor 301 is electrically connected to a write word line 305. One of a source and a drain of the transistor 301 is electrically connected to a write bit line 308. A gate of the transistor 303 is electrically connected to the other of the source and the drain of the transistor 301. One of a source and a drain of the transistor 303 is electrically connected to a read bit line 307. The other of the source and the drain of the transistor 303 is electrically connected to a fixed potential line 309. One electrode of the capacitor 304 is electrically connected to the other of the source and the drain of the transistor 301 and the gate of the transistor 303. The other electrode of the capacitor 304 is electrically connected to a read word line 306. Note that a node X refers to a node where the other of the source and the drain of the transistor 301, the gate of the transistor 303, and one electrode of the capacitor 304 are electrically connected to each other. As a potential supplied to the fixed potential line 309, a ground potential (GND) or 0 (V) can be used, for example. In addition, the transistor 301 is a transistor whose channel region is formed with an oxide semiconductor (OS); on the other hand, there is no particular limitation on the semiconductor material for forming a channel region of the transistor 303.
In the memory cell in FIG. 38B, switching of the transistor 303 can be controlled in accordance with the potential of the node X. Moreover, the potential of the node X can be controlled by capacitive coupling with the read word line 306. The memory cell in FIG. 38B can therefore store multi-level data. That is, by judging the state (the on state or the off state) of the transistor 303 under a plurality of conditions with different potentials of the read word line 306, data can be read out even when the potential of the node X is a multivalued potential. Note that the data reading can be performed by, for example, judging an output signal of a voltage divider circuit constituted by the transistor 303. Further, the memory cell in FIG. 38B can also be used as a memory cell that stores binary data.
FIG. 38C is a circuit diagram illustrating a specific example of a memory cell different from that in FIG. 38B. The memory cell in FIG. 38C is one of n memory cells arranged in one column. The memory cell includes a transistor 311, a transistor 312, and a capacitor 313. A gate of the transistor 311 is electrically connected to a write word line 314. One of a source and a drain of the transistor 311 is electrically connected to a bit line 315. A gate of the transistor 312 is electrically connected to the other of the source and the drain of the transistor 311. One electrode of the capacitor 313 is electrically connected to the other of the source and the drain of the transistor 311 and the gate of the transistor 312. The other electrode of the capacitor 313 is electrically connected to a read word line 316. In addition, one of the source and the drain of the transistor 312 in the k-th memory cell (k is a natural number greater than or equal to 2 and less than n) is electrically connected to the other of the source and the drain of the transistor 312 in the (k−1)th memory cell. The other of the source and the drain of the transistor 312 in the k-th memory cell is electrically connected to one of the source and the drain of the transistor 312 in the (k+1)th memory cell. Note that one of the source and the drain of the transistor 312 in the first memory cell functions as an output terminal. The other of the source and the drain of the transistor 312 in the n-th memory cell is grounded. Note that a node Y refers to a node where the other of the source and the drain of the transistor 311, the gate of the transistor 312, and one electrode of the capacitor 313 are electrically connected to each other. Note that the transistor 311 in the memory cell in FIG. 38C is a transistor whose channel region is formed with an oxide semiconductor (OS); on the other hand, there is no particular limitation on the semiconductor material for forming a channel region of the transistor 312 in the memory cell.
In the memory cell in FIG. 38C, switching of the transistor 312 can be controlled in accordance with the potential of the node Y. Moreover, the potential of the node Y can be controlled by capacitive coupling with the read word line 316. Note that in a semiconductor device including the memory cell illustrated in FIG. 38C, in order to read data held in any one of n memory cells arranged in one column, the potentials of read word lines 316 connected to (n−1) memory cells other than the memory cell subjected to data reading are raised to high-level potentials. Thus, the transistors 312 included in the (n−1) memory cells other than the memory cell subjected to data reading are turned on. Consequently, one of the source and the drain of the transistor 312 in the memory cell subjected to data reading becomes electrically connected to the output terminal, and the other of the source and the drain thereof becomes grounded. Here, data can be obtained by judging the state (the on state or the off state) of the transistor 312 in the memory cell subjected to data reading. Specifically, data can be obtained in such a manner that, for example, a voltage divider circuit is constituted by the transistor 312 included in the memory cell subjected to data reading and an output signal of the voltage divider circuit is judged. Note that in order to judge multi-level data in the memory cell in FIG. 38C, the state (the on state or the off state) of the transistor 312 needs to be judged under a plurality of conditions with different potentials of the read word line 316. Further, the memory cell in FIG. 38C can also be used as a memory cell that stores binary data.
In each of the memory cells illustrated in FIGS. 38B and 38C, data is held in the node that is electrically connected to the other of the source and the drain of the transistor whose channel region is formed with an oxide semiconductor and is brought into a floating state when the transistor is turned off. As has been described, the off-state current (leakage current) of the transistor whose channel region is formed with an oxide semiconductor is extremely low. Therefore, the memory cell has excellent data retention. In addition, the memory cell array 200 including the memory cell can be formed over one substrate through the same process as the data latch circuit 203. The number of steps for forming the semiconductor device can be reduced as a result. Thus, the reduction in production cost, the increase in yield, and the like can be achieved.
This application is based on Japanese Patent Application serial No. 2010-188727 and No. 2011-107809 filed with Japan Patent Office on Aug. 25, 2010 and May 13, 2011, respectively, the entire contents of which are hereby incorporated by reference.

## Claims

1. A semiconductor device comprising a latch circuit, the latch circuit comprising a first inverter, a second inverter, a first transistor, a second transistor, and a node, wherein a gate of the first transistor is electrically connected to an output terminal of the first inverter,
wherein one of a source and a drain of the first transistor is electrically connected to the node,
wherein the other of the source and the drain of the first transistor is electrically connected to an input terminal of the second inverter,
wherein a gate of the second transistor is electrically connected to an output terminal of the second inverter,
wherein one of a source and a drain of the second transistor is electrically connected to the output terminal of the first inverter,
wherein the other of the source and the drain of the second transistor is electrically connected to the node, and
wherein an oxide semiconductor is included in a channel region in each of the first transistor and the second transistor.

2. The semiconductor device according to claim 1, wherein the node is brought into a floating state when the first transistor and the second transistor are turned off.

3. The semiconductor device according to claim 1, wherein a conductivity type of the first transistor is the same type as that of the second transistor.

4. The semiconductor device according to claim 1, wherein the node is brought into a floating state when each signal input to the first inverter and the second inverter has logic “1”.

5. The semiconductor device according to claim 1, further comprising a first NAND gate and a second NAND gate,
wherein each of the first NAND gate and the second NAND gate comprises a first input terminal and a second input terminal,
wherein an output terminal of the first NAND gate is electrically connected to the input terminal of the first inverter,
wherein an output terminal of the second NAND gate is electrically connected to the input terminal of the second inverter, and
wherein the first input terminal of the first NAND gate is electrically connected to the first input terminal of the second NAND gate.

6. The semiconductor device according to claim 5, wherein the node is brought into a floating state when each signals input to the second input terminal of the first NAND gate and the second input terminal of the second NAND gate has logic “0” or when a signal input to the first input terminal of the first NAND gate and the first input terminal of the second NAND gate has logic “0”.

7. The semiconductor device according to claim 5, further comprising a third inverter,
wherein each of the first NAND gate and the second NAND gate further comprises a third input terminal,
wherein an input terminal of the third inverter is electrically connected to the node and the third input terminal of the second NAND gate, and
wherein an output terminal of the third inverter is electrically connected to the third input terminal of the first NAND gate.

8. A semiconductor device comprising a latch circuit, the latch circuit comprising a first inverter, a second inverter, a first transistor, a second transistor, and a node,
wherein a gate of the first transistor is electrically connected to an output terminal of the first inverter,
wherein one of a source and a drain of the first transistor is electrically connected to the node,
wherein the other of the source and the drain of the first transistor is electrically connected to an input terminal of the second inverter,
wherein a gate of the second transistor is electrically connected to an output terminal of the second inverter,
wherein one of a source and a drain of the second transistor is electrically connected to the output terminal of the first inverter,
wherein the other of the source and the drain of the second transistor is electrically connected to the node,
wherein an oxide semiconductor is included in a channel region in each of the first transistor and the second transistor,
wherein the first inverter includes a transistor, and
wherein the first transistor and the second transistor are located over the transistor.

9. The semiconductor device according to claim 8, wherein the node is brought into a floating state when the first transistor and the second transistor are turned off.

10. The semiconductor device according to claim 8, wherein a conductivity type of the first transistor is the same type as that of the second transistor.

11. The semiconductor device according to claim 8, wherein the node is brought into a floating state when each signal input to the first inverter and the second inverter has logic “1”.

12. The semiconductor device according to claim 8, further comprising a first NAND gate and a second NAND gate,
wherein each of the first NAND gate and the second NAND gate comprises a first input terminal and a second input terminal,
wherein an output terminal of the first NAND gate is electrically connected to the input terminal of the first inverter,
wherein an output terminal of the second NAND gate is electrically connected to the input terminal of the second inverter, and
wherein the first input terminal of the first NAND gate is electrically connected to the first input terminal of the second NAND gate.

13. The semiconductor device according to claim 12, wherein the node is brought into a floating state when each signals input to the second input terminal of the first NAND gate and the second input terminal of the second NAND gate has logic “0” or when a signal input to the first input terminal of the first NAND gate and the first input terminal of the second NAND gate has logic “0”.

14. The semiconductor device according to claim 12, further comprising a third inverter,
wherein each of the first NAND gate and the second NAND gate further comprises a third input terminal,
wherein an input terminal of the third inverter is electrically connected to the node and the third input terminal of the second NAND gate, and
wherein an output terminal of the third inverter is electrically connected to the third input terminal of the first NAND gate.

15. The semiconductor device according to claim 8, wherein a channel formation of the transistor includes a silicon.

16. A semiconductor device comprising a latch circuit, the latch circuit comprising a first inverter, a second inverter, a first transistor, a second transistor, and a node,
wherein a gate of the first transistor is electrically connected to an output terminal of the first inverter,
wherein one of a source and a drain of the first transistor is electrically connected to the node,
wherein the other of the source and the drain of the first transistor is electrically connected to an input terminal of the second inverter,
wherein a gate of the second transistor is electrically connected to an output terminal of the second inverter,
wherein one of a source and a drain of the second transistor is electrically connected to the output terminal of the first inverter,
wherein the other of the source and the drain of the second transistor is electrically connected to the node,
wherein an oxide semiconductor is included in a channel region in each of the first transistor and the second transistor,
wherein the first inverter includes a transistor whose channel formation region is included in a semiconductor substrate, and
wherein the first transistor and the second transistor are located over the transistor.

17. The semiconductor device according to claim 16, wherein the node is brought into a floating state when the first transistor and the second transistor are turned off.

18. The semiconductor device according to claim 16, wherein a conductivity type of the first transistor is the same type as that of the second transistor.

19. The semiconductor device according to claim 16, wherein the node is brought into a floating state when each signal input to the first inverter and the second inverter has logic “1”.

20. The semiconductor device according to claim 16, further comprising a first NAND gate and a second NAND gate,
wherein each of the first NAND gate and the second NAND gate comprises a first input terminal and a second input terminal,
wherein an output terminal of the first NAND gate is electrically connected to the input terminal of the first inverter,
wherein an output terminal of the second NAND gate is electrically connected to the input terminal of the second inverter, and
wherein the first input terminal of the first NAND gate is electrically connected to the first input terminal of the second NAND gate.

21. The semiconductor device according to claim 20, wherein the node is brought into a floating state when each signals input to the second input terminal of the first NAND gate and the second input terminal of the second NAND gate has logic “0” or when a signal input to the first input terminal of the first NAND gate and the first input terminal of the second NAND gate has logic “0”.

22. The semiconductor device according to claim 20, further comprising a third inverter,
wherein each of the first NAND gate and the second NAND gate further comprises a third input terminal,
wherein an input terminal of the third inverter is electrically connected to the node and the third input terminal of the second NAND gate, and
wherein an output terminal of the third inverter is electrically connected to the third input terminal of the first NAND gate.

23. The semiconductor device according to claim 16, wherein the semiconductor substrate is a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate, or an SOI substrate.