# Patent

## Title
Apparatus and method to coordinate calendar searches in a network scheduler

## Abstract

A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer and input signals from array and a clock line providing current time. The results of the search are loaded into a Winner Valid array and a Winner Location array. A final decision logic circuit parses information in the Winner Valid array and Winner Location array to generate a final Winner Valid Signal, the identity of the winning calendar and the winning location. Winning is used to define the status of the calendar in the calendar status array that is selected as a result of a search process being executed on a plurality of calendars in the calendar status array.

## Background
The present application claims priority of the Provisional Application Ser. No. 60/325,501 filed on Sep. 27, 2001.
CROSS REFERENCE TO RELATED PATENT APPLICATIONS
The present application relates to the following patent applications, assigned to the assignee of the present invention, which are fully incorporated herein by reference:
Published Patent Application, Publication No. US-2002-0021368-A1, Publication Date: Feb. 21, 2002, filed Apr. 12, 2001 (priority date Apr. 13, 2000), Ser. No. 09/834,141, entitled “Method and System for Network Processor Scheduling Based on Service Levels”;
patent application Ser. No. 09/966,304, filed Sep. 27, 2001 by Darryl J. Rumph, entitled “Configurable Hardware Scheduler Calendar Search Algorithm”;
patent application Ser. No. 09/384,691, filed Aug. 27, 1999 by Brian M. Bass et al., entitled “Network Processor Processing Complex and Methods” sometimes referred to herein as the Network Processing Unit Patent or NPU patent;
patent application Ser. No. 09/546,651, filed Apr. 10, 2000, by Peter I. A. Barri et al., entitled “Method and System for Managing Congestion in a Network”. This patent is sometimes referred to herein as the Flow Control Patent;
patent application Ser. No. 09/547,280, filed Apr. 11, 2000, by Marco Heddes et al., entitled “Unified method and System for Scheduling and Discarding Packets in Computer Networks”. This patent is sometimes referred to herein as the Packet Discard Patent.
patent application Ser. No. 10/242,151, filed Sep. 12, 2002, by Darryl Rumph, entitled “Scalable Hardware Scheduler Time Based Calendar Search Algorithm”.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to communication network apparatus such as is used to link information handling systems or computers of various types and capabilities and to components and methods for data processing in such an apparatus. More particular the present invention relates to schedulers used in such devices to indicate when the next packet is to be transmitted from queues within the devices.
2. Description of the Prior Art
Scheduling the transmission of packets between points within a communications device or between points in the communications device and an external transmission network is well known in the prior art. The conventional approach is to provide a plurality of queues within the device and packets to be transmitted are enqueued to selected queues. A timing device sometimes called a timing wheel or calendar is searched to determine when the next packet is to be dequeued and forwarded from the queues. The selection, queueing and dequeueing of packets are controlled by several factors collectively referred to as Quality of Service (QoS). Because the factors and QoS requirements are well known in the prior art further discussion is not warranted. Suffice it to say U.S. Pat. Nos. 5,533,020 and 6,028,843 are examples of prior art.
Even though the prior art timing devices work well for their intended purpose it is believed that as the number of network users increases and more demand is made for better or higher Quality of Service (QoS) a more practical and efficient timing device will be required.
The requirement that the timing device should be able to support more customers and at the same time provide higher QoS poses a dilemma for the designer. The designer's dilemma is based on the fact that a design that addresses or solves the increased customer problem could adversely affect QoS whereas a design that improves QoS may not necessarily handle a large number of customers.
As a general proposition the increase in customer numbers can be solved by an increase in he number of calendars used in the design. But as the number of calendars increase more time will be required to process the calendars. With QoS time is of the essence. So, as the processing time increases QoS tends to deteriorate. As a consequence the designer is faced with the problems of processing a relatively large number of calendars within a relatively short time interval.
Another problem is that the design should be adaptive to face changing needs of the communication marketplace. If the design is not adaptive whenever conditions, such as addition of customers, change the current design would have to be redone. A more desirable outcome is to have a design which requires minor changes to meet the new requirements. Stated another way the design should be adaptive to accommodate changes.
Many scheduler and associated timing devices are fabricated in solid logic technology. In this technology large number of circuits are fabricated on relatively small areas of silicon termed chip. Space or real estate on the chip is at a premium. As a consequence the designer is allotted a relatively small surface area in which to place the circuits needed to provide the timing function of the scheduler. The requirement to fit the design into the limited space presents another problem for the designer.
In view of the above there is a need to provide an improved timing device to schedule movement of packets within a communications network.
SUMMARY OF THE INVENTION
The present invention solves the problems by providing timing system including a single search engine, and related logic circuits that search multiple calendars in a predefined time interval and provide a calendar number and location in the calendar that should next be serviced by the scheduler. In addition, the timing system is optimized to fit into a relatively small silicon area.
More particular the optimized timing system includes a search engine that searches a plurality of calendars and provide a calendar and calendar location (winner information) within a predefined time interval termed a “tick”. The results of the searches are stored in a Winner Valid Array which identifies the array that has been selected and the Winning Location Array which identifies the selected location within the selected array.
A final decision logic circuit parses information in the Winner Valid Array and Winning Location Array to generate a Final Winner Valid output, the number of the winning calendar and the winning location within the winning calendar. The final results are used to service the related flow queue.
A control Finite State Machine (FSM) responsive to several control input signals generates control signals to drive the calendar array, single search engine, current pointer array, winning location array and final decision selector logic.
In one of the illustrated embodiments the calendar array includes n(n>1) time based calendars and x(x>1) non-time based calendars. By using multiple calendars the design can be easily adapted to accommodate changed conditions.
As used in this document a time based calendar uses two variables, namely: current pointer (CP) and current time (CT) to identify a search zone within the calendar. The CP identifies the location of a calendar whereat the search engine begins and the CT identifies the location whereat the search terminates. In the illustrated embodiment n=12.
A non-time based calendar uses only one variable CP to identify the location whereat the search begins. The ending location is the one preceding the start location in this regard the search zone in the non-time based calendar wraps. In the illustrated embodiment x=40.
As a consequence in the illustrated embodiment at most fifty-two (52) calendars have to be maintained, with the capability to perform calendar searches as per the requirements. At most, 15 calendar searches have to be conducted within a “tick” cycle, which is defined as the time it takes to enqueue one packet and dequeue one packet from a flow queue. In the current system, this is defined as a minimum of 20 system clock cycles. At a minimum, each time-based calendar must be searched during each tick cycle, independent of activity against this calendar. A non-time-based calendar search needs to be conducted only when an action is taken against that calendar, such as an attach or detach.
The values set forth herein are exemplary of the illustrated embodiment and should not be construed as a limitation on the scope of the invention.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention together with the above and other advantages may best be understood from the following detailed description of the illustrated embodiment of the invention illustrate in the drawings; wherein:
FIG. 1 is a block diagram of an interface device or Network Processor including teachings of the present invention.
FIG. 2 shows a block diagram of the Embedded Processor Complex (EPC), DN Enqueue and DN Scheduler.
FIG. 3 shows a block diagram with more details of the Network Processor and scheduler including teachings of the present invention.
FIG. 4 shows a logical representation of the scheduler including the timing subsystem according to the teachings of the present invention.
FIG. 5 shows a block diagram of the timing system according to teachings of the present invention.
FIG. 6 shows a flowchart of the Control Finite State Machine (FSM).
FIG. 7 shows a flowchart of the Final Decision Selector logic.
FIG. 8 shows a block diagram of the Calendar Search Engine.
FIG. 9 shows Table I of the initialization routine which is done by the FSM.
FIG. 10 shows Table II illustrating Array accesses during a “tick” cycle.
FIG. 11 shows Table III illustrating Type I search.
FIG. 12 shows Table IV illustrating Type II search.
FIG. 13 shows Table V illustrating Type III search.
FIG. 14 shows Table VI illustrating Type IV search.
FIG. 15 shows Table VII illustrating Type V search.



DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT
The invention described hereinafter may be used in any environment, particularly in computers, where a structure with a specific number of calendars is to be searched. It works well in communications devices such as an interface device, also called Network Processor, and as such is described in that environment. However, this should not be construed as a limitation on the scope of the invention since it is well within the skill of one skilled in the art to make changes or modification to adapt the invention to several other technologies. Any such changes or modification is intended to be covered by the claims set forth herein.
In the following description of the preferred embodiment, the best implementations of practicing the invention presently known to the inventors will be described with some particularity. However, this description is intended as a broad, general teaching of the concepts of the present invention in a specific embodiment but is not intended to be limiting the present invention to that as shown in this embodiment, especially since those skilled in the relevant art will recognize many variations and changes to the specific structure and operation shown and described with respect to these figures.
FIG. 1 shows a block diagram of the interface device chip that includes the substrate 10 and a plurality of subassemblies integrated on the substrate. The sub-assemblies are arranged into an upside configuration and a downside configuration, with the “upside” configuration (sometimes also referred to as an “ingress”) referring to those components relating to data inbound to the chip from a data transmission network (up to or into the chip) and “downside” (sometimes referred to as an “egress”) referring to those components whose function is to transmit data from the chip toward the data transmission network in an outbound fashion (away from the chip or down and into the network). The invention described hereinafter is in the egress portion of the chip. Data flows follow the respective arrangements of the upside and downside configurations; thus, there is a upside data flow and a downside data flow in the system of FIG. 1. The upside or ingress configuration elements include an Enqueue-Dequeue-Scheduling UP (EDS-UP) logic 16, multiple multiplexed MAC's-UP (PMM-UP) 14, Switch Data Mover-UP (SDM-UP) 18, System Interface (SIF) 20, Data Align Serial Link A (DASL-A) 22 and Data Align Serial Link B (DASL-B) 24. Data links are more fully described in the Link Patent referenced above, and reference should be made to that document for a greater understanding of this portion of the system. It should be understood that the preferred embodiment of the present invention uses the data links as more fully described in that patent, other systems can be used to advantage with the present invention, particularly those which support relatively high data flows and system requirements, since the present invention is not limited to those specific auxiliary devices such as the data links which are employed in the preferred embodiment.
The components depicted on the downside (or egress) of the system include data links DASL-A 26 and DASL-B 28, system interface SIF 30, switch data mover SDM-DN 32, enqueue-dequeue-scheduler EDS-DN 34 and multiple multiplexed MAC's for the egress PMM-DN 36. The substrate 10 also includes a plurality of internal static random access memory components (S-RAM's), a traffic management scheduler 40 (TRAFFIC MGT SCHEDULER) also known as the Egress Scheduler containing the teachings of the present invention and an embedded processor complex 12 described in greater depth in the NPU Patent referenced above. An interface device 38 is coupled by the respective DMU busses to PMM 14, 36. The interface device 38 could be any suitable hardware apparatus for connecting to the L1 circuitry, such as Ethernet physical (ENET PHY) devices or asynchronous transfer mode framing equipment (ATM FRAMER), both of which are examples of devices which are well known and generally available for this purpose in the trade. The type and size of the interface device are determined, at least in part, by the network media to which the present chip and its system are attached. A plurality of external dynamic random access memory devices (D-RAMS) and a S-RAM are available for use by the chip.
While here particularly disclosed for networks in which the general data flow outside the relevant switching and routing devices is passed through electric conductors such as wires and cables installed in buildings, the present invention contemplates that the network switches and components thereof could be used in a wireless environment as well. For example, the media access control (MAC) elements herein disclosed may be replaced with suitable radio frequency devices, such as those made from silicon germanium technology, which would result in the connection of the device disclosed directly to a wireless network. Where such technology is appropriately employed, the radio frequency elements can be integrated into the VLSI structures disclosed herein by a person of skill in the appropriate arts. Alternatively, radio frequency or other wireless response devices such as infrared (IR) response devices can be mounted on a blade with the other elements herein disclosed to achieve a switch apparatus which is useful with wireless network apparatus.
The arrows show the general flow of data within the interface system shown in FIG. 1. Frames of data or messages (also sometimes referred to as packets or information units) received from an Ethernet MAC 14 off the ENET PHY block 38 via the DMU bus are placed in internal data store buffers 16a by the EDS-UP device 16. The frames may be identified as either normal frames or guided frames, which then relates to method and location of the subsequent processing in the plurality of processors in the EPC. After the input units or frames are processed by one of the plurality of processors in the embedded processor complex, the completed information units are scheduled through the scheduler 40 out of the processing unit 10 and onto the data transmission network through the PMM-DN multiplexed MAC's 36 and the physical layer 38. It is the scheduling of data by the scheduler 40 and in particular timing system within the scheduler that the present invention will describe hereinafter.
FIG. 2 is a block diagram of a processing system which can employ the present invention to advantage. In this FIG. 2, a plurality of processing units 110 are located between a dispatcher unit 112 and a completion unit 120. Each incoming frame F (from a switch, not shown, attached to the present data processing system) is received and stored into a DOWN data store (or DN DS) 116, then sequentially removed by the dispatcher 112 and assigned to one of the plurality of processing units 110, based on a determination by the dispatcher 112 that the processing unit is available to process the frame. Greater detail on the structure and function of the processing units 110 in particular, and the processing system in general, can be found in the NPU Patent references above and patent applications and descriptions of the individual components such as a flow control device detailed in the Flow Control Patent. Interposed between the dispatcher 112 and the plurality of processing units 110 is a hardware classifier assist 118 which is described in more detail in a pending patent application Ser. No. 09/479,027 filed Jan. 7, 2000 by J. L. Calvignac et al. and assigned to the assignee of the present invention, an application which is incorporated herein by reference. The frames which are processed by the plurality of network processors 110 go into a completion unit 120 which is coupled to the DN Enqueue 34 through a flow control system as described in the Flow Control Patent and the Packet Discard Patent. The DN Enqueue 34 is coupled to the Dn Scheduler which is coupled through the PMM DN MAC's 36, then by the DMU data bus to the physical layer 38 (the data transmission network itself).
FIG. 3 shows a block diagram of the data flow on the Egress side of the Network Processor. It should be noted that Network Processor (NP) and Interface Device are used interchangeably. To make the figure less complicated only components which are necessary to understand the invention are shown. The components include Data Management and Buffering 40, Embedded Processor Complex 42, Flow Queues 0-Z, target port (TP) queues 0-Y, Port Data Movement 44 and Egress Scheduler 46. Each egress packet enters the Network Processor from a switched fabric against a “connection”, that is, a definition of a path from the switched fabric to a specific output port. Prior to sending of any packet data this path is defined. Included in this path is the addressing information that is a part of the packet “header”. This header is part of a table definition in the EPC that allows the EPC to determine the destination flow queue to which the data is enqueued. Each flow queue has a Queue Control Block (QCB) contained in the scheduler function that defines the destination target port (TP) in that flow queue.
Still referring to FIG. 3, egress packets enter the Network Processor and are buffered (stored) by Data Management and Buffering 40 which is responsible for managing the pointer to the packet data. These pointers will be passed to each functional block that will process the packet ending with the step where the packet data exits the Network Processor through the output ports. The Egress Scheduler 46 monitors the flow queues, and as packets are placed in a selected queue, the Egress Scheduler initiates movements of those packets in accordance with the invention to be described hereinafter and other Quality of Service (QoS) requirements to the appropriate target port from which the port data movement 44 packages the data in accordance with predetermined transmission protocol such as ethernet, etc., and forwards the data through one of the ports 0 through port w.
FIG. 4 shows a logical block diagram of Egress Scheduler 46. The function of Egress Scheduler 46 is to monitor the flow queues and at appropriate times determined by the invention herein move packets from flow queue to the target port (TP) Queue. To this end the Egress Scheduler 46 includes a plurality of functions which cooperate to provide the overall function of the scheduler. Included in the functions are the flow queue monitor logic which, among other things, monitors flow queue to determine when a data packet is placed in a flow queue by the Embedded Processor Complex. The Egress Scheduler 46 also includes the timing subsystem (to be described hereinafter) according to teachings of the present invention, calendar attach logic etc.
It should be noted that even though the functions which are necessary for the Egress Scheduler 46 to carry out its function are shown in FIG. 4 as internal to the scheduler this is only a logical representation. In an actual Network Processor some of these functions may be located elsewhere in the Network Processor and not necessarily within the scheduler itself.
Still referring to FIGS. 3 and 4, the data packets enter the traffic flow queue 0-Z at a given queue id. Each of the queue ids has a level of service requirement, as specified via the QoS parameters. When a packet enters a queue, Timing Subsystem (described below) of the Scheduler 46 determines when this packet may exit the same traffic queue id. This determination is performed by attaching the queue id to one of the locations of a calendar in the timing system (details set forth herein) per the queue service requirements and using the network scheduler decision algorithm. There may be more than one packet in the traffic queue at any one time in that another packet may enter the same queue id before the scheduler determines that a packet may exit the queue. When there is one or more data packets in a traffic flow queue a queue will be attached to one of the many network scheduler calendars which indicates that the queue will be serviced at a later time. When a packet exits the queue, the scheduler will remove the queue id from the calendar location from which it was attached. If a packet exits the traffic queue and there is at least one additional packet in the queue, the scheduler will reattach this queue ID to another calendar location for service (packet exits from the queue) at a later time. If there are no more packets in the queue after a packet exits, the scheduler will not reattach this queue ID to a calendar location. The scheduler continues to select traffic queues for service, one by one, until there are no more remaining packets in the traffic flow queues. During normal scheduler operation only one packet may enter a traffic flow queue during a “TICK” cycle. A “TICK” cycle is defined as a fixed number of system clock cycles in duration, and only one packet may enter and exit any of the traffic queues during a “TICK” 'cycle. Whenever one or more packets are in a traffic queue, this queue ID will be attached to one of the network scheduler calendars by the scheduler. This attachment indicates that a packet is due at some time in the future to exit the traffic queue. Only one packet may enter/exit one traffic queue at a time so there cannot be simultaneous packet entries into two or more queues nor can there be simultaneous packet exits from two or more queues.
In particular, FIG. 3 shows a diagram of the Network Scheduler operating as follows:
Data packets enter the traffic queue at a given queue ID. Each of the queue ID's have a level of service requirement. When a packet enters a queue, the network scheduler determines when this packet may exit the same traffic queue. There may be more than one packet in the traffic queue at any given time, in that another packet may enter the same queue before the first packet has exited the queue. The determination of when a packet may exit a flow queue is performed by (1) attaching the queue ID to one of the Calendars at a specific calendar location, as specified by the Scheduler algorithm; and (2) considering this queue ID, along with other queue ID's that have been attached to the same or other calendar location for service via a calendar search. The search will determine which calendar location is the proper location that should be serviced next, if at all, and this calendar location is determined to be the “winning calendar location”. The flow queue ID that has been attached to the winning calendar location will be serviced via moving a packet from this flow queue. At this time, the scheduler will detach this queue ID from the location where it was attached. If there is an additional packet in the queue after the packet has exited, the scheduler will reattach this queue ID to another calendar location per the algorithm. If there are no more packets in the queue after the first packet has exited, the scheduler will not reattach this queue ID to a calendar. The scheduler continues to select traffic queues for service in this fashion, one-by-one, until there are no more remaining packets in any of the traffic queues.
FIG. 5 shows a block diagram of the timing subsystem according to the teachings of the present invention. The timing system includes Calendar Status Array 50, Control Finite State Machine (FSM) 52, Calendar Search Engine 54, Current Working Pointer Array (CP) 56, Selector 55, Winning Location Array 60, Winner Valid Array 58 and Final Decision Selector logic 62. The named structures are operable interconnected as shown in the figure.
Calendar Status Array 50 includes Q calendars. In the disclosed embodiment Q=52. However, this value of Q should not be a limitation on the scope of the invention since the number of calendars chosen is a design choice and does not intend to limit the teachings of the present invention. The Q calendars includes 12 time based calendars and 40 non-time based calendars. In FIG. 5 the time based calendars are numbered 0 through 11 while the non-time based calendars are labeled 12 through 51. The arrays are identical in the sense that each one includes a memory of M continuous storage locations. In the preferred embodiment of this invention M=512. Each location includes a 2-state status bit and an identifier which corresponds to the ID number of a flow queue within the system. When a packet is placed into a flow queue the scheduler attaches the flow queue number to a location on one of the calendars and activates (turns on) the corresponding status bit. The described invention does the calendar searches described below, determines whether or not a winner is valid, and selects the Winning Calendar and Winning Location and returns this information to the Scheduler which detaches the queue ID from the location and deactivates (turn off) the status bit, if necessary. The information is used to move a frame from a flow queue to a port queue or other location within the device.
Control Finite State Machine (FSM) is the structure that controls the other structures within the timing subassembly of the present invention. The Control FSM performs initialization function and starts the different sequences that are required in order to search the calendar. A flowchart showing the logic used in the Control FSM will be given subsequently. In one embodiment of the present invention the FSM can initiate five types of searches or sequences. Once the search type is initiated the manipulation of structures within the system is carried out by tables which are discussed hereinafter. The five types of searches are:

    1. Neither an attached nor a detached time based search (Search Type I)
    2. Attached to a time based calendar (Search Type II)
    3. Attached to a non-time based calendar (Search Type III)
    4. Detached from a time based calendar (Search Type IV)
    5. Detached from a non-time based calendar (Search Type V)

The Control FSM 52 includes a plurality of input control lines. The input control lines include Add Item which indicates that an item is to be attached to a particular calendar location; Remove Item indicating an item is to be detached from a particular calendar location; Item Information which includes calendar number and calendar location; Last Item Being Detached indicating that the item is the last one from this calendar location (LIBD) to be detached; Current Time indicating current time; Begin Tick Cycle indicating the beginning of a tick period; Reset indicating the system should be reset; Start Initialization indicating the Control FSM should start initializing the system and Winner_Valid feedback indicating a winner has been found and is valid. Depending on the input of the named signals, the control FSM will generate signals to control the structure to which its output lines are connected.



The calendar search engine 54 performs the searches to be conducted and output Winner Valid and Winning Calendar Location on the ports labeled as Winner Valid and Winning Calendar Location. The input into calendar search engine 54 includes a current time port to which current time is applied; Calendar Status Bits port to which M bits from the Calendar Status Array are applied; Attach/Detach/Location port to which attach signal detach is applied; the Search Type port indicating the type of search to be conducted and Current Working Pointer port indicating the position from which the search should begin.
The Current Working Pointer (CP) array 56 is a memory having P consecutive locations with P equal to the number of calendars in the Calendar Status Array. In the disclosed embodiment P equals 52 labeled 0 through 51. The width of each location in the CP array is log2(M), wherein log2(M) equals the bit width of a value that will point to each bit of an entry in the calendar status array. In the disclosed embodiment each calendar has 512 locations. Therefore, M equals 9 (29=512). The Current Working Pointer Array structure 56 holds the CP identity of the 52 calendars and the location whereat the CP is positioned within a particular calendar. The addressing structure is identical to that of the Calendar Status Array 50, in that locations 0-11 are for the time based calendars and locations 12-51 are for the 40 non-time based calendars. As will be described hereinafter during initialization, the Control FSM 52 writes the value of Current Time into the CP array for each of the time based calendars and an arbitrary choice of zero for each of the non-time based calendars. When it is time to perform a calendar search using the Calendar Search Engine 54 a read of the CP array structure is performed, and the array corresponding to the target calendar is presented to the CP calendar search engine via the Current Working Pointer port already described. The Selector 55 receives a signal from the Winner Valid Array and depending on the value of a bit position in the Winner Valid (WV) Array selects either the CP or CT. In particular, if the bit is a zero the Selector selects the CT input signal to apply to the Current Working Pointer port and if a logical 1 selects the CP signal line to apply to the Current Working Pointer port. The Winner Valid Array structure 58 includes a memory 1 bit wide and 52 locations deep. Each location indicates, via a logical bit, whether or not a Winner has been found by the search engine for each of the calendars. There is one bit for each of the calendars. During initialization, the control FSM writes a value of logical zeroes to all the locations. The bits for each are updated with the results of each of the searches.
The Winning Location Array 60 is of the same structure as the previously described Current Working Pointer Array. It is a memory containing 52 locations labeled 0-51 and each location being of width log2(M), used to identify a location within a calendar. This structure does not have to be initialized as it is qualified by the corresponding Winner Valid Array bit. If a winner is found by the Calendar Search Engine the Control FSM stores a Winning Calendar Location in the Winning Calendar Location Array concurrently with the winner_valid bit in the location corresponding to the appropriate calendar.
The Final Decision Selector Logic 62 includes combinatorial logic (details given below) which determine the true “Winner”. This is performed as per the Scheduler algorithm which is a priority search. The Control FSM accesses each location. The Winner Valid Array, beginning with location 0 and incremented through each location in the array. The first location that contains a non-zero bit will be the true winner, and the corresponding entry in the Winning Calendar Location Array will appear at the output along with Winner Valid and the Winning Calendar Address.
FIG. 6 shows a flowchart of the logic in the Control FSM. As stated previously, the Control FSM initialized the structure shown in FIG. 5 and initiates the search routines. The initialization routine is set forth below in the table shown in FIG. 9 and the action taken relative to each structure after it has been initiated by the Control FSM to perform one of the searches set forth above is controlled by tables set forth in the figures below.
Still referring to FIG. 6, the flowchart begins in block 64. Block 64, which initializes last_non_time_cal_serviced to a value of zero (arbitrarily chosen) is entered. Last_non_time_cal_serviced is an input to the final decision selector. Next, decision block 66, which asks if a begin_tick_cycle signal is active, is entered. If the answer to block 66 is no, decision block 66 is re-entered. If the answer to block 66 is yes, then block 68, which initializes two counters, “cycle” and “cal_num” both to values of zero, is entered. The “cycle” counter is a count which increments once each system clock cycle, and determines when the final decision logic (FIG. 5) is to be activated. The “cal_num” counter is the count which keeps track of the time-based calendars. The time-based calendars have a cal_num range of zero to eleven. Decision block 70, which asks if the attach input signal is active on this clock cycle, is entered. If the answer to block 70 is no, then decision block 74, which asks if the detach input signal is active on this clock cycle, is entered. If the answer to block 70 is yes, then decision block 72, which asks if the attach calendar is less than 12, is entered. If the answer to block 72 is yes, then block 78, which indicates that (1) the search type is time-based, (2) the search type is of Type 2, and (3) the value of the ct_sel (used to determine the value of ct that is sent to the calendar search engine) is equal to a value of attach_cal modulo 4. Block 86, which says to initiate the attach search sequence to the attach cal number, cal_address, and cal_location, is then entered. If the answer to block 72 is no, then block 80, which indicates that (1) the search type is non-time-based, and (2) the search type is of Type 3. Block 86, which was described above, is then entered.
If the answer to decision block 74 (described above) is yes, then decision block 88, which asks if the detach calendar is less than 12 (time-based) is entered. If the answer to decision block 88 is yes, then decision block 96, which indicates that (1) the search type is time based, (2) the value of ct_sel is equal to a value of detach_cal modulo 4, and (3) the search type is a Type 4 search. Block 102, which says to (1)initiate the detach search sequence to the detach cal_num, cal_address, and cal_location using the search, and (2) used the LIBD (last item being detached) input to update the proper calendar status bit in the calendar status array, is then entered.
If the answer to decision block 88, which was described above, is no, then block 92, which indicates that (1) the search type is a non-time-based search, and (2) the is search type is of Type 5, is then entered. Next, block 98, which indicates that a stored value called “stored_last_serviced” takes on the value of the detach_cal input. This stored value will be used when the final decision selector is activated. Block 102, which was described earlier, is then entered. When exiting block 102, block 90, which will be described later, is then entered.
If the answer to decision block 74, which was described earlier, is no, then block 76, which asks if the value of cal_num is greater than 11, is then entered. If the answer to block 74 is no, then block 82, which says to initiate a time-based search (Type 1) of the calendar indicated by cal_num, is then entered. Next block 84, which increments the value of cal_num by a value of one, is then entered. Decision block 90, which asks if the cycle num is greater than 18 (used to determine if the final decision selector function is to be activated) is then entered. If the answer to block 76 is yes, then decision block 90, described earlier, is entered.
If the answer to decision block 90 is no, then block 94, which increments the value of cycle_num by a value of one, is then entered. Next, decision block 70, which was described earlier, is then entered. If the answer to decision block 90 is yes, then block 100, which (1) initiates the final decision selector, and, (2) initiates a read of the wining location array if a winner is found, is then entered. It should also be noted that the stored_last_serviced. Block 104, which indicates that the search sequence is complete, and the winner valid and Winner Info outputs are updated to reflect the final outcome of the search. Block 105, which says to give the value of last_non_time_cal_svcd the value of stored_last_serviced, is then entered. Then decision block 66, which waits for the next begin_tick_cycle signal, is entered.
This flow chart is of a cyclical nature, so there is no ending point.
FIG. 7 shows a flowchart of the logic used in the Final Decision Selector Logic 62. The flowchart begins in block 106 and ends in block 136. After leaving block 106, block 108, which initializes a cal_num counter to a value of zero, is then entered. Decision block 110, which asks if the winner_valid_array_entry for cal_num is equal to a value of logic 1 (valid) is entered. If the answer to decision block 110 is yes, then block 116 is entered. Block 116 indicates that (1) the winner_valid output is true (logic 1), (2) the winning calendar output is the value of cal_num, (3) the value of cal_num is passed to the Control FSM to use as an index to the Winning Location Array, (4) the data from this read will be the winning location output. Block 136, the ending block, is then entered.
If the answer to decision block 110 is no, then block 112, which increments the value of cal_num by 1, is entered. Decision block 114, which asks if cal_num is equal to 12 (on a non-time-based calendar) is then entered. If the answer to block 114 is no, then decision block 110, described above, is entered. If the answer to block 114 is yes, then Decision block 118, which asks if there is a non-time-based winner, is entered. There is a non-time-based winner if at least one of the winner valid bits for calendars 12 to 51 are valid (logic 1). If the answer to block 118 is yes, then block 120, which sets a counter, called “non_time_cal_cnt” to a value of last_non_time_cal_serviced+1. Last_non_time_cal_serviced comes from the Control FSM. Decision block 122, which asks if the value of non_time_cal_cnt is equal to 52 is entered. If the answer to block 122 is yes, then block 124, which sets the value of non-time_cal_cnt to a value of 12, is entered. Decision block 124 serves the purpose of performing the “circular” portion of the search, and wraps the counter back to the lowest non-time-based calendar index. Decision block 126, which asks if the value of non_time_cal_cnt is equal to the value of last_non_time_cal_serviced, is then entered. If the answer to decision block 122 is no, then decision block 126 is entered. If the answer to block 126 is yes, then block 134, which indicates to the control FSM that no winner was found, is then entered. If the answer to block 118, which was described earlier, is no, then block 134 is entered. After leaving block 134, then block 136, the ending block is entered.
If the answer to decision block 126 is no, then decision block 130, which asks if the winner_valid entry for location non_time_cal_cnt is logic 1, is entered. If the answer to block 130 is yes, then block 132, which indicates that a (1) a winner was found and (2) cal_number is equal to non_time_cal_cnt, is entered. Next, block 116, which was described earlier, is entered. If the answer to decision block 130 is no, then block 128, which increments the non_time_cal_cnt by a value of 1 is then entered. Decision block 122, which was described earlier, is then entered.
FIG. 8 shows a block diagram for the Calendar Search Engine 54 (FIG. 5). The Calendar Search Engine 54 includes a time based search facility 138 and non-time based search facility 140. The output from the time based search facility 138 and the non-time based search facility 140 are outputted and selected through output selector 144 which is activated by the search type signal delayed a predefined amount by Delay Circuit 142. In the disclosed embodiment Delay Circuit 142 is set to a value of one clock cycle delay. Of course other clock cycle delays can be used depending on the designer's choice. The outputs from either the non-time based search algorithm 140 or time based search algorithm 138 are selected by the output selector 144 and output as Winner Valid and Winning Calendar Location information. The time based search algorithm 138 is substantially identical to the search algorithm described in U.S. patent application Ser. No. 09/966,304 filed Sep. 27, 2001 by Darryl Rumph identified above and incorporated herein by reference to complete the description of this feature, if necessary. Likewise, the non-time based search algorithm 140 is substantially identical to the search algorithm described in U.S. patent application Ser. No. 10/242,151, filed Sep. 12, 2002 by Darryl Rumph, identified above and fully incorporated herein by reference to complete the detailed description of this feature, if necessary.
The Current Time input is generated by current time decision logic 136. For the current implementation, the current time input is a 20-bit value. Portions of this value are used as the value of current time for the time-based calendar searches. For this implementation, the 9-bit value of current time is chosen as a function of ct_sel: If ct_sel equals zero, then ct equals curr_time_in(8:0). If ct_sel equals one, then ct equals curr_time_in(12:4). If ct_sel equals two, then ct equals curr_time_in(16:8). Finally, if ct_sel equals 3, then ct equals curr_time_in(20:12).
The input control signals calendar status bit, current working pointer and search type signals have already been described and will not be repeated.
FIG. 9 shows Table I of the initialization routine which is done by the FSM 52 (FIG. 5). The table shows that the actions taken are performed on each structure of the system shown in FIG. 5. The first column in the table is labeled clock cycle number and indicates the clock cycle value at which actions are taken on the structure in FIG. 5. Column 2 lists the Array Location. As discussed above there are 52 arrays labeled 0 through 51 which are shown in the array location column. The third column labeled Array Names indicate the arrays that are serviced during the named clock cycle. The fourth column labeled Access Type indicates what is being done to the structure. In this case the structure is written into. Finally, the fifth column labeled Write Data indicates the data which is written into the named structure. By way of example, the first row of the table indicates that at cycle 1 of the clock, array 0 is being serviced and the calendar status array, the cp array and the winner array are each written with all zeroes. In a similar manner each line in the table can be explained and further explanation of the respective lines will not be given.
FIG. 10 shows Table II illustrating array accesses during a tick (20 clock cycles) TDM (Time Division Multiplex) with neither attach or detach actions. During the period where there are no calendar attaches nor detaches immediately following initialization, there are no winners at the output. Therefore, the winner data output from the structure will indicate that there is not a valid winner at the end of the 20th cycle and repeat until all items are attached to the calendar.
Still referring to FIG. 10 the headings are labeled Clock Cycle Number, Array Location, Array Names, Access Type, Write Data, Search Engine Inputs and Search Engine Output. The interpretation of these headings based upon previous discussion are self-explanatory and further details will not be given. The action taken on each machine cycle are also indicated in the Table, are self-explanatory and will not be discussed further.
FIG. 11 shows Table III illustrating type I search which has been identified and described above. The headings in the Table are labeled Clock Cycle Number, Array Location, Array Names, Access Type, Write Data, Search Engine Inputs, Search Engine Output and a Comments column. The headings in the first seven columns are self-explanatory and the information in the Comments column further explains activities taken relative to structures in FIG. 5. The entry in this table is also self-explanatory and further description will not be given. It should be noted that at the end of clock cycle 3 the output of the search is stored in the Winner Valid and Winning Location Arrays at address N.
FIG. 12 shows Table IV illustrating type II search. For a type II search an attach has occurred to a time based calendar at a specific calendar location. The type II search of calendar N where N is the address (number) of a time based calendar is shown in Table IV. The headings in Table IV are the same as the headings in Table III and will not be repeated herein. At the end of three clock cycles the output of the type II search is stored in the Winner Valid and Winning Location arrays in address N. The array structure now contains the updates as a result of the attach.
FIG. 13 shows Table V illustrating type III search. For a type III search an attach has occurred to a non-time based calendar at a specific calendar location. Table V shows the detail of the type III search of calendar N, where N is the address of a time based calendar and the attach is initiated on clock cycle 1. At the end of clock cycle 3 the output of the type III search is stored in the Winner Valid and Winning Location Arrays in address N. The array structure now contains the update as a result of the attach.
FIG. 14 shows Table VI illustrating type IV search. For a type IV search, a detach has occurred to a time based calendar at a specific calendar location. The “last item being detached” (LIBD) input indicates whether the calendar status bit for the search is to be a logical 1 or logical 0. An LIBD equal to 1 means the status bit should be logical 0 for the search. LIBD equal to 0 means the status bit should be logical 1 for the search. Table VI shows the details of the type IV search of calendar N where N is the address of the time based calendar and the attach is initiated on clock cycle 1. At the end of clock cycle 4 the output of the type 4 search is stored in the Winner Valid and Winning Location Arrays in Address N. The array structures now contain the update as a result of the detach.
FIG. 15 shows Table VII illustrating type V search. For a type V search, a detach has occurred to a non-time based calendar at a specific calendar location. As for a type IV search discussed above the “last item being detached” (LIBD) input indicates whether the calendar status bit for the search is to be a logical 1 or a logical 0. LIBD equal to 1 means a status bit should be logical 0 for the search. LIBD equal to 0 means the status bit should be logical 1 for the search. FIG. 15 shows the details of the type V search of calendar N, where N is the address of a time based calendar and the attached is initiated on clock cycle 1. At the end of clock cycle 4 the output of the type V search is stored in the Winner Valid and Winning Location Array in address M. The array structure now contains the updates as a result of the detach.
It should be noted that these actions which initiate accesses to the arrays are being pipelined, and care must be taken such that there is not a “collision” for access of the same resource on the same clock cycle. This is true for both read accesses and write accesses. Also, because of hardware limitations, it generally takes at one clock cycle to access an array structure, so there is a requirement that there must be at least one system clock cycle between attaches and detaches.
Because of the finite amount of time required to access the winner array structure during the final decision process, there can be neither attaches nor detaches after cycle 18 of a tick period.
It is to be understood that the above described embodiment is merely illustrative of the application of principles of the invention and that other arrangements or embodiments may be devised by someone skilled in the art without departing from the spirit and scope of the invention.

## Claims

1. A system including:
a network processor;
a scheduler operatively connected within said network processor;
a timing subsystem operatively coupled to the scheduler, said timing subsystem including:
a search engine;
an array of calendars with outputs operatively coupled to inputs of said search engine;
a Winner Valid array operatively coupled to the calendar search engine;
a Winning Location array operatively coupled to the calendar search engine;
a Current Working Pointer array having outputs operatively coupled to the calendar search engine;
a controller responsive to received signals to generate control signals which put the timing subsystem in an initial state and causes the calendar search engine to search identified calendars and load results of searches into the Winner Valid Array and Winning Location Array within a predefined time interval; and

a final decision logic circuit arrangement operatively coupled to the Winning Location Array and the Winning Valid Array, wherein said final decision logic circuit arrangement parses information in said Winning Location Array and said Winning Valid Array to select one of the calendars as a Winner, selects a location in the Winner as Winning Location and generates a signal indicating the Winner and Winning Location are valid; and
wherein the network processor includes:
n flow queues, n>1;
m port queues, m>1; and
an embedded processor complex that routes packets into said flow queues wherein said scheduler is responsive to signals generated by the final decision logic circuit arrangement to cause the packets to be transported from the flow queues to the port queues.

2. The system of claim 1 wherein the array of calendars includes a first set of time based calendars in which a search zone over which the search engine searches is delineated by a Current Pointer (CP) and Current Time (CT).

3. The system of claim 2 wherein the first set includes n calendars.

4. The system of claim 3 wherein n=12.

5. The system of claim 2 wherein the array of calendars includes a second set of non-time based calendars which use the CP to delineate the beginning of a search zone.

6. The system of claim 5 wherein the second set includes X non-time based calendar.

7. The system of claim 6 wherein X=40.

8. The system of claim 1 wherein each calendar in the array of calendars has 512 locations.

9. The system of claim 1 wherein the search engine includes
a time based search arrangement operable to search a first set of calendars within the array of calendars;
a non-time based search arrangement operable to search a second set of calendars within the array of calendars; and
a selector responsive to a selection type signal to select outputs from the time based search arrangement and non-time based search arrangement.

10. The system of claim 9 wherein the first set of calendars includes time based calendar having search region bounded by a current pointer (CP) location and current time (CT) location.

11. The system of claim 10 wherein the second set of calendars includes non-time based calendar having search region identified by a current pointer location.

12. The system of claim 1, furthering including a control Finite State Machine (FSM) that generates control signals in response to one or more input signals, wherein the control signals control the search engine and the logic.

13. A system including:
a network processor;
a scheduler operatively connected within said network processor; and
a timing subsystem operatively coupled to the scheduler, said timing subsystem including:
a search engine;
an array of calendars with outputs operatively coupled to inputs of said search engine;
a Winner Valid array operatively coupled to the calendar search engine;
a Winning Location array operatively coupled to the calendar search engine;
a Current Working Pointer array having outputs operatively coupled to the calendar search engine;
a controller responsive to received signals to generate control signals which put the timing subsystem in an initial state and causes the calendar search engine to search identified calendars and load results of searches into the Winner Valid Array and Winning Location Array within a predefined time interval;
a time based search arrangement operable to search a first set of calendars within the array of calendars;
a non-time based search arrangement operable to search a second set of calendars within the array of calendars; and
a selector responsive to a selection type signal to select outputs from the time based search arrangement and non-time based search arrangement; and
a final decision logic circuit arrangement operatively counted to the Winning Location Array and the Winning Valid Array, wherein said final decision logic circuit arrangement parses information in said Winning Location Array and said Winning Valid Array to select one of the calendars as a Winner, selects a location in the Winner as Winnine Location and generates a signal indicating the Winner and Winning Location are valid.

14. The system of claim 13 wherein the network processor includes n flow queues, n>1; m port queues, m>1; and an embedded processor complex That routes packets into said flow queues wherein said scheduler is responsive to signals generated byte final decision logic circuit arrangement to cause the packets to be transported from the flow queues to the port queues.

15. The system of claim 13 wherein the first set of calendars includes time based calendar having search region bounded by a current pointer (CP) location and current time (CT) location.

16. The system of claim 15 wherein the second set of calendars includes non-time based calendar having search region identified by a current pointer location.

17. The. system of claim 13, furthering including a control Finite State Machine (FSM) that generates control signals in response to one or more input signals, wherein the control signals control the search engine.

18. The system of claim 13 wherein the first set of calendars includes twelve calendars.

19. The system of claim 13 wherein the second set of calendars includes forty calendars.