# Patent

## Title
Bandgap reference circuit

## Abstract

A bandgap reference circuit is proposed. To remove parasitic effects, this includes the combination of a first circuit section (1), which generates a temperature-proportional voltage, and a second circuit section (2), which generates an inversely temperature-proportional voltage. The bandgap reference circuit generates a bandgap reference voltage (Ubg) as the sum of the temperature-proportional voltage of the first circuit section (1) and the inversely temperature-proportional voltage of the second circuit section (2). To remove the parasitic effects, both circuit sections (1, 2) include bipolar transistor circuits with multiple bipolar transistors (Q1-Q4; Q5-Q8), so that both the temperature-proportional voltage and the inversely temperature-proportional voltage are generated in the form of a sum and difference formation of multiple base-emitter voltages of the appropriate bipolar transistors.

## Background
FIELD OF THE INVENTION
This invention concerns a bandgap reference circuit, which is used to provide a bandgap voltage, particularly in the form of a base-emitter voltage of a bipolar transistor, as a high-precision reference voltage.
BACKGROUND
Bandgap reference circuits traditionally have a bipolar transistor. A bandgap reference voltage is derived from the base-emitter voltage of the bipolar transistor and provided. However, at their base and emitter terminals bipolar transistors have parasitic resistances, which affect the base-emitter voltage on which the function of the bandgap reference circuit is based. This will be explained in more detail below on the basis of FIG. 4.
FIG. 4 shows a bipolar transistor with a parasitic base resistance Rb and a parasitic emitter resistance Re. The bipolar transistor is driven by a collector current Ic. The base-emitter voltage Ube of the bipolar transistor shown in FIG. 4 is defined as follows:




  
    
      
        
          U
          be
        
        =
        
          
            
              U
              t
            
            ⁢
            
              
            
            ⁢
            
              ln
              ⁡
              
                (
                
                  
                    I
                    c
                  
                  
                    I
                    s
                  
                
                )
              
            
          
          +
          
            
              
                I
                c
              
              ⁡
              
                (
                
                  1
                  +
                  
                    1
                    β
                  
                
                )
              
            
            ⁢
            
              
            
            ⁢
            
              R
              e
            
          
          +
          
            
              I
              c
            
            ⁢
            
              1
              β
            
            ⁢
            
              R
              b
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




where Is is the reverse current of the bipolar transistor, and β is the current amplification of the bipolar transistor. From Formula (1), the effect of the parasitic base and emitter resistances on the base-emitter voltage can be seen. These parasitic resistances result in the corresponding bandgap reference circuit being affected by parasitic temperature coefficients, which can only be controlled with difficulty and consequently result in imprecision and uncertainty in the circuit production.

Since all the voltages which are derived from the parasitic resistances are also referred to the collector current Ic, the effect of the parasitic resistances on the base-emitter voltage can be seen as derived from a virtual compensating resistance Req at the emitter of the bipolar transistor, as is shown schematically in FIG. 5. For the base-emitter voltage Ube, the result, depending on the collector current Ic and compensating resistance Req, is:




  
    
      
        
          
            
              
                U
                be
              
              =
              
                
                  
                    U
                    t
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    ln
                    ⁡
                    
                      (
                      
                        
                          I
                          c
                        
                        
                          I
                          s
                        
                      
                      )
                    
                  
                
                +
                
                  
                    I
                    c
                  
                  ⁡
                  
                    (
                    
                      
                        
                          
                            β
                            +
                            1
                          
                          β
                        
                        ⁢
                        
                          R
                          e
                        
                      
                      +
                      
                        
                          R
                          b
                        
                        β
                      
                    
                    )
                  
                
              
            
          
        
        
          
            
              =
              
                
                  
                    U
                    t
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    ln
                    ⁡
                    
                      (
                      
                        
                          I
                          c
                        
                        
                          I
                          s
                        
                      
                      )
                    
                  
                
                +
                
                  
                    I
                    c
                  
                  ⁢
                  
                    R
                    eq
                  
                
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




Consequently, to remove the effect of the parasitic resistances, the aim must be to compensate for the effect of the compensating resistance Req (shown in FIG. 5) on the base-emitter voltage Ube. Traditionally, base-emitter interfaces are connected in series for this purpose.

For this purpose, in particular, constructing bandgap reference circuits in such a way that a temperature-proportional voltage, that is a voltage with a positive temperature coefficient, is added to a voltage which is inversely temperature-proportional and consequently has a negative temperature coefficient, in such a way that the resulting voltage has a negligible temperature coefficient, is known. The temperature-proportional voltage can be obtained as a voltage difference between two transistors which are operated with different current densities, whereas the voltage with the negative temperature coefficient is obtained as a voltage over a base-emitter interface.
The principle explained above will be described in more detail below with reference to FIG. 6, wherein in FIG. 6 a circuit arrangement called a Widlar bandgap reference circuit is shown.
The circuit arrangement shown in FIG. 6 consists essentially of a temperature-proportional first circuit section 1, which can also be called the PTAT (“proportional to absolute temperature”) circuit section, and an inversely temperature-proportional second circuit section 2, which can be called the IPTAT (“inversely proportional to absolute temperature”) circuit section. The first circuit section 1 includes two bipolar transistors Q1 and Q2, which are connected to each other as shown in FIG. 6. The bipolar transistors Q1 and Q2 are also connected to resistors Rbias, Rt1 and Rt2, as shown in FIG. 6. The first circuit section 1 generates a temperature-proportional current, which flows via the bipolar transistor Q2 and resistor Rt2 and generates a voltage UR12, which is proportional to the absolute temperature, there. The second circuit section 2 includes a bipolar transistor Q3, the base-emitter voltage UbeQ3 of which is inversely proportional to the absolute temperature. The output of the bandgap reference circuit is connected to the two circuit sections 1, 2 in such a way that the bandgap reference voltage Ubg which can be tapped there is defined by the sum of the voltages UR12 and UbeQ3.
Irrespective of the fact that using the bandgap reference circuit shown in FIG. 6, a bandgap reference voltage with a mostly negligible temperature coefficient can be generated, the parasitic resistances which were explained above on the basis of FIGS. 4 and 5 are still included in the circuit, and because of their temperature coefficients they affect the base-emitter voltages of the relevant bipolar transistors and consequently the bandgap reference voltage of the entire circuit.
SUMMARY
This invention is therefore based on the object of providing a bandgap reference circuit in which there is compensation for the effect of parasitic resistances, so that a high-precision bandgap reference voltage can be generated.
According to the invention, this object is achieved by a bandgap reference circuit according to preferred and advantageous embodiments of this invention.
According to embodiments of the invention, it is proposed that with a first circuit section a temperature-proportional voltage should be generated, and with a second circuit section an inversely temperature-proportional voltage should be generated, in such a way that as the combination, particularly the sum, of both voltages, the desired bandgap reference voltage can be tapped via an output terminal. To remove the effect of parasitic resistances in both circuit sections, the appropriate voltage is generated as a combination of multiple base-emitter voltages of corresponding bipolar transistors of an appropriate bipolar transistor circuit.
The temperature-proportional first circuit section preferably includes four bipolar transistors, which are connected to each other in such a way that at a resistor which is connected to the emitter of one of the bipolar transistors a voltage proportional to the absolute temperature is generated. This voltage consists of the sum of two base-emitter voltages of two of the four bipolar transistors, from which in turn the base-emitter voltages of the other two bipolar transistors are subtracted. This temperature-proportional voltage is directly related to a corresponding temperature-proportional current, which corresponds to the collector current of the bipolar transistor connected to the above-mentioned resistor, and is preferably fed to the inversely temperature-proportional second circuit section.
By specially choosing the currents which flow via the individual bipolar transistors and the effective transistor areas of the individual bipolar transistors of the first circuit section, it is possible to achieve that the effect of the parasitic resistances is completely removed.
The inversely temperature-proportional second circuit section preferably also includes multiple bipolar transistors, which are connected to each other in such a way that as the inversely temperature-proportional voltage, a base-emitter voltage consisting of the sum of the base-emitter voltages of two of the bipolar transistors, from which the base-emitter voltage of another bipolar transistor is subtracted, can be obtained. If the effective transistor area of these three bipolar transistors is chosen to conform to a specified ratio, compensation for the effect of the parasitic resistance can also be achieved for the second circuit section.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention is explained in more detail below, with reference to the attached drawings and on the basis of a preferred embodiment.
FIG. 1 shows a simplified circuit diagram of a PTAT circuit section of a bandgap reference circuit according to a preferred embodiment of this invention,
FIG. 2 shows a simplified circuit diagram of an IPTAT circuit section of the bandgap reference circuit according to the invention,
FIG. 3 shows the complete bandgap reference circuit consisting of the circuit sections shown in FIGS. 1 and 2,
FIG. 4 shows a bipolar transistor with parasitic base and emitter resistances,
FIG. 5 shows a replacement circuit diagram for the bipolar transistor shown in FIG. 4, with an equivalent parasitic emitter resistance, and
FIG. 6 shows a Widlar bandgap reference circuit according to the prior art.



DETAILED DESCRIPTION
In FIG. 1, a circuit diagram of a PTAT circuit section 1 of a bandgap reference circuit according to the invention is shown. This circuit section generates a temperature-proportional voltage and a corresponding temperature-proportional current It.
For this purpose, the circuit section 1 includes four bipolar transistors Q1-Q4, which are connected to each other as shown in FIG. 1. The bipolar transistor Q1, with its collector-emitter link, is connected between a positive supply voltage potential and earth. The collector of the bipolar transistor Q1 is connected to the base of the bipolar transistor Q2. The current which is fed to the connecting point between the collector of the bipolar transistor Q1 and the base of the bipolar transistor Q2 is designated I1. The emitter of the bipolar transistor Q2 is connected to the base of the bipolar transistor Q1. The base of the bipolar transistor Q3 is also connected to the collector of the bipolar transistor Q1, and the emitter of the bipolar transistor Q3 is connected to the base of the bipolar transistor Q4. The bipolar transistor Q4, with its collector-emitter link, similarly to the bipolar transistor Q1, is connected between the positive supply voltage potential and earth. Between the earth potential and the emitter of the bipolar transistor Q4, a resistor Rt1 is arranged. The above-mentioned temperature-proportional current It corresponds to the collector current of the bipolar transistor Q4.
In FIG. 1, for clarity, the individual parasitic resistances are not shown.
Ideally, the voltage which drops out at the resistor Rt1 should be temperature-proportional. If it is assumed that a bipolar transistor of area n can be understood as n individual transistors, the voltage URt1 which drops out at the resistor Rt1 can be calculated as follows:




  
    
      
        
          
            
              
                U
                Rt1
              
              =
              
              ⁢
              
                
                  U
                  be1
                
                +
                
                  U
                  be2
                
                -
                
                  U
                  be3
                
                -
                
                  U
                  be4
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    U
                    t
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    ln
                    ⁡
                    
                      (
                      
                        
                          I
                          1
                        
                        
                          I
                          s1
                        
                      
                      )
                    
                  
                
                +
                
                  
                    R
                    eq1
                  
                  ⁢
                  
                    I
                    1
                  
                
                +
                
                  
                    U
                    t
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    ln
                    ⁡
                    
                      (
                      
                        
                          I
                          2
                        
                        
                          I
                          s2
                        
                      
                      )
                    
                  
                
                +
                
                  
                    R
                    eq2
                  
                  ⁢
                  
                    I
                    2
                  
                
                -
              
            
          
        
        
          
            
              
              ⁢
              
                
                  
                    U
                    t
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    ln
                    ⁡
                    
                      (
                      
                        
                          I
                          3
                        
                        
                          I
                          s3
                        
                      
                      )
                    
                  
                
                -
                
                  
                    R
                    eq3
                  
                  ⁢
                  
                    I
                    3
                  
                
                -
                
                  
                    U
                    t
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    ln
                    ⁡
                    
                      (
                      
                        
                          I
                          t
                        
                        
                          I
                          s4
                        
                      
                      )
                    
                  
                
                -
                
                  
                    R
                    eq4
                  
                  ⁢
                  
                    I
                    t
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    U
                    t
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    ln
                    ⁡
                    
                      (
                      
                        
                          
                            
                              I
                              1
                            
                            ⁢
                            
                              I
                              2
                            
                          
                          
                            
                              I
                              3
                            
                            ⁢
                            
                              I
                              t
                            
                          
                        
                        ⁢
                        
                          
                            
                              A
                              3
                            
                            ⁢
                            
                              A
                              4
                            
                          
                          
                            
                              A
                              1
                            
                            ⁢
                            
                              A
                              2
                            
                          
                        
                      
                      )
                    
                  
                
                +
                
                  
                    R
                    eq
                  
                  ⁡
                  
                    (
                    
                      
                        
                          I
                          1
                        
                        
                          A
                          1
                        
                      
                      +
                      
                        
                          I
                          2
                        
                        
                          A
                          2
                        
                      
                      -
                      
                        
                          I
                          3
                        
                        
                          A
                          3
                        
                      
                      -
                      
                        
                          I
                          t
                        
                        
                          A
                          4
                        
                      
                    
                    )
                  
                
              
            
          
        
        
          
            
              
              ⁢
              
                (
                
                  
                    R
                    eqn
                  
                  =
                  
                    
                      R
                      eq
                    
                    
                      A
                      n
                    
                  
                
                )
              
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




Ubei designates the base-emitter voltage of the bipolar transistor Qi, where i=1 . . . 4, and Isi designates the reverse current of the bipolar transistor Qi. Ut designates the thermoelectric voltage, and Reqi designates the compensating resistance, at the emitter of the bipolar transistor Qi according to the circuit diagram shown in FIG. 5. Finally, Ai designates the transistor area of the bipolar transistor Qi. Req is the equivalent parasitic resistance of a unit transistor.

To generate an exclusively temperature-proportional voltage URt1, according to Formula (3) the following two conditions must be fulfilled:




  
    
      
        
          
            
              
                
                  
                    
                      I
                      1
                    
                    ⁢
                    
                      I
                      2
                    
                  
                  
                    
                      I
                      3
                    
                    ⁢
                    
                      I
                      t
                    
                  
                
                ⁢
                
                  
                    
                      A
                      3
                    
                    ⁢
                    
                      A
                      4
                    
                  
                  
                    
                      A
                      1
                    
                    ⁢
                    
                      A
                      2
                    
                  
                
              
              ≠
              1
            
          
          
            and
          
          
            
              
                
                  
                    I
                    1
                  
                  
                    A
                    1
                  
                
                +
                
                  
                    I
                    2
                  
                  
                    A
                    2
                  
                
              
              =
              
                
                  
                    I
                    3
                  
                  
                    A
                    3
                  
                
                +
                
                  
                    I
                    t
                  
                  
                    A
                    4
                  
                
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




In the preferred application case, the currents I1, I2, I3 correspond to the temperature-proportional output current It, which can be implemented by using appropriate current mirrors (not shown in FIG. 1 for simplicity). In this special application case, for instance, A1=4, A2=6, A3=12 and A4=3 can be chosen, obviously without the transistor areas being restricted to this particular embodiment.

In FIG. 2, an IPTAT circuit section 2 of the bandgap reference circuit according to the invention is shown.
In contrast to the traditional Widlar bandgap reference circuit shown in FIG. 6, in which the IPTAT circuit section includes only one bipolar transistor, according to FIG. 2 four bipolar transistors Q5-Q8, connected to each other, are provided. Whereas in the prior art the base-emitter voltage, which is inversely proportional to temperature, of the only bipolar transistor is relatively strongly affected by the parasitic resistances of the bipolar transistor, by using the circuit arrangement shown in FIG. 2 a base-emitter voltage can be obtained as an inversely temperature-proportional voltage Ube0, which is not affected by parasitic base or emitter resistances. According to FIG. 2, this is achieved by two base-emitter voltages first being added and a base-emitter voltage being subtracted from the sum, so that by suitable transistor scaling compensation of all parasitic effects can be achieved.
As can be seen in FIG. 2, the temperature-proportional current It which is generated from the PTAT circuit section 1 is used as the operating current for the bipolar transistors Q5 and Q6, which are connected as diodes (the collector and base of the bipolar transistors Q5 and Q6 are each short-circuited). It is also assumed that the two bipolar transistors Q6 and Q8 are identically dimensioned.
The base of the bipolar transistor Q5 is connected to the base of the bipolar transistor Q7, whereas the base of the bipolar transistor Q6 is connected to the base of the bipolar transistor Q8. Additionally, the emitter of the bipolar transistor Q5 is connected to the collector of the bipolar transistor Q6, whereas the emitter of the bipolar transistor Q7 is connected to the collector of the bipolar transistor Q8. The emitter terminals of the bipolar transistors Q6 and Q8 are each connected to earth potential. Between the emitter of the bipolar transistor Q7 and the collector of the bipolar transistor Q8, there is an output terminal.
The output voltage of the circuit section shown in FIG. 2 is defined as follows (the bipolar transistor Q7 gives Ube, whereas the bipolar transistor Q8 gives the current through the bipolar transistor Q7):




  
    
      
        
          
            
              
                U
                be0
              
              =
              
              ⁢
              
                
                  U
                  be5
                
                +
                
                  U
                  be6
                
                -
                
                  U
                  be7
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    U
                    t
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    ln
                    ⁡
                    
                      (
                      
                        
                          I
                          t
                        
                        
                          I
                          s5
                        
                      
                      )
                    
                  
                
                +
                
                  
                    R
                    eq5
                  
                  ⁢
                  
                    I
                    t
                  
                
                +
                
                  
                    U
                    t
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    ln
                    ⁡
                    
                      (
                      
                        
                          I
                          t
                        
                        
                          I
                          s6
                        
                      
                      )
                    
                  
                
                +
                
                  
                    R
                    eq6
                  
                  ⁢
                  
                    I
                    t
                  
                
                -
              
            
          
        
        
          
            
              
              ⁢
              
                
                  
                    U
                    t
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    ln
                    ⁡
                    
                      (
                      
                        
                          I
                          t
                        
                        
                          I
                          s7
                        
                      
                      )
                    
                  
                
                -
                
                  
                    R
                    eq7
                  
                  ⁢
                  
                    I
                    t
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    U
                    t
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    ln
                    ⁡
                    
                      (
                      
                        
                          I
                          t
                        
                        ⁢
                        
                          
                        
                        ⁢
                        
                          
                            I
                            s7
                          
                          
                            
                              I
                              s5
                            
                            ⁢
                            
                              I
                              s6
                            
                          
                        
                      
                      )
                    
                  
                
                +
                
                  
                    R
                    eq
                  
                  ⁢
                  
                    
                      I
                      t
                    
                    ⁡
                    
                      (
                      
                        
                          1
                          
                            A
                            5
                          
                        
                        +
                        
                          1
                          
                            A
                            6
                          
                        
                        -
                        
                          1
                          
                            A
                            7
                          
                        
                      
                      )
                    
                  
                
              
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




Regarding the values which are included in Formula (5), refer to the explanations about Formula (3).
To compensate for the parasitic part of Ube0, the following condition must be fulfilled:




  
    
      
        
          
            1
            
              A
              5
            
          
          +
          
            1
            
              A
              6
            
          
        
        =
        
          1
          
            A
            7
          
        
      
    
    
      
        (
        6
        )
      
    
  




In FIG. 3, the bandgap reference circuit consisting of the two circuit sections 1, 2 is shown as a whole. Additionally to FIG. 2, between the emitter of the bipolar transistor Q5 and the collector of the bipolar transistor Q6, a resistor Rt2 is inserted, so that at the resistor Rt2, because of the temperature-proportional current It, a temperature-proportional voltage URt2 drops out. Thus, for the bandgap reference voltage Ubg which can be tapped between the emitter of the bipolar transistor Q7 and the collector of the bipolar transistor Q8, the following applies:

Ubg=Ube0+URt2  (7)

From Formula (7), it can be seen that the bandgap reference voltage Ubg consists of the sum of the inversely temperature-proportional voltage Ube0 and the temperature-proportional voltage URt2, but because of the special construction of the two circuit sections 1, 2, there is compensation for the effects of parasitic resistances of the bipolar transistors which are used. Thus in total, a bandgap reference voltage without a temperature coefficient, or with only a negligible temperature coefficient, is provided, and additionally effects of parasitic resistances are removed.
From FIG. 3, it can be seen that the temperature-proportional current It which is generated by the PTAT circuit section 1 is used to operate the whole bandgap reference circuit. In FIG. 3, the current mirrors which are used to impress the current It onto the bipolar transistors Q1-Q3 and the bipolar transistors Q5-Q6 are indicated in the form of an appropriate current balancing circuit 3 in combination with appropriate current sources.
Since the PTAT circuit section 1 is itself biased with the current It, care should be taken that operation of the PTAT circuit section 1 is started correctly, which can be done simply by using a startup circuit.

## Claims

1. A bandgap reference circuit, comprising:
a first circuit section having a first plurality of bipolar transistors configured to generate a temperature-proportional voltage, the temperature-proportional voltage generated as a combination of multiple base-emitter voltages of at least some of the first plurality of bipolar transistors;
a second circuit section having a second plurality of bipolar transistors configured to generate an inversely temperature-proportional voltage, the inversely temperature-proportional voltage generated as a combination of multiple base-emitter voltages of at least some of the second plurality of bipolar transistors; and
wherein the first circuit section and the second circuit section are connected to each other in such a way that, at an output terminal of the bandgap reference circuit, a bandgap reference voltage is tapped as a combination of the temperature-proportional voltage of the first circuit section and the inversely temperature-proportional voltage of the second circuit section;
wherein the first circuit section includes four bipolar transistors connected such that the temperature-proportional voltage is generated as the sum of the base-emitter voltages of first and second of the four bipolar transistors minus the base-emitter voltages of third and fourth of the four bipolar transistors;
a collector of the first bipolar transistor of the first circuit section is connected to a base of the second bipolar transistor and a base of the third bipolar transistor of the first circuit section;
an emitter of the second bipolar transistor of the first circuit section is connected to a base of the first bipolar transistor of the first circuit section;
an emitter of the third bipolar transistor of the first circuit section is connected to a base of the fourth bipolar transistor of the first circuit section; and
the temperature-proportional voltage is provided at an emitter of the fourth bipolar transistor of the first circuit section.

2. The bandgap reference circuit according to claim 1, wherein the first circuit section and the second circuit section are connected to each other in such a way that, at the output terminal of the bandgap reference circuit, the bandgap reference voltage is tapped as the sum of the temperature-proportional voltage of the first circuit section and the inversely temperature-proportional voltage of the second circuit section.

3. The bandgap reference circuit according to claim 1, wherein the four bipolar transistors of the first circuit section are configured to generate the temperature-proportional voltage proportionally to the expression




  
    
      U
      t
    
    ⁢
    
      
    
    ⁢
    
      ln
      ⁡
      
        (
        
          
            
              
                I
                1
              
              ⁢
              
                I
                2
              
            
            
              
                I
                3
              
              ⁢
              
                I
                t
              
            
          
          ⁢
          
            
              
                A
                3
              
              ⁢
              
                A
                4
              
            
            
              
                A
                1
              
              ⁢
              
                A
                2
              
            
          
        
        )
      
    
  
  ,




where I1 designates a current which is provided to a connecting point between the collector of the first bipolar transistor and the base of the second bipolar transistor, I2 designates a current which is derived from a connecting point between the base of the first bipolar transistor and the emitter of the second bipolar transistor, I3 designates a current which is derived from a connecting point between the emitter of the third bipolar transistor and the base of the fourth bipolar transistor, It designates a current which is fed to a collector of the fourth bipolar transistor, and Ut designates the thermoelectric voltage, and where A1, A2, A3 and A4 designate a transistor area of the first, second, third and fourth bipolar transistor respectively of the first circuit section.

4. The bandgap reference circuit according to claim 3, wherein the currents I1, I2, I3, It and the transistor areas A1, A2, A3, A4 are chosen so that the following is true:




  
    
      
        I
        1
      
      
        A
        1
      
    
    +
    
      
        I
        2
      
      
        A
        2
      
    
  
  =
  
    
      
        I
        3
      
      
        A
        3
      
    
    +
    
      
        
          I
          t
        
        
          A
          4
        
      
      .

5. The bandgap reference circuit according to claim 3, wherein the first circuit section is in such a form that the currents I1, I2, I3 and It are substantially the same.

6. The bandgap reference circuit according to claim 3, wherein the first circuit section includes current mirrors, so that each of the currents I1, I2, I3 is generated as a current which is generated from the current It by the current mirrors.

7. A bandgap reference circuit, comprising:
a first circuit section having a first plurality of bipolar transistors configured to generate a temperature-proportional voltage, the temperature-proportional voltage generated as a combination of multiple base-emitter voltages of at least some of the first plurality of bipolar transistors;
a second circuit section having a second plurality of bipolar transistors configured to generate an inversely temperature-proportional voltage, the inversely temperature-proportional voltage generated as a combination of multiple base-emitter voltages of at least some of the second plurality of bipolar transistors; and
wherein the first circuit section and the second circuit section are connected to each other in such a way that, at an output terminal of the bandgap reference circuit, a bandgap reference voltage is tapped as a combination of the temperature-proportional voltage of the first circuit section and the inversely temperature-proportional voltage of the second circuit section, wherein the second circuit section includes three bipolar transistors configured such that the inversely temperature-proportional voltage is generated as the sum of base-emitter voltages of first and second of the three bipolar transistors minus a base-emitter voltage of a third of the three bipolar transistors.

8. The bandgap reference circuit according to claim 7, wherein:
the second circuit section includes a first bipolar transistor, a second bipolar transistor and a third bipolar transistor;
an emitter of the first bipolar transistor of the second circuit section is connected to a collector of the second bipolar transistor of the second circuit section,
a collector and base of the first bipolar transistor and the collector and a base of the second bipolar transistor of the second circuit section are connected to each other,
the base of the first bipolar transistor of the second circuit section being connected to a base of the third bipolar transistor of the second circuit section, and
the inversely temperature-proportional voltage of the second circuit section is generated at an emitter of the third bipolar transistor of the second circuit section.

9. Bandgap reference circuit according to claim 8, wherein the second circuit section includes a fourth bipolar transistor, the base of which is connected to the base of the second bipolar transistor of the second circuit section, and the collector of which is connected to the emitter of the third bipolar transistor of the second circuit section.

10. Bandgap reference circuit according to claim 9, wherein the second bipolar transistor of the second circuit section and the fourth bipolar transistor of the second circuit section have the same design.

11. Bandgap reference circuit according to claim 8, wherein the bipolar transistors of the second circuit section are connected to each other in such a way that the inversely temperature-proportional voltage is generated according to the expression




  
    
      U
      t
    
    ⁢
    
      
    
    ⁢
    
      ln
      ⁡
      
        (
        
          
            I
            t
          
          ⁢
          
            
          
          ⁢
          
            
              I
              s7
            
            
              
                I
                s5
              
              ⁢
              
                I
                s6
              
            
          
        
        )
      
    
  
  ,




where It designates a current which is fed to a connecting point between the collector and the base of the first bipolar transistor of the second circuit section, Is5 designates a reverse current of the first bipolar transistor of the second circuit section, Is6 designates a reverse current of the second bipolar transistor of the second circuit section, Is7 designates a reverse current of the third bipolar transistor of the second circuit section, and Ut designates the thermoelectric voltage.

12. Bandgap reference circuit according to claim 8, wherein the first bipolar transistor, the second bipolar transistor and the third bipolar transistor of the second circuit section have transistor areas according to the relationship




  
    
      
        1
        
          A
          5
        
      
      +
      
        1
        
          A
          6
        
      
    
    =
    
      1
      
        A
        7
      
    
  
  ,




where A5 designates the transistor area of the first bipolar transistor of the second circuit section, A6 designates the transistor area of the second bipolar transistor of the second circuit section, and A7 designates the transistor area of the third bipolar transistor of the second circuit section.

13. Bandgap reference circuit according to claim 8, wherein the first circuit section is designed such that, depending on the temperature-proportional voltage, it generates a temperature-proportional current, and wherein current mirrors are provided between the first circuit section and the second circuit section in such a way that a current is fed to a connecting point between the collector and the base of the first bipolar transistor of the second circuit section, corresponding to the temperature-proportional current of the first circuit section, which is replicated by the current mirrors.

14. A bandgap reference circuit, comprising:
a first circuit section having at least four bipolar transistors configured to generate a temperature-proportional voltage, the temperature-proportional voltage generated as a combination of multiple base-emitter voltages of at least some of the at least four bipolar transistors;
a second circuit section having at least three bipolar transistors configured to generate an inversely temperature-proportional voltage, the inversely temperature-proportional voltage generated as a combination of multiple base-emitter voltages of at least some of the at least three bipolar transistors; and
wherein the first circuit section and the second circuit section are connected to each other in such a way that, at an output terminal of the bandgap reference circuit, a bandgap reference voltage is tapped as a combination of the temperature-proportional voltage of the first circuit section and the inversely temperature-proportional voltage of the second circuit section;
wherein the temperature-proportional voltage is generated as the sum of the base-emitter voltages of first and second of the four bipolar transistors minus the base-emitter voltages of third and fourth of the four bipolar transistors a collector of the first bipolar transistor of the first circuit section is connected to a base of the second bipolar transistor and a base of the third bipolar transistor of the first circuit section;
an emitter of the second bipolar transistor of the first circuit section is connected to a base of the first bipolar transistor of the first circuit section;
an emitter of the third bipolar transistor of the first circuit section is connected to a base of the fourth bipolar transistor of the first circuit section; and
the temperature-proportional voltage is provided at an emitter of the fourth bipolar transistor of the first circuit section.

15. The bandgap reference circuit according to claim 14, wherein the second circuit section includes three bipolar transistors configured such that the inversely temperature-proportional voltage is generated as the sum of base-emitter voltages of first and second of the three bipolar transistors minus a base-emitter voltage of a third of the three bipolar transistors.

16. The bandgap reference circuit according to claim 15, wherein:
the second circuit section includes a first bipolar transistor, a second bipolar transistor and a third bipolar transistor;
an emitter of the first bipolar transistor of the second circuit section is connected to a collector of the second bipolar transistor of the second circuit section,
a collector and base of the first bipolar transistor and the collector and a base of the second bipolar transistor of the second circuit section are connected to each other,
the base of the first bipolar transistor of the second circuit section being connected to a base of the third bipolar transistor of the second circuit section, and
the inversely temperature-proportional voltage of the second circuit section is generated at an emitter of the third bipolar transistor of the second circuit section.

17. The bandgap reference circuit according to claim 16, wherein the second circuit section includes a fourth bipolar transistor having a base connected to the base of the second bipolar transistor of the second circuit section, the fourth bipolar transistor further including a collector connected to the emitter of the third bipolar transistor of the second circuit section.