# Patent

## Title
Method for clock control of clocked half-rail differential logic with sense amplifier and single-rail logic

## Abstract

Clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention do not include complementary logic elements. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. In addition, the clocked half-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic block to provide a driver function.

## Background
FIELD OF THE INVENTION
The present invention relates generally to logic circuits and, more particularly, to half-rail differential logic circuits.
BACKGROUND OF THE INVENTION
With the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power circuits and systems. This demand has motivated circuit designers to depart from conventional circuit designs and venture into more power efficient alternatives. As part of this effort, half-rail differential logic has emerged as an important design tool for increasing power efficiency.
FIG. 1A shows a schematic diagram of one embodiment of a clocked half-rail differential logic circuit 100 designed according to the principles of the invention set forth in patent application Ser. No. 09/927,751, entitled “Clocked Half-Rail Differential Logic”, filed Aug. 9, 2001, in the name of the present inventor, assigned to the assignee of the present invention, and incorporated herein by reference, in its entirety. As seen in FIG. 1A, a clock signal CLK is coupled to an input node 132 of a clock inverter 134 to yield a clock-not signal CLKBAR at output node 136 of clock inverter 134.
As also seen in FIG. 1A, clocked half-rail differential logic circuit 100 includes a first supply voltage 102 coupled to a source, or first flow electrode 130, of a PFET 101. The signal CLKBAR is coupled to a control electrode or gate 103 of PFET 101 and a control electrode or gate 129 of an NFET 109. A drain, or second flow electrode 104, of PFET 101 is coupled to both a source, or first flow electrode 106, of a PFET 105 and a source, or first flow electrode 108, of a PFET 107. A control electrode or gate 116 of PFET 105 is coupled to a first flow electrode 140 of NFET 109 and an OUTBAR terminal 113. A control electrode or gate 114 of PFET 107 is coupled to a second flow electrode 138 of NFET 109 and an OUT terminal 111. A drain, or second flow electrode 110, of PFET 105 is coupled to OUT terminal 111 and a drain, or second flow electrode 112, of PFET 107 is coupled to OUTBAR terminal 113.
OUT terminal 111 is coupled to a terminal 118 of a base logic portion 123A of a logic block 123 and OUTBAR terminal 113 is coupled to a terminal 120 of a complementary logic portion 123B of logic block 123. Base logic portion 123A of logic block 123 includes any type of differential logic and/or circuitry used in the art including various logic gates, logic devices and circuits. Complementary logic portion 123B of logic block 123 includes any type of complementary differential logic and/or circuitry used in the art including various logic gates, logic devices and circuits. As discussed in more detail below, since clocked half-rail differential logic circuit 100 was a dual rail logic circuit, requiring an output OUT 111 and a complementary output OUTBAR 113, in the prior art, logic block 123 had to include both a base logic portion 123A, such as an AND gate, OR gate, XOR gate, etc. and the complementary logic portion 123B of base logic portion 123A, such as a NAND gate, NOR gate, XNOR gate, etc. Logic block 123 also includes first and second input terminals 151 and 153 that are typically coupled to an OUT and OUTBAR terminal of a previous clocked half-rail differential logic circuit stage (not shown).
Logic block 123 also includes fourth terminal 122 coupled to a drain, or first flow electrode 124, of an NFET 125. A gate or control electrode 127 of NFET 125 is coupled to the signal CLK and a source, or second flow electrode 126, of NFET 125 is coupled to a second supply voltage 128.
A particular embodiment of a clocked half-rail differential logic circuit 100 is shown in FIG. 1A. Those of skill in the art will recognize that clocked half-rail differential logic circuit 100 can be easily modified. For example, different transistors, i.e., first, second and third PFETs 101, 105 and 107 or first and second NFETs 109 and 125 can be used. In particular, the NFETs and PFETS shown in FIG. 1A can be readily exchanged for PFETs and NFETs by reversing the polarities of the supply voltages 102 and 128, or by other well known circuit modifications. Consequently, the clocked half-rail differential logic circuit 100 that is shown in FIG. 1A is simply used for illustrative purposes.
Clocked half-rail differential logic circuit 100 had two modes, or phases, of operation; a pre-charge phase and an evaluation phase. In one embodiment of a clocked half-rail differential logic circuit 100, in the pre-charge phase, the signal CLK was low or a digital “0” and the signal CLKBAR was high or a digital “1”. Consequently, first PFET 101 and second NFET 125 were not conducting or were “off” and logic block 123 was isolated from first supply voltage 102 and second supply voltage 128. In addition, during the pre-charge phase, first NFET 109 was conducting or was “on” and, therefore, OUT terminal 111 was shorted to OUTBAR terminal 113. Consequently, the supply voltage to logic block 123 was approximately half the supply voltage 102, i.e., for a first supply voltage 102 of Vdd and a second supply voltage 128 of ground, logic block 123 operated at around Vdd/2. During pre-charge, second and third PFETs 105 and 107 were typically not performing any function.
In one embodiment of a clocked half-rail differential logic circuit 100, in the evaluation phase, the signal CLK was high or a digital “1” and the signal CLKBAR was low or a digital “0”. Consequently, first PFET 101 and second NFET 125 were conducting or were “on” and first NFET 109 was not conducting or was “off”. Consequently, depending on the particular logic in logic block 123, either second PFET 105, or third PFET 107, was conducting or was “on” and the other of second PFET 105, or third PFET 107, was not conducting or was “off”. As a result, either OUT terminal 111 went from approximately half first supply voltage 102 to approximately second supply voltage 128 or OUTBAR terminal 113 went from approximately half first supply voltage 102 to approximately first supply voltage 102, i.e., for a first supply voltage 102 of Vdd and a second supply voltage 128 of ground, OUT terminal 111 went from approximately Vdd/2 to zero and OUTBAR terminal 113 went from approximately Vdd/2 to Vdd.
Clocked half-rail differential logic circuits 100 marked a significant improvement over prior art half-rail logic circuits in part because clocked half-rail differential logic circuit 100 does not require the complex control circuitry of prior art half-rail differential logic circuits and is therefore simpler, saves space and is more reliable than prior art half-rail differential logic circuits. As a result, clocked half-rail differential logic circuits 100 are better suited to the present electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation. However, clocked half-rail differential logic circuit 100 has some limitations.
For instance, as noted above, since clocked half-rail differential logic circuit 100 was a dual rail logic circuit, requiring an output OUT 111 and a complementary output OUTBAR 113, in the prior art, logic block 123 had to include both a base logic function, via base logic portion 123A of logic block 123, such as an AND gate, OR gate, XOR gate, etc. and the complementary logic function, via complementary logic portion 123B of logic block 123, such as a NAND gate, NOR gate, XNOR gate, etc.
FIG. 1B shows one particular embodiment of a clocked half-rail differential logic circuit 100A that includes a base logic portion 123A that is an AND gate and a complementary logic portion 123B that is a NAND gate. As shown in FIG. 1B, AND gate 123A includes NFET 161 and NFET 163 connected in series. Input 151 is coupled to the control electrode, or gate, of NFET 161 and input 153 is coupled to the control electrode or gate of NFET 163. As also shown in FIG. 1B, NAND gate 123A includes NFET 171 and NFET 173 connected in parallel. Input 151BAR is coupled to the control electrode, or gate, of NFET 171 and input 153BAR is coupled to the control electrode or gate of NFET 173. Consequently, in the prior art, four transistors were required to provide the output OUT 111 and its complementary output OUTBAR 113.
This need in the prior art to include both a base logic function and its complementary logic function resulted in an increase in power usage, an increase in space used, an increase in design complexity, and an increase in heat production.
In addition, clocked half-rail differential logic circuit 100 worked very well under conditions of a light load, for instance under conditions where fan out was less than four. However, clocked half-rail differential logic circuit 100 was less useful under conditions of a heavy load, for instance, in cases where fan out exceeded four. The shortcomings of clocked half-rail differential logic circuit 100 arose primarily because under heavy load conditions logic block 123, and the transistors and components making up logic block 123, had to be increased in size to act as a driver for the next stage in the cascade. This in turn meant that logic block 123 was large, slow and inefficient. The problem was further aggravated as additional clocked half-rail differential logic circuits 100 were cascaded together to form the large chains commonly used in the industry. Consequently, the full potential of clocked half-rail differential logic circuit 100 was not realized and its use was narrowly limited to light load applications.
What is needed is a method and apparatus for creating clocked half-rail differential logic circuits that use less power, generate less heat, require less space, are simpler in design, and that are capable of efficient use under heavy loads so that they are more flexible, more space efficient and more reliable than prior art half-rail differential logic circuits.
SUMMARY OF THE INVENTION
According to the invention, the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention do not include complementary logic portions. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output OUTBAR. Consequently, clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention use less power and, therefore, generate less heat, require less space, and are simpler in design so that they are more flexible, more space efficient and more reliable than prior art half-rail differential logic circuits.
In addition, the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention include a sense amplifier circuit that is triggered by the delayed clock of the following stage, i.e., the clock input to the sense amplifier circuit of the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention is additionally delayed with respect to the delayed clock that drives the clocked half-rail logic. The addition of the sense amplifier circuit, and second delayed clock signal, according to the invention, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the logic block, and the transistors and components making up the logic block, to provide the driver function. Consequently, the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art half-rail differential logic circuits.
The clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention can be cascaded together to form the chains commonly used in the industry. When the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention are cascaded together, the advantages of the clocked half-rail differential logic circuits of the invention are particularly evident and the gains in terms of power efficiency, size reduction, and flexibility are further pronounced.
One embodiment of the invention is a clocked half-rail differential logic circuit with single-rail logic and sense amplifier that includes a clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal and a clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a first transistor including a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode. The first transistor first flow electrode is coupled to a first supply voltage.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a second transistor, the second transistor including a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode. The first transistor second flow electrode is coupled to the second transistor first flow electrode and the second transistor second flow electrode is coupled to the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a third transistor, the third transistor including a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode. The first transistor second flow electrode is coupled to the third transistor first flow electrode and the third transistor second flow electrode is coupled to the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a fourth transistor, the fourth transistor including a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode. The second transistor control electrode is coupled to the fourth transistor first flow electrode and the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal. The third transistor control electrode is coupled to the fourth transistor second flow electrode and the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a base logic portion, the base logic portion including a base logic portion first input terminal, a base logic portion second input terminal, a base logic portion OUT terminal, and a base logic portion fourth terminal. The base logic portion OUT terminal is coupled to the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a fifth transistor, the fifth transistor including a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode. The fifth transistor first flow electrode is coupled to the base logic portion fourth terminal and the fifth transistor second flow electrode is coupled to a second supply voltage.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a complementary output transistor, the complementary output transistor including a complementary output transistor first flow electrode, a complementary output transistor second flow electrode and a complementary output transistor control electrode. According to the invention, the complementary output transistor first flow electrode is coupled to the second flow electrode of the third transistor and the OUTBAR terminal of the clocked half-rail differential logic circuit with single-rail logic and sense amplifier. The complementary output transistor second flow electrode is coupled to the first flow electrode of the fifth transistor. The complementary output transistor control electrode is coupled to the second flow electrode of the fourth transistor and the OUT terminal of the clocked half-rail differential logic circuit with single-rail logic and sense amplifier.
In one embodiment of the invention, a first clock signal CLKA is coupled to the fifth transistor control electrode. A first clock-not signal CLKABAR is coupled to the first transistor control electrode and the fourth transistor control electrode.
In one embodiment of the invention, the clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a sense amplifier circuit coupled between the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal and the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal.
In one embodiment of the invention, the clocked half-rail differential logic circuit with single-rail logic and sense amplifier includes a sixth transistor, the sixth transistor including a sixth transistor first flow electrode, a sixth transistor second flow electrode and a sixth transistor control electrode. The second transistor second flow electrode is coupled to the sixth transistor first flow electrode. The sixth transistor second flow electrode is coupled to a first node. The sixth transistor control electrode is coupled to the fourth transistor second flow electrode and the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal.
In one embodiment of the invention, the clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a seventh transistor, the seventh transistor including a seventh transistor first flow electrode, a seventh transistor second flow electrode and a seventh transistor control electrode. The third transistor second flow electrode is coupled to the seventh transistor first flow electrode. The seventh transistor second flow electrode is coupled to the first node. The seventh transistor control electrode is coupled to the fourth transistor second flow electrode and the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal.
In one embodiment of the invention, the clocked half-rail differential logic circuit sense amplifier circuit also includes an eighth transistor, the eighth transistor including an eighth transistor first flow electrode, an eighth transistor second flow electrode and an eighth transistor control electrode. The eighth transistor first flow electrode is coupled to the first node and the eighth transistor second flow electrode is coupled to a second supply voltage. A second clock signal CLKB is coupled to the eighth transistor control electrode of the clocked half-rail differential logic circuit with single-rail logic and sense amplifier. In one embodiment of the invention, the second clock signal CLKB is delayed a predetermined time with respect to the first clock signal CLKA.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.



BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in, and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the advantages and principles of the invention. In the drawings:
FIG. 1A shows a schematic diagram of a clocked half-rail differential logic circuit;
FIG. 1B shows one particular embodiment of a clocked half-rail differential logic circuit that includes a base logic portion that is an AND gate and a complementary logic portion that is a NAND gate;
FIG. 2A shows a schematic diagram of one embodiment of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier designed according to the principles of the present invention;
FIG. 2B shows one particular embodiment of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier that includes a base logic portion that is an AND gate;
FIG. 3 shows one embodiment of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier according to the principles of the present invention; and
FIG. 4 is a one embodiment of a timing diagram for the cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention shown in FIG. 3.



DETAILED DESCRIPTION
The invention will now be described in reference to the accompanying drawings. The same reference numbers may be used throughout the drawings and the following description to refer to the same or like parts.
According to the invention, the clocked half-rail differential logic circuits with single-rail logic and sense amplifier (200A in FIG. 2A, 200B in FIG. 2B and 300A, 300B and 300C in FIG. 3) of the invention do not include complementary logic portions (123B in FIGS. 1A and 1B). According to the invention, the complementary logic function of the prior art is replaced by a single complementary output transistor (281 in FIGS. 2A and 2B) appropriately sized to provide the complementary output OUTBAR (213 in FIGS. 2A and 2B). Consequently, clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention use less power and, therefore, generate less heat, require less space, and are simpler in design so that they are more flexible, more space efficient and more reliable than prior art half-rail differential logic circuits.
In addition, the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention include a sense amplifier circuit (280 in FIGS. 2A and 2B) that is triggered by the delayed clock of the following stage, i.e., the clock input to the sense amplifier circuit of the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention is additionally delayed with respect to the delayed clock that drives the clocked half-rail logic. The addition of the sense amplifier circuit, and second delayed clock signal, according to the invention, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the logic block, and the transistors and components making up the logic block, to provide the driver function. Consequently, the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art half-rail differential logic circuits.
The clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention can be cascaded together to form the chains (301 in FIG. 3) commonly used in the industry. When the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention are cascaded together, the advantages of the clocked half-rail differential logic circuits of the invention are particularly evident and the gains in terms of power efficiency, size reduction, and flexibility are further pronounced.
FIG. 2A shows a schematic diagram of one embodiment of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A designed according to the principles of the present invention. As seen in FIG. 2A, a clock signal CLKA is coupled to an input node 232 of a clock inverter 234 to yield a clock-not signal CLKABAR at output node 236 of clock inverter 234.
As also seen in FIG. 2A, clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A includes a first supply voltage 202 coupled to a source, or first flow electrode 230, of a PFET 201. The signal CLKABAR is coupled to a control electrode or gate 203 of PFET 201 and a control electrode or gate 229 of an NFET 209. A drain, or second flow electrode 204, of PFET 201 is coupled to both a source, or first flow electrode 206, of a PFET 205 and a source, or first flow electrode 208, of a PFET 207. A control electrode or gate 216 of PFET 205 is coupled to a first flow electrode 240 of NFET 209 and an OUTBAR terminal 213. A control electrode or gate 214 of PFET 207 is coupled to a second flow electrode 238 of NFET 209 and an OUT terminal 211. A drain, or second flow electrode 210, of PFET 205 is coupled to OUT terminal 211 and a drain, or second flow electrode 212, of PFET 207 is coupled to OUTBAR terminal 213.
OUT terminal 211 is coupled to a first terminal 218 of a base logic portion 123A. Base logic portion 123A includes any type of differential logic and/or circuitry used in the art including various logic gates, logic devices and circuits such as AND gates, OR gates, XOR gates etc. Base logic portion 123A also includes first and second input terminals 151 and 153 that are typically coupled to an OUT and OUTBAR terminal of a previous clocked half-rail differential logic circuit with single-rail logic and sense amplifier stage (not shown).
Base logic portion 123A also includes fourth terminal 222 coupled to a drain, or first flow electrode 224, of an NFET 225. A gate or control electrode 227 of NFET 225 is coupled to the signal CLKA and a source, or second flow electrode 226, of NFET 225 is coupled to a second supply voltage 228.
According to the invention, clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A also includes a complementary output transistor 281. Complementary output transistor includes a complementary output transistor first flow electrode 283, a complementary output transistor second flow electrode 285 and a complementary output transistor control electrode 287. According to the invention, complementary output transistor first flow electrode 283 is coupled to second flow electrode 212 of PFET 207 and OUTBAR terminal 213 of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A. Complementary output transistor second flow electrode 285 is coupled to first flow electrode 224 of NFET 225. According to the invention, complementary output transistor control electrode 287 is coupled to second flow electrode 238 of the NFET 209 and OUT terminal 211 of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A.
According to the invention, clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A also includes sense amplifier circuit 280. In one embodiment of the invention, sense amplifier circuit 280 includes a sixth transistor, NFET 215, including a drain 251, a source 253 and a control electrode or gate 252. Drain 210 of PFET 205 is coupled to drain 251 of NFET 215. Source 253 of NFET 215 is coupled to a first node 255. Gate 252 of NFET 215 is coupled to source 240 of NFET 209 and clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal 213.
In one embodiment of the invention, sense amplifier circuit 280 also includes a seventh transistor, NFET 217, including a drain 259, a source 257 and a control electrode or gate 258. Drain 212 of PFET 207 is coupled to drain 259 of NFET 217. Source 257 of NFET 217 is coupled to first node 255. Gate 258 of NFET 217 is coupled to drain 238 of NFET 209 and clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal 211.
In one embodiment of the invention, sense amplifier circuit 280 of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A also includes an eighth transistor, NFET 270, including a drain 268, a source 221 and a control electrode or gate 277. Drain 268 of NFET 270 is coupled to first node 255. Source 221 of NFET 270 is coupled to second supply voltage 228. A delayed, or second, clock signal CLKB is coupled to control electrode or gate 277 of NFET 270. According to one embodiment of the invention, clock signal CLKB is delayed with respect to clock signal CLKA by a predetermined time.
As shown above, according to the invention, the complementary logic portion 123B in FIGS. 1A and 1B, is eliminated and replaced by complementary output transistor 281 (FIG. 2A). According to the invention, complementary output transistor 281 is sized, i.e., has channel dimensions, e.g., channel width, which are smaller than the effective channel dimensions, e.g., effective channel width, of the transistors making up base logic portion 123A. According to the invention, this is specifically done to insure that discharge path 251A, between OUT terminal 211 and second supply voltage 228 through base logic portion 123A, is faster than the discharge path 251B, between OUTBAR terminal 213 and second supply voltage 228, through complementary output transistor 281, to insure proper operation of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A.
As discussed above, clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A of the invention includes sense amplifier circuit 280 that is triggered by delayed, or second, clock signal CLKB of the following stage, i.e., the clock signal CLKB to gate 277 of NFET 270 of sense amplifier circuit 280 is additionally delayed with respect to the first clock signal CLKA. Clock-not signal CLKABAR is coupled to gate 203 of PFET 201 and gate 229 of NFET 209. The addition of sense amplifier circuit 280 and second delayed clock signal CLKB, according to the invention, allows sense amplifier circuit 280 to act as the driver circuit and therefore there is no need for increasing the size of base logic portion 123A, or the components of base logic portion 123A, to provide the driver function. Consequently, clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A of the invention is capable of operating efficiently under heavy load conditions without the significant reduction in speed associated with half-rail differential logic circuits 100.
In operation, in the pre-charge phase, i.e., when signal CLKA on control electrode, or gate, 227 of NFET 225 is low, NFET 209 shorts the complementary terminals OUT 211 and OUTBAR 213 to each other, thereby equalizing the voltage on complementary terminals OUT 211 and OUTBAR 213 at near half supply voltage 202, in one embodiment Vdd/2. The voltage levels at input terminals 151 and 153 are also at near half supply voltage 202, in one embodiment Vdd/2.
In the evaluation phase, i.e., when signal CLKA on control electrode, or gate, 227 of NFET 225 switches to high, NFET 225 and PFET 201 conduct, NFET 209 is off, and complementary output transistor 281 starts to conduct. The voltage on OUTBAR terminal 213 starts to drop gradually because there is a direct path to second supply voltage 228, in one embodiment ground, through complementary output transistor 281 and NFET 209. If the combination of input signals on terminals 151 and 153 provides a path to second supply voltage 228, in one embodiment ground, on OUT terminal 211, then the voltage on OUT terminal 211 begins to drop, and drop at a faster rate than voltage drop rate on OUTBAR terminal 213, thus creating a differential voltage between OUT terminal 211 and OUTBAR terminal 213. According to the invention, sense amplifier circuit 280 is then activated by the delayed clock signal CLKB on control electrode 277 of NFET 270 that turns on NFET 270. With NFET 270 on, the discharge of either OUT terminal 211 and OUTBAR terminal 213, via NFET 215 or NFET 217, is accelerated.
As discussed above, according to the invention, the discharge path 251A of OUT terminal 211 is faster than the discharge path 251B of OUTBAR terminal 213. The cross-coupled transistor PFET 207 subsequently pulls OUTBAR terminal to first supply voltage 202, in one embodiment Vdd. If the combination of input signals on terminals 151 and 153 do not provide a path to ground for OUT terminal 211, then OUTBAR terminal 213 continues to discharge and PFET 205 charges OUT terminal 211 to first supply voltage 202, in one embodiment Vdd, when it reaches its conduction threshold.
A particular embodiment of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A is shown in FIG. 2A. Those of skill in the art will recognize that clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A can be easily modified. For example, different transistors, i.e., PFETs 201, 205 and 207 or NFETs 209, 215, 217, 270, 281 and 225 can be used. In particular, the NFETs and PFETS shown in FIG. 2A can be readily exchanged for PFETs and NFETs by reversing the polarities of the supply voltages 202 and 228, or by other well known circuit modifications. Consequently, the clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A that is shown in FIG. 2A is simply used for illustrative purposes.
FIG. 2B shows one particular embodiment of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200B that includes a base logic portion 123A that is an AND gate. As shown in FIG. 2B, AND gate 123A includes NFET 161 and NFET 163 connected in series. Input 151 is coupled to the control electrode, or gate, of NFET 161 and input 153 is coupled to the control electrode or gate of NFET 163. As also shown in FIG. 2B, according to the invention, NAND gate 123B of FIG. 1B, including NFET 171 and NFET 173, is replaced by single complementary output transistor 281 (FIG. 2B). Consequently, in this most simple example, using the method and structure of the invention results a significant reduction in components. Of course, those of skill in the art will recognize that when more complicated logic functions make up base logic portion 123A, using the present invention, even more components will be eliminated at an even greater savings in terms of dissipated power and heat, space, and circuit complexity.
As discussed above, clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A can be cascaded together with other clocked half-rail differential logic circuits with single-rail logic and sense amplifier 200A to form the chains commonly used in the industry. When clocked half-rail differential logic circuits with single-rail logic and sense amplifier 200A of the invention are cascaded together, the advantages of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A is particularly evident and the gains in terms of power efficiency, size reduction and flexibility are further pronounced.
When clocked half-rail differential logic circuits with single-rail logic and sense amplifier 200A of the invention are cascaded together, the advantages of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A is particularly evident and the gains in terms of efficiency, size reduction and flexibility are further pronounced. When clocked half-rail differential logic circuits with single-rail logic and sense amplifier 200A of the invention are cascaded together, the clock signal CLKA is, according to the invention, timed to be at least the delay of the previous clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A (not shown) to ensure each clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A.
FIG. 3 shows one embodiment of a cascaded chain 301 of clocked half-rail differential logic circuits with single-rail logic and sense amplifier 300A, 300B, and 300C and 300N of the present invention. Each clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A, 300B, 300C and 300N represents a stage in cascaded chain 301. In one embodiment of the invention, each clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A, 300B, 300C and 300N is similar to clocked half-rail differential logic circuit with single-rail logic and sense amplifier 200A discussed above with respect to FIG. 2A.
As seen in FIG. 3, clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A includes: a first clock input terminal 326A; a second clock input terminal 327A; an OUT terminal 311A; and an OUTBAR terminal 313A.
Clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300B includes: a first clock input terminal 326B; a second clock input terminal 327B; an input terminal 351B, coupled to OUT terminal 311A of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A; an inputBar terminal 353B, coupled to OUTBAR terminal 313A of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A; an output terminal 311B; and an OUTBAR terminal 313B. Likewise, clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300C includes: a first clock input terminal 326C; a second clock input terminal 327C; an input terminal 351C, coupled to output terminal 311B of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300B; an inputBar terminal 353C, coupled to OUTBAR terminal 313B of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300B; an output terminal 311C; and an OUTBAR terminal 313C.
Clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N includes: a first clock input terminal 326N; a second clock input terminal 327N; an input terminal 351N, coupled to an output terminal 311N−1 (not shown) of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N−1 (not shown); an inputbar terminal 353N, coupled to an OUTBAR terminal 313N−1 (not shown) of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N−1 (not shown); an output terminal 311N; and an OUTBAR terminal 313N.
According to the invention, any number of clocked half-rail differential logic circuits with single-rail logic and sense amplifiers 300A, 300B, 300C and 300N can be employed with cascaded chain 301. As also shown in FIG. 3, and discussed above, output terminal 311A of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A couples signal OUTA to input terminal 351B of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300B and OUTBAR terminal 313A of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A couples signal OUTBARA to inputBar terminal 353B of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300B. Likewise, output terminal 311B of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300B couples signal OUTB to input terminal 351C of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300C and OUTBAR terminal 313B of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300B couples signal OUTBARB to inputBar terminal 353C of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300C. In addition, output terminal 311N of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N couples signal OUTN to an input terminal 351N+1 (not shown) of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N+1 (not shown) and OUTBAR terminal 313N of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N couples signal OUTBARN to an inputbar terminal 353N+1 (not shown) of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N+1 (not shown).
According to the invention, each clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A, 300B, 300C and 300N of cascaded chain 301 receives its own delayed first clock signal CLKA 361, CLKB 371, CLKC 381 and CLKN 391, respectively. According to the invention clock signals CLKA 361, CLKB 371, CLKC 381 and CLKN 391 are provided to clocked half-rail differential logic circuit with single-rail logic and sense amplifiers 300A, 300B, 300C and 300N, respectively, by introducing delay circuits 363, 373, 383 and 393 between successive clocked half-rail differential logic circuits with single-rail logic and sense amplifier 300A, 300B, 300C and 300N. Consequently, delay circuit 363 introduces a delay time between signal CLKA 361, coupled to first clock input terminal 326A of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A, and signal CLKB 371, coupled to first clock input terminal 326B of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300B. Delay circuit 373 introduces a delay time between signal CLKB 371 and signal CLKC 381, coupled to first clock input terminal 326C of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300C. Two delay circuits 363 and 373 introduce two delay times between signal CLKA 361 and signal CLKC 381. Likewise, a series of N−1 delay circuits, and N−1 delay times, exists between signal CLKA 361 and signal CLKN 391, coupled to first clock input terminal 326N of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N, and a further delay circuit 393 introduces a further delay time between CLKN 391 and CLK N+1 (not shown) coupled to a first clock input terminal 326N+1 (not shown) of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N+1 (not shown).
Delay circuits 363, 373, 383 and 393 are any one of many delay circuits known in the art such as inverters, or groups of inverters, gates, transistors or any other elements that introduce a time delay. According to the invention, delay circuits 363, 373, 383 and 393 are used to ensure the activation of each stage, i.e., each clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A, 300B, 300C and 300N, is timed such that the delay of the clock is longer than the evaluation duration of the previous stage. In one embodiment of the invention, the delayed clock signals CLKA 361, CLKB 371, CLKC 381 and CLKN 391 are timed to switch high (active) when the differential input voltage to clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A, 300B, 300C and 300N reaches a predetermined voltage level. The clock delay can be adjusted according to the predetermined differential voltage level required for robustness and the specific needs of the circuit designer. This differential voltage level is typically a function of process and will vary from circuit to circuit and system to system.
In addition, according to the invention, each clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A, 300B, 300C and 300N of cascaded chain 301 receives a second delayed clock signal at its second clock input terminal 327A, 327B, 327C and 327N, respectively. In one embodiment of the invention, the second delayed clock signal for a given clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A, 300B, 300C and 300N of cascaded chain 301 is the delayed clock signal of the following clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A, 300B, 300C and 300N in cascaded chain 301. In this embodiment of the invention, the second delayed clock signal for a given clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A, 300B, 300C and 300N of cascaded chain 301 is provided by coupling the second clock terminal 327A, 327B, 327C and 327N of a given clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A, 300B, 300C and 300N, respectively, to the first clock input terminal 326B, 326C, 326D (not shown), 326N and 326N+1 (not shown) of the following stage 300B, 300C, 300N and 300N+1 (not shown).
Thus, in FIG. 3, line 320A couples second clock input terminal 327A of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A to first clock input terminal 326B of clocked half-rail differential logic circuit 300B and delay circuit 363 introduces a delay time between signal CLKA 361, coupled to first clock input terminal 326A of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A, and signal CLKB 371, coupled to second clock input terminal 327A of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A. Likewise, line 320B couples second clock input terminal 327B of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300B to first clock input terminal 326C of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300C and delay circuit 373 introduces a delay time between signal CLKB 371, coupled to first clock input terminal 326B of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300B, and signal CLKC 381, coupled to second clock input terminal 327B of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300B.
Similarly, line 320C couples second clock input terminal 327C of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300C to first clock input terminal 326D (not shown) of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300D (not shown) and delay circuit 383 introduces a delay time between signal CLKC 381, coupled to first clock input terminal 326C of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300C, and signal CLKD 382, coupled to second clock input terminal 327C of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300C. Likewise, line 320N couples first clock input terminal 326N+1 (not shown) of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N+1 (not shown) to second clock input terminal 327N of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N and delay circuit 393 introduces a delay time between signal CLKN 391, coupled to first clock input terminal 326N of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N, and signal CLKN+1 392, coupled to second clock input terminal 327N of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300N.
In one embodiment of the invention, second clock input terminals 327A, 327B, 327C and 327N of clocked half-rail differential logic circuits with single-rail logic and sense amplifier 300A, 300B, 300C and 300N, respectively, are coupled to sense amplifiers (not shown in FIG. 3) in clocked half-rail differential logic circuit with single-rail logic and sense amplifiers 300A, 300B, 300C and 300N, such as sense amplifier circuit 280 in FIG. 2A, and the signals CLKB, CLKC, CLKD, and CLKN+1 are used as described above with respect to FIG. 2A to trigger the sense amplifiers (not shown in FIG. 3) in clocked half-rail differential logic circuit with single-rail logic and sense amplifiers 300A, 300B, 300C and 300N.
FIG. 4 is one embodiment of a timing diagram for cascaded chain 301 of clocked half-rail differential logic circuits with single-rail logic and sense amplifier 300A, 300B, and 300C and 300N of FIG. 3. As seen in FIG. 3 and FIG. 4 together, according to one embodiment of the invention, at time T0, i.e., point T0 400A in FIG. 4, signal CLKA 461 starts to go high. After a short switching delay 460, such as the short switching delay inherent in any circuit, signal OUTA 411A at OUTA terminal 311A starts to switch high at point 466. Corresponding signal OUTBARA at OUTBAR terminal 313A starts to discharge to low at point 467. Note that, as discussed above, points 466 and 467 typically represent potentials of approximately Vdd/2.
According to the present invention, signal CLKB 471 is delayed a delay time 472 with respect to signal CLKA 461 by delay circuit 363. At point 473, i.e., time T1 400B, signal CLKB 471 starts to rise and thereby activates a sense amplifier, such as sense amplifier 280 in FIG. 2A, which, according to the invention, is part of clocked half-rail differential logic circuit with single-rail logic and sense amplifier 300A. Once the sense amplifier is activated, Output OUTA 411A pulls strongly to high starting at point 465 and reaches high point 464 rapidly. Note the difference in the slope of signal OUTA between points 466 and 465, when the sense amplifier is not activated, and points 465 and 464, when the sense amplifier is activated. Likewise, corresponding signal OUTBARA 413A pulls strongly low, starting at point 468, to low point 469 when the sense amplifier is activated.
At point 463A, in its pre-charge phase, CLKA 461 starts to switch low. After a short delay, OUTA 411A and OUTBARA 413A begin to equalize at points 464A and 469A, respectively, and reach approximate equilibrium at points 466A and 467A at a potential close to Vdd/2.
As also seen in FIG. 3 and FIG. 4 together, according to one embodiment of the invention, at time T1, i.e., point T1 400B in FIG. 4, signal CLKB 471 starts to go high. After a short switching delay 470, such as the short switching delay inherent in any circuit, signal OUTB 411B at OUTB terminal 311B starts to switch high at point 476. Corresponding signal OUTBARB at OUTBAR terminal 313B starts to discharge to low at point 477. Note that, as discussed above, points 476 and 477 typically represent potentials of approximately Vdd/2.
According to the present invention, signal CLKC 481 is delayed a delay time 482 with respect to signal CLKB 471 by delay circuit 373. At point 483, i.e., time T2 400C, signal CLKC 481 starts to rise and thereby activates a sense amplifier, such as sense amplifier 280 in FIG. 2A, which, according to the invention, is part of clocked half-rail differential logic circuit 300B. Once the sense amplifier is activated, Output OUTB 411B pulls strongly to high starting at point 475 and reaches high point 474 rapidly. Note the difference in the slope of signal OUTB between points 476 and 475, when the sense amplifier is not activated, and points 475 and 474, when the sense amplifier is activated. Likewise, corresponding signal OUTBARB 413B pulls strongly low, starting at point 478, to low point 479 when the sense amplifier is activated.
At point 473A, in its pre-charge phase, CLKB 471 starts to switch low. After a short delay, OUTB 411B and OUTBARB 413B begin to equalize at points 474A and 479A, respectively, and reach approximate equilibrium at points 476A and 477A at a potential close to Vdd/2.
As also seen in FIG. 3 and FIG. 4 together, according to one embodiment of the invention, at time T2, i.e., point T2 400c in FIG. 4, signal CLKC 481 starts to go high. After a short switching delay 480, such as the short switching delay inherent in any circuit, signal OUTC 411C at OUTC terminal 311C starts to switch high at point 486. Corresponding signal OUTBARC at OUTBAR terminal 313C starts to discharge to low at point 487. Note that, as discussed above, points 486 and 487 typically represent potentials of approximately Vdd/2.
According to the present invention, signal CLKD 491 is delayed a delay time 492 with respect to signal CLKC 481 by delay circuit 383. At point 493, i.e., time T3 400D, signal CLKD 491 starts to rise and thereby activates a sense amplifier, such as sense amplifier 280 in FIG. 2A, which, according to the invention, is part of clocked half-rail differential logic circuit 300C. Once the sense amplifier is activated, Output OUTC 411C pulls strongly to high starting at point 485 and reaches high point 484 rapidly. Note the difference in the slope of signal OUTC between points 486 and 485, when the sense amplifier is not activated, and points 485 and 484, when the sense amplifier is activated. Likewise, corresponding signal OUTBARC 413C pulls strongly low, starting at point 488, to low point 489 when the sense amplifier is activated.
At point 483A, in its pre-charge phase, CLKC 481 starts to switch low. After a short delay, OUTC 411C and OUTBARC 413C begin to equalize at points 484A and 489A, respectively, and reach approximate equilibrium at points 486A and 487A at a potential close to Vdd/2.
As discussed above, according to the invention, any number of clocked half-rail differential logic circuits with single-rail logic and sense amplifier 300A, 300B, 300C and 300N can be employed with cascaded chain 301. In addition, the process discussed above will repeat for each switching of the system clock. Those of skill in the art will further recognize that the choice of signal highs and signal lows was made arbitrarily in FIG. 4 for illustrative purposes only and that at other times, and in other embodiments of the invention, signal highs could be replaced with signal lows and vice-versa.
When the clocked half-rail differential logic circuits of the invention are cascaded together, the advantages of the clocked half-rail differential logic circuits of the invention are particularly evident and the gains in terms of power efficiency, size reduction, heat reduction and flexibility are further pronounced.
The foregoing description of an implementation of the invention has been presented for purposes of illustration and description only, and therefore is not exhaustive and does not limit the invention to the precise form disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practicing the invention.
For example, for illustrative purposes specific embodiments of the invention were shown with specific transistors. However, the NFETs and PFETS shown in the figures can be readily exchanged for PFETs and NFETs by reversing the polarities of the supply voltages or by other well known circuit modifications.
Consequently, the scope of the invention is defined by the claims and their equivalents.

## Claims

1. A method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier comprising:
providing a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier, said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprising: 
a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier first clock input terminal; 
a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier second clock input terminal; 
at least one first clocked half-rail differential logic circuit with single-rail logic and sense amplifier data input terminal; and 
at least one first clocked half-rail differential logic circuit with single-rail logic and sense amplifier data output terminal; 

providing a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier, said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprising: 
a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier first clock input terminal; 
a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier second clock input terminal; 
at least one second clocked half-rail differential logic circuit with single-rail logic and sense amplifier data input terminal; and 
at least one second clocked half-rail differential logic circuit with single-rail logic and sense amplifier data output terminal; 

coupling a first clock signal to said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier first clock input terminal; 
coupling a second clock signal to said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier first clock input terminal and said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier second clock input terminal; 
coupling said at least one first clocked half-rail differential logic circuit with single-rail logic and sense amplifier data output terminal to said at least one second clocked half-rail differential logic circuit with single-rail logic and sense amplifier data input terminal; and 
delaying said first clock signal by a predetermined delay time to create said second clock signal.

2. The method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier of claim 1, further comprising:
coupling a delay circuit between said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier clock input terminal and said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier clock input terminal for delaying said second clock signal with respect to said first clock signal by said predetermined delay time.

3. The method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier of claim 2, wherein;
said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprises a sense amplifier circuit coupled to said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier second clock input terminal; and 
said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprises a sense amplifier circuit coupled to said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier second clock input terminal.

4. The method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier of claim 3, wherein;
said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprises a base logic portion coupled to a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal, further wherein; 
said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprises a complementary output transistor coupled to a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal, further wherein; 
said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprises a base logic portion coupled to a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; and 
said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprises a complementary output transistor coupled to a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal.

5. The method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier of claim 2, wherein;
said delay circuit comprises at least one inverter.

6. A method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier comprising:
providing a first supply voltage; 
providing a second supply voltage; 
providing a first clocked half-rail differential logic circuit with single-rail logic, said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprising: 
a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal; 

a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first supply voltage being coupled to said first transistor first flow electrode; 
a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said first transistor second flow electrode being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor second flow electrode being coupled to said third transistor first flow electrode, said third transistor second flow electrode being coupled to said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal; 
a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode, said second transistor control electrode being coupled to said fourth transistor first flow electrode and said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal, said third transistor control electrode being coupled to said fourth transistor second flow electrode and said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
a base logic portion, said base logic portion comprising a base logic portion first input terminal, a base logic portion second input terminal, a base logic portion OUT terminal, and a base logic portion fourth terminal, said base logic portion OUT terminal being coupled to said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode, said fifth transistor first flow electrode being coupled to said base logic portion fourth terminal, said fifth transistor second flow electrode being coupled to said second supply voltage, said fifth transistor control electrode being coupled to a first clock signal; 
a complementary output transistor, said complementary output transistor comprising a complementary output transistor first flow electrode, a complementary output transistor second flow electrode and a complementary output transistor control electrode, said complementary output transistor first flow electrode being coupled to said third transistor second flow electrode and said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal, said complementary output transistor second flow electrode being coupled to said fifth transistor first flow electrode, said complementary output transistor control electrode being coupled to said fourth transistor second flow electrode and said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier sense amplifier circuit coupled between said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal and said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal, said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier sense amplifier circuit having an input terminal coupled to a second clock signal; 
providing a second clocked half-rail differential logic circuit with single-rail logic, said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprising: 
a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal; 

a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first supply voltage being coupled to said first transistor first flow electrode; 
a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said first transistor second flow electrode being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor second flow electrode being coupled to said third transistor first flow electrode, said third transistor second flow electrode being coupled to said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal; 
a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode, said second transistor control electrode being coupled to said fourth transistor first flow electrode and said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal, said third transistor control electrode being coupled to said fourth transistor second flow electrode and said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
a base logic portion, said base logic portion comprising a base logic portion first input terminal, a base logic portion second input terminal, a base logic portion OUT terminal, and a base logic portion fourth terminal, said base logic portion OUT terminal being coupled to said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode, said fifth transistor first flow electrode being coupled to said base logic portion fourth terminal, said fifth transistor second flow electrode being coupled to said second supply voltage, said fifth transistor control electrode being coupled to said second clock signal; 
a complementary output transistor, said complementary output transistor comprising a complementary output transistor first flow electrode, a complementary output transistor second flow electrode and a complementary output transistor control electrode, said complementary output transistor first flow electrode being coupled to said third transistor second flow electrode and said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal, said complementary output transistor second flow electrode being coupled to said fifth transistor first flow electrode, said complementary output transistor control electrode being coupled to said fourth transistor second flow electrode and said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; and 
a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier sense amplifier circuit coupled between said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal and said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal, said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier sense amplifier circuit having an input terminal coupled to a third clock signal; 
delaying said first clock signal by a predetermined delay time to create said second clock signal; and 
delaying said second clock signal by a predetermined delay time to create said third clock signal.

7. The method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier of claim 6, wherein;
said a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier sense amplifier circuit comprises: 
a sixth transistor, said sixth transistor comprising a sixth transistor first flow electrode, a sixth transistor second flow electrode and a sixth transistor control electrode, said second transistor second flow electrode being coupled to said sixth transistor first flow electrode, said sixth transistor second flow electrode being coupled to a first clocked half-rail differential logic circuit with single-rail logic and sense amplifier first node, said sixth transistor control electrode being coupled to said fourth transistor first flow electrode and said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal; 
a seventh transistor, said seventh transistor comprising a seventh transistor first flow electrode, a seventh transistor second flow electrode and a seventh transistor control electrode, said third transistor second flow electrode being coupled to said seventh transistor first flow electrode, said seventh transistor second flow electrode being coupled to said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier first node, said seventh transistor control electrode being coupled to said fourth transistor second flow electrode and said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
an eighth transistor, said eighth transistor comprising an eighth transistor first flow electrode, an eighth transistor second flow electrode and an eighth transistor control electrode, said eighth transistor first flow electrode being coupled to said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier first node, said eighth transistor second flow electrode being coupled to said second supply voltage, said eighth transistor control electrode being coupled to receive said second clock signal, further wherein; 
said a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier sense amplifier circuit comprises: 
a sixth transistor, said sixth transistor comprising a sixth transistor first flow electrode, a sixth transistor second flow electrode and a sixth transistor control electrode, said second transistor second flow electrode being coupled to said sixth transistor first flow electrode, said sixth transistor second flow electrode being coupled to a second clocked half-rail differential logic circuit with single-rail logic and sense amplifier first node, said sixth transistor control electrode being coupled to said fourth transistor first flow electrode and said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal; 
a seventh transistor, said seventh transistor comprising a seventh transistor first flow electrode, a seventh transistor second flow electrode and a seventh transistor control electrode, said third transistor second flow electrode being coupled to said seventh transistor first flow electrode, said seventh transistor second flow electrode being coupled to said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier first node, said seventh transistor control electrode being coupled to said fourth transistor second flow electrode and said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
an eighth transistor, said eighth transistor comprising an eighth transistor first flow electrode, an eighth transistor second flow electrode and an eighth transistor control electrode, said eighth transistor first flow electrode being coupled to said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier first node, said eighth transistor second flow electrode being coupled to said second supply voltage, said eighth transistor control electrode being coupled to receive said third clock signal.

8. The method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier of claim 7, wherein;
said first supply voltage is Vdd and said second supply voltage is ground.

9. The method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier of claim 8, wherein;
said first transistor, said second transistor, and said third transistor of said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier and said first transistor, said second transistor, and said third transistor of said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier are PFETs.

10. The method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier of claim 9, wherein;
said fourth transistor, said fifth transistor, said sixth transistor, said seventh transistor, said eighth transistor, and said complementary output transistor of said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier and said fourth transistor, said fifth transistor, said sixth transistor, said seventh transistor, said eighth transistor, and said complementary output transistor of said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier are NFETs.

11. The method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier of claim 7, wherein;
said base logic portion of said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier and said base logic portion of said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprise digital logic.

12. The method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier of claim 7, wherein;
said base logic portion of said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier and said base logic portion of said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprise logic gates.

13. The method for clock control of a cascaded chain of clocked half-rail differential logic circuits with single-rail logic and sense amplifier of claim 7, wherein;
said base logic portion of said first clocked half-rail differential logic circuit with single-rail logic and sense amplifier and said base logic portion of said second clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprise an AND gate.

14. A method for clock control of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprising:
providing a first supply voltage; 
providing a second supply voltage; 
providing a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode; 
coupling said first supply voltage to said first transistor first flow electrode; 
providing a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode; 
coupling said first transistor second flow electrode to said second transistor first flow electrode; 
coupling said second transistor second flow electrode to a clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
providing a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode; 
coupling said first transistor second flow electrode to said third transistor first flow electrode; 
coupling said third transistor second flow electrode to a clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal; 
providing a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode; 
coupling said second transistor control electrode to said fourth transistor first flow electrode and said clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal; 
coupling said third transistor control electrode to said fourth transistor second flow electrode and said clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
providing a base logic portion, said base logic portion comprising a base logic portion first input terminal, a base logic portion second input terminal, a base logic portion OUT terminal, and a base logic portion fourth terminal; 
coupling said base logic portion OUT terminal to said clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
providing a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode; 
coupling said fifth transistor first flow electrode to said base logic portion fourth terminal; 
coupling said fifth transistor second flow electrode to said second supply voltage; 
providing a first clock signal; 
coupling said fifth transistor control electrode to said first clock signal; 
providing a complementary output transistor, said complementary output transistor comprising a complementary output transistor first flow electrode, a complementary output transistor second flow electrode and a complementary output transistor control electrode; 
coupling said complementary output transistor first flow electrode to said third transistor second flow electrode and said clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal; 
coupling said complementary output transistor second flow electrode to said fifth transistor first flow electrode; 
coupling said complementary output transistor control electrode to said fourth transistor second flow electrode and said clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
providing a clocked half-rail differential logic circuit with single-rail logic and sense amplifier sense amplifier circuit; 
coupling said clocked half-rail differential logic circuit with single-rail logic and sense amplifier sense amplifier circuit between said clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal and said clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal, said clocked half-rail differential logic circuit with single-rail logic and sense amplifier sense amplifier circuit having an input terminal; 
providing a second clock signal; 
coupling said clocked half-rail differential logic circuit with single-rail logic and sense amplifier sense amplifier circuit input terminal coupled to said second clock signal; and 
delaying said first clock signal by a predetermined delay time to create said second clock signal.

15. The method for clock control of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier of claim 14, wherein;
said a clocked half-rail differential logic circuit with single-rail logic and sense amplifier sense amplifier circuit comprises: 
a sixth transistor, said sixth transistor comprising a sixth transistor first flow electrode, a sixth transistor second flow electrode and a sixth transistor control electrode, said second transistor second flow electrode being coupled to said sixth transistor first flow electrode, said sixth transistor second flow electrode being coupled to a clocked half-rail differential logic circuit with single-rail logic and sense amplifier first node, said sixth transistor control electrode being coupled to said fourth transistor first flow electrode and said clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal; 
a seventh transistor, said seventh transistor comprising a seventh transistor first flow electrode, a seventh transistor second flow electrode and a seventh transistor control electrode, said third transistor second flow electrode being coupled to said seventh transistor first flow electrode, said seventh transistor second flow electrode being coupled to said clocked half-rail differential logic circuit with single-rail logic and sense amplifier first node, said seventh transistor control electrode being coupled to said fourth transistor second flow electrode and said clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal; 
an eighth transistor, said eighth transistor comprising an eighth transistor first flow electrode, an eighth transistor second flow electrode and an eighth transistor control electrode, said eighth transistor first flow electrode being coupled to said clocked half-rail differential logic circuit with single-rail logic and sense amplifier first node, said eighth transistor second flow electrode being coupled to said second supply voltage, said eighth transistor control electrode being coupled to receive said second clock signal.

16. The method for clock control of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier of claim 15, wherein;
said first supply voltage is Vdd and said second supply voltage is ground.

17. The method for clock control of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier of claim 16, wherein;
said first transistor, said second transistor, and said third transistor are PFETs.

18. The method for clock control of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier of claim 17, wherein;
said fourth transistor, said fifth transistor, said sixth transistor said seventh transistor, said eighth transistor, and said complementary output transistor are NFETs.

19. The method for clock control of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier of claim 15, wherein;
said base logic portion of said clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprises logic gates.

20. The method for clock control of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier of claim 15, wherein;
said base logic portion of said clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprises an AND gate.

21. The method for clock control of a clocked half-rail differential logic circuit with single-rail logic and sense amplifier of claim 15, wherein;
said base logic portion of said clocked half-rail differential logic circuit with single-rail logic and sense amplifier comprises an OR gate.