# Patent

## Title
Light emitting device, method of driving pixel circuit, and driving circuit

## Abstract

A method of driving a pixel circuit is provided. The pixel circuit includes a light emitting element that emits light by receiving a driving current, a driving transistor that generates the driving current, and a light-emission control transistor of the same conductivity type as that of the driving transistor, the light-emission control transistor being arranged on a path through which the driving current flows from the driving transistor to the light emitting element. The method includes setting the gate potential of the light-emission control transistor so that the light-emission control transistor is turned on in the saturation region for a light emitting period during which the light emitting element is allowed to emit light.

## Background
This application is a U.S. Divisional of U.S. application Ser. No. 11/765,206 filed Jun. 19, 2007, which claims the benefit of priority to Japanese Patent Application No. 2006-183054 filed Jul. 3, 2006, the contents of which are incorporated herein by reference.


BACKGROUND
1. Technical Field
The present invention relates to a technique of controlling a light emitting element, such as an organic light emitting diode.
2. Related Art
Light emitting devices using active elements, such as thin film transistors, for controlling a current (hereinafter, referred to as a driving current) supplied to a light emitting element have been proposed. FIG. 18 shows the arrangement of a driving transistor TDR and a light-emission control transistor TEL on a path through which a driving current IDR flows, the arrangement being disclosed in, for example, U.S. Pat. No. 6,229,506 and JP-A-2003-22049. The driving transistor TDR generates the driving current IDR according to the gate potential. The light-emission control transistor TEL, arranged between the driving transistor TDR and a light emitting element E, switches to the ON state for a predetermined period (hereinafter, referred to as a light emitting period), thus permitting supply of the driving current IDR into the light emitting element E.
Although the operating points of most of the driving transistors TDR are set so as to lie within a saturation region, the driving current IDR is changed in accordance with the drain-source voltage of the corresponding driving transistor TDR by the channel length modulation effect. On the other hand, the electrical characteristics of each light emitting element E include errors (e.g., an error from a design value and a variation between elements). For example, the relationship between the driving current IDR and the voltage across the light emitting element E may differ from element to element. The difference in voltage across the light emitting element E between the elements leads to a fluctuation in drain-source voltage between the driving transistors TDR. Unfortunately, even when the gate potentials of the respective driving transistors TDR are set to the same value, the driving current IDR supplied to each light emitting element E (therefore, the light intensity thereof) differs from element to element in accordance with its electrical characteristics.
SUMMARY
An advantage of some aspects of the invention is to reduce the influence of the electrical characteristics of a light emitting element on a driving current.
According to an aspect of this invention, there is provided a method of driving a pixel circuit including a light emitting element that emits light by receiving a driving current, a driving transistor that generates the driving current, and a light-emission control transistor of the same conductivity type as that of the driving transistor, the light-emission control transistor being arranged on a path through which the driving current flows from the driving transistor to the light emitting element. The method includes setting the gate potential of the light-emission control transistor so that the light-emission control transistor is turned on in the saturation region for a light emitting period during which the light emitting element is allowed to emit light.
In accordance with this aspect of the invention, since the light-emission control transistor operates in the saturation region for the light emitting period, even when the potential of the node between the light-emission control transistor and the light emitting element changes in accordance with the electrical characteristics of the light emitting element, a change of the potential of the node between the light-emission control transistor and the driving transistor (the drain potential of the driving transistor) is suppressed. Therefore, the influence of the electrical characteristics of the light emitting element on the driving current can be reduced.
In an embodiment (e.g., a first embodiment which will be described below), preferably, the driving transistor and the light-emission control transistor are of P-channel type, the driving transistor is arranged between a first power supply line (e.g., a power supply line L1 in FIG. 3) and the light-emission control transistor, the light emitting element is arranged between the light-emission control transistor and a second power supply line (e.g., a power supply line L2 in FIG. 3). In this case, when let −VEL (−VEL<0) be the potential of the second power supply line with reference to the potential of the first power supply line, let VEL—MAX (VEL—MAX<0) be the voltage across the light emitting element with a maximum voltage drop with reference to the potential of the electrode thereof on the light-emission control transistor side, let VT2 (VT2<0) be the threshold voltage of the light-emission control transistor, and let VG—ON be the gate potential of the light-emission control transistor, the gate potential of the light-emission control transistor for the light emitting period is set so as to satisfy the following relation: VG—ON>−VEL−VEL—MAX+VT2. In this case, the light-emission control transistor can be reliably allowed to operate in the saturation region.
Preferably, when let VDATA—MAX (VDATA—MAX<0) be the gate-source voltage of the driving transistor of which the driving current reaches its maximum value and let VT1 (VT1<0) be the threshold voltage of the driving transistor, the gate potential of the light-emission control transistor for the light emitting period is set so as to satisfy the following relation: VG—ON<VDATA—MAX−VT1+VT2. In this case, since the driving transistor operates in the saturation region, the driving transistor can be used as a stable constant current source.
In another embodiment (e.g., a second embodiment which will be described below), the driving transistor and the light-emission control transistor may be of N-channel type, the light emitting element may be arranged between a first power supply line (e.g., a power supply line L1 in FIG. 8) and the light-emission control transistor, the driving transistor may be arranged between the light-emission control transistor and a second power supply line (e.g., a power supply line L2 in FIG. 8). Preferably, when let VEL (VEL>0) be the potential of the first power supply line with reference to the potential of the second power supply line, let VEL—MAX (VEL—MAX>0) be the voltage across the light emitting element with a maximum voltage drop with reference to the potential of the electrode thereof on the light-emission control transistor side, let VT2 (VT2>0) be the threshold voltage of the light-emission control transistor, and let VG—ON be the gate potential of the light-emission control transistor, the gate potential of the light-emission control transistor for the light emitting period is set so as to satisfy the following relation: VG—ON<VEL−VEL—MAX+VT2. In this case, the light-emission control transistor can be reliably allowed to operate in the saturation region.
Preferably, when let VDATA—MAX (VDATA—MAX>0) be the gate-source voltage of the driving transistor of which the driving current reaches its maximum value and let VT1 (VT1>0) be the threshold voltage of the driving transistor, the gate potential of the light-emission control transistor for the light emitting period is set so as to satisfy the following relation: VG—ON>VDATA—MAX−VT1+VT2. Since the driving transistor operates in the saturation region, therefore, the driving transistor can be used as a stable constant current source.
In another embodiment (e.g., a fourth embodiment which will be described below), preferably, the pixel circuit includes a writing control transistor (e.g., a transistor SW1 shown in FIG. 12) arranged on a path extending from a node (e.g., a node N1 shown in FIG. 12) between the driving transistor and the light-emission control transistor. The light-emission control transistor and the writing control transistor have the same conductivity type and size. The same potential as that at which the light-emission control transistor is turned on for the light emitting period is supplied to the gate of the writing control transistor for a writing period precedent to the light emitting period to turn on the writing control transistor. The gate potential of the driving transistor is set by a current (e.g., a current IDATA in FIG. 12) flowing through the driving transistor, the node, and the writing control transistor when the writing control transistor is turned on. In this case, since the potential supplied to the gate of the writing control transistor for the writing period is the same as that supplied to the gate of the light-emission control transistor for the light emitting period, the potential at the node between the driving transistor and the light-emission control transistor for the writing period substantially coincides with that for the light emitting period. Therefore, the amount of current flowing through the driving transistor for the writing period can be made coincide with that for the light emitting period with high accuracy.
According to another aspect of the invention, there is provided a driving circuit for driving a pixel circuit including a light emitting element that emits light by receiving a driving current, a driving transistor that generates the driving current, and a light-emission control transistor of the same conductivity type as that of the driving transistor, the light-emission control transistor being arranged on a path through which the driving current flows from the driving transistor to the light emitting element. The driving circuit includes a light-emission control circuit that sets the gate potential of the light-emission control transistor so that the light-emission control transistor is turned on in the saturation region for a light emitting period during which the light emitting element is allowed to emit light. In this case, since the light-emission control transistor operates in the saturation region for the light emitting period, the influence of the electrical characteristics of the light emitting element on the driving current can be reduced.
According to another aspect of the invention, a light emitting device includes a pixel circuit and a light-emission control circuit. The pixel circuit includes a light emitting element that emits light by receiving a driving current, a driving transistor that generates the driving current, and a light-emission control transistor of the same conductivity type as that of the driving transistor, the light-emission control transistor being arranged on a path through which the driving current flows from the driving transistor to the light emitting element. The light-emission control circuit sets the gate potential of the light-emission control transistor so that the light-emission control transistor is turned on in the saturation region for a light emitting period during which the light emitting element is allowed to emit light. In this case, since the light-emission control transistor operates in the saturation region for the light emitting period, the influence of the electrical characteristics of the light emitting device on the driving current can be reduced.
Preferably, the pixel circuit includes a writing control transistor, a writing control circuit, and a data supply circuit. The writing control transistor is arranged between a data line and a node located between the driving transistor and the light-emission control transistor. The writing control circuit turns on the writing control transistor for a writing period precedent to the light emitting period. The data supply circuit supplies a current to the data line for the writing period to set the gate potential of the driving transistor. The light-emission control transistor and the writing control transistor have the same conductivity type and size. The potential supplied from the writing control circuit to the gate of the writing control transistor for the writing period is equivalent to that supplied from the light-emission control circuit to the gate of the light-emission control transistor for the light emitting period. In this case, since the gate potential of the writing control transistor for the writing period is the same as that of the light-emission control transistor for the light emitting period, the amount of current flowing through the driving transistor for the writing period can be made coincide with that for the light emitting period with high accuracy.
The light emitting device of the invention may be used in various electronic apparatuses. Typical examples of the electronic apparatuses include apparatuses (e.g., a personal computer and a mobile phone) each including the light emitting device as a display. Applications of the light emitting device of the invention are not limited to apparatuses for image display. The light emitting device of the invention can be used in various applications, such as an exposure apparatus (exposure head) for irradiating an image carrier, e.g., a photosensitive drum with a light beam to form a latent image on the image carrier and various illuminating apparatuses including an apparatus (backlight), arranged on the rear of a liquid crystal display, for illuminating the display, and an apparatus, mounted on an image reader, e.g., a scanner, for illuminating a document sheet.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
FIG. 1 is a block diagram of the structure of a light emitting device according to a first embodiment of the invention.
FIG. 2 is a timing chart showing the waveforms of selection signals and light-emission control signals.
FIG. 3 is a circuit diagram of the structure of a pixel circuit according to the first embodiment.
FIG. 4 is a conceptual diagram explaining the range of an ON potential VG—ON.
FIG. 5 is a graph showing curves each representing the relationship between current and voltage across a light emitting element.
FIGS. 6A and 63 are graphs showing curves each representing the relationship between a potential VDATA and a driving current IDR.
FIGS. 7A and 7B are graphs showing curves each representing the relationship between the potential VDATA and the potential at a node.
FIG. 8 is a circuit diagram of the structure of a pixel circuit according to a second embodiment of the invention.
FIG. 9 is a conceptual diagram explaining the range of an ON potential VG—ON.
FIG. 10 is a circuit diagram of the structure of a pixel circuit according to a third embodiment of the invention.
FIG. 11 is a timing chart explaining the operation of the pixel circuit shown in FIG. 10.
FIG. 12 is a circuit diagram of the structure of a pixel circuit according to a fourth embodiment of the invention.
FIG. 13 is a block diagram of the structure of a light emitting device according to the fourth embodiment.
FIG. 14 is a timing chart showing the waveforms of a selection signal and a light-emission control signal.
FIG. 15 is a perspective view of an electronic apparatus (personal computer) to which the invention is applied.
FIG. 16 is a perspective view of another electronic apparatus (mobile phone) to which the invention is applied.
FIG. 17 is a perspective view of another electronic apparatus (personal digital assistant) to which the invention is applied.
FIG. 18 is a circuit diagram of an arrangement for driving a light emitting element.



DESCRIPTION OF EXEMPLARY EMBODIMENTS
First Embodiment
FIG. 1 is a block diagram of a light emitting device for use as an image display unit in various electronic apparatuses. A light emitting device D according to a first embodiment of the invention includes an element array 10 and peripheral circuits (i.e., a power supply circuit 20, a writing control circuit 22, a light-emission control circuit 24, and a data supply circuit 26). The element array 10 includes many pixel circuits P. The peripheral circuits control the pixel circuits P. Each pixel circuit P includes a light emitting element E which emits light by receiving a current.
In the element array 10, m selection lines 12 extending in the X direction, m light-emission control lines 14 extending in the X direction, and n data lines 16 extending in the Y direction that is perpendicular to the X direction (each of m and n is a natural number of two or more). Each light-emission control line 14 pairs with the corresponding selection line 12. Each pixel circuit P is arranged in the vicinities of the points of intersection of the selection line 12, the light-emission control line 14, and the data line 16. Therefore, these pixel circuits P are arranged in the X and Y directions in a matrix of m rows×n columns.
The power supply circuit 20 serves as a unit that generates a voltage for use in the light emitting device D. The power supply circuit 20 generates a high power supply potential VH and a low power supply potential VL. The high power supply potential VH serves as a reference potential (0 V) for the voltages across respective components and is supplied to the element array 10 via a power supply line L1. The low power supply potential VL is lower than the high power supply potential VH by a voltage VEL and is supplied to the element array 10 via a power supply line L2. The power supply circuit 20 also generates an ON potential VG—ON and an OFF potential VG—OFF for use in the light-emission control circuit 24. In the present embodiment, the ON potential VG—ON is lower than the OFF potential VG—OFF. The ON potential VG—ON and the OFF potential VG—OFF will be described in detail later.
The writing control circuit 22 serves as a unit (e.g., an m-bit shift register) that generates selection signals GWT[1] to GWT[m] for sequential selection of the m selection lines 12 and outputs the signals to the respective selection lines 12. Referring to FIG. 2, the selection signal GWT[i] supplied to the ith (i is a natural number satisfying 1≦i≦m) selection line 12 goes to a low level (selected) for an ith writing period (horizontal scanning period) PWT of one frame period (1V) and is held at a high level (unselected) for a period other than the writing period in one frame.
Again referring to FIG. 1, the light-emission control circuit 24 serves as a unit (e.g., an m-bit shift register) that generates light-emission control signals GEL[1] to GEL[m] for specifying a period (hereinafter, referred to as a light emitting period) during which the light emitting element E actually emits light and outputs the signals to the respective light-emission control lines 14. Referring to FIG. 2, the light-emission control signal GEL[i], supplied to the ith light-emission control line 14, becomes the ON potential VG—ON for a light emitting period PEL corresponding to a predetermined time length after the writing period PWT, during which the selection signal GWT[i] becomes the low level. The light-emission control signal GEL[i] is held at the OFF potential VG—OFF for a period other than the light emitting period PEL in one frame.
Referring to FIG. 1, the data supply circuit 26 serves as a unit (e.g., n voltage-output D/A converters) for generating data signals S[i] to S[n] to specify a gray scale level (light intensity) of the light emitting element E and outputs the signals to the respective data lines 16. As for the data signal S[j] supplied to the jth data line 16 for the writing period PWT during which the selection signal GWT[i] becomes the low level, the data signal S[j] is controlled at a potential VDATA according to the specified gray scale level of the pixel circuit P at the intersection of the ith row and the jth column.
The specific structure of each pixel circuit P will now be described with reference to FIG. 3. FIG. 3 illustrates only one pixel circuit P at the intersection of the ith row and the jth column. The pixel circuits P constituting the element array 10 have the same structure. Referring to FIG. 3, the light emitting element E in the pixel circuit P is arranged on a path connecting to both of the power supply lines L1 and L2. The light emitting element E in accordance with this embodiment is an organic light emitting diode including an anode, a cathode, and a luminous layer arranged between the anode and the cathode. The luminous layer comprises an organic electroluminescent (EL) material. The light emitting element E emits light having an intensity (luminance) according to the amount of the driving current IDR flowing between the anode and the cathode. The cathode of the light emitting element E is connected to the power supply line L2.
A P-channel driving transistor TDR is arranged on the path through which the driving current IDR flows (between the power supply line L1 and the light emitting element E). The driving transistor TDR serves as a unit that generates the driving current IDR whose amount depends on the gate potential. The source of the driving transistor TDR is connected to the power supply line L1. A capacitor C1 is arranged between the gate and the source (the power supply line L1) of the driving transistor TDR. A P-channel transistor SW1 for controlling the electrical connection (conduction/non-conduction) between the gate of the driving transistor TDR and the data line 16 is arranged therebetween. The gates of the transistors SW1 belonging to the ith row are connected to the ith selection line 12.
A light-emission control transistor TEL for controlling the electrical connection between the drain of the driving transistor TDR and the anode of the light emitting element E is arranged therebetween (i.e., on the path of the driving current IDR supplied from the driving transistor TDR to the light emitting element E). The conductivity type of the light-emission control transistor TEL is the P-channel type, the same as that of the driving transistor TDR. The gates of the light-emission control transistors TEL belonging to the ith row are connected to the ith light-emission control line 14. The ON potential VG—ON generated by the power supply circuit 20 is set to a level at which the light-emission control transistor TEL is turned on when this potential is supplied to the gate thereof. The OFF potential VG—OFF is set to a level at which the light-emission control transistor TEL is turned off when this potential is supplied to the gate thereof.
When the selection signal GWT[i] goes to the low level during the writing period PWT, the respective transistors SW1 belonging to the ith row simultaneously switch to the ON state. In the pixel circuit P at the intersection of the ith row and the jth column, the potential VDATA of the data signal S[j] is supplied to the gate of the driving transistor TDR and electric charges according on the potential VDATA are stored in the capacitor C1. The potential VDATA is set in accordance with a desired light intensity specified for the light emitting element E so that the driving transistor TDR operates in the saturation region when the light intensity of the light emitting element E reaches its maximum value. On the other hand, the light-emission control signal GEL[i] goes to the OFF potential VG—OFF during the writing period PWT. Accordingly, while the light-emission control transistor TEL is held at the OFF state, the driving current IDR is interrupted, so that the light emitting element E is turned off.
After the writing period PWT, the selection signal GWT[i] goes to the high level, so that each transistor SW1 switches to the OFF state. The gate of the driving transistor TDR is held at the potential VDATA by the capacitor C1 during the light emitting period PEL following the writing period PWT. On the other hand, since the light-emission control signal GEL[i] is set to the ON potential VG—ON during the light emitting period PEL, the light-emission control transistor TEL is turned on, thus establishing the path of the driving current IDR. Therefore, the driving current IDR according to the potential VDATA at the gate of the driving transistor TDR is supplied to the light emitting element E via the power supply line L1, the driving transistor TDR, and the light-emission control transistor TEL. Consequently, the light emitting element E emits light with a light intensity depending on the potential VDATA.
A current ID flowing between the drain and the source of a transistor operating in the saturation region is expressed as the following Expression (1):

ID=(β/2)(VGS−VT)2(1+λ·VDS)  (1)

where β denotes the gain coefficient of the transistor, VT denotes the threshold voltage thereof, VGS indicates the gate-source voltage thereof, VDS denotes the drain-source voltage thereof, and λ denotes a channel length modulation coefficient representing a change (gradient) in the current ID when the voltage VDS changes by a unit amount in the saturation region. As will be understood from Expression (1), although the driving transistor TDR operates in the saturation region for the light emitting period PEL, the driving current IDR (corresponding to the current ID in Expression (1)) depends on the drain-source voltage VDS of the driving transistor TDR, more specifically, the potential at a node N1 between the driving transistor TDR and the light-emission control transistor TEL.

On the other hands, the electrical characteristics of each light emitting element E change due to various factors, such as an ambient temperature of the light emitting device D and elapsed time after formation of the light emitting element E. Furthermore, one light emitting device D has a variation in electrical characteristics between the light emitting elements E. Since the device D has a variation in characteristics between the light emitting elements E as described above, the potential at a node N2 (the anode of the light emitting element E) between the light emitting element E and the light-emission control transistor TEL changes in accordance with the characteristics of the light emitting element E. Assuming that the light-emission control transistor TEL operates in a non-saturation region (linear region) for the light emitting period PEL, the potential at the node N1 (the voltage VDS across the driving transistor TDR) changes in accordance with the potential at the node N2. As will be understood from Expression (1), therefore, the driving current IDR changes in accordance with the characteristics of the light emitting element E. This leads to a variation in light intensity (gray scale level) between the respective light emitting elements E.
According to this embodiment, in order to solve the above-described disadvantages, the power supply circuit 20 generates the ON potential GG—ON so that each light-emission control transistor TEL is turned on in the saturation region for the light emitting period PEL. When the channel length modulation coefficient λ is sufficiently small in Expression (1), the current ID flowing through the transistor is approximated by the following Expression (2):

ID=(β/2)(VGS−VT)2.  (2)

As will be understood from Expression (2), the current ID flowing through the transistor operating in the saturation region is determined by the gate-source voltage VGS and the threshold voltage VT. In other words, when the current ID is fixed, the gate-source voltage VGS is also fixed to a predetermined value. Assuming that the light-emission control transistor TEL operates in the saturation region, the gate-source voltage VGS of the light-emission control transistor TEL is determined in accordance with the driving current IDR generated by the driving transistor TDR. Therefore, the potential at the node N1 is determined in accordance with the ON potential VG—ON supplied to the gate of the light-emission control transistor TEL and is not affected by a change of the potential at the node N2 caused by a variation in the characteristics of the light emitting element E. In Expression (2), the influence of the channel length modulation effect of the light-emission control transistor TEL is ignored. If the channel length modulation effect is taken into consideration in a manner similar to Expression (1), since the channel length modulation coefficient λ is sufficiently small, the change of the potential at the node N1 caused by the variation in the characteristics of the light emitting element E is sufficiently suppressed as compared to the case where the light-emission control transistor TEL operates in the non-saturation region. As described above, according to this embodiment, setting the operating point of the light-emission control transistor TEL within the saturation region suppresses the change of the potential at the node N1. Advantageously, if there is a variation in the electrical characteristics of the light emitting element E, the driving current IDR according to the potential VDATA of the data signal S[j] can be generated with high accuracy.
When the driving current IDR approximates zero, the gate-source voltage VGS of the light-emission control transistor TEL sufficiently approximates the threshold voltage VT2 of the light-emission control transistor TEL. In other words, the difference between the ON potential VG—ON supplied to the gate of the light-emission control transistor TEL and the potential VN1 at the node N1 (the source of the light-emission control transistor TEL), therefore, the gate-source voltage VGS of the light-emission control transistor TEL approximates the threshold voltage VT2 (VG—ON−VN1≈VT2). Therefore, the potential VN1 at the node N1 is held in the neighborhood of the difference between the ON potential VG—ON and the threshold voltage VT2 (VN1≈VG—ON−VT2). In other words, the characteristics of the light emitting element E are hardly affected by the potential VN1 at the node N1.
Conditions of the ON potential VG—ON necessary for the operation of the light-emission control transistor TEL in the saturation region will now be described. In order to allow the light-emission control transistor TEL to operate in the saturation region, it is necessary that the drain-source voltage VDS of the light-emission control transistor TEL should be below the difference between the gate-source voltage VGS and the threshold voltage VT2 (VT2<0) (VDS<VGS−VT2). When let VN2 be the potential at the node N2, the above-described condition is expressed by the following Expression (a1):

VN2<VG—ON−VT2.  (a1)

Let VEL—MAX be the voltage across the light emitting element E with a maximum voltage drop (i.e., when the voltage drop across the light emitting element E reaches its maximum value). The voltage VEL—MAX is determined with reference to a voltage applied to the anode in consideration of the range of variation in the characteristics of the light emitting element E and the driving current IDR (VEL—MAX<0). In other words, the voltage VEL—MAX is the voltage across a light emitting element E when the maximum driving current IDR is supplied (the highest gray scale level is designated) to the light emitting element across which the voltage reaches its maximum value because of errors of the electrical characteristics of the many light emitting elements E constituting the element array 10. Since the maximum value of the potential VN2 in Expression (a1) is expressed by (−VEL−VEL—MAX), the range of the ON potential VG—ON for the operation of the light-emission control transistor TEL in the saturation region is expressed by the following Expression (a2):

VG—ON>−VEL−VEL—MAX+VT2.  (a2)

In this embodiment, the driving transistor TDR operates in the saturation region for most of the range where the light intensity (gray scale level) of the light emitting element E changes. In order to allow the driving transistor TDR to operate in the saturation region, it is necessary that the drain-source voltage VDS of the transistor should be below the difference between the gate-source voltage VGS and the threshold voltage VT1 (VT1<0) (VDS<VGS−VT1). When let VDATA—MAX be the maximum value of the potential VDATA of the data signal S[j], the above-described condition is expressed by the following Expression (a3):

VN1<VDATA—MAX−VT1.  (a3)

The potential VDATA—MAX is the potential at the gate of the driving transistor TDR of which the driving current IDR reaches its maximum value (i.e., the highest gray scale level is designated) (VDATA—MAX<0).

Further, in order to turn on the light-emission control transistor TEL for the light emitting period PEL, it is necessary that the gate-source voltage of the light-emission control transistor TEL should be below the threshold voltage VT2. In other words, the following Expression (a4) is satisfied:

VG—ON−VN1<VT2.  (a4)

The following Expression (a5) is derived from the Expressions (a3) and (a4):

VG—ON<VDATA—MAX−VT1+VT2.  (a5)

The ON potential VG—ON is selected from the range satisfying the following Expression (a6) as shown in FIG. 4 using Expressions (a2) and (a5):

VDATA—MAX−VT1+VT2>VG—ON>−VEL−VEL—MAX+VT2.  (a6)

As for the OFF potential VG—OFF, a voltage at which the light-emission control transistor TEL is turned off may be used. For example, the high power supply potential VH (0 V) is used as the OFF potential VG—OFF.
An advantage obtained in the case where the light-emission control transistor TEL operates in the saturation region for the light emitting period PEL will now be described while being compared to the case (hereinafter, referred to as a comparative example) where the light-emission control transistor TEL operates in the non-saturation region. In the following description, it is assumed that the power supply potential VL of the power supply line L2 is set to −VEL (=−18 V), the ON potential VG—ON in this embodiment is −9 V, and the ON potential VG—ON in the comparative example is −18 V. It is further assumed that a light emitting elements E has characteristics A and another light emitting element E has characteristics B as shown in FIG. 5. Referring to FIG. 5, when the driving current IDR is set to the same value in both of the light emitting elements E, the voltage across the light emitting element E having the characteristics B is higher than that of the light emitting element E having the characteristics A.
FIGS. 6A and 6B are graphs showing the relationship between the amplitude (absolute value) of the potential VDATA and the driving current IDR with respect to the characteristics A and B. FIG. 6A shows results in this embodiment. FIG. 6B shows results in the comparative example. In the comparative example, in the use of the same potential VDATA, the driving currents IDR differ from each other in accordance with the characteristics of the respective light emitting elements E. On the other hand, in this embodiment, in the use of the same potential VDATA, the value of the driving current IDR flowing to the light emitting element E having the characteristics A accurately coincides with that flowing to the other light emitting element B having the characteristics B.
FIGS. 7A and 73 are graphs showing the relationship between the amplitude of the potential VDATA and the potentials at the nodes (N1 and N2) with respect to the characteristics A and B. Similar to FIGS. 6A and 6B, FIG. 7A shows results in this embodiment and FIG. 7B shows results in the comparative example. Referring to FIG. 7B, when each light-emission control transistor TEL operates in the non-saturation region, the potential at the node N2 changes in accordance with the characteristics of the corresponding light emitting element E. Further, the potential at the node N1 changes in association with the potential at the node N2. On the other hand, referring to FIG. 7A, the potential at the node N2 changes in accordance with the characteristics of each light emitting element E in this embodiment. However, since each light-emission control transistor TEL operates in the saturation region, the potential at the node N1 does not change in both of the light emitting element E having the characteristics A and that having the characteristics B.
As for an arrangement for maintaining the potential at the node N1 at a predetermined value irrespective of the characteristics of the corresponding light emitting element E, for example, a transistor (hereinafter, referred to as a buffer transistor) different from the light-emission control transistor TEL may be arranged between the light-emission control transistor TEL and the driving transistor TDR. During the light emitting period PEL, the light-emission control transistor TEL is allowed to operate in the non-saturation region in a manner similar to the comparative example and the buffer transistor is allowed to operate in the saturation region, thus reducing the influence of the characteristics of the light emitting element E on the potential at the node N1. Unfortunately, the number of transistors constituting the pixel circuit P is increased by adding the buffer transistor. On the other hand, in this embodiment, one light-emission control transistor TEL realizes a function of a switching element for controlling supply of the driving current IDR to the corresponding light emitting element E and a function for reducing the influence of the electrical characteristics of the light emitting element E on the potential at the node N1. Advantageously, the structure of the pixel circuit P can be simplified as compared to the arrangement with the buffer transistor.
Second Embodiment
A second embodiment of the invention will now be described. Components having the same functions and operations as those of the components in the first embodiment are designated by the same reference numerals and a detail description thereof is omitted.
FIG. 8 is a circuit diagram of the structure of a pixel circuit P in the second embodiment. As shown in FIG. 8, transistors (e.g., a driving transistor TDR, a light-emission control transistor TEL, and a transistor SW1) constituting the pixel circuit P are of N-channel type. Therefore, the relationship among power supply lines L1 and L2 and components of the pixel circuit P is the reverse of that in the first embodiment. In other words, the anode of a light emitting element E is connected to the power supply line L1 and the source of the driving transistor TDR is connected to the power supply line L2. The potential VL of the power supply line L2 is a reference potential (0 V) for the voltages across respective components. The potential VH of the power supply line L1 is higher than the potential VL by a voltage VEL (VEL>0). The light-emission control transistor TEL is arranged between the cathode of the light emitting element E and the drain of the driving transistor TDR. The position of the transistor SW1 and that of a capacitor C1 are the same as those in the first embodiment.
A light-emission control signal GEL[i] becomes an ON potential VG—ON for a light emitting period PEL and is held at an OFF potential VG—OFF for a period other than the light emitting period PEL in a manner similar to the first embodiment. Since the light-emission control transistor TEL is of N-channel type, the ON potential VG—ON is higher than the OFF potential VG—OFF. The ON potential VG—ON is determined so that the light-emission control transistor TEL operates in the saturation region in a manner similar to the first embodiment. Conditions for the ON potential VG—ON will be described below.
Since it is necessary that the drain-source voltage VDS of the light-emission control transistor TEL should exceed the difference between the gate-source voltage VGS and the threshold voltage VT2 (VT2>0) of the transistor so that the transistor operates in the saturation region, the following Expression (b1) is satisfied:

VN2>VG—ON−VT2.  (b1)

Since the maximum potential VN2 in Expression (b1) is expressed as VEL−VEL—MAX, the following Expression (b2) is derived from Expression (b1) (VEL—MAX>0):

VG—ON<VEL−VEL—MAX+VT2.  (b2)

In addition, since it is necessary that the drain-source voltage VDS of the driving transistor TDR should exceed the difference between the gate-source voltage VGS and the threshold voltage VT1 (VT1>0) of the transistor in order to allow the driving transistor TDR to operate in the saturation region, the following Expression (b3) is satisfied:

VN1>VDATA—MAX−VT1.  (b3)

A potential VDATA—MAX (VDATA—MAX>0) in Expression (b3) is the potential (maximum value of a potential VDATA) at the gate of the driving transistor TDR of which a driving current IDR reaches its maximum value.

Further, since the light-emission control transistor TEL switches to the ON state during the light emitting period PEL, the following Expression (b4) is satisfied:

VG—ON−VN1>VT2.  (b4)

The following Expression (b5) is derived from Expressions (b3) and (b4):

VG—ON>VDATA−MAX−VT1+VT2.  (b5)

The ON potential VG—ON in this embodiment is selected from the range satisfying the following Expression (b6) using Expressions (b2) and (b5) as shown in FIG. 9:

VDATA—MAX−VT1+VT2<VG—ON<VEL−VEL—MAX+VT2.  (b6)

As for the OFF potential VG—OFF, a potential at which the light-emission control transistor TEL is turned off may be used. For example, the low power supply potential VL (0 V) may be used as the OFF potential VG—OFF.
As described above, since the light-emission control transistor TEL operates in the saturation region during the light emitting period PEL in this embodiment, the influence of the electrical characteristics of each light emitting element E on the driving current IDR flowing therethrough can be reduced.
Third Embodiment
FIG. 10 is a circuit diagram of the structure of a pixel circuit P according to a third embodiment of the invention. Referring to FIG. 10, the pixel circuit P according to this embodiment includes a transistor SW2 and a capacitor C2 in addition to the same components as those in the first embodiment. The transistor SW2 is a P-channel transistor, arranged between the gate and the drain of a driving transistor TDR, for controlling the electrical connection between the gate and the drain. A control signal GCP[i] is supplied from a driving circuit (not shown) to the gate of the transistor SW2 via a control line 18. The capacitor C2 includes an electrode E1 and an electrode E2. The electrode E1 is connected to the gate of the driving transistor TDR. The transistor SW2, arranged between the electrode E2 and a data line 16, controls the electrical connection therebetween.
FIG. 11 is a timing chart showing the waveforms of signals supplied to the pixel circuit P at the intersection of the ith row and the jth column. Referring to FIG. 11, a resetting period PRS and a compensating period PCP are set just before a writing period PWT. A selection signal GWT[i] becomes a low level during the resetting period PRS, the compensating period PCP, and the writing period PWT and becomes a high level for a light emitting period PEL. A light-emission control signal GEL[i] goes to an ON potential VG—ON for each of the resetting period PRS and the light emitting period PEL and goes to an OFF potential VG—OFF (VG—OFF>VG—ON) during the compensating period PCP and the writing period PWT. The control signal GCP[i] becomes a low level during the resetting period PRS and the compensating period PCP and becomes a high level during the writing period PWT and the light emitting period PEL.
The operation of one pixel circuit P will now be described. Since the light-emission control signal GEL[i] becomes the ON potential VG—ON during the resetting period PRS, a light-emission control transistor TEL is held in the ON state. Since the control signal GCP[i] changes to the low level during this period, the gate of the driving transistor TDR is connected to its drain via the transistor SW2. During the resetting period PRS, therefore, the gate (electrode E1) of the driving transistor TDR is initialized to a voltage according to the electrical characteristics of the light emitting element E. During the resetting period PRS and the compensating period PCP, while the transistor SW2 is being held in the ON state in response to the selection signal GWT[i], a data signal S[j] is held at a reference potential VREF. Consequently, the electrode E2 is held at the reference potential VREF.
When the compensating period PCP starts, the light-emission control signal GEL[i] changes to the OFF potential VG—OFF, so that the light-emission control transistor TEL is turned off. Therefore, the potential at the gate of the driving transistor TDR (i.e., the electrode E1 of the capacitor C2) converges on a level corresponding to the difference between the power supply potential VH (0 V) of the power supply line L1 and the threshold voltage VT1 of the driving transistor TDR until the compensating period PCP terminates.
During the writing period PWT, the change of the control signal GCP[i] to the high level causes the gate of the driving transistor TDR to disconnect its drain and the data signal S[j] changes from the reference potential VREF to a potential VDATA while the transistor SW2 is being held in the ON state. Since the impedance at the gate of the driving transistor TDR is sufficiently high, the potential at the electrode E1 (i.e., the potential at the gate of the driving transistor TDR) changes in accordance with a change of the potential at the electrode E2 (i.e., a change of the difference between the reference potential VREF and the potential VDATA). In other words, the gate of the driving transistor TDR is set to a potential depending on the potential VDATA. During the light emitting period PEL, after the writing period PWT, setting of the light-emission control signal GEL[i] to the ON potential VG—ON causes the light-emission control transistor TEL to turn on, so that a driving current IDR depending on the potential at the gate of the driving transistor TDR is supplied to the light emitting element E via the light-emission control transistor TEL. Consequently, the light emitting element E emits light with an intensity depending on the potential VDATA.
As described above, in this embodiment, the potential at the gate of the driving transistor TDR is allowed to converge on a potential corresponding to the threshold voltage VT1 for the compensating period PCP and is changed using the capacitor C2 for the writing period PWT, so that the gate of the driving transistor TDR is set to a potential depending on the potential VDATA. Therefore, an error in the threshold voltage VT1 of the driving transistor TDR can be compensated for and the driving current IDR depending on the potential VDATA can be generated with high accuracy.
The ON potential VG—ON in this embodiment is selected from the range expressed by the following Expression (c) for allowing the light-emission control transistor TEL and the driving transistor TDR to operate in the saturation region in a manner similar to the first embodiment using Expression (a6). Therefore, the same advantages as those of the first embodiment are obtained in this embodiment.

VDATA—MAX−VT1+VT2>VG—ON>−VEL−VEL—MAX+VT2  (c)

A potential VDATA—MAX in this embodiment is the potential at the gate of the driving transistor TDR set during the writing period PWT when the potential VDATA is selected so that the driving current IDR reaches its maximum value and is different from the potential VDATA of the data line 16.
Fourth Embodiment
A fourth embodiment of the invention will now be described. The foregoing embodiments have described the pixel circuits P of a voltage programming type in which the light intensity of each light emitting element E is set in accordance with the potential VDATA of the data line 16. Pixel circuits P according to the fourth embodiment are of a current programming type in which the light intensity of each light emitting element E is set in accordance with a current IDATA flowing through a data line 16.
FIG. 12 is a circuit diagram showing the structure of a pixel circuit P. Referring to FIG. 12, the pixel circuit P according to this embodiment includes transistors SW1 and SW2 of P-channel type which is the same as that of a driving transistor TDR and that of a light-emission control transistor TEL. The transistor SW1 is arranged on a path extending between the data line 16 and a node N1, which is located between the driving transistor TDR and the light-emission control transistor TEL. The transistor SW1 controls the electrical connection between the drain of the driving transistor TDR and the data line 16. The transistor SW1 and the light-emission control transistor TEL are arranged close to each other and have the same size (channel length, channel width). The transistor SW2 controls the electrical connection between the gate and the drain of the driving transistor TDR. The gates of the respective transistors SW1 and SW2 are connected to a selection line 12.
FIG. 13 is a block diagram of the structure of a light emitting device D according to this embodiment. Referring to FIG. 13, a power supply circuit 20 supplies an ON potential VG—ON and an OFF potential VG—OFF to each of a light-emission control circuit 24 and a writing control circuit 22 (VG—ON<VG—OFF). As shown in FIG. 14, the writing control circuit 22 sets a selection signal GWT[i] to the ON potential VG—ON for a writing period PWT and sets the selection signal to the OFF potential VG—OFF for a period (including a light emitting period PEL) other than the writing period PWT. The waveform of a light-emission control signal GEL[i] is the same as that in the first embodiment.
A data supply circuit 26 serves as a unit (for example, n current-output D/A converters) for setting a data signal S[j] to a current IDATA depending on a gray scale level designated for a pixel circuit P at the intersection of the ith row and the jth column for the writing period PWT during which the selection signal GWT[i] becomes the ON potential VG—ON.
In the above-described arrangement, when the selection signal GWT[i] changes to the ON potential VG—ON during the writing period PWT, the gate of the driving transistor TDR is connected to its drain via the transistor SW2. In addition, the supply of the ON potential VG—ON causes the transistor SW1 to turn on. Therefore, the current IDATA of the data signal S[j] flows from a power supply line L1 into the jth data line 16 via the driving transistor TDR, the node N1, and the transistor SW1 as shown by a broken line in FIG. 12. Consequently, a voltage depending on the current IDATA is held in a capacitor C1.
During the light emitting period PEL after the writing period PWT, the selection signal GWT[i] is set to the OFF potential VG—OFF, so that the transistors SW1 and SW2 are turned off. When the light-emission control signal GEL[i] changes to the ON potential VG—ON and the light-emission control transistor TEL is turned on, a driving current IDR according to the potential at the gate of the driving transistor TDR (i.e., a potential held by the capacitor C1 for the preceding writing period PWT) is supplied to the light emitting element E via the light-emission control transistor TEL. Consequently, the light emitting element E emits light with an intensity depending on the current IDATA.
In this embodiment, the ON potential VG—ON is selected from the range expressed by the following Expression (d) in which the light-emission control transistor TEL is allowed to operate in the saturation region in a manner similar to the first embodiment using Expression (a6). Therefore, the same advantages as those of the first embodiment are obtained in this embodiment.

VDATA—MAX−VT1+VT2>VG—ON>−VEL−VEL—MAX+VT2  (d)

A potential VDATA—MAX in Expression (d) is the potential (VDATA—MAX<0) at the gate of the driving transistor TDR set during the writing period PWT when the current IDATA is selected so that the driving current TDR reaches its maximum value.
In this embodiment, the transistor SW1 and the light-emission control transistor TEL are arranged close to each other and have the same characteristics (i.e., the same conductivity type and the same size). Further, the transistor SW1 and the light-emission control transistor TEL are turned on according to the same ON potential VG—ON. With this arrangement, the potential at the node N1 (potential at the drain of the driving transistor TDR) for the writing period PWT coincides with that for the light emitting period PEL. Therefore, the amount of the current IDATA for the writing period PWT can be accurately made coincide with that of the driving current IDR for the light emitting period PEL. In other words, the light intensity of the light emitting element E can be controlled with high accuracy in accordance with the current IDATA.
Modifications
The above-described embodiments may be variously modified. Modifications will be described below. The following modifications may be appropriately used in combination.
First Modification
In each of the first to third embodiments, the ON potential VG—ON and the OFF potential VG—OFF generated by the power supply circuit 20 may be used as voltages for the selection signals GWT[1] to GWT[m] generated by the writing control circuit 22 in a manner similar to the fourth embodiment. With this arrangement, the number of voltages generated by the power supply circuit 20 is reduced, thus achieving a reduction in scale of the power supply circuit 20 and a reduction in power consumption.
Second Modification
In each of the third and fourth embodiments, each pixel circuit P includes P-channel transistors. The conductivity type of transistors in FIGS. 10 and 12 may be appropriately changed to N-channel type in a manner similar to the second embodiment. Further, it is unnecessary that all of transistors constituting each pixel circuit P have the same conductivity type. In other words, so long as the driving transistor TDR and the light-emission control transistor TEL have the same conductivity type, the transistors SW1 and SW2 may have any conductivity type.
Third Modification
With the arrangement in which the driving transistor TDR operates in the saturation region in the same way as in the foregoing embodiments, the driving transistor TDR can be allowed to serve as a constant current source for stably generating the driving current IDR. Since the desired advantages of the invention are obtained so long as the light-emission control transistor TEL operates in the saturation region, it is not always necessary to set the operating point of the driving transistor TDR in the saturation region. For example, it is unnecessary to satisfy Expression (a5) in the first embodiment and Expression (b5) in the second embodiment.
Fourth Modification
In each of the above-described embodiments, the organic light-emitting diode has been described as the light emitting element E. The invention can be applied to various light emitting devices using light emitting elements other than the organic light-emitting diodes. Various light emitting elements, such as a light emitting diode each including a luminous layer made of an inorganic electroluminescent material, a field emission (FE) element, a surface-conduction electron-emitter (SE), and a ballistic electron surface emitting (BS) element, may be used in the invention.
Applications
Electronic apparatuses related to the invention will now be described. FIGS. 15 to 17 illustrate electronic apparatuses each including the above-described light emitting device D as a display unit.
FIG. 15 is a perspective view of a mobile personal computer including the light emitting device D. A personal computer 2000 includes the light emitting device D for image display and a main body 2010 provided with a power supply switch 2001 and a keyboard 2002. The light emitting device D enables clear image display with a wide viewing angle because the light emitting device D includes organic light-emitting diodes as the light emitting elements E.
FIG. 16 is a perspective view of a mobile phone including the light emitting device D. A mobile phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the light emitting device D for image display. Operating the scroll buttons 3002 scrolls images displayed on the light emitting device D.
FIG. 17 is a perspective view of a personal digital assistant (PDA) including the light emitting device D. A PDA 4000 includes a plurality of operation buttons 4001, a power supply switch 4002, and the light emitting device D for image display. Operating the power supply switch 4002 allows for display of various pieces of information, such as an address list and a schedule book, on the light emitting device D.
Electronic apparatuses, each including the light emitting device of the invention, include a digital still camera, a television, a video camera, a car navigation system, a pager, an electronic organizer, an electronic paper, an electronic calculator, a word processor, a workstation, a video phone, a POS terminal, a printer, a scanner, a copy machine, a video player, and an apparatus having a touch panel in addition to the apparatuses shown in FIGS. 15 to 17. Applications of the light emitting device of the invention are not limited to apparatuses for image display. For example, an electrophotographic image forming apparatus uses an exposure unit (line head) for exposing a photosensitive member in accordance with an image to be formed on a recording member, such as a sheet of paper. The light emitting device of the invention may also be used as this type of exposure device.
The entire disclosure of Japanese Patent Application No. 2006-183054, filed Jul. 3, 2006 is expressly incorporated by reference herein.

## Claims

1. A method of driving a light emitting device including
a first power supply line, a second power supply line, a first transistor that is P-channel type, a driving transistor that controls a driving current flowing between the first power supply line and the first transistor and that is P-channel type, a light emitting element having a first electrode coupled to the first transistor and a second electrode coupled to the second power supply line, a capacitor having a first end coupled to a first gate of the driving transistor and a second end, and a second transistor coupled between the second end of the capacitor and a data line, the method comprising:
setting a first gate potential of the driving transistor through the second transistor and the data line by turning the second transistor on and turning the first transistor off during a writing period,
supplying the driving current through the first transistor to the light emitting element for a light emitting period during which the light emitting element is allowed to emit light,
when let −VEL(−VEL<0) be a second potential of the second power supply line with reference to a first potential of the first power supply line, let VEL—MAX(VEL—MAX<0) be a maximum voltage drop of the light emitting element, let VT2(VT2<0) be a first threshold voltage of the first transistor, and let VG—ON be a second gate potential of the first transistor, the second gate potential of the first transistor for the light emitting period is set so as to satisfy the following relation:


VG—ON>−VEL−VEL—MAX+VT2.

2. The method according to claim 1, wherein
when let VDATA—MAX (VDATA—MAX<0) be a gate-source voltage of the driving transistor of which the driving current reaches its maximum value and let VT1(VT1<0) be a second threshold voltage of the driving transistor, the second gate potential of the first transistor for the light emitting period is set so as to satisfy the following relation:


VG—ON<VDATA—MAX−VT1+VT2.

3. The method according to claim 1, wherein
the first transistor and the second transistor have the same conductivity type and the same size.

4. The method according to claim 3, wherein
the same potential as that at which the first transistor is turned on for the light emitting period is supplied to a gate of the second transistor for the writing period.

5. The light emitting device according to claim 4, wherein
when let VDATA—MAX (VDATA—MAX<0) be a gate-source voltage of the driving transistor of which the driving current reaches its maximum value and let VT1 (VT1<0) be a second threshold voltage of the driving transistor, the second gate potential of the first transistor for the light emitting period is set so as to satisfy the following relation:


VG—ON<VDATA—MAX−VT1+VT2.

6. The light emitting device according to claim 4, wherein
the first transistor and the second transistor have the same conductivity type and the same size.

7. The method according to claim 6, wherein
the same potential as that at which the first transistor is turned on for the light emitting period is supplied to a gate of the second transistor for the writing period.

8. A light emitting device comprising:
a first power supply line;
a second power supply line;
a first transistor that is P-channel type;
a driving transistor that controls a driving current flowing between the first power supply line and the first transistor and that is P-channel type;
a light emitting element having a first electrode coupled to the first transistor and a second electrode coupled to the second power supply line;
a capacitor having a first end coupled to a first gate of the driving transistor and a second end;
a second transistor coupled between the second end of the capacitor and a data line; and
a circuit that turns the second transistor on and that turns the first transistor off during a writing period, the circuit setting a first gate potential to a first gate of the first transistor for a light emitting period during which the light emitting element is allowed to emit light,
when let −VEL (−VEL<0) be a second potential of the second power supply line with reference to a first potential of the first power supply line, let VEL—MAX(VEL—MAX<0) be a maximum voltage drop of the light emitting element, let VT2 (VT2<0) be a first threshold voltage of the first transistor, and let VG—ON be the first gate potential, the first gate potential for the light emitting period is set so as to satisfy the following relation:


VG-ON>−VEL−VEL—MAX+VT2.