# Patent

## Title
Successive approximation AD converter and successive approximation AD conversion method

## Abstract

A successive approximation AD converter includes a DA converter that converts a higher conversion data greater than an approximate value into an analog higher converted voltage and converts a lower conversion data less than the approximate value into an analog lower converted voltage; a sample-and-hold circuit that samples and holds voltage differences between an input voltage and each of the higher converted voltage and the lower converted voltage; a comparator that outputs a first comparison result indicating whether the input voltage is greater or less than the higher converted voltage and a second comparison result indicating whether the input voltage is greater or less than the lower converted voltage; and an operation unit that changes the approximate value based on the first comparison result and the second comparison result, and changes a next higher conversion data and a next lower conversion data based on the changed approximate value.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
The present application is based upon and claims the benefit of priority of Japanese Patent Application No. 2013-012146, filed on Jan. 25, 2013, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
An aspect of this disclosure relates to a successive approximation AD converter and a successive approximation AD conversion method.
2. Description of the Related Art
A microprocessor is generally provided in a portable electronic apparatus such as a cell phone, a personal digital assistant (PDA), or a digital camera to control a system in the electronic apparatus. For example, the microprocessor monitors and controls the temperature of the electronic apparatus and the voltage of a battery in the electronic apparatus. For this purpose, an electronic apparatus generally includes sensors for detecting its temperature and a battery voltage, and a microprocessor of the electronic apparatus typically includes an analog-to-digital (AD) converter for converting analog signals output from the sensors into digital signals. An AD converter to be included in a microprocessor preferably has a small circuit size. An example of such an AD converter is a successive approximation AD converter.
FIG. 18 is a circuit diagram illustrating a configuration of a related-art successive approximation AD converter. In FIG. 18, an analog voltage Vin is input to an input terminal 10. A sample-and-hold circuit 11 samples and holds a voltage difference between the analog voltage Vin and an output voltage of a digital-to-analog (DA) converter 14 with reference to a reference voltage Vref.
A dynamic latch comparator 12 compares an output voltage of the sample-and-hold circuit 11 with the reference voltage Vref and supplies the comparison result, which indicates whether the analog voltage Vin is greater or less than the output voltage of the DA converter 14, to a successive approximation register and operation unit 13. The successive approximation register and operation unit 13 generates next (or subsequent) DA conversion data (data to be converted in the next DA conversion process) based on the comparison result supplied from the dynamic latch comparator 12, and supplies the generated data to the DA converter 14. The successive approximation register and operation unit 13 also supplies digital data, which is a final conversion result, to an output circuit 16.
A control circuit 15 receives a clock signal and a conversion start command, generates timing signals φ1, φ2, and φ3, supplies the timing signals φ1, φ2, and φ3 to the sample-and-hold circuit 11 and the dynamic latch comparator 12, generates a control signal indicating a start or an end, and supplies the control signal to the successive approximation register and operation unit 13. The output circuit 16 outputs the digital data that is the final conversion result.
First, the timing signal φ1 is set at 1 and the timing signal φ2 is set at 0 to turn on switches SW1 and SW3 and turn off a switch SW2 of the sample-and-hold circuit 11. As a result, a charge corresponding to (Vref−Vin) is stored in a capacitor C1 of the sample-and-hold circuit 11.
Next, a DAC voltage VDAC is output from the DA converter 14, and the timing signal φ1 is set at 0 and the timing signal φ2 is set at 1 to turn off the switches SW1 and SW3 and turn on the switch SW2 of the sample-and-hold circuit 11. As a result, a voltage VA at a terminal of the capacitor C1 on the side of a differential amplifier 11a becomes VA=Vref+(VDAC−Vin). The voltage VA indicates a voltage difference between the DAC voltage VDAC and the input voltage Vin with reference to the reference voltage Vref. The successive approximation register and operation unit 13 generates next DA conversion data based on the comparison result supplied from the dynamic latch comparator 12. The above-described successive approximation process is repeated from the most significant bit (MSB) to the least significant bit (LSB) of DA conversion data (data to be converted from analog to digital) to generate digital data that is the final conversion result.
Japanese Laid-Open Patent Publication No. 2010-245927 discloses a successive approximation AD conversion circuit including a comparison circuit for comparing an input analog voltage and a comparison voltage. The comparison circuit includes an initial amplifier stage that is used in common, a first comparison unit including a first amplifier stage connected via a coupling capacitor to the initial amplifier stage, a second comparison unit including a second amplifier stage connected via a coupling capacitor to the initial amplifier stage, a first comparison point shift circuit connected to an input terminal of the first amplifier stage, and a second comparison point shift circuit connected to an input terminal of the second amplifier stage. The first comparison point shift circuit and the second comparison point shift circuit shift the comparison voltage for a predetermined amount in opposite directions when amplifying a potential difference between the input analog voltage and the comparison voltage.
Japanese Laid-Open Patent Publication No. 2011-120011 discloses an analog-digital converter including a DAC that outputs a reference analog signal corresponding to a multi-bit digital signal, first and second comparators that compare an input analog signal Vin with the reference analog signal, a selection circuit that selects one of the comparison results of the first and second comparators, and a control circuit that sequentially changes the multi-bit digital signal in multiple steps based on the selected comparison result such that the reference analog signal becomes close to the input analog signal. The control circuit controls the selection circuit to select the comparison result of the first comparator in steps up to a middle step and select the comparison result of the second comparator in steps following the middle step, and thereby changes bit values of the multi-bit digital signal according to a non-binary algorithm.
With the related-art configuration of FIG. 18, however, the successive approximation AD converter requires a long settling time that is the time from when the DA converter 14 starts outputting the DAC voltage VDAC until when the voltage VA of the terminal of the capacitor C1 on the side of the differential amplifier 11a becomes stable at VA=Vref+(VDAC−Vin) and the dynamic latch comparator 12 becomes able to output correct comparison results. Accordingly, the related-art successive approximation AD converter requires a long conversion time.
Also, the successive approximation AD conversion circuit of Japanese Laid-Open Patent Publication No. 2010-245927 requires two comparison units, i.e., the first comparison unit and the second comparison unit. With this configuration, it is troublesome to adjust the two comparison units to make their comparison characteristics the same.
SUMMARY OF THE INVENTION
In an aspect of this disclosure, there is provided a successive approximation AD converter including a DA converter that converts a higher conversion data greater than an approximate value into an analog higher converted voltage and converts a lower conversion data less than the approximate value into an analog lower converted voltage; a sample-and-hold circuit that samples and holds voltage differences between an input voltage input from an outside and each of the higher converted voltage and the lower converted voltage; a comparator that outputs, based on the voltage differences output from the sample-and-hold circuit, a first comparison result indicating whether the input voltage is greater or less than the higher converted voltage and a second comparison result indicating whether the input voltage is greater or less than the lower converted voltage; and an operation unit that changes the approximate value based on the first comparison result and the second comparison result, changes a next higher conversion data and a next lower conversion data based on the changed approximate value, and outputs the changed next higher conversion data and next lower conversion data to the DA converter. The successive approximation AD converter is configured such that operations of the DA converter, the sample-and-hold circuit, the comparator, and the operation unit are repeated to obtain a final approximate value that is output as AD converted data. The operation unit determines a next order in which the next higher conversion data and the next lower conversion data are output to the DA converter based on the first comparison result, the second comparison result, and a previous order in which the higher conversion data and the lower conversion data have been output.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram illustrating an exemplary configuration of a successive approximation AD converter according to an embodiment;
FIG. 2 is a timing chart of signals output from components of the successive approximation AD converter of FIG. 1;
FIG. 3 is a drawing used to describe exemplary operations of the successive approximation AD converter of FIG. 1;
FIG. 4A is a graph illustrating variation of an exemplary output voltage of a DA converter;
FIG. 4B is a drawing used to describe an exemplary operation of codes;
FIG. 5 is a circuit diagram illustrating an exemplary configuration of a successive approximation register and operation unit;
FIG. 6 is a table illustrating a relationship among approximate values, DA conversion data, and increments;
FIG. 7 is a table illustrating comparison data corresponding to comparison results and orders;
FIG. 8A is a flowchart illustrating a part of a successive approximation process according to a first embodiment;
FIG. 8B is a flowchart illustrating another part of the successive approximation process according to the first embodiment;
FIG. 9 is a drawing illustrating an example of an output voltage waveform of a DA converter;
FIG. 10 is a drawing illustrating another example of an output voltage waveform of a DA converter;
FIG. 11 is a graph used to describe settling time;
FIG. 12 is a table illustrating simulation results of conversion time according to the related-art;
FIG. 13 is a table illustrating simulation results of conversion time according to an embodiment;
FIG. 14A is a flowchart illustrating a part of a successive approximation process according to a second embodiment;
FIG. 14B is a flowchart illustrating another part of the successive approximation process according to the second embodiment;
FIG. 14C is a flowchart illustrating another part of the successive approximation process according to the second embodiment;
FIG. 15A is a flowchart illustrating a part of a successive approximation process according to a third embodiment;
FIG. 15B is a flowchart illustrating another part of the successive approximation process according to the third embodiment;
FIG. 15C is a flowchart illustrating another part of the successive approximation process according to the third embodiment;
FIG. 15D is a flowchart illustrating another part of the successive approximation process according to the third embodiment;
FIG. 16A is a drawing illustrating an exemplary switching probability distribution of an analog input and a digital output;
FIG. 16B is a drawing illustrating another exemplary switching probability distribution of an analog input and a digital output;
FIG. 17 is a circuit diagram illustrating a variation of the successive approximation AD converter of FIG. 1; and
FIG. 18 is a circuit diagram illustrating a configuration of a related-art successive approximation AD converter.



DESCRIPTION OF THE PREFERRED EMBODIMENTS
Preferred embodiments of the present invention are described below with reference to the accompanying drawings.
<Circuit Configuration>
FIG. 1 is a circuit diagram illustrating an exemplary configuration of a successive approximation analog-to-digital (AD) converter according to an embodiment. In FIG. 1, an analog voltage Vin is input to an input terminal 20. A sample-and-hold circuit 21 samples and holds the analog voltage Vin or a voltage difference between the analog voltage Vin and an output voltage of a digital-to-analog (DA) converter 25 with reference to a reference voltage Vref.
A comparator 22 is, for example, a dynamic latch comparator and has a hysteresis characteristic. The comparator 22 compares an output voltage of the sample-and-hold circuit 21 with the reference voltage Vref and supplies the comparison result to latch circuits 23A and 23B. The comparison result becomes 1 when the voltage difference between the analog voltage Vin and the output voltage of the DA converter 25 is greater than the reference voltage Vref, and becomes 0 when the voltage difference is less than the reference voltage Vref. In other words, the comparison result indicates whether the analog voltage Vin is greater or less than the output voltage of the DA converter 25. The comparison result becomes 1 when the analog voltage Vin is greater than the output voltage of the DA converter 25, and becomes 0 when the analog voltage Vin is less than the output voltage of the DA converter 25. The connection between the sample-and-hold circuit 21 and the comparator 22 may be configured to transmit a differential signal.
The latch circuit 23A latches a comparison result (CMPA) and supplies the latched comparison result to a successive approximation register and operation unit 24 when the value of a timing signal φ3A is 1 (high level). The latch circuit 23B latches a comparison result (CMPB) and supplies the latched comparison result to the successive approximation register and operation unit 24 when the value of a timing signal φ3B is 1 (high level).
The successive approximation register and operation unit 24 determines the corresponding bit based on the comparison results supplied from the latch circuits 23A and 23B, generates next (or subsequent) DA conversion data (data to be converted in the next DA conversion process), supplies the next DA conversion data as comparison data to the DA converter 25, and supplies a final conversion result to an output circuit 27.
A control circuit 26 receives a clock signal and a conversion start command from the outside, generates timing signals φ1, φ2, φ3A, and φ3B, supplies the timing signals φ1, φ2, φ3A, and φ3B to the sample-and-hold circuit 21 and the latch circuits 23A and 23B, generates a control signal indicating a start or an end, and supplies the control signal to the successive approximation register and operation unit 24. The control circuit 26 also outputs a conversion end command to the outside. The output circuit 27 outputs digital data that is the final conversion result (final approximate value) to the outside.
The timing signal φ1 is set at 1 (high level) and the timing signal φ2 is set at 0 (low level) at the timing of a sampling operation in FIG. 2 to turn on switches SW1 and SW3 and turn off a switch SW2 of the sample-and-hold circuit 21. As a result, a charge corresponding to (Vref−Vin) is stored in a capacitor C1 of the sample-and-hold circuit 21.
Next, at the timing of a first comparison operation A in FIG. 2, a DAC voltage VDACA is output from the DA converter 25, and the timing signal φ1 is set at 0 and the timing signal φ2 is set at 1 to turn off the switches SW1 and SW3 and turn on the switch SW2 of the sample-and-hold circuit 21. As a result, a voltage VA at a terminal of the capacitor C1 on the side of a differential amplifier 21a becomes VAA=Vref+(VDAcA−Vin). In this case, the voltage VA indicates a voltage difference between the DAC voltage VDACA and the input voltage Vin with reference to the reference voltage Vref. The latch circuit 23A latches a comparison result that is supplied from the comparator 22 at a timing when the timing signal φ3A is 1, and supplies the latched comparison result to the successive approximation register and operation unit 24.
Next, at the timing of a first comparison operation B in FIG. 2, a DAC voltage VDACB is output from the DA converter 25, and the timing signal φ1 is set at 0 and the timing signal φ2 is set at 1 to turn off the switches SW1 and SW3 and turn on the switch SW2 of the sample-and-hold circuit 21. As a result, the voltage VA at the terminal of the capacitor C1 on the side of the differential amplifier 21a becomes VAB=Vref+(VDACB−Vin). In this case, the voltage VA indicates a voltage difference between the DAC voltage VDACB and the input voltage Vin with reference to the reference voltage Vref. The latch circuit 23B latches a comparison result that is supplied from the comparator 22 at a timing when the timing signal φ3B is 1, and supplies the latched comparison result to the successive approximation register and operation unit 24. Second and succeeding comparison operations A and B are performed in a similar manner.
FIG. 3 is a drawing used to describe exemplary operations of the successive approximation AD converter of the present embodiment. FIG. 3 illustrates a comparison operation for a (n−1)th bit and a comparison operation for a (n−2)th bit. In the present embodiment, an original comparison point is used as a reference point, and two comparison points are set at positions shifted upward and downward from the original comparison point. The comparison points are set such that a shift amount V from the original comparison point becomes smaller as the number of performed comparison operations increases. Instead of decreasing the shift amount V each time, the shift amount V may be set such that V≦FS/2n×2(k−2) is satisfied at a comparison operation for a k-th bit and the same shift amount V may be used throughout the process. Also, the shift amount V may be decreased at intervals. In FIG. 3, FS indicates a potential difference between the upper limit and the lower limit of a full scale range (FSR) indicating a range of voltages that can be converted from analog to digital.
Comparison results are represented by three types of codes (1, 0), (0, 1), and (0, 0) according to input voltage ranges. Code (1, 0) indicates that the outputs from the latch circuits 23A and 23B are “1, 1”. Code (0, 1) indicates that the outputs from the latch circuits 23A and 23B are “0, 1”. Code (0, 0) indicates that the outputs from the latch circuits 23A and 23B are “0, 0”.
In the comparison operation for the (n−2)th bit, the comparison points are shifted according to a code indicating the comparison result of the (n−1)th bit. When the comparison result of the (n−1)th bit is (1, 0), both of the comparison points are shifted to higher positions as indicated by (1) in FIG. 3. When the comparison result of the (n−1)th bit is (0, 1), the comparison points are shifted such that they come closer to each other as indicated by (2) in FIG. 3. When the comparison result of the (n−1)th bit is (0, 0), both of the comparison points are shifted to lower positions as indicated by (3) in FIG. 3. Thus, according to the comparison result (code) of the previous comparison operation, the next comparison operation is performed in one of the ranges indicated by (1), (2), and (3) in FIG. 3. With the above process, redundant determination is performed using a shift amount V between the two comparison points as a redundant determination range.
FIG. 4A is a graph illustrating variation of an exemplary output voltage of the DA converter 25 performing an AD conversion process according to the above described method. With the present embodiment where two comparison points are set at positions shifted upward and downward from the original comparison point, determination errors at higher-order bits are less likely to occur and accurate final conversion results can be obtained when the potential of the input voltage Vin is close to the original comparison point as illustrated by FIG. 4A.
Results (three types of 2-bit codes) obtained by repeating comparison operations as described above are added by the successive approximation register and operation unit 24. In the example of FIG. 4B, the successive approximation register and operation unit 24 shifts the results by one digit from each other, adds the shifted results, and truncates the least significant bit to obtain an AD conversion result. Instead of being truncated, the least significant bit may be rounded up.
FIG. 5 is a circuit diagram illustrating an exemplary configuration of the successive approximation register and operation unit 24. As illustrated by FIG. 5, the successive approximation register and operation unit includes a comparison determination-add/subtract circuit 24a, a DAC register 24b, and a successive approximation register (SAR) 24c. The comparison determination-add/subtract circuit 24a determines an approximate value SARi based on the comparison results CMPA and CMPB supplied from the latch circuits 23A and 23B, and generates DA conversion data DACLi and DACHi for obtaining a next approximate value SARi+1 by performing an addition/subtraction process on the determined approximate value SARi. DACLi indicates lower (or smaller) DA conversion data, and DACHi indicates higher (or larger) DA conversion data.
The comparison determination-add/subtract circuit 24a stores the DA conversion data DACLi and DACHi for the next bit in the DAC register 24b, and stores the approximate value SARi in the successive approximation register 24c. The DA conversion data DACLi and DACHi are read sequentially from the DAC register 24b and supplied to the DA converter 25. The approximate value SARi read from the successive approximation register 24c is supplied to the comparison determination-add/subtract circuit 24a to perform the addition/subtraction process to obtain the next approximate value SARi+1. Also, all bits of digital data, i.e., a conversion result, are supplied from the successive approximation register 24c to the output circuit 27.
An exemplary process performed by the successive approximation register and operation unit 24 is described below. In the exemplary process, it is assumed that the analog voltage Vin is converted into 12-bit digital data.
FIG. 6 is a table illustrating a relationship among approximate values SARi, DA conversion data DACLi and DACHi, and increments SARi. In FIG. 6, SAR1 is 211=2048, DACL1 is SAR1−2(n−3)=SAR1−29, and DACH1 is SAR1+2(n−3)=SAR1+29. Similarly, DACL2 is SAR2−2(n−4)=SAR2−28, and DACH2 is SAR2+2(n−4)=SAR2+28.
In the example of FIG. 6, the amount of change from the approximate value SAR2 to each of the lower conversion data DACL2 and the higher conversion data DACH2 is one half (±28) of the amount of change (±29) from the approximate value SAR1 to the approximate value SAR2. However, the amount of change from the approximate value SAR2 to each of the lower conversion data DACL2 and the higher conversion data DACH2 may be set at any value that is less than or equal to one half (±28) of the amount of change (±29) from the approximate value SAR1 to the approximate value SAR2.
FIG. 7 is a table illustrating comparison data DACA(i+1) and DACB(i+1) that are to be stored in the DAC register 24b and correspond to comparison results CMPAi and CMPBi and orders ORDERi. FIG. 7 also illustrates values to be set for orders ORDER(i+1) of the comparison data DACA(i+1) and DACB(i+1). The comparison data DACAi indicates a value to be compared first, and the comparison data DACBi indicates a value to be compared after the comparison data DACAi. The order ORDERi=0 indicates that comparison with the higher DA conversion data DACHi is performed first and comparison with the lower DA conversion data DACLi is performed next. The order ORDERi=1 indicates that comparison with the lower DA conversion data DACLi is performed first and comparison with the higher DA conversion data DACHi is performed next. The value of the initial order ORDER1 may be set at, for example, 1.
In FIG. 7, when the comparison result CMPAi is 0, the comparison result CMPBi is 0, and the order ORDERi is 0, the higher DA conversion data DACH(i+1) is set as the comparison data DACA(i+1) and the lower DA conversion data DACL(i+1) is set as the comparison data DACB(i+1). Also, the next order ORDER(i+1) is set at 0.
When the comparison result CMPAi is 0, the comparison result CMPBi is 1, and the order ORDERi is 0, the lower DA conversion data DACL(i+1) is set as the comparison data DACA(i+1) and the higher DA conversion data DACH(i+1) is set as the comparison data DACB(i+1). In this case, the next order ORDER(i+1) is set at 1.
In the example of FIG. 7, the next order ORDER(i+1) becomes 0 when both of the comparison results CMPAi and CMPBi are 0 and the order ORDERi is 0. On the other hand, the next order ORDER(i+1) becomes 1 when at least one of the comparison results CMPAi and CMPBi is 1 and the order ORDERi is 0. Also, the next order ORDER(i+1) becomes 0 when at least one of the comparison results CMPAi and CMPBi is 0 and the order ORDERi is 1. Further, the next order ORDER(i+1) becomes 1 when both of the comparison results CMPAi and CMPBi are 1 and the order ORDERi is 1.
Setting the next order ORDER(i+1) as described above makes it possible to minimize the amount of change between the comparison data DACBi that is the second output in the previous comparison and the comparison data DACA(i+1) that is the first output in the next comparison, and thereby makes it possible to minimize the settling time. This in turn makes it possible to minimize the amount of charge stored in the capacitor C1 when the comparison data DACA(i+1) is output, and thereby makes it possible to reduce the power consumption for a conversion process.
First Embodiment
FIGS. 8A and 8B are flowcharts illustrating a successive approximation process performed by the successive approximation register and operation unit 24 according to a first embodiment. In FIG. 8A, the successive approximation register and operation unit 24 sets “i” at 1, sets ORDER1 at 1, and starts conversion at step S1. The successive approximation register and operation unit 24 starts sampling of the analog voltage Vin at step S2, and ends the sampling at step S3. Next, the successive approximation register and operation unit 24 starts comparison at step S4.
The successive approximation register and operation unit 24 supplies the comparison data DACAi to the DA converter 25 at step S5, and latches the comparison result CMPA at step S6. Then, the successive approximation register and operation unit 24 supplies the comparison data DACBi to the DA converter 25 at step S7, and latches the comparison result CMPB at step S8.
In FIG. 8B, the successive approximation register and operation unit 24 determines, at step S9, whether CMPA=1 and CMPB=1 are true. When CMPA=1 and CMPB=1 are true, the successive approximation register and operation unit 24, at step S10, sets SARi+ΔSARi as the approximate value SAR(i+1). When CMPA=1 and CMPB=1 are not true, the successive approximation register and operation unit 24 determines, at step S11, whether CMPA=0 and CMPB=0 are true. When CMPA=0 and CMPB=0 are true, the successive approximation register and operation unit 24, at step S12, sets SARi−ΔSARi as the approximate value SAR(i+1). When CMPA=0 and CMPB=0 are not true, the successive approximation register and operation unit 24, at step S13, sets SARi as the approximate value SAR(i+1).
The successive approximation register and operation unit 24 sets next SAR(i+1), DACA(i+1), and DACB(i+1) at step S14 based on the relationships illustrated by FIGS. 6 and 7, and sets the next order ORDER(i+1) at step S15 based on the relationships illustrated by FIGS. 6 and 7. The successive approximation register and operation unit 24 increments “i” (i=i+1) at step S16, and determines whether i=n is true at step S17. Here, “n” indicates the number of bits of digital data to be obtained by conversion. When i=n is not true, the process proceeds to step S5 of FIG. 8A. When i=n is true, the process proceeds to step S18.
When “i” reaches “n” (i=n) and the least significant bit is processed, the successive approximation register and operation unit 24 supplies the comparison data DACAi to the DA converter 25 at step 18, and latches the comparison result CMPA at step S19. At step S20, the successive approximation register and operation unit 24 determines whether CMPA=1 is true. When CMPA=1 is true, the successive approximation register and operation unit 24 sets SARi as SAR(i+1) at step S21. When CMPA=1 is not true, the successive approximation register and operation unit 24 sets SARi−ΔSARi as SAR(i+1) at step S22. Then, the successive approximation register and operation unit 24, at step S23, sets SAR(i+1) in the successive approximation register (SAR) 24c to output SAR(i+1) as converted digital data, and terminates the process.
FIGS. 9 and 10 are drawings illustrating exemplary voltage waveforms output by the DA converter 25 when the input voltage is Vin. FIG. 9 illustrates a case where a comparison time t is set at 10τ(τ is a time constant of the sample-and-hold circuit 21), and FIG. 10 illustrates a case where the comparison time t is set at 3τ.
Here, with a related-art successive approximation AD conversion circuit where only one comparison point is used, settling time T1 indicated in FIG. 11 is necessary to correctly determine the output voltage of a DA converter. On the other hand, according to the present embodiment where two comparison points are used and the range between the comparison points is used as a redundant determination range, settling time can be reduced to T2 indicated in FIG. 11.
FIG. 12 is a table illustrating simulation results of conversion time for converting 12 bits according to the related art, and FIG. 13 is a table illustrating simulation results of conversion time for converting 12 bits according to the present embodiment. According to the related art, as illustrated by FIG. 12, the number of conversion operations for converting 12 bits is 13 and the total conversion time is 86.1 τ (τ is a time constant). According to the present embodiment, as illustrated by FIG. 13, the number of conversion operations for converting 12 bits is 25 and the total conversion time is 47.2 τ. Thus, according to the present embodiment, although the number of conversion operations increases, the total conversion time is reduced.
As the simulation results indicate, the first embodiment makes it possible to perform accurate AD conversion at high speed. Also, the first embodiment requires only one comparator 22 and therefore eliminates the need to make uniform the comparison characteristics (including offsets) of multiple comparators.
Second Embodiment
FIGS. 14A through 14C are flowcharts illustrating a successive approximation process performed by the successive approximation register and operation unit 24 according to a second embodiment. In the second embodiment, redundant determination using two comparison points is performed for higher m bits (m≦n; e.g., 6) of 12-bit digital data, and normal determination using one comparison point is performed for lower (12-m) bits.
In FIG. 14A, the successive approximation register and operation unit 24 sets “i” at 1, sets ORDER1 at 1, and starts conversion at step S31. The successive approximation register and operation unit 24 starts sampling of the analog voltage Vin at step S32, and ends the sampling at step S33. Next, the successive approximation register and operation unit 24 starts comparison at step S34.
The successive approximation register and operation unit 24 supplies the comparison data DACAi to the DA converter 25 at step S35, and latches the comparison result CMPA at step S36. Then, the successive approximation register and operation unit 24 supplies the comparison data DACBi to the DA converter 25 at step S37, and latches the comparison result CMPB at step S38.
In FIG. 14B, the successive approximation register and operation unit 24 determines, at step S39, whether CMPA=1 and CMPB=1 are true. When CMPA=1 and CMPB=1 are true, the successive approximation register and operation unit 24, at step S40, sets SARi+ΔSARi as the approximate value SAR(i+1). When CMPA=1 and CMPB=1 are not true, the successive approximation register and operation unit 24 determines, at step S41, whether CMPA=0 and CMPB=0 are true. When CMPA=0 and CMPB=0 are true, the successive approximation register and operation unit 24, at step S42, sets SARi−ΔSARi as the approximate value SAR(i+1). When CMPA=0 and CMPB=0 are not true, the successive approximation register and operation unit 24, at step S13, sets SARi as the approximate value SAR(i+1).
The successive approximation register and operation unit 24 sets next SAR(i+1), DACA(i+1), and DACB(i+1) at step S44 based on the relationships illustrated by FIGS. 6 and 7, and sets the next order ORDER(i+1) at step S45 based on the relationships illustrated by FIGS. 6 and 7. The successive approximation register and operation unit 24 increments “i” (i=i+1) at step S46, and determines whether i=m+1 is true at step S47. When i=m+1 is not true, the process proceeds to step S35 of FIG. 14A. When i=m+1 is true, the process proceeds to step S48.
The successive approximation register and operation unit 24 supplies the comparison data DACAi to the DA converter 25 at step S48, and latches the comparison result CMPA at step S49. At step S50, the successive approximation register and operation unit 24 determines whether CMPA=1 is true. When CMPA=1 is true, the successive approximation register and operation unit 24 sets SARi+ΔSARi as SAR(i+1) at step S51. When CMPA=1 is not true, the successive approximation register and operation unit 24 sets SARi−ΔSARi as SAR(i+1) at step S52. At step S53, the successive approximation register and operation unit 24 sets next SAR(i+1) and DACA(i+1) at step S53 based on the relationships illustrated by FIGS. 6 and 7. Then, the successive approximation register and operation unit 24 increments “i” (i=i+1) at step S55, and determines whether i=n is true at step S55. When i=n is not true, the process proceeds to step S48. When i=n is true, the process proceeds to step S56 of FIG. 14C.
The successive approximation register and operation unit 24 supplies the comparison data DACAi to the DA converter 25 at step S56, and latches the comparison result CMPA at step S57. At step S58, the successive approximation register and operation unit 24 determines whether CMPA=1 is true. When CMPA=1 is true, the successive approximation register and operation unit 24 sets SARi as SAR(i+1) at step S59. When CMPA=1 is not true, the successive approximation register and operation unit 24 sets SARi−ΔSARi as SAR(i+1) at step S60. Then, the successive approximation register and operation unit 24, at step S61, sets SAR(i+1) in the successive approximation register (SAR) 24c to output SAR(i+1) as converted digital data, and terminates the process.
In the second embodiment, normal determination using one comparison point is performed for the lower (12-m) bits where the variation of the approximate value SAR, i.e., the variation in the output voltage of the DA converter 25, becomes smaller than that in the higher m bits. Accordingly, compared with the first embodiment, the second embodiment makes it possible to reduce the number of comparison operations and the total conversion time.
Third Embodiment
FIGS. 15A through 15d are flowcharts illustrating a successive approximation process performed by the successive approximation register and operation unit 24 according to a third embodiment. In the third embodiment, after performing redundant determination for higher m bits of 12-bit digital data, redundant determination is repeated x (e.g., 4) times for lower (12-m) bits using SAR obtained in the redundant determination for the higher m bits and the determination results are averaged to improve the accuracy of redundant determination.
In FIG. 15A, the successive approximation register and operation unit 24 sets “i” at 1, sets “j” at 0, sets ORDER1 at 1, and starts conversion at step S71. The successive approximation register and operation unit 24 starts sampling of the analog voltage Vin at step S72, and ends the sampling at step S73. Next, the successive approximation register and operation unit 24 starts comparison at step S74.
The successive approximation register and operation unit 24 supplies the comparison data DACAi to the DA converter 25 at step S75, and latches the comparison result CMPA at step S76. Then, the successive approximation register and operation unit 24 supplies the comparison data DACBi to the DA converter 25 at step S77, and latches the comparison result CMPB at step S78.
In FIG. 15B, the successive approximation register and operation unit 24 determines, at step S79, whether CMPA=1 and CMPB=1 are true. When CMPA=1 and CMPB=1 are true, the successive approximation register and operation unit 24, at step S80, sets SARi+ΔSARi as the approximate value SAR(i+1). When CMPA=1 and CMPB=1 are not true, the successive approximation register and operation unit 24 determines, at step S81, whether CMPA=0 and CMPB=0 are true. When CMPA=0 and CMPB=0 are true, the successive approximation register and operation unit 24, at step S82, sets SARi−ΔSARi as the approximate value SAR(i+1). When CMPA=0 and CMPB=0 are not true, the successive approximation register and operation unit 24, at step S83, sets SARi as the approximate value SAR(i+1).
The successive approximation register and operation unit 24 sets next SAR(i+1), DACA(i+1), and DACB(i+1) at step S84 based on the relationships illustrated by FIGS. 6 and 7, and sets the next order ORDER(i+1) at step S85 based on the relationships illustrated by FIGS. 6 and 7. The successive approximation register and operation unit 24 increments “i” (i=i+1) at step S86, and determines whether i=m+1 is true at step S87. When i=m+1 is not true, the process proceeds to step S75 of FIG. 15A. When i=m+1 is true, the process proceeds to step S88.
At step S88, the successive approximation register and operation unit 24 saves SAR(i+1), which is a comparison result of the higher m bits, in a variable A. The successive approximation register and operation unit supplies the comparison data DACAi to the DA converter 25 at step S89, and latches the comparison result CMPA at step S90. Then, the successive approximation register and operation unit 24 supplies the comparison data DACBi to the DA converter 25 at step S91, and latches the comparison result CMPB at step S92.
At step S93 of FIG. 15C, the successive approximation register and operation unit 24 determines whether CMPA=1 and CMPB=1 are true. When CMPA=1 and CMPB=1 are true, the successive approximation register and operation unit 24, at step S94, sets SARi+ΔSARi as the approximate value SAR(i+1). When CMPA=1 and CMPB=1 are not true, the successive approximation register and operation unit 24 determines, at step S95, whether CMPA=0 and CMPB=0 are true. When CMPA=0 and CMPB=0 are true, the successive approximation register and operation unit 24, at step S96, sets SARi−ΔSARi as the approximate value SAR(i+1). When CMPA=0 and CMPB=0 are not true, the successive approximation register and operation unit 24, at step S97, sets SAR, as the approximate value SAR(i+1).
The successive approximation register and operation unit 24 sets next SAR(i+1), DACA(i+1), and DACB(i+1) at step S98 based on the relationships illustrated by FIGS. 6 and 7, and sets the next order ORDER(i+1) at step S99 based on the relationships illustrated by FIGS. 6 and 7. The successive approximation register and operation unit 24 increments “i” (i=i+1) at step S100, and determines whether i=n is true at step S101. When i=n is not true, the process proceeds to step S89 of FIG. 15B. When i=n is true, the process proceeds to step S106 of FIG. 15D.
The successive approximation register and operation unit 24 supplies the comparison data DACAi to the DA converter 25 at step S106 of FIG. 15D, and latches the comparison result CMPA at step S107. At step S108, the successive approximation register and operation unit 24 determines whether CMPA=1 is true. When CMPA=1 is true, the successive approximation register and operation unit 24 sets SARi as SAR(i+1) at step S109. When CMPA=1 is not true, the successive approximation register and operation unit 24 sets SARi−ΔSARi as SAR(i+1) at step S110.
The successive approximation register and operation unit 24 sets SAR(i+1) in a variable SAR at step S111, and sets the value of the variable SAR in a variable Bj at step S112. At step S113, the successive approximation register and operation unit 24 sets “i” at “m+1” (i=m+1) and increments “j” (j=j+1). Then, the successive approximation register and operation unit 24 determines, at step S114, whether j=x is true. When j=x is not true, the successive approximation register and operation unit 24 sets the comparison result of the higher m bits, which is saved in the variable A, in the variable SAR, and proceeds to step S89. On the other hand, when j=x is true, the successive approximation register and operation unit 24 calculates an average AVE of the total of B1 through Bx at step S116. Then, the successive approximation register and operation unit 24 sets the average AVE in the successive approximation register (SAR) 24c to output the average AVE as converted digital data, and terminates the process.
When the switching probability distribution of an analog input and a digital output is concentrated on a switching point as illustrated by FIG. 16A, the accuracy of redundant determination is good. On the other hand, when the switching probability distribution of an analog input and a digital output is not concentrated on a switching point as illustrated by FIG. 16B, the accuracy of redundant determination is degraded. The third embodiment makes it possible to prevent the degradation of the accuracy of redundant determination.
Steps S112, S116, and S117 of FIG. 15D may be changed below. For example, at step S112, instead of setting the value of the variable SAR in the variable Bj, a difference between the value of the variable SAR and the value of the variable A may be set in the variable Bj. Also, an average AVE of the total of differences B1 through Bx may be obtained at step S116, and a value obtained by adding the average AVE to the value of the variable A may be set in the successive approximation register (SAR) 24c at step S117 and output as converted digital data.
Thus, according to the third embodiment, redundant determination is repeated x times for the lower (12-m) bits and the determination results are averaged to improve the noise tolerance and the accuracy of redundant determination.
Steps S89 through S105 of the third embodiment may be replaced with steps S48 through S55 of the second embodiment.
<Variation of Circuit Configuration>
FIG. 17 is a circuit diagram illustrating a variation of the successive approximation AD converter of FIG. 1. In FIG. 17, an analog voltage Vin is input to an input terminal 20. A sample-and-hold circuit 21 samples and holds the analog voltage Vin or a voltage difference between the analog voltage Vin and an output voltage of a DA converter (DAC) 25 with reference to a reference voltage Vref.
A dynamic latch comparator 31A has a hysteresis characteristic. The dynamic latch comparator 31A compares an output voltage of the sample-and-hold circuit 21 with the reference voltage Vref and generates a comparison result that becomes 1 when the voltage difference between the analog voltage Vin and the output voltage of the DA converter 25 is greater than the reference voltage Vref and becomes 0 when the voltage difference is less than the reference voltage Vref. The dynamic latch comparator 31A latches the comparison result (CMPA) and supplies the latched comparison result to a successive approximation register and operation unit 24 when the value of a timing signal φ3A is 1.
A dynamic latch comparator 31B has a hysteresis characteristic. The dynamic latch comparator 31B compares an output voltage of the sample-and-hold circuit 21 with the reference voltage Vref and generates a comparison result that becomes 1 when the voltage difference between the analog voltage Vin and the output voltage of the DA converter 25 is greater than the reference voltage Vref and becomes 0 when the voltage difference is less than the reference voltage Vref. The dynamic latch comparator 31B latches the comparison result (CMPB) and supplies the latched comparison result to the successive approximation register and operation unit 24 when the value of a timing signal φ3B is 1.
The successive approximation register and operation unit 24 determines the corresponding bit based on the comparison results supplied from the dynamic latch comparators 31A and 31B, generates next DA conversion data, supplies the next DA conversion data as comparison data to the DA converter 25, and supplies a final conversion result to an output circuit 27.
A control circuit 26 receives a clock signal and a conversion start command from the outside, generates timing signals φ1, φ2, φ3A, and φ3B, supplies the timing signals φ1, φ2, φ3A, and φ3B to the sample-and-hold circuit 21 and the dynamic latch comparators 31A and 31B, generates a control signal indicating a start or an end, and supplies the control signal to the successive approximation register and operation unit 24. The control circuit 26 also outputs a conversion end command to the outside. The output circuit 27 outputs digital data representing the final conversion result (final approximate value).
An aspect of this disclosure provides a successive approximation AD converter and a successive approximation AD conversion method that make it possible to perform accurate AD conversion at high speed.
A successive approximation AD converter and a successive approximation AD conversion method are described above as preferred embodiments. However, the present invention is not limited to the specifically disclosed embodiments, and variations and modifications may be made without departing from the scope of the present invention.

## Claims

1. A successive approximation AD converter, comprising:
a DA converter that converts a higher conversion data greater than an approximate value into an analog higher converted voltage and converts a lower conversion data less than the approximate value into an analog lower converted voltage;
a sample-and-hold circuit that samples and holds voltage differences between an input voltage input from an outside and each of the higher converted voltage and the lower converted voltage;
a comparator that outputs, based on the voltage differences output from the sample-and-hold circuit, a first comparison result indicating whether the input voltage is greater or less than the higher converted voltage and a second comparison result indicating whether the input voltage is greater or less than the lower converted voltage; and
an operation unit that changes the approximate value based on the first comparison result and the second comparison result, changes a next higher conversion data and a next lower conversion data based on the changed approximate value, and outputs the changed next higher conversion data and next lower conversion data to the DA converter,
wherein the successive approximation AD converter is configured such that operations of the DA converter, the sample-and-hold circuit, the comparator, and the operation unit are repeated to obtain a final approximate value that is output as AD converted data; and
wherein the operation unit determines a next order that indicates whether the next higher conversion data or the next lower conversion data is to be output first to the DA converter, based on the first comparison result, the second comparison result, and a previous order that indicates whether the higher conversion data or the lower conversion data was output first.

2. The successive approximation AD converter as claimed in claim 1,
wherein when the first and second comparison results indicate that the input voltage is less than both of the higher converted voltage and the lower converted voltage, and the higher conversion data has been output before the lower conversion data in the previous order, the operation unit determines the next order such that the next higher conversion data is output before the next lower conversion data;
wherein when the first and second comparison results indicate that the input voltage is greater than at least one of the higher converted voltage and the lower converted voltage, and the higher conversion data has been output before the lower conversion data in the previous order, the operation unit determines the next order such that the next lower conversion data is output before the next higher conversion data;
wherein when the first and second comparison results indicate that the input voltage is less than at least one of the higher converted voltage and the lower converted voltage, and the lower conversion data has been output before the higher conversion data in the previous order, the operation unit determines the next order such that the next higher conversion data is output before the next lower conversion data; and
wherein when the first and second comparison results indicate that the input voltage is greater than both of the higher converted voltage and the lower converted voltage, and the lower conversion data has been output before the higher conversion data in the previous order, the operation unit determines the next order such that the next lower conversion data is output before the next higher conversion data.

3. The successive approximation AD converter as claimed in claim 1, wherein the operation unit sets an amount of change from the changed approximate value to each of the next higher conversion data and the lower conversion data at a value that is less than or equal to one half of an amount of change of the changed approximate value.

4. The successive approximation AD converter as claimed in claim 1, wherein for lower bits of a plurality of bits representing the approximate value,
the DA converter converts, instead of the higher conversion data and the lower conversion data, the approximate value into an analog converted voltage,
the sample-and-hold circuit samples and holds a voltage difference between the input voltage and the converted voltage of the approximate value, instead of the voltage differences between the input voltage and each of the higher converted voltage and the lower converted voltage,
the comparator outputs, instead of the first and second comparison results, a third comparison result indicating whether the input voltage is greater or less than the converted voltage of the approximate value, and
the operation unit changes the approximate value based on the third comparison result instead of the first and second comparison results.

5. The successive approximation AD converter as claimed in claim 1, wherein the successive approximation AD converter is configured such that a process performed by the DA converter, the sample-and-hold circuit, the comparator, and the operation unit is repeated multiple times for lower bits of a plurality of bits representing the approximate value to obtain a plurality of final approximate values, and an average of the final approximate values is output as the AD converted data.

6. A successive approximation AD conversion method performed by a successive approximation AD converter, the method comprising:
converting a higher conversion data greater than an approximate value into an analog higher converted voltage and converting a lower conversion data less than the approximate value into an analog lower converted voltage by a DA converter of the successive approximation AD converter;
sampling and holding voltage differences between an input voltage input from an outside and each of the higher converted voltage and the lower converted voltage;
outputting, based on the voltage differences, a first comparison result indicating whether the input voltage is greater or less than the higher converted voltage and a second comparison result indicating whether the input voltage is greater or less than the lower converted voltage; and
changing the approximate value based on the first comparison result and the second comparison result, and changing a next higher conversion data and a next lower conversion data, which are to be output to the DA converter, based on the changed approximate value,
wherein the converting, the sampling and holding, the outputting, and the changing are repeated to obtain a final approximate value that is output as AD converted data; and
wherein a next order that indicates whether the next higher conversion data or the next lower conversion data is to be output first to the DA converter is determined, based on the first comparison result, the second comparison result, and a previous order that indicates whether the higher conversion data or the lower conversion data was output first.

7. The successive approximation AD conversion method as claimed in claim 6,
wherein when the first and second comparison results indicate that the input voltage is less than both of the higher converted voltage and the lower converted voltage, and the higher conversion data has been output before the lower conversion data in the previous order, the next order is determined such that the next higher conversion data is output before the next lower conversion data;
wherein when the first and second comparison results indicate that the input voltage is greater than at least one of the higher converted voltage and the lower converted voltage, and the higher conversion data has been output before the lower conversion data in the previous order, the next order is determined such that the next lower conversion data is output before the next higher conversion data;
wherein when the first and second comparison results indicate that the input voltage is less than at least one of the higher converted voltage and the lower converted voltage, and the lower conversion data has been output before the higher conversion data in the previous order, the next order is determined such that the next higher conversion data is output before the next lower conversion data; and
wherein when the first and second comparison results indicate that the input voltage is greater than both of the higher converted voltage and the lower converted voltage, and the lower conversion data has been output before the higher conversion data in the previous order, the next order is determined such that the next lower conversion data is output before the next higher conversion data.

8. The successive approximation AD conversion method as claimed in claim 6, wherein an amount of change from the changed approximate value to each of the next higher conversion data and the lower conversion data is set at a value that is less than or equal to one half of an amount of change of the changed approximate value.

9. The successive approximation AD conversion method as claimed in claim 6, wherein for lower bits of a plurality of bits representing the approximate value,
instead of the higher conversion data and the lower conversion data, the approximate value is converted into an analog converted voltage,
instead of the voltage differences between the input voltage and each of the higher converted voltage and the lower converted voltage, a voltage difference between the input voltage and the converted voltage of the approximate value is sampled and held,
instead of the first and second comparison results, a third comparison result indicating whether the input voltage is greater or less than the converted voltage of the approximate value is output, and
the approximate value is changed based on the third comparison result instead of the first and second comparison results.

10. The successive approximation AD conversion method as claimed in claim 6, wherein a process including the converting, the sampling and holding, the outputting, and the changing is repeated multiple times for lower bits of a plurality of bits representing the approximate value to obtain a plurality of final approximate values, and an average of the final approximate values is output as the AD converted data.