Exhibit1036IDT-TSMCFoundryAgreementFinalDraftA




FOUNDRY AGREEMENT
This FOUNDRY AGREEMENT (the “Agreement”) is made this 3rd day of August, 2009, (the “Effective Date”), by and between INTEGRATED DEVICE TECHNOLOGY, INC., a Delaware corporation with its principal place of business at 6024 Silver Creek Valley Road, San Jose, CA 95138 (“IDT”), Taiwan Semiconductor Manufacturing Co., Ltd., a company duly incorporated under the laws of the Republic of China with its principal place of business at No. 8, Li-Hsin Rd., 6, Science-Based Industrial Park, Hsin-Chu, Taiwan 300-77, R.O.C., and TSMC North America, a California corporation with its principal place of business at 2585 Junction Avenue, San Jose, CA 95014 (together with Taiwan Semiconductor Manufacturing Co., Ltd., “TSMC”).  
WHEREAS, IDT has designed and developed certain semiconductor products which it sells to the commercial market and wishes to contract with TSMC for the manufacture of such products;
WHEREAS, IDT has developed certain proprietary semiconductor manufacturing process technology associated with such semiconductor products, and desires to provide, license and qualify such process technology for use by TSMC at TSMC facilities solely for the purpose of manufacturing products for IDT;
WHEREAS, TSMC has the capacity and skill to manufacture high quality semiconductor products in volume;
WHEREAS, IDT and TSMC desire to establish a strategic supplier relationship where TSMC will utilize its capacity and proprietary process technology to manufacture certain semiconductor products for IDT; and
WHEREAS, the parties now wish to establish the terms and conditions for the licensing and provision of manufacturing process technology from IDT to TSMC, the qualification of TSMC processes and facilities for manufacture of IDT products, the fabrication of semiconductor products by TSMC and provision of related services, and the purchase of the same by IDT from TSMC, as more specifically set forth herein;


NOW, THEREFORE, in consideration of the mutual promises of the parties, and of good and valuable consideration, it is agreed by and among the parties as follows:
1.DEFINITIONS
The following capitalized terms, and other capitalized terms defined elsewhere in this Agreement, will have the meanings ascribed thereto wherever used in this Agreement and terms in the singular shall encompass and include the plural and words in the plural shall encompass and include the singular.  Terms not defined herein shall be given their plain English meaning; provided, however, those terms, acronyms and phrases known in the semiconductor industry that are not defined shall be interpreted in accordance with their generally accepted industry meaning:
1.1    “Affiliate” means an entity that, through one or more intermediaries, controls, is controlled by or is under common control with IDT or TSMC.  For this purpose, “control” will mean either, ownership of more than 50% of the voting securities of the entity, or having possession, of the power to direct or cause the direction of the management and policies of such entity.  An entity shall be deemed an Affiliate only for so long as such control exists.  





1.2    “Business Day” means any day other than a Saturday, a Sunday or a day on which banking institutions located in the jurisdiction in which the person to whom notice is to be provided is located are authorized or obligated by law or executive order to close. 
1.3    “Change of Control” means a merger or consolidation with another entity resulting in a change in the possession, directly or indirectly, of the power, vote more than fifty percent (50%) of the voting securities with respect to such party.
1.4    “Confidential Information” shall mean any information disclosed by one party to the other in connection with this Agreement, whether in electronic, written, graphic, oral, machine readable or other tangible or intangible form, that is marked or identified at the time of disclosure as “Confidential” or “Proprietary” or in some other manner so as to clearly indicate its confidential nature.  
1.5    “Current Forecast” shall mean, at any given time, the most recently accepted Forecast by TSMC.
1.6    “Die” shall mean one of the integrated circuit devices on a Wafer. 
1.7    “Engineering Change” shall mean any change to the process, materials, equipment, Technology, location and any other items listed in TSMC’s standard specifications for a Qualified Process, including those changes that would affect the performance, function, Yield or reliability of the Wafers.
1.8    “Engineering Wafers” shall mean prototype Wafer or Wafers required for a Qualification Plan or delivered to IDT for testing pursuant to IDT’s request.
1.9    “Epidemic Failure” shall mean Wafer failures (i) having the same or similar cause, (ii) occurring within three (3) years after the date of delivery of the Wafers to IDT, (iii) resulting from defects in materials, TSMC’s workmanship, TSMC Manufacturing Process Technology , (iv) having a consecutive two-month failure rate equal to or in excess of 1.0% of total number of Wafers delivered to IDT during applicable period (“Threshold Failure Rate”), and (v) not caused by any Exclusive Event (as defined in Section 8.3). The Threshold Failure Rate shall apply to all Wafers unless IDT and TSMC have agreed in writing to an alternative metric for a particular Lot. 
1.10    “Gross Die per Wafer” means the total quantity of Die candidates on each Wafer, whether or not the Die is operational when the Wafer has completed the manufacturing process.
1.11    “IDT Manufacturing Process Technology” means (a) the IDT-proprietary manufacturing process Technology applicable to the manufacture of the current Products as further described in the Transfer Plan or otherwise provided by IDT to TSMC during the term of this Agreement. and (b) any Improvements to such Technology made by IDT.
1.12    “Improvements” means with respect to any Technology, all discoveries, innovations, improvements, enhancements, derivative works, or modifications of or to such Technology 
1.13    “Intellectual Property Rights” shall mean rights in and to all (a) Patents, (b) copyrights, (c) unpatented information, trade secrets, data, or materials, (d) mask work rights, and (e) any other intellectual or other proprietary rights of any kind now known or hereafter recognized in any jurisdiction, but not for purposes of this Agreement, any trademarks, service marks, trade names, trade dress, domain names and similar rights.





1.14    “Lot” means a group of Wafers which are processed simultaneously.  Each Lot will be assigned a specific alpha/numeric identification that distinguishes it from any other group that contains the same type of Die so that each Lot can be separately identified.
1.15    “Lead Time” shall mean the time between the date an order is accepted by TSMC and the date the Wafers are made available for shipment by TSMC.  The Lead Time will vary depending on the Wafers ordered and will be established in advance by mutual agreement of the parties.  
1.16    “Minimum Yield” means, with respect to a particular Wafer, the minimum acceptable Yield for such Wafer as set forth in the applicable Specifications.  If the Minimum Yield is not set forth in the applicable Specifications, the Minimum Yield shall be set to sixty-five percent (65%) of the average Yield of the first three hundred (300) completed Wafers for such Product. 
1.17    "Net Die per Wafer" means the total quantity of Die on a Wafer that pass the Probe Program applicable to that Wafer.
1.18    “Patent” means U.S. and foreign patents and patent applications claiming any inventions or discoveries made, developed, conceived, or reduced to practice, including all divisions, substitutions, continuations, continuations-in-part, and any reissues, re-examinations and extensions thereof.
1.19    "Probe Program" means the specific set of electrical and mechanical tests provided by IDT to perform Wafer level test respecting the conformance of Wafers to the applicable Specifications.
1.20    “Product” shall mean certain specific IDT-proprietary integrated circuit devices to be manufactured as Dies on Wafers by TSMC.
1.21    “Qualification Plan” shall mean the qualification tests and schedules to be agreed upon by the parties under which a Qualified Process is established and tested at the TSMC Facilities and the Wafers are manufactured using the Qualified Process to meet the Specifications, as may be amended by the parties for each Qualified Process.
1.22    “Qualification” or “Qualified” shall mean the mutual determination that the Wafers meet the Specifications in accordance with the Qualification Plan.
1.23    “Qualified Process” shall mean the Wafer manufacturing processes used at the TSMC Facilities for production of Wafers and any other Wafer manufacturing process approved by the parties to produce Wafers on IDT’s behalf.
1.24    “Scrap” means any Wafer that either (a) is not in conformance with the requirements of this Agreement for Wafers to be sold to IDT, (b) that IDT notifies TSMC may be scrapped if it has been in the Wafer Bank for within fifteen (15) months from creation, or (c) has been in the Wafer Bank for more than fifteen (15) months from creation.
1.25    “Specifications” shall mean the IDT specifications that are agreed upon by TSMC, including design and performance specifications, Yield requirements and reliability metrics, for each Product.  The initial Specifications are attached hereto as Exhibit A.
1.26    “Technology” means any and all technical information, specifications, drawings, records, documentation, works of authorship or other creative works, ideas, algorithms, models, databases, ciphers/





keys, systems architecture, network protocols, research, development, and manufacturing information, software (including object code and source code), application programming interfaces (APIs), innovations, logic designs, circuit designs, technical data, manufacturing processes, recipes and methods.
1.27    “Transfer Plan” means the plan agreed upon by the parties in writing and attached hereto as Exhibit C describing the process by which IDT will provide TSMC access to the applicable IDT Process Technology for modification and implementation by the parties at the applicable TSMC Facilities to manufacture Wafers for IDT.
1.28    “TSMC Direct Competitor” means a company that derives a significant portion of its annual revenue from performing wafer foundry services.
1.29    “TSMC Facilities” means the TSMC physical manufacturing and managed facilities located at Fab 3 in Hsin-chu, Fab 8 in Hsin-chu, and such other facilities owned or controlled by TSMC as may be qualified by IDT (and specifically approved by IDT in writing) to produce Wafers for IDT.
1.30    “TSMC Manufacturing Process Technology” shall mean (a) a semiconductor manufacturing method or technology conceived, developed, licensed or owned by TSMC either independently or jointly with a third party and (b) any Improvements to such Technology made by TSMC.
1.31    Wafer Bank” means an inventory of Wafers manufactured by TSMC and held in inventory prior to metallization for release and purchase by IDT in accordance with the terms and conditions of this Agreement.
1.32    “Wafers” shall mean the direct material substrate (raw material) which as a result of the semiconductor fabrication process are incrementally transformed to consist of several operational Dies in unpackaged form for the Products to be manufactured by TSMC using the Qualified Processes. 
1.33    “Yield” means the percentage represented by Net Die per Wafer divided by Gross Die per Wafer.
2.    PROCESS IMPLEMENTATION AND QUALIFICATION
2.1    IDT Process Technology Transfer.  IDT will deliver to TSMC the IDT Process Technology to be implemented at the TSMC Facilities in accordance with the provisions of the Transfer Plan.  Without limiting the foregoing, it is the intention of IDT to transfer all masks for .35 micron and larger geometry  IDT Process Technologies from IDT Fab 4 to a TSMC Facility solely for use in the manufacture of Wafers by TSMC.  With respect to 0.18 micron and below IDT Manufacturing Process Technologies that are transferred to TSMC Facilities, TSMC will create new masks at IDT’s expense.  For masks provided by IDT, TSMC may use such masks or at TSMC’s sole discretion and expense choose to build new masks, except that if any single mask provided by IDT is defective upon receipt by TSMC during the process transfer time period, then TSMC shall build a new mask to replace the defective mask at IDT’s expense with IDT’s approval. Both IDT and TSMC will contribute necessary technical resources and personnel for successfully implementing the Transfer Plan and incorporating the IDT Process Technology, as modified per the Transfer Plan, at the TSMC Facilities within the applicable schedule set forth in the Transfer Plan.
2.2    Engineering Wafer Run.  In accordance with the mutually agreed Specifications and Qualification Plan for a particular Product and pricing terms, TSMC will fabricate Engineering Wafers for such Product based on the applicable process Technology at the designated TSMC Facility and deliver the 





Engineering Wafers to IDT.
2.3    Evaluation.  IDT will evaluate the Engineering Wafers provided by TSMC in accordance with the applicable Qualification Plan.  If the Engineering Wafers meet the Specifications, the manufacturing process at the designated TSMC Facility shall be deemed a “Qualified Process” for the applicable Product.  
2.4    Engineering Changes.  
(a)    TSMC will give IDT prior written notice of any Engineering Change, and will supply engineering and experimental data supporting such change and obtain IDT’s written approval, all in accordance with TSMC’s standard Engineering Change Notice procedure.
(b)    In addition, IDT may also request, in writing, that TSMC incorporate Engineering Changes into Wafers or the manufacturing processes to manufacture Wafers.  Such requests will include a description of the proposed change reasonably sufficient to permit TSMC to evaluate the feasibility of making such Engineering Changes.  TSMC will use commercially reasonable efforts to, within five (5) business days, advise IDT in writing of the feasibility of the requested Engineering Change and the terms and conditions under which TSMC would achieve the requested Engineering Change. The requested Engineering Change would only be implemented after IDT and TSMC reach mutual agreement that such requested Engineering Change is warranted and feasible and on a plan to implement such requested Engineering Change.  If an Engineering Change, as determined by the parties, is required for safety or regulatory requirements, TSMC will immediately implement such Engineering Change according to the terms and conditions as mutually agreed upon by the parties in writing.  
2.5    Technical Assistance.  TSMC agrees to provide IDT with commercially reasonable technical assistance and advice on an ongoing as needed basis at no extra cost to IDT unless agreed to by IDT in writing.  Such technical assistance shall include providing reasonable information, failure analysis support, device engineering or other expertise needed to handle Product returns, field failure analysis, design support, and device engineering and process improvement and implementation support.
2.6    Tooling.  Tooling purchased or manufactured by TSMC and paid for by IDT shall become and remain the property of IDT, including all Intellectual Property Rights related thereto that is not created, owned or licensed by TSMC.  TSMC agrees that such tooling will be used by TSMC only for the benefit of IDT and shall be delivered to IDT upon request. TSMC agrees to provide IDT with a complete inventory of all such tooling upon written request.  All tooling shall be properly used subject to ordinary wear and tear, shall be maintained and/or repaired at TSMC’s expense and shall bear a label (in conspicuous letters so as to be readily seen and not readily removable or defaceable) indicating that such Tooling is the property of IDT.
3.    QUALITY MANUFACTURING AND REPORTING REQUIREMENTS
3.1    Quality Requirements. 
(a)    Without limiting any other provision set forth in this Agreement, TSMC will manufacture Wafers in compliance with the Specifications and, to the extent agreed in writing by TSMC, as well the following additional IDT specifications: (i) 9.1.QCC-4000, Quality System Requirements for Manufacturing Subcontractors, Material Companies and Services Group and (ii) 9.1.2.SOC-0601, Company Requirements for the Manufacture of Foundry Wafers.  IDT may adopt additional requirements 





from time to time and IDT will notify TSMC in advance regarding any such requirements, and to the extent agreed in writing by TSMC, such requirement may be included into a part of the Specifications.
(b)    At all times during the term of this Agreement, TSMC shall maintain certifications under ISO 9001, TS16949 and ISO 14001. Upon request by IDT, TSMC shall provide IDT with copies of the appropriate certificates of registration verifying TSMC’s compliance with the foregoing certifications.
3.2    Failure and Defect Reporting. The parties will notify each other in writing of any detected failure mechanisms and/or defects which are present, or which they suspect might be present, in completed Wafers.
3.3    Non-Conforming Wafers; Scrap Disposal.  TSMC shall have established, documented, and maintained procedures to ensure that Wafers that do not conform to the Specifications are prevented from unintended use or shipment to IDT and from potential unauthorized use by any third party. Nonconforming Wafers shall otherwise be held in a secure location until they can be promptly scrapped by TSMC. TSMC shall destroy and properly dispose of all Scrap or recycle in such a way in order to prevent any unauthorized sale of any Wafers, subject to IDT approval. TSMC will maintain Scrap procedures and will record all Wafers scrapped including Lot history, reason for scrap and IDT's approval for scrap. IDT shall have the right to audit the scrap procedures and to witness scrap of IDT's material with reasonable notice.
3.4    Business Continuity.  TSMC shall implement and maintain at all times during the term of this Agreement a business continuity program that is reasonably calculated to minimize the impact of potential interruptions on TSMC’s operations, including to the extent reasonable, as a result of force majeure events.  TSMC shall share details of its business continuity program with IDT upon IDT’s request.  In the actual event of a business interruption, TSMC shall use commercially reasonable efforts to implement the measures identified in its business continuity plan.  TSMC also agrees to keep IDT reasonably informed of the progress of any such undertakings.
3.5    Manufacturing Metrics.  TSMC agrees to provide reasonable customary manufacturing metrics to IDT including data applicable to Wafers as mutually agreed. In addition, TSMC agrees to provide reasonable raw data for these metrics such that the data could be calculated using IDT’s standard formulae, and to enable IDT to access this data from TSMC in real time.
3.6    Work In Process Reporting.  On a daily basis, TSMC will provide IDT with data feeds regarding with the work in process, including information such as the purchase order number, the Release Request number, Lot number, total number of process steps, number of process steps completed, process step name (provided that the process step name for Wafers at the Wafer Bank shall be “Wafer Bank”), total number of masking steps, number of masking steps completed, start date, expected ship date and committed ship date.  
3.7    Reliability Records and Data.  TSMC agrees to provide the following information relating to the quality or reliability of the Wafers and the quality systems used to comply with the required standards and specifications:
(a)    TSMC will maintain history records for all Lots during the term of this Agreement and for a period of five (5) years from the termination of this Agreement.  TSMC will provide IDT with access to all Lot history records, upon reasonable notice to TSMC, both during and after the term of this Agreement, and if mutually agreed in writing, TSMC will transfer all Lot history records to IDT.





(b)    TSMC agrees to provide reasonable reliability data which demonstrates the ability of the Qualified Processes used for all Wafers to meet the agreed-upon reliability criteria set forth in the applicable Specifications. Any exceptions to these criteria will be reviewed on a Product-by-Product basis.  IDT shall have the right to use reliability data concerning the Wafers for the purposes of preparing sales and promotional information concerning the Wafers for IDT’s customers, provided however that such reliability data will be transmitted subject to a non-disclosure agreement having terms and conditions no less restrictive than those terms with respect to confidentiality in this Agreement.  TSMC’s reliability testing methods and conditions shall be subject to the review of IDT, and shall be changed as mutually agreed in writing.
(c)    TSMC agrees to maintain sufficient documentation regarding all Wafers sold to IDT for five (5) years after the applicable shipment.  All Wafers shall be traceable to a unique Lot number assigned by TSMC.  Lot traceability for Wafers shall be maintained throughout the entire process from fabrication through verification testing, packing and shipment. Traceability and full history for Wafers shall include substrate vendor identification and lot number, quality control data, and process deviation notes.
(d)    Subject to TSMC’s reasonable security, confidentiality and personal conduct requirements, on at least seven (7) days prior written notice and the schedules and agenda as mutually agreed upon by the parties in writing, IDT may conduct an on-site inspection and audit of the process and manufacturing records relevant to the Wafers, provided that the audits will occur no more often than twice annually.  Upon prior notice to TSMC of at least thirty (30) days and with TSMC’s prior consent, such consent not to be unreasonably withheld, IDT may bring IDT customers to conduct on-site visits and inspection of the TSMC Facilities and applicable process and manufacturing records relevant to the Wafers, provided IDT and its customers have executed a non-disclosure agreement relating thereto with TSMC.
3.8    Process Control Information, On-Line Information Access. On an ongoing basis as reasonably requested by IDT, TSMC will provide IDT with process control information using a communication mechanism that is mutually agreed. Such information may include: process and electrical test Yield results, calibration schedules, environmental monitor information for air, gases and DI water, documentation of operator qualification and training, documentation of traceability, process verification information, and trouble report currently available from TSMC’s document control center in a format pursuant to TSMC’s standard document retention policy. IDT will have access to the foregoing information and reports and other relevant information.
4.    CAPACITY PLANNING AND ORDERING PROCESS
4.1    Manufacturing Relationship.  IDT agrees to purchase Wafers from TSMC throughout the term of this Agreement in accordance with the terms and conditions of this Agreement as may be ordered by IDT from time to time at its sole discretion.  Except for the right of first negotiation set forth in Section 4.2, and subject to TSMC’s Intellectual Property Rights including trademarks, this Agreement shall not be construed to limit in any way IDT’s rights to contract with other parties to manufacture, assemble, test, design or develop products, or to engage in such activities itself.  
4.2    Right of First Negotiation.  During the term of this Agreement, TSMC shall have a right of first negotiation with respect to all future business related to the manufacture of wafers for IDT.  Notwithstanding the foregoing, TSMC shall have no right of first negotiation with respect to any future business related to the manufacture of wafers for IDT if (i) IDT previously granted such business to a third party or (ii) the manufacture of wafers requires the reuse of Technology that is only available at the facilities of an existing third party supplier and TSMC is unable to provide a solution that is compatible 





therewith.
4.3    Forecasts and Capacity Commitment.  In July of each year, IDT and TSMC will agree to a twelve (12) month demand support plan by technology and by TSMC fab for the subsequent year (the “Annual Capacity Support Plan”).  By the fifteen (15th) day of each calendar month during the term of this Agreement, IDT will provide to TSMC, in writing, a rolling 1 year forecast by quarter for IDT’s volume requirements for Wafers by technology and by TSMC fab (a “Forecast”), with each Forecast covering the one (1) year period commencing at the beginning of the immediately subsequent month.  The Forecast will be divided into quarterly segments, wherein the first quarter of the Forecast will be binding to IDT, the second quarter will be subject to IDT’s commercially reasonable efforts to follow through with orders, and the third and fourth quarters of the Forecast will be considered budgetary.  TSMC may only reject a Forecast in writing within ten (10) days of receipt thereof if:
(a)    The forecast has an increase over the last accepted forecast at the same technology and fab of greater than 5% for the first quarter period or; 
(b)    The forecast has an increase over the last accepted forecast at the same technology and fab of greater than 15% for the second quarter period or;
(c)    The forecast has an increase over the last accepted forecast at the same technology and fab of greater than 20% for the third and forth quarter or;
(d)    The total one (1) year forecast is greater than greatest of the last accepted forecast or 36,000 wafers per quarter.
(e)    For any one month during the first six (6) months of the forecast, IDT’s forecast is equivalent to or greater than one hundred forty percent (140%) of Annual Capacity Support Plan for that given month at the same technology and same fab, This condition (e) shall apply until such time as IDT has sufficiently qualified a second .18 micron fab facility at TSMC at which time the parties shall agree on an increase in the planning capacity.
Any forecast not specifically rejected in writing by TSMC during such period shall be deemed accepted by TSMC.  The accepted  forecast   shall constitute TSMC’s minimum supply commitment for the applicable period, provided that the volumes in such accepted forecast is equivalent to or less than fourteen  thousand (14,000) pieces of 8-inch wafers per calendar month and thirty-six thousand (36,000) pieces of 8-inch wafers per calendar quarter (the “TSMC Maximum Capacity Support”).   The foregoing Forecast and TSMC Maximum Capacity Support shall only apply to the Products defined in Exhibit B. 
4.4    Cycle Times.
(a)    TSMC shall use commercially reasonable efforts to ensure the following: (i) Wafers released from the Wafer Bank in accordance with Section 4.6(a) below will be processed at 1.0 days per masking layer provided the daily release quantity does not exceed 500 wafers per day in Fab 8 and 300 wafers per day in Fab 3 and (ii) non-bank Wafers shall be processed at 1.3 days per masking layer for the Products defined in Exhibit B Section 1.3; and at 1.4 days per masking layer for the Products defined in Exhibit B Section 1.4;1.5 and 1.6.
(b)    Notwithstanding the foregoing, at each TSMC Facility qualified for running IDT products utilizing wafer banking, TSMC reserve three (3) “hot lots” for Engineering Wafers to be 





processed at a maximum of 0.8 days per masking layer, for no additional expediting fee.   
(c)     The foregoing cycle time in this Section 4.4 shall only apply to the Products defined in Exhibit B.
4.5    Purchase Orders.  
(a)    IDT will purchase Wafers from TSMC pursuant to purchase orders issued by IDT referencing this Agreement that specify the purchase order number, type and quantity of Wafers ordered, the place(s) of delivery, and required delivery date(s).  IDT may issue either individual purchase orders or blanket purchase orders.  Purchase orders may take the form of electronic submissions in a mutually-acceptable format so long as they contain the same information specified above for purchase orders, even if such submissions may not be referred to specifically as “purchase orders” when transmitted.  
(b)    TSMC shall provide written order acknowledgements by confirmed facsimile, electronic transmission, or other mutually-agreed means within three (3) Business Days of receipt of purchase orders, and any purchase order not specifically rejected in writing by TSMC during such period shall be deemed accepted.  
(c)    TSMC shall accept any purchase order submitted by IDT to the extent that such purchase order is consistent with the Forecast (plus any agreed upon upside support), Lead Times, and minimum Lot size requirements.  The minimum starting Lot size for production Wafers is twenty-five (25) Wafers.  The minimum starting Lot size for Engineering Wafers shall be twelve (12) Wafers. From time to time both parties will meet and discuss minimum starting lot size for specific bank products.
(d)    IDT will provide final Product definitions no later than one (1) week prior to the start date of production for such Product.  In the event that IDT fails to provide final Wafer definitions by such date, then the parties shall mutually agree upon a revised production schedule for such Wafer.   
(e)    In the event of any discrepancy between a purchase order or sales acknowledgment form or other notice and the terms of this Agreement, this Agreement shall prevail and any different or additional terms shall be deemed rejected.












4.6    Wafer Bank. 
(a)    Blanket Purchase Orders.  TSMC agrees to maintain the Wafer Bank in the amounts requested by IDT pursuant to written purchase orders referencing this Agreement that specify the type and 





quantity of Wafers to placed in the Wafer Bank.  TSMC agrees to start Wafers as requested and process to a mutually-agreed Wafer Bank process step to hold for future Release Requests (as defined below).  Notwithstanding the foregoing, the total of number of Wafers in the Wafer Bank during any calendar quarter shall be equal to or less than fifty percent (50%) of the volume of Wafers set forth in the Current Forecast for the following quarter as requested by IDT for each TSMC Facility.  The Wafer Bank will be arranged such that inventory carried in the Wafer Bank will be deemed inventory of TSMC for financial accounting purposes.  
(b)    Release Requests.  IDT may from time to time submit written requests to TSMC that specify the type and quantity of Wafers to be released from the Wafer Bank and further processing instructions (the “Release Requests”).  TSMC will release the requested Wafers within twenty-four (24) hours of receipt of a Release Request, provided that such Release Request is received by TSMC during normal business hours on a Business Day.  The minimum Lot size for a Release Request is five (5) Wafers for production releases or two (2). Wafers for engineering releases.  Wafers released from the Wafer Bank will be invoiced at the current production pricing on the expected date of shipment. 
(c)    Unused Inventory.  After Wafers have been in the Wafer Bank for fifteen (15) months, IDT may then elect to either (i) instruct TSMC to designate such Wafers as Scrap, in which case TSMC will invoice IDT fifty percent (50%) of the then-current price of such Wafers, or (ii) submit a Release Request for such Wafers in accordance with Section 4.6 (b).
4.7    Cancellations.  IDT may cancel any purchase order or portion thereof for Wafers upon written notice to TSMC prior to the date of shipment by TSMC.  Where notice of cancellation is given prior to the start of production of the ordered Wafers, IDT will not liable for any cancellations charge.  Where notice of cancellation is given after the start of production of the ordered Wafers, IDT agrees in such instance to pay TSMC as TSMC’s sole and exclusive remedy and IDT’s sole and exclusive obligation for such cancellation all verified, a prorated price of Wafers based upon the layers completed.
4.8    Reschedules.  IDT may reschedule the delivery of any purchase order or portion thereof for Wafers, without charge, upon notice to TSMC prior to the start of production of the ordered Wafers.  
4.9    Materials/Capacity Shortage. If the materials or components used by TSMC to manufacture the Wafers are in short supply or if TSMC’s production capacity is constrained such that TSMC is unable to completely fulfill IDT’s then current Wafer forecast and accepted purchase orders, TSMC will provide timely notice thereof to IDT, which notice will include the expected duration of the shortage or constrained capacity and the impact on the Forecast.  For IDT production orders above thirty-six 36,000 pieces of 8-inch wafer per quarter (“quarter” specified in this Section 4.9 shall mean the three consecutive month period during any calendar year commencing on the first day of each of the months of January, April, July and October), TSMC will allocate available materials for production of Wafers for IDT at the minimum level of twelve thousand 12,000 pieces of 8-inch wafer per month (“month” specified in this Section 4.9 shall mean a calendar month) and will use commercially reasonable efforts to support any previously accepted up-side in a manner that is consistent with TSMC’s top fifteen (15) contract customers during the same time period. 
4.10    Reticle Holds.  TSMC agrees to retain reticles for Wafers for at least eighteen (18) months following the last applicable Wafer delivery for the applicable reticle.  At the end of such eighteen (18) month period, TSMC may notify IDT in writing that the reticle has not been used during such period.  The parties agree to discuss in such event whether IDT anticipates any further Wafer orders requiring use of such reticle.  If IDT in good faith does anticipate future orders, or is required by a commitment to a customer to maintain the availability of a Product requiring such reticle, then TSMC shall continue to hold 





and maintain such reticle.  If IDT agrees in writing that the reticle is no longer needed to produce Wafers, TSMC agrees to deliver such reticle to IDT or destroy such reticle, at IDT’s direction.
5.    DELIVERY
5.1    Packaging.  TSMC will mark and package the Wafers for shipment to IDT in accordance with the mutually agreed specifications at TSMC’s expense.  If packaging is not specified, then the following terms shall apply:  All Wafers shipped by TSMC pursuant to this Agreement shall be packaged, marked, and otherwise prepared for shipment in a manner that is (a) in accordance with good commercial practice; and (b) adequate to ensure safe arrival of the Wafers at IDT’s requested destination.
5.2    Delivery.  TSMC will use commercially reasonable efforts to cooperate with IDT to determine delivery logistics that will ensure safe and timely delivery of Wafers to IDT.  TSMC will deliver the Wafers EXW (Ex Works Incoterms 2000) TSMC’s factory.  Title and risk of loss to the Wafers shall pass to IDT upon delivery to a carrier or forwarder. TSMC shall deliver the Wafers to IDT with ninety-six  percent (96%) on time delivery (“OTD”).  OTD shall means delivery up to seven (7) days before but zero (0) days after the scheduled delivery date. If TSMC wants to make shipments prior to the requested ship date, TSMC must first receive approval to do so in writing from IDT.   TSMC agrees to notify IDT in writing as soon as possible upon learning of any circumstances that may delay delivery of Wafer to IDT.  In the event that TSMC is unable to prevent a delay and thus is unable to make timely delivery of an order through no fault of IDT, then IDT shall have the option to either (a) cancel the affected order for which costs will be settled between the parties, or (b) accept late delivery of the Wafer and TSMC will make delivery as soon as possible, utilizing an expedited shipping method at no additional cost to IDT.  Time is of the essence for all delivery obligations under this Agreement.  If TSMC wants to make partial lot shipments, TSMC must first receive approval to do so in writing from IDT
5.3    Wafer Acceptance Testing by IDT.  TSMC will certify to IDT with each shipment that the Wafers contained in the shipment have successfully passed the applicable Probe Program and comply with the applicable Specifications.  Acceptance testing of Wafers delivered to IDT or a third party designated by IDT may be performed by IDT following receipt.  If IDT rejects any Wafers or determines that a Wafer has a different Net Die per Wafer than certified by TSMC, then IDT and TSMC will confer and determine the reason for the rejection or the inaccurate count of Net Die per Wafer.  TSMC will immediately exercise its commercially reasonable efforts to develop and implement a corrective action plan for any errors, including manufacturing errors or defects identified in its systems.
5.4    Wafer Acceptance Testing by TSMC.
(a)    Outgoing Visual Inspection.  TSMC will perform an outgoing visual inspection on all wafers manufactured by TSMC prior to shipment to IDT.  TSMC will certify that all such wafers meet TSMC’s then applicable outgoing visual defect specification.
(b)    If TSMC detects any significant fabrication-related defects in any Wafers, TSMC with IDT assistance will, use commercially reasonable efforts to perform failure analysis, and provide a corrective action plan to correct the failure mechanisms and/or defects. 
(c)    Results from TSMC testing processes will be accessible and available to IDT for review. These results must be available in electronic form at the conclusion of each test Lot and must conform to the summary structure agreed upon by the parties.





5.5    Minimum Yields.  A standard Yield will be established and agreed to by the parties for each Product based on the average Yield of the first three hundred (300) Wafers of each Product manufactured using Qualified Processes and passing all production tests. Any Wafer manufactured by TSMC that yields less than sixty five percent (65%) of the standard Yield for such Product shall, if sorted by TSMC, be scrapped, or, if sorted or if blind built and final tested by IDT, be deemed defective and returnable for replacement pursuant to Section 8.3 below.
(a)    Within 6 months of successful Product qualification, it is expected that TSMC will meet or exceed the yield that IDT experiences.  If this is not the case, or if in the future the yield is not consistent with the yield of current products manufactured by IDT, TSMC will support IDT in determining the root cause and implement process fixes as needed.  
5.6    Scribeline Electrical Test.  Unless otherwise stated in the Specifications for a particular Product, and without limiting any other testing and acceptance procedures, all Wafers manufactured by TSMC will be measured at five (5) test sites distributed across each Wafer.  Both parties shall agree on a set of wafer acceptance test (“WAT”) parameters and limits.  Any Wafer failing more than two (2) sites on any given WAT parameter shall be scrapped by TSMC, at TSMC’s sole cost and expense.  
5.7    Maverick Lot/Wafer Program. TSMC and IDT will work together to implement a program to eliminate shipment of any non standard material, regardless of the wafer yield requirement of Sec 5.5.
6.    PRICING, COST ALLOCATION AND PAYMENT
6.1    Pre-Production Cost Allocation.  Except as otherwise set forth herein, TSMC shall bear all costs associated with establishing facilities capable of implementing Qualified Processes and producing Wafers.
(a)    Non-Recurring Engineering Payment.  In connection with the accomplishment of the Transfer Plan, IDT agrees to make a one-time non-recurring engineering (“NRE”) payment to TSMC as specifically set forth in the Transfer Plan.  
(b)    Mask Costs.  For the avoidance of doubt, mask costs are not included in the NRE payment.  The pricing for masks purchased for the manufacture of Products is set forth in Exhibit B attached hereto.
6.2    Wafer Pricing
(a)    Pricing.  The pricing for all Products and associated mask sets purchased under this Agreement is set forth in Exhibit B attached hereto, and such Product pricing will be in effect from the Effective Date until the fifth (5th) anniversary of the Effective Date (the “Initial Pricing Term”), unless such pricing is earlier adjusted by the mutual agreement of the parties.  Separate pricing will apply and be mutually agreed upon in advance in writing by the parties for any Products run on 150mm or 300mm Wafers.  The pricing set forth in Exhibit B includes all manufacturing and operating expenses, excluding freight costs, and IDT shall not be separately charged for any costs or expenses for any raw materials, labor, equipment expenses, supplies, depreciation, overhead, or any other special requirements unless an exception has been agreed to in writing in advance by IDT.  For the second half of the term of this agreement and any subsequent renewed term, TSMC and IDT will negotiate in good faith for wafer pricing as commercially reasonable in a competitive market. However, except as stipulated in Section 6.2 (b), in 





no event shall subsequently negotiated pricing per Product be higher than the previously agreed upon prices.  


(b)    Pricing Reviews.  For the duration of the 5-year pricing offered by TSMC, TSMC shall have the right to meet on each anniversary of the effective date to review pricing efficiencies.  In the event of the occurrence of a material event which TSMC reasonably believes causes severe hardship to TSMC, TSMC may request to meet in good faith with IDT and, with appropriate executive-level involvement, to consider and/or negotiate a commercially reasonable adjustment to the prices set forth in this Agreement.  Neither party shall have any obligation to the other party with regard to the terms set forth in this Section if the parties fail to reach a mutually acceptable agreement after good faith negotiation (but for the avoidance of doubt, the parties' obligations under the remainder of this Agreement shall continue in full force and effect). 
6.3    Shipping Costs.  IDT shall bear, in addition to the Wafer pricing agreed upon by the parties, the amount of any freight, insurance, handling and other duties levied on the shipment of Wafers.
6.4    Invoicing and Payment.  For each shipment of Wafers to IDT, TSMC shall invoice IDT on or after the delivery date of such Wafers.  TSMC’s invoices shall set forth the amounts due from IDT for such shipment and shall contain sufficient detail to allow IDT to determine the accuracy of the amounts billed.  Payment by IDT shall be made in U.S. Dollars through wire transfer in cash within thirty (30) days after invoice date.  
6.5    Taxes.  Unless otherwise explicitly stated, the prices specified in this Agreement are exclusive of any sales, use, excise, royalty, consumption or similar taxes, and of any export and import duties, which may be levied upon or collectible by TSMC as a result of the sale or shipment of the products to IDT or its customers.  IDT agrees to pay and otherwise be fully responsible for any such taxes and duties, unless in lieu thereof IDT provides TSMC with an exemption certificate acceptable to the relevant governmental authorities.
7.    AUDIT AND INSPECTION
7.1    Site Visits. IDT may send its employees or customers, who have executed a non-disclosure agreement related to site visits specified in this Section, at any time upon at least seven (7) days prior written notice and according to the schedules and agenda as mutually agreed upon by the parties to visit TSMC Facilities to inspect fabrication of Wafers and conduct other activities contemplated by this Agreement.  Such visits shall be conducted during TSMC’s normal working hours.  While visiting TSMC’s facilities, each visitor shall at all times fully comply with TSMC’s plant rules and regulations as well as all reasonable instructions that may be issued by TSMC employees and personnel accompanying any such visitor.  TSMC agrees to grant these employees reasonable access the factory and support facilities.  At the reasonable request of IDT, TSMC will assist IDT in obtaining the appropriate visas for any IDT employees to participate in a site visit.  IDT will have the right to audit the TSMC Facilities upon at least seven (7) days prior written notice during normal business hours of the applicable TSMC Facility, subject to the requirements of this Section 7.1.  
7.2    Program Reviews. IDT and TSMC agree to participate in regular monthly program reviews by a program review committee established by IDT and TSMC to focus on operational details of the installation, qualification, and ongoing performance of the manufacturing processes.





7.3    Business Review Meetings.  The parties will plan and schedule business reviews at least quarterly.  The review will focus on current and forecasted business activities, feedback on performance and factory metrics, key improvement programs and activities focused on enabling the relationship between the parties and will review the status of open issues and action items. 
8.    LIMITED WARRANTY; WARRANTY DISCLAIMER
8.1    Limited Warranty.  TSMC represents and warrants that all Wafers: (a) shall be clear of any liens, restrictions, encumbrances, and other claims; (b) shall be manufactured in accordance with applicable laws; and (c) for a period of thirty-six (36) months from the delivery date , for those Wafers for which IDT’s customer requires such 36-month  period, or for twenty-four (24) months for those Wafers for which IDT’s customer requires such 24-month period, and otherwise for twelve (12) months from the delivery date  (as for given Wafers, the “Warranty Period”), that such Wafers shall meet the applicable Specifications and shall be free from any defects in material and workmanship under normal use. All Engineering Wafers are delivered “AS IS,” without any warranty of any kind.
8.2    Remedies for Breach of Warranty.  If, during any Warranty Period, any Wafers purchased hereunder do not meet the warranties specified herein without involving any Exclusive Event (as defined in Section 8.3 below), IDT may, at IDT's option (i) require TSMC to replace or correct at no cost to IDT any defective or nonconforming Wafers pursuant to the Product return procedures set forth in Section 8.3 below, or (ii) return any nonconforming Wafers to TSMC at TSMC's expense for credit of the amounts invoiced to IDT by TSMC and shipping costs thereof.  TSMC shall bear all transportation costs incurred in connection with the replacement or repair of defective Products.  The warranty specified in Sections 8.1 through 8.3 constitutes TSMC's exclusive liability and IDT's exclusive remedy for any non-conforming Wafers or for any defects in material or workmanship of the Wafers. In addition to TSMC’s obligation to replace or correct wafers at no cost to IDT, TSMC shall be responsible for reimbursement in the form of credit, for one half (1/2) of IDT’s reasonable out of pocket costs and expenses incurred in connection with a Warranty claim, including but not limited to rework and assembly costs, but IN NO EVENT SHALL TSMC’S LIABILITY HEREUNDER EXCEED THE SUM OF FIVE HUNDRED THOUSAND US DOLLARS (USD $500,000) PER CALENDAR YEAR. 
8.3    Return of Wafers. In the event that IDT elects to return nonconforming Wafers to TSMC, IDT will notify TSMC of the nonconformance and of IDT’s intent to return the nonconforming Wafers.  Upon receipt of IDT’s notification to TSMC of the nonconformance, if TSMC determines that such nonconforming Wafers contain defects which are not due to any event caused by IDT or any third party not authorized by TSMC including but not limited to, accident, abuse, misuse, neglect, improper installation, handling or packing, repair or alteration by IDT , IDT’s representative or agent or any third party not authorized by TSMC or by improper testing or usage contrary to any instructions issued by TSMC (the “Exclusive Event”), TSMC will deliver replacement Wafers according to mutually agreed schedules, and will provide all the assistance and authorization required to return the nonconforming Wafers to TSMC according to mutually agreed schedules. The nonconforming Wafers will be returned to TSMC at TSMC’s expense and TSMC will be liable and will assume all title and responsibility for all Wafers during return transport, including liability caused by hazardous substance releases during such transport. TSMC will immediately investigate to determine the cause of the nonconformance and will promptly notify IDT in writing of its findings.
8.4    Additional Warranties.  In addition, TSMC and IDT make the following representations and warranties:
(a)     Each party has the right to enter into this Agreement and its performance of this 





Agreement will comply, at its own expense, with the terms of any contract, obligation, law, regulation or ordinance to which it is or becomes subject; and
(b)    No claim, lien, or action exists or is threatened against either party that would interfere with the applicable party’s manufacture, use or sale of the Products. 
(c)    None of the Products contain nor are any of the Products manufactured using ozone depleting substances such as halons, chlorofluorocarbons, hydrochlorofluorocarbons, methyl chloroform and carbon tetrachloride as defined by the Montreal Protocol.  TSMC shall comply with all requirements of applicable laws relating to restrictions on use of lead and other hazardous materials in electronic Products (including without limitation, the RoHS and WEEE directives).
8.5    No Waiver. No inspection or acceptance, approval or acquiescence by IDT with respect to the Wafers shall relieve TSMC from any portion of its warranty obligation nor will waiver by IDT of any specification requirement for one or more items constitute a waiver of such requirements for remaining items unless expressly agreed by IDT in writing.
8.6    Disclaimer.  EXCEPT AS EXPRESSLY PROVIDED IN THIS SECTION 8, TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, TSMC EXPRESSLY DISCLAIMS ALL WARRANTIES AND CONDITIONS REGARDING THE WAFERS PROVIDED HEREUNDER, WHETHER EXPRESS, IMPLIED OR STATUTORY, AND INCLUDING BUT NOT LIMITED TO ALL WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE.  THE REMEDIES PROVIDED IN THIS SECTION 8 SHALL CONSTITUTE THE SOLE AND EXCLUSIVE REMEDY WITH RESPECT TO BREACH OF WARRANTY.
9.     EPIDEMIC FAILURE 
9.1    Affected Product.  Upon the occurrence of an Epidemic Failure, the remedies of Sections 9.2 and 9.3 shall apply to the entire Product(s) affected or potentially affected by the same root cause failure (“Affected Product”) as so identified pursuant to Section 9.2. For clarification purpose, the parties shall discuss in good faith to identify and screen out whether the aforementioned Affected Product shall be applicable to the level and scope of affected Lot or Wafer or Die.
9.2    Failure Analysis; Corrective Action Program.  In the event of a suspected Epidemic Failure, IDT shall promptly notify TSMC in writing, and provide, if known and as may then exist, a description of the failure, and the suspected Lot numbers, serial numbers or other identifiers, and delivery dates, of the Affected Product.  IDT shall also deliver or make available to TSMC samples of the failed Wafers for testing and analysis.  Upon receipt of such Wafers from IDT, TSMC shall promptly provide its preliminary findings regarding the cause of the failure.  The parties shall cooperate and work together to determine the root cause.  Thereafter, TSMC shall promptly provide the results of its root cause analysis, its proposed plan for the identification of and the repair and/or replacement of the Affected Product which may be affected Lot or affected Wafer or affected Die, and such other appropriate information. TSMC shall recommend a corrective action program, subject to IDT’s written approval, that identifies the Affected Product for repair or replacement, and minimizes disruption to the end user. Upon receipt of IDT’s written approval, TSMC shall implement the corrective action program.
9.3    Remedy.  Upon the occurrence of an Epidemic Failure, TSMC shall: (1) at IDT's option: (i) either repair and/or replace the Affected  Product at no cost to IDT, or (ii) provide a credit to IDT in an amount equal to the cost to IDT for qualified replacement of Product acceptable to IDT; and (2) credit IDT for all necessary rework, assembly, labor, equipment and processing costs reasonably incurred by IDT or 





third parties in the implementation of the corrective action program, including reasonable test procedures, test equipment, the testing of Wafers, reasonable freight, transportation, customs, duties, insurance, storage, handling and other necessary incidental shipping costs incurred by IDT in connection with the repair and/or replacement of the Affected Product .  TSMC’S ANNUAL MAXIMUM LIABILITY TO IDT WITH RESPECT TO EPIDEMIC FAILURES SHALL BE AS FOLLOWS: THE AMOUNT OF FIVE MILLION US DOLLARS (USD 5,000,000) DURING THE FIRST 12 MONTHS AFTER THE EFFECTIVE DATE, AND THE AMOUNT OF FIVE MILLION US DOLLARS (USD 5,000,000) DURING THE NEXT 12 MONTH PERIOD, AND THE GREATER OF FIVE MILLION US DOLLARS (USD 5,000,000) OR THE SUM OF TWENTY PERCENT (20%) OF THE AGGREGATE PAYMENTS MADE TO TSMC BY IDT OR MADE ON BEHALF OF IDT DURING THE PRIOR CONTRACT YEAR FOR EACH CONTRACT YEAR THEREAFTER. THE REMEDIES IN THIS SECTION 9 CONSTITUTE THE SOLE AND EXCLUSIVE REMEDY WITH RESPECT TO EPIDEMIC FAILURE.


10.    INDEMNIFICATION
10.1    IDT Indemnity.  Except as provided for in Section 10.2 below, IDT shall, at its own expense, indemnify, defend and hold TSMC harmless from and against any liabilities, losses, damages, costs or expenses, including reasonable attorneys’ fees, arising from any third party action, claim, suit or proceeding alleging infringement or misappropriation of such third party’s Intellectual Property Rights only to the extent arising from TSMC making Wafers for IDT in compliance with any IDT Product designs or use of any IDT Manufacturing Process Technology, or TSMC’s compliance with or implementation of any of IDT’s specific  instructions if such claim, suit or proceeding would not have arisen but for such compliance with IDT’s specific instructions and/or IDT’s Product designs, provided that TSMC (a) gives IDT prompt written notice of any such claim, (b) gives IDT through counsel of its choice, sole control of the defense or settlement of such claim; (c) gives IDT all necessary information, assistance and authority to defend such claim, at IDT’s request and reasonable expense; and (d) IDT shall not be responsible for any settlement made by TSMC without IDT's written permission. 
10.2    TSMC Indemnity.  Except as provided for in Section 10.1, TSMC shall, at its own expense, indemnify, defend and hold IDT harmless from and against any liabilities, losses, damages, costs or expenses, including reasonable attorneys’ fees, arising from any third party action, claim, suit or proceeding alleging infringement or misappropriation of such third party’s Intellectual Property Rights only to the extent arising from use of TSMC Manufacturing Process Technology for manufacturing the applicable Wafers; provided that IDT (a) gives TSMC prompt written  notice of any such claim, (b) gives TSMC through counsel of its choice, sole control of the defense or settlement of such claim; (c) gives TSMC all necessary information, assistance and authority to defend such claim, at TSMC’s request and reasonable expense; and (d) TSMC shall not be responsible for any settlement made by IDT without TSMC's written permission. If the use and sale of any of the Wafers or Products is prohibited by court order as a result of a suit within the scope of this Section 10.2, TSMC, at no expense to IDT, will, at TSMC’s option, (a) obtain for IDT the right to use and sell the Wafers and Products or (b) substitute an equivalent method for manufacturing the Wafers and Products which are acceptable to and qualified by IDT or (c) if neither of the foregoing is possible on commercially reasonable terms,  then TSMC shall credit IDT an amount equivalent to the payments actually made by IDT to TSMC for the affected Wafers or Products. 
10.3    Order By Law.  Notwithstanding the foregoing, IDT also agrees that if TSMC is required by law to respond as a third party to any formal discovery request in a proceeding or suit involving a claim arising solely from IDT’s Product designs or any IDT Manufacturing Process Technology by any judicial 





or administrative authority or agent who has competent jurisdiction over disputes related to the Product, IDT shall indemnify and hold TSMC harmless from and against any and all actual expenses, including reasonable attorneys’ fees and costs, reasonably incurred by TSMC in responding to such request(s).  In such event, TSMC shall give IDT a reasonably prompt written notice of the discovery requests and TSMC shall be represented by counsel of its choice.  IDT agrees not to sue TSMC in connection with TSMC's provision of information pursuant to and in compliance with the procedures set forth in the foregoing.
10.4    Process for Alleged Infringement to Products.  If any Product is alleged to infringe any Intellectual Property Rights of a third party for reasons attributable to IDT, the parties will discuss in good faith and agree upon certain necessary measures to deal with such allegation. If the parties are unable to come to aforementioned agreement, they will refer resolution of the issue to the Senior Management Representatives. For the avoidance of doubt in the event that IDT directs TSMC to continue the manufacture of Wafers affected by such claim, IDT shall indemnify and hold TSMC harmless in accordance with section 10.1 and provide with assurance measures as reasonably requested by TSMC.
10.5    The remedies provided in this Section 10 shall constitute the sole and exclusive remedy with respect to claims, suits or proceedings alleging infringement or misappropriation of Intellectual Property Rights.
11.    INTELLECTUAL PROPERTY OWNERSHIP
11.1    Technology Owned by IDT.  As between TSMC and IDT, IDT shall own all rights, title and interest (including all Intellectual Property Rights) to any and all:
(a)    IDT Technology. Technology developed or acquired by IDT or any of its Affiliates prior to or independently of this Agreement, including any IDT Manufacturing Process Technology, as well as any Technology expressly described in any Specifications as “IDT Technology” or otherwise provided by IDT to TSMC, including any Improvements made by IDT to this technology in the future.
11.2    Technology Owned by TSMC.  As between TSMC and IDT, TSMC shall own all rights, title and interest (including all Intellectual Property Rights) to any and all:
(a)    TSMC Technology.  Technology developed or acquired by TSMC or any of its Affiliates prior to or independently of this Agreement, including TSMC Manufacturing Process Technology as well as Technology expressly described in any Specifications as “TSMC Technology” or otherwise provided by TSMC to IDT, including any Improvements made by TSMC to this technology in the future.
12.    INTELLECTUAL PROPERTY LICENSES
12.1    License Grant to TSMC.  Subject to the terms and conditions of this Agreement, IDT hereby grants to TSMC under all applicable Intellectual Property Rights in IDT Technology a worldwide, fully-paid, royalty-free, non-transferable, non-exclusive, revocable, license, without right to sublicense, to make, import, offer to sell and sell Wafers only to IDT for as long as such Wafers remain in production for IDT at TSMC.
12.2    Embedded Third Party Technology.  TSMC acknowledges and agrees that IDT may incorporate or otherwise include third party software or hardware as part of the IDT Technology and/or in Improvements thereto, such as open source software (“Embedded Third Party Technology”). Such 





Embedded Third Party Technology may only be used as part of the IDT Technology, and subject to any terms applicable thereto.  IDT shall notify TSMC in writing of any requirements to use the Embedded Third Party Technology that is not otherwise explicitly provided in this Agreement.
12.3    Reservation of Rights.  No right, title or interest is granted by either party whether expressly or by implication to or under any of its Intellectual Property Rights or rights in Technology, other than those rights and licenses expressly granted in this Agreement.  Each party reserves to itself all rights not expressly granted under this Agreement.
13.    INSURANCE: 
13.1    TSMC shall maintain insurance covering its assumed obligations and risks pursuant to this Agreement. TSMC shall obtain and maintain at TSMC’s expense the following minimum insurance:
(a)    Comprehensive general liability with limits not less than $20,000,000.
(b)    Employer’s liability insurance covering employees in compliance with all statutory regulations in each location where Products are being manufactured and TSMC is located.
(c)    Appropriate levels of mitigation for environmental and errors and omissions risks either through insurance programs or self retention.
14.    TERM AND TERMINATION
14.1    Term.  This Agreement shall commence on the Effective Date and shall continue until the tenth anniversary of the Effective Date, unless terminated earlier by either party pursuant to Section 14.2.  This Agreement shall automatically be renewed thereafter for additional [two (2)] year terms unless a party delivers to the other party at least [one (1)] year prior written notice of intent not to renew the Agreement.
14.2    Termination of Agreement.  This Agreement may be terminated as follows:
(a)    The parties may terminate this Agreement upon mutual written consent at any time.
(b)    This Agreement may be terminated by either party upon the material breach of this Agreement by the other party and the failure to cure such breach within thirty (30) days after receipt of notice of intended termination. 
(c)    Starting five (5) years after the Effective Date, IDT may terminate this Agreement for convenience upon six (6) months prior written notice to TSMC.
(d)    Each party reserves the right to immediately terminate this Agreement in writing in the event that:
 
i.upon or after the bankruptcy, insolvency, dissolution or winding up of the other party;


ii.there is any change in the other party's business operations, ownership or management, whether from a consolidation or merger with, or sale or transfer of substantially all assets or 





otherwise to, a TSMC Direct Competitor.
 
The parties agree that this Section shall not apply if the party whose business is changing as described above has obtained the other party’s prior written approval, which shall not be unreasonably withheld or delayed, to proceed and conclude the above events.


14.3    Effect of Termination.  
(a)    Upon termination of this Agreement, TSMC shall have no further delivery obligations other than continuing to manufacture and deliver all confirmed purchase orders accepted prior to of the termination of this Agreement.  The termination of this Agreement shall not affect any payment rights accrued as of the date such termination, including payment of any work-in-process.  The termination of this Agreement shall not release either party from any liability which has already accrued to the other party as of the date of such termination.
(b)    Upon termination of this agreement, if TSMC intends to obsolete or cease manufacturing of any process required to manufacture IDT Products, TSMC will provide Twelve (12) month notification of the last date a purchase order can be placed for delivery of wafers in the following twelve (12) months.
(c)    In the event of termination for convenience by TSMC or by IDT as a result of TSMC’s breach of this Agreement, TSMC will grant to IDT on reasonable terms and conditions under Intellectual Property Rights in TSMC’s Improvements to IDT’s Manufacturing Process Technology a worldwide, fully-paid, royalty-free, non-exclusive, license, without right to sublicense, as necessary to make, have made, import, offer to sell and sell IDT products using the IDT Manufacturing Process Technology.
14.4    Survival.  Notwithstanding any termination of this Agreement, Sections 1, 8, 9, 10, 11, 12.1, 12.3, 14.3, 14.4, 15, 16 and 17 shall survive any termination of this Agreement.


15.    CONFIDENTIALITY
(a)    Confidentiality.  The terms and conditions under the Non-disclosure Agreement (the "NDA") dated January 15, 2006, and as amended by the parties, shall govern any information disclosed under this Agreement that meets the definition of "Confidential Information" under the NDA, and such information shall be used only for the purposes specified herein.
15.2    Effect of the NDA.  In the event the NDA terminates or expires before the term of this Agreement, the term of the NDA shall be deemed co-existent with this Agreement for all purposes hereunder.
15.3    Publicity.  The parties agree to issue a mutually-acceptable press release regarding the existence of this Agreement and the other agreements referenced herein promptly following the Effective Date.  All other press releases regarding the relationship envisioned by this Agreement shall be subject to 





the mutual written acceptance of the parties, such acceptance not to be unreasonably conditioned, delayed or withheld.
16.    LIMITATION OF LIABILITY
16.1    EXCEPT FOR A BREACH OF A LICENSE GRANT OR A CONFIDENTIALITY OBLIGATION, OR AS OTHERWISE SPECIFICALLY REQUIRED IN SECTIONS 8, 9 AND 10 IN NO EVENT SHALL EITHER PARTY OR ITS RESPECTIVE AFFILIATES BE LIABLE FOR ANY LOST PROFITS, OR FOR ANY SPECIAL, INDIRECT, EXEMPLARY, CONSEQUENTIAL OR INCIDENTAL DAMAGES, WHETHER IN CONTRACT, WARRANTY, TORT, STRICT LIABILITY OR OTHERWISE, EVEN IF NOTIFIED OF THE LIKELIHOOD OF SUCH A CLAIM.  NOTWITHSTANDING FOREGOING, FOR CLARIFCATION PURPOSE , THE REMEDIES PROVIDED IN SECTION 8 SHALL CONSTITUTE THE SOLE AND EXCLUSIVE REMEDY WITH RESPECT TO BREACH OF WARRANTY AND THE REMEDIES PROVIDED IN SECTION 9 SHALL CONSTITUTE THE SOLE AND EXCLUSIVE REMEDY WITH RESPECT TO EPIDEMTIC FAILURE.
EXCEPT FOR A BREACH OF A LICENSE GRANT, A CONFIDENTIALITY OBLIGATION, OR AS OTHERWISE SPECIFICALLY SET FORTH SECTIONS 8 AND  9, EACH PARTY’S LIABILITY TO THE OTHER PARTY FOR ANY  CLAIM ARISING FROM ANY CAUSE INCLUDING, BUT NOT LIMITED TO, THE MANUFACTURE, SALE, DELIVERY, NON-DELIVERY, USE OF OR INABILITY TO USE ANY PRODUCTS, EITHER SEPARATELY OR IN COMBINATION WITH ANY OTHER GOODS OR EQUIPMENT, SHALL IN NO EVENT EXCEED .
 (A) THE SUM OF $5 MILLION FOR THE FIRST CONTRACT YEAR;
(B) THE SUM OF $5 MILLION FOR THE SECOND CONTRACT YEAR; AND
(C) THE GREATER OF FIVE MILLION US DOLLARS (USD 5,000,000) OR THE AVERAGE AMOUNT OF THE SUM OF TWENTY PERCENT (20%) OF THE AGGREGATE PAYMENTS MADE TO TSMC BY IDT OR MADE ON BEHALF OF IDT DURING THE PRIOR CONTRACT YEAR AND THE TOTAL AMOUNT OF PRICES PAID BY IDT FOR THE PURCHASE ORDER(S) IN WHICH THE SPECIFIC PRODUCT THAT DIRECTLY GIVES RISE TO THE INDEMNITY OR CLAIM WAS INCLUDED FOR EACH CONTRACT YEARS THEREAFTER.  


The parties acknowledge and agree that the foregoing limitations of liability are an essential element of this Agreement and that in their absence the terms of this Agreement would be substantially different.


17.    MISCELLANEOUS
17.1    Rights in Bankruptcy.  All rights and licenses granted to either party under or pursuant to this Agreement are, and will otherwise be deemed to be, for purposes of Section 365(n) of the U.S. Bankruptcy Code (the “Bankruptcy Code”), licenses of rights to “intellectual property” as defined under Section 101 of the Bankruptcy Code.  The parties agree that each party, as licensee of such rights under this Agreement, will retain and may fully exercise all of its rights and elections as a licensee of intellectual 





property under the Bankruptcy Code.  
17.2    Governing Law.  This Agreement and any dispute arising from the construction, performance or breach hereof shall be governed by and construed and enforced in accordance with the laws of the State of California, without reference to its conflict of law principles. TSMC agrees that upon IDT’s request, all disputes arising hereunder shall be adjudicated in the state and federal courts having jurisdiction over disputes arising in Santa Clara County, California, and TSMC hereby agrees to consent to the personal jurisdiction of such courts.
17.3    Assignment.  Neither party may assign this Agreement, in whole or in part, whether directly or by operation of law, or as part of a Change of Control event, without the prior written consent of the other party, which consent shall not be unreasonably conditioned, delayed or withheld.  Any purported assignment without such consent shall be void and of no effect.  Subject to the foregoing sentence, this Agreement will be binding on and inure to the benefit of the parties and their respective successors and permitted assigns.  For the avoidance of doubt TSMC will not withhold consent if the Assignee is not a TSMC Direct Competitor.
17.4    Representation by Legal Counsel.  Each party hereto represents that it has been represented by legal counsel in connection with this Agreement and acknowledges that it has participated in the drafting hereof.  In interpreting and applying the terms and provisions of this Agreement, the parties agree that no presumption shall exist or be implied against the party that drafted such terms and provisions.  
17.5    Waiver.  It is agreed that no waiver by either party hereto of any breach or default of any of the covenants or agreements herein set forth shall be deemed a waiver as to any subsequent and/or similar breach or default.
17.6    Severability.  In the event that any provision of this Agreement becomes or is declared by a court of competent jurisdiction to be illegal, unenforceable or void, this Agreement shall continue in full force and effect to the fullest extent permitted by law without said provision, and the parties shall amend the Agreement to the extent feasible to lawfully include the substance of the excluded term to as fully as possible realize the intent of the parties and their commercial bargain except to the extent that such amendment can not preserve the essential purpose of this Agreement.
17.7    Independent Contractors.  The relationship of the parties hereto is that of independent contractors.  The parties hereto are not deemed to be agents, partners or joint ventures of the others for any purpose as a result of this Agreement or the transactions contemplated thereby.
17.8    Compliance with Laws.  In exercising their rights and performing their obligations under this Agreement, each party shall fully comply in all material respects with the requirements of any and all applicable laws, regulations, rules and orders of any governmental body having jurisdiction over the exercise of rights and the performance of obligations by either party under this Agreement.
17.9    Export Control Regulations.  The rights and obligations of the parties under this Agreement, shall be subject in all respects to United States laws and regulations and applicable foreign laws and regulations as shall from time to time govern the license and delivery of Technology abroad or importation of the same, including the United States Foreign Assets Control Regulations, Transaction Control Regulations and Export Control Regulations, as amended, and any successor legislation issued by the Department of Commerce, International Trade Administration, or Office of Export Licensing. TSMC and IDT will take all appropriate measures to comply with these regulations and will defend, indemnify and hold the other party harmless from all damages arising out of or in connection with any violation 





thereof. 
17.10    Environmental Matters.
(a)    TSMC will indemnify and hold IDT harmless from and against any liability, loss, damage, cost or expense (including reasonable attorneys fees)  arising from or caused by any toxic or hazardous substances or chemicals, as those terms are defined by applicable environmental health or safety laws or regulations, which are used in performance of this Agreement by TSMC, present in Scrap disposed of or destroyed by TSMC, or present on any of the TSMC Facilities in or during TSMC’s performance of this Agreement.  
(b)    TSMC hereby represents and warrants that all products manufactured by TSMC and delivered to IDT under this Agreement will comply with applicable federal environmental laws and regulations.
17.11    Ethical Dealings.  Each party will be familiar and will strictly comply with all laws and regulations on bribery, corruption, and prohibited business practices.  Each party acknowledges that it will not offer, promise or make or agree to make any payments or gifts (of money or anything of value) directly or indirectly to anyone for the purpose of influencing or inducing anyone to influence decisions in favor of the other party. Without limiting any other provision of this Agreement, TSMC shall not engage in any illegal or unethical practices, including without limitation the Foreign Corrupt Practices Act of 1977 and any anti-boycott laws, as amended, and any implementing regulations.  Each party shall indemnify and hold the other party harmless from and against any liabilities, damages, costs and expenses, including reasonably attorneys’ fees and costs, resulting from any of its breach of this Section 17.11.
17.12    Subcontracting.  TSMC shall not subcontract its obligations under this Agreement to a third party without the prior written consent of IDT.  If such consent is given, TSMC shall remain responsible for all of its obligations as specified in this Agreement.
17.13    Notices.  All notices, requests and other communications hereunder shall be in writing and shall be hand delivered, or sent by express delivery service with confirmation of receipt, or sent by registered or certified mail, return receipt requested, postage prepaid, or by facsimile transmission (with written confirmation copy by registered first-class mail), in each case to the respective address or facsimile number indicated below. Any such notice shall be deemed to have been given when received.  Either party may change its address or facsimile number by giving the other party written notice, delivered in accordance with this Section.
To TSMC:
Attn: General Counsel 
No. 8 LiHsin Rd. 6
Science Based Industrial Park
Hsinchu, Taiwan 300-77
Republic of China


To IDT:
Integrated Device Technology, Inc. 






    Attn: General Counsel 
    6024 Silver Creek Valley Road 
    San Jose, CA 95138
17.14    Force Majeure.  Neither party shall lose any rights hereunder or be liable to the other party for damages or losses on account of failure of performance by the defaulting party if the failure is occasioned by war, strike, fire, Act of God, earthquake, flood, lockout, embargo, act of terrorism, governmental acts or orders or restrictions, failure of suppliers, or any other reason where failure to perform is beyond the reasonable control and not caused by the negligence, intentional conduct or misconduct of the non-performing party and such party has exerted all reasonable efforts to avoid or remedy such force majeure; provided, however, that in no event shall a party be required to settle any labor dispute or disturbance.
17.15    Headings; Construction.  The headings to the clauses, sub-clause and parts of this Agreement are inserted for convenience of reference only and are not intended to be part of or to affect the meaning or interpretation of this Agreement. The terms “this Agreement,” “hereof,” “hereunder” and any similar expressions refer to this Agreement and not to any particular Section or other portion hereof. As used in this Agreement, the words “include” and “including,” and variations thereof, will be deemed to be followed by the words “without limitation” and “discretion” means sole discretion.
17.16    Governing Language. The official text of this Agreement shall be in the English language, and any interpretation or construction of this Agreement shall be based solely on the English-language text.
17.17    Counterparts.  This Agreement may be executed in counterparts, each of which shall be deemed to be an original and all of which together shall be deemed to be one and the same agreement.
17.18    Complete Agreement.  This Agreement with its Exhibits, constitutes the entire agreement, both written and oral, between the parties with respect to the subject matter hereof, and all prior agreements respecting the subject matter hereof (including confidentiality agreements), either written or oral, express or implied, shall be abrogated and canceled.  No amendment or change hereof or addition hereto shall be effective or binding on either of the parties hereto unless reduced to writing and executed by the respective duly authorized representatives of IDT and TSMC.   In the event of a conflict between the terms and conditions of this Agreement and its Exhibits, the terms and conditions of this Agreement shall prevail.


[Signature page follows]







IN WITNESS WHEREOF, the parties have signed this Agreement effective as of the date first set forth above.
INTEGRATED DEVICE TECHNOLOGY, INC.
By: /s/  THEODORE L. TEWKSBURY III        
Name: Theodore L. Tewksbury III        
Title: Chief Executive Officer , President and Director    


TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD..
By: /s/ C.C Wei        
Name: C.C Wei        
Title: Sr. VP Mainstream Technology Business        


TSMC NORTH AMERICA.
By:/s/ R. B. Cassidy II             
Name: R.B. Cassidy II        
Title: President    





    
EXHIBIT A
IDT Transfer Product Qualification Specifications
		
	1.
	Specification requirements for twenty-six (26) IDT product qualification vehicles as defined in Exhibit D.


		
	1.1.
	All process modules must meet IDT process module specification and Process Evaluation test specifications. 


		
	1.2.
	Each of the product qualification vehicles must  pass standard IDT qualification requirements, based on minimum 3 separate production lots per IDT Specification FRA-0040.


		
	1.3.
	Each of the product qualification vehicles that are currently tested and binned according to operational speed, must meet or exceed current IDT speed distributions at all device corners (process, temperature and voltage).


		
	1.4.
	For each IDT product qualification vehicle that currently requires burn-in, TSMC manufactured products must meet IDT FIT rates with equal or less burn in time the IDT manufactured product currently requires. 


		
	1.5.
	For each of the product qualification vehicles that currently do not require burn-in, TSMC manufactured product must meet the short term (BIM) and long term (Life Test) FIT rate (average of the past 4 quarters) of the IDT manufactured product.


		
	1.6.
	The average yield of minimum 3 wafer lots for each of the product qualification vehicles must meet 90% of current IDT product sort and final yield (average of the last 2 quarters).


		
	2.
	Specification requirements for IDT Extension products as defined in Exhibit D and all other future IDT transfer products.


		
	2.1.
	Each of the Extension products must pass standard IDT qualification requirements on a minimum of one lot per IDT Specification FRA-0040.


		
	2.2.
	Each of the Extension products that are currently tested and binned according to operational speed, must meet or exceed current IDT speed distributions at all device corners (process, temperature and voltage).


		
	2.3.
	For each IDT Extension products that currently requires burn-in, TSMC manufactured products must meet IDT FIT rates with equal or less burn in time the IDT manufactured product currently requires. 


		
	2.4.
	For each of the Extension products that currently do not require burn-in, TSMC manufactured product must meet the short term (BIM) and long term (Life Test) FIT rate (average of the past 4 quarters) of the IDT manufactured product.







		
	2.5.
	The average yield of minimum 3 wafer lots for each of the Extension products will need to meet 90% of current IDT product sort and final yield (average of the last 2 quarters).


		
	3.
	BIM criteria: Total 2,500 units from 3 – 5 Fab lots will be taken to perform 40 hrs BIM. Criteria: 5 valid rejects or less from 2,500 units and no any lot has more than 2 BIM failures


FIT Rate: IDT product family FIT rate can be found at WWW.IDT.COM







EXHIBIT B-Pricing 
1.    WAFER PRICING
1.34    Wafer prices will be determined by multiplying the number of process mask layers used to manufacture a Product with all of the required options including Implant, MiM, and Deep Nwell,  PIP, fuse, polyimide, passivation, and HR Poly and the US$ per mask layer for a given process technology set forth below. For the purposes of the calculation of process mask layers, the ASM Zero layer and Open Frame layers will not be included.  
1.35    For Wafers with more or fewer metal layers than the standard metal layers, the Wafer price shall be the price calculated for the standard metal layers plus or minus the metal adder listed for each technology below per metal layer added or subtracted.  As an example only; a .18u, five layer metal process utilizing 27 masking layers would use 23 layers as a 3 layer metal product (Standard Metal Layers). Therefore in 2010 the pricing would be 23 X $20.48 + 2 X $44 (metal adder) = $559.04.
1.36    For IDT Fab 4 Products produced on IDT transfer processes and IDT Fab 4 Products that will be using TSMC Al metallization, Logic and Mix-signal processes on 200mm wafers (i.e. currently running or otherwise intended to run in IDT Fab 4, the Wafer price is equal to the product of (i) the “$ per masking layer” from Table 1 below and (ii) the number of process masking steps for products with three layer metals. The Wafer price of any Product with more than or fewer than three layer metal will be incremented or decremented, respectively, by the “$ per metal” in Table 2 below.  The Epi option price is $30 per Wafer.


	
							
	Table 1 - $ per masking layer

	Calendar Year
	2009
	2010
	2011
	2012
	2013
	2014

	$ per masking layer
	$20.48
	$20.48
	$19.05
	$18.1
	$17.22
	$16.45






	
							
	Table 2 - $ per metal

	Calendar Year
	2009
	2010
	2011
	2012
	2013
	2014

	$ per metal 
(2 mask layers)
	$44
	$44
	$43
	$42
	$41
	$40






1.37    For IDT Products using TSMC Al metallization, Logic and Mix-signal processes on 200mm wafers (i.e. currently running or otherwise intended to run at TSMC using TSMC process), the wafer price is equal to the product of (i) the “$ per masking layer” from Table 3 below and (ii) the number of process masking steps for products with three layer metals. The Wafer price of any Product with more than or 





fewer that three layer metals will be incremented or decremented, respectively, by the “$ per metal” in Table 4 below. The Epi option price is $30 per Wafer.
EXHIBIT B-Pricing 
	
							
	Table 3 - $ per masking layer

	Calendar Year
	-----
	2010
	2011
	2012
	2013
	2014

	$ per masking layer
	-----
	$20.48
	$19.05
	$18.1
	$17.22
	$16.45






	
							
	Table 4 - $ per metal

	Calendar Year
	-----
	2010
	2011
	2012
	2013
	2014

	$ per masking layer 
(2 mask layers)
	-----
	$44
	$43
	$42
	$41
	$40






1.38    For IDT Products utilizing TSMC 0.25um and 0.18um High Voltage technology on 200mm wafers, greater than or equal to 12V, the Wafer price is equal to the product of (i) the “$ per masking layer” from Table 5 below (for 0.25um High Voltage technology) or Table 6 below (for 0.18um High Voltage technology), as applicable, and (ii) the number of process masking steps for Products with three layer metals. The Wafer price of any Product with more than or fewer than three layer metals will be incremented or decremented, respectively, by the “$ per metal” in Table 7 below. Additional $30 for Epi wafer is required for both 0.25um and 0.18um High Voltage technologies.
	
							
	Table 5 - $ per masking layer (for 0.25um High Voltage technology)

	Calendar Year
	-----
	2010
	2011
	2012
	2013
	2014

	$ per masking layer
	-----
	$22.53
	$20.96
	$19.91
	$18.94
	$18.1






	
							
	Table 6 -  $ per masking layer (for 0.18um High Voltage technology)

	Calendar Year
	-----
	2010
	2011
	2012
	2013
	2014

	$ per masking layer
	-----
	$24.17
	$22.48
	$21.36
	$20.32
	$19.41











	
							
	Table 7 - $ per metal

	Calendar Year
	-----
	2010
	2011
	2012
	2013
	2014

	$ per masking layer 
(2 mask layers)
	-----
	$44
	$43
	$42
	$41
	$40






EXHIBIT B-Pricing 
1.39    For IDT Products using TSMC 0.13um Copper metallization on 200mm, the Wafer price will be equal to the product of (i) the “$ per masking layer” from Table 8 below and (ii) the number of process masking steps for Products with six layer metals. The Wafer price for any Product with more or fewer than six layer metal will be incremented or decremented, respectively, by the “$ per metal” in Table 9 below. The Epi option price is $30 per Wafer.
	
							
	Table 8 - $ per masking layer

	Calendar Year
	-----
	2010
	2011
	2012
	2013
	2014

	$ per masking layer
	-----
	$26.01
	$24.19
	$22.99
	$21.87
	$20.89






	
							
	Table 9 - $ per metal

	Calendar Year
	-----
	2010
	2011
	2012
	2013
	2014

	$ per masking layer 
(2 mask layers)
	-----
	$88
	$86
	$84
	$82
	$80






2.    MASK PRICING
2.7    All masks purchased for the manufacture of the Products identified in Section  1.3 of this Exhibit B will be discounted forty-five percent (45%) from latest quoted prices dated August 26, 2008 (TSMC Quotation ID:IDT-7787).
2.8    All masks purchased for the manufacture of the Products identified in Section 1.4, 1.5 and 1.6 of this Exhibit B will be discounted thirty percent (30%) from latest quoted prices dated August 26, 2008 (TSMC Quotation ID:IDT-7787).





Exhibit C - Transfer Plan
NRE:  TSMC shall invoice IDT a one time Non Recurring Engineering (NRE) charge of $1,050,000 for the transfer and qualification of IDT Fab 4 IDT Manufacturing Process Technology and Products to TSMC Facilities. The NRE shall cover all short loop, full run Engineering Wafers and engineering support required for the transfer of the applicable IDT Manufacturing Process Technology and Products. Once implementation of the IDT Manufacturing Process Technology at the applicable TSMC Facilities are finalized, TSMC will provide at no additional cost 3 (three) six-wafer qualification Lots per Product vehicle for a total of twenty-six (26) Product vehicles.  Mask costs are not included in the NRE.
		
	1.
	Transfer Schedule: It is expected that twenty-four (24) months after the signing of this agreement, the transfer, qualification and phase 1 products production ramp will have been completed. Exhibit E details this schedule.


 
		
	2.
	The invoice dates of the NRE payments will be based on Company meeting the following milestones.


		
	2.1.
	25% at the signing of this Agreement.


		
	2.2.
	25% upon successful qualification results of Phase 1 logic Process Qualification Vehicles as defined in Exhibit D. This is expected within Twelve (12) months of the signing this Agreement.


		
	2.3.
	25% upon successful qualification results of Phase 2 Process qualification vehicles as defined in Exhibit D. This is expected within eighteen (18) months of the signing of this Agreement.


		
	2.4.
	25% upon successful qualification and characterization of all IDT transfer products as defined in Exhibit D. This is expected within twenty-four (24) months of the signing of this Agreement.


		
	2.5.
	TSMC will use commercially reasonable efforts to work with IDT to meet the schedule. 


		
	3.
	It is the intention of IDT to transfer all IDT products currently running in IDT Fab 4. After the successful qualification of the 26 Product vehicles, IDT will run qualification wafers on each extension product as defined in Exhibit D at IDT’s expense.  If the transferred product does not meet IDT specifications as per Exhibit A, TSMC will provide additional engineering support as needed to provide additional qualification wafers to IDT at no additional cost until IDT specifications have been met.




		
	4.
	Process R&D.  If in the future IDT determines that certain products are not meeting IDT customer requirements or if IDT determines that additional process steps will give IDT products an advantage, TSMC agrees to use commercially best effort to provide IDT the engineering support to develop and implement the process improvements required to meet IDT customer needs or improve the product. 






























Exhibit D – Transfer Products
Transfer Products: This is a listing of the products that IDT intends to transfer at this time.  The total number may very in the future and the product classification may change from Process Qualification Vehicle to Extension Product.  However, the total number of process qualification vehicles will not exceed 26.





	
								
	Phase 1 Process Qualification Vehicles (11 Total)
	 
	 

	 
	IDT Part #
	IDT Flow
	#P/M Layers
	IDT Process Name
	Technology

	P1QV 1
	71T756Z
	F4R11651CR
	2.5 DPG ISSG
	1P3M
	C11.5 SAC

	P1QV 2
	71V656Z
	F4R11657
	3.3
	1P3M
	C11.5 SAC

	P1QV 3
	70VP258T
	F4R11670CR
	3.3 ISSG
	1P4M
	C11.5 SAC

	P1QV 4
	PP341HXXXY
	F4R11710
	1/8/2005
	2P5M PICO
	C11.5 PCA

	P1QV 5
	70T3519Z
	F4R12514
	2.5
	1P5M
	CEMOS 12.5

	P1QV 6
	71P746Z
	F4R14008
	1.8
	1P5M
	CEMOS 14

	P1QV 7
	72V265Y
	F4R8036
	3.3
	2P2M
	CEMOS 8

	P1QV 8
	72265Y
	F4R8041
	5
	2P2M
	CEMOS 8

	P1QV 9
	70V28Y
	F4R9028
	3.3 N-Type
	3P2M
	CEMOS 9

	P1QV 10
	71024M
	F4R9038
	5
	3P2M
	CEMOS 9

	P1QV 11
	AV286HXXXZ
	F4R9800
	3.3
	1P3M
	CEMOS 9.5

	Phase 1 Extension products (80 total)
	 
	 
	 
	 
	 

	 
	IDT Part #
	IDT Flow
	#P/M Layers
	IDT Process Name
	Technology

	P1EP1
	72V3690X
	F4R11633
	3.3
	1P3M
	C11.5 SAC

	P1EP2
	70V7519Z
	F4R11633
	3.3
	1P3M
	C11.5 SAC

	P1EP3
	72V36B1XB
	F4R11637
	3.3
	1P3M
	C11.5 SAC

	P1EP4
	72V7166Z
	F4R11648
	3.3
	1P4M
	C11.5 SAC

	P1EP5
	72V7327Z
	F4R11648
	3.3
	1P4M
	C11.5 SAC

	P1EP6
	72V5155Z
	F4R11648
	3.3  P/P+
	1P4M
	C11.5 SAC

	P1EP7
	70V659Z
	F4R11649
	3.3
	1P4M
	C11.5 SAC

	P1EP8
	70V3599Z
	F4R11649
	3.3
	1P4M
	C11.5 SAC

	P1EP9
	72T72B5Z
	F4R11651
	2.5 DPG ISSG
	1P3M
	C11.5 SAC

	P1EP10
	70V25T
	F4R11654
	3.3
	1P4M
	C11.5 SAC

	P1EP11
	71V124H
	F4R11657
	3.3
	1P3M
	C11.5 SAC

	P1EP12
	71V556X
	F4R11657
	3.3
	1P3M
	C11.5 SAC

	P1EP13
	71V576Y
	F4R11657
	3.3
	1P3M
	C11.5 SAC

	P1EP14
	71V424Y
	F4R11657CR
	3.3
	1P3M
	C11.5 SAC

	P1EP15
	71V676Z
	F4R11659
	3.3
	1P3M
	C11.5 SAC

	P1EP16
	5T9110Z
	F4R11660
	2.5 DPG 750
	1P3M
	C11.5 NONS

	P1EP17
	5T9316Z
	F4R11660
	2.5 DPG 750
	1P3M
	C11.5 NONS

	P1EP18
	PP411HXXXZ
	F4R11710
	1/8/2005
	2P5M
	C11.5 PCA

	P1EP19
	PP412HXXXZ
	F4R11710
	1/8/2005
	2P5M
	C11.5 PCA

	P1EP20
	PP399HXXXZ
	F4R11710
	1/8/2005
	2P5M Joplin
	C11.5 PCA

	P1EP21
	PP345HXXAY
	F4R11710
	1/8/2005
	2P5M Yangtz
	C11.5 PCA

	P1EP22
	PP408Hxxx_U
	F4R11710
	1/8/2005
	2P5M
	C11.5 PCA

	P1EP23
	PP401HXXXZ
	F4R11718
	1/8/2005
	2P5M Cyrus
	C11.5 PCA

	P1EP24
	71T124G
	F4R12512
	2.5
	1P3M
	CEMOS 12.5

	P1EP25
	70T651Z
	F4R12514A
	2.5
	1P5M
	CEMOS 12.5

	P1EP26
	70TP269Z
	F4R12537
	2.5 /514+L-18
	1P5M
	CEMOS 12.5

	P1EP27
	70P3519Z
	F4R14007
	1.8/3.3
	1P6M
	CEMOS 14

	P1EP28
	70V27W
	F4R14007L1
	1.8/3.3
	1P6M
	CEMOS 14

	P1EP29
	71V424V
	F4R14009
	1.8/3.3
	1P4M
	CEMOS 14

	P1EP30
	723651Y
	F4R8016
	5
	2P2M
	CEMOS 8




		
	•
	Exhibit D Transfer Products









	
						
	Phase 1 Extension products (80 total)Continued
	 
	 

	 
	IDT Part #
	IDT Flow
	#P/M Layers
	IDT Process Name
	Technology

	P1EP31
	7205W
	F4R8016
	5
	2P2M
	CEMOS 8

	P1EP32
	7206X
	F4R8016
	5
	2P2M
	CEMOS 8

	P1EP33
	7204S
	F4R8016
	5
	2P2M
	CEMOS 8

	P1EP34
	7202Q
	F4R8016
	5
	2P2M
	CEMOS 8

	P1EP35
	70121R
	F4R8016
	5
	2P2M
	CEMOS 8

	P1EP36
	7134W
	F4R8016
	5
	2P2M
	CEMOS 8

	P1EP37
	7132S
	F4R8016
	5
	2P2M
	CEMOS 8

	P1EP38
	7133W
	F4R8018
	5
	2P2M
	CEMOS 8

	P1EP39
	7207Y
	F4R8026
	5
	2P1M
	CEMOS 8

	P1EP40
	7208Y
	F4R8026
	5
	2P1M
	CEMOS 8

	P1EP41
	7164L
	F4R8026
	5
	2P1M
	CEMOS 8

	P1EP42
	71256L
	F4R8026
	5
	2P1M
	CEMOS 8

	P1EP43
	79341X
	F4R8028
	5
	2P2M
	CEMOS 8

	P1EP44
	70914Y
	F4R8032
	5
	2P2M
	CEMOS 8

	P1EP45
	72V02Q
	F4R8035
	3.3
	2P2M
	CEMOS 8

	P1EP46
	72V04S
	F4R8035
	3.3
	2P2M
	CEMOS 8

	P1EP47
	72V05W
	F4R8035
	3.3
	2P2M
	CEMOS 8

	P1EP48
	72V225U
	F4R8035
	3.3
	2P2M
	CEMOS 8

	P1EP49
	72V251Y
	F4R8035
	3.3
	2P2M
	CEMOS 8

	P1EP50
	72V245V
	F4R8035
	3.3
	2P2M
	CEMOS 8

	P1EP51
	72V241W
	F4R8035
	3.3
	2P2M
	CEMOS 8

	P1EP52
	72225U
	F4R8040
	5
	2P2M
	CEMOS 8

	P1EP53
	72241W
	F4R8040
	5
	2P2M
	CEMOS 8

	P1EP54
	7054Y
	F4R8041
	5
	2P2M
	CEMOS 8

	P1EP55
	72211W
	F4R8046
	5
	2P2M
	CEMOS 8

	P1EP56
	72245V
	F4R8046
	5
	2P2M
	CEMOS 8

	P1EP57
	71V256YY
	F4R9008CR
	3.3 N-Type
	3P2M
	CEMOS 9

	P1EP58
	72294Z
	F4R9014
	5
	3P2M
	CEMOS 9

	P1EP59
	72V294Z
	F4R9015
	3.3 N-Type
	3P2M
	CEMOS 9

	P1EP60
	70V3579Z
	F4R9018
	3.3 P-Type
	3P2M
	CEMOS 9


















Exhibit D
Transfer Products







	
						
	Phase 1 Extension products (80 total)Continued
	 
	 

	 
	IDT Part #
	IDT Flow
	#P/M Layers
	IDT Process Name
	Technology

	P1EP61
	71V632Z
	F4R9021
	3.3 N-Type
	3P2M
	CEMOS 9

	P1EP62
	71V432V
	F4R9021
	3.3 N-Type
	3P2M
	CEMOS 9

	P1EP63
	728985Z
	F4R9023
	5
	1P3M
	CEMOS 9

	P1EP64
	729082Z
	F4R9023
	5
	1P3M
	CEMOS 9

	P1EP65
	72V3674Y
	F4R9028
	3.3
	3P2M
	CEMOS 9

	P1EP66
	70V25U
	F4R9028
	3.3
	3P2M
	CEMOS 9

	P1EP67
	70V27X
	F4R9028
	3.3
	3P2M
	CEMOS 9

	P1EP68
	723674Y
	F4R9035
	5
	3P2M
	CEMOS 9

	P1EP69
	7028Y
	F4R9035
	5
	3P2M
	CEMOS 9

	P1EP70
	7025U
	F4R9035
	5
	3P2M
	CEMOS 9

	P1EP71
	7027X
	F4R9035
	5
	3P2M
	CEMOS 9

	P1EP72
	71256TT
	F4R9038
	5
	3P2M
	CEMOS 9

	P1EP73
	71124N
	F4R9038
	5
	3P2M
	CEMOS 9

	P1EP74
	AV310HXXXZ
	F4R9800
	3.3
	1P3M
	CEMOS 9.5

	P1EP75
	AV265HXXXZ
	F4R9800
	3.3
	1P3M
	CEMOS 9.5

	P1EP76
	AV284HXXXZ
	F4R9800
	3.3
	1P3M
	CEMOS 9.5

	P1EP77
	AV264HXXXZ
	F4R9800
	3.3
	1P3M
	CEMOS 9.5

	P1EP78
	AV265HXXXY
	F4R9802
	3.3
	1P4M
	CEMOS 9.5

	P1EP79
	AV367HXXXZ
	F4R9804
	3.3
	1P3M
	CEMOS 9.5

	P1EP80
	AV264HXXAZ
	F4R9805
	3.3
	1P3M
	CEMOS 9.5








	
						
	Phase 2 Process Qualification Vehicles (13 Total)
	 
	 

	 
	IDT Part #
	IDT Flow
	#P/M Layers
	IDT Process Name
	Technology

	P2QV1
	5V9885XXXY
	F4R11645
	3.3 MIM CAP
	1P3M
	C11.5 NONS

	P2QV2
	4CP877Y
	F4R11662
	1.8
	1P3M
	C11.5 NONS

	P2QV3
	AT270HXXXZ
	F4R11680
	2.5 DPG N2O DNW
	1P4M
	C11.5 NONS

	P2QV4
	AV278HXXXZ
	F4R11681
	3.3 606+DNW
	1P3M
	C11.5 NONS

	P2QV5
	AP298HXXXZ
	F4R11707NS
	1.8/3.3
	1P3M
	C11.5 SAC

	P2QV6
	82P2828Z
	F4R12526
	1.8/3.3
	1P6M
	CEMOS 12.5

	P2QV7
	40024PB
	F4R8020CR
	5
	1P2M N-type
	CEMOS 8

	P2QV8
	40056X
	F4R8021
	5
	1P2M P-type -Teos etch back
	CEMOS 8

	P2QV9
	40V056A
	F4R8022
	3.3
	1P2M
	CEMOS 8

	P2QV10
	3VH2862Z
	F4R8030CR
	5
	1P2M
	CEMOS 8

	P2QV11
	4V3807Z
	F4R8508
	3.3
	1P3M
	CEMOS 8.5

	P2QV12
	AP402HXXXZ
	F4R11706NS
	1.8/5 OTP
	2P3M Clomel
	C11.5 SAC

	P2QV13
	AV406HXXXZ
	F4R11721
	3.3/12 E2 Temp Sensor2P4M +MIM
	 
	C11.5 NONS
















Exhibit D-Transfer Products







	
						
	Phase 2 Extension products (44 total)
	 
	 

	 
	IDT Part #
	IDT Flow
	#P/M Layers
	IDT Process Name
	Technology

	P2EP1
	5V2310Z
	F4R11606
	3.3
	1P3M P
	C11.5 NONS

	P2EP2
	5V8737Z
	F4R11617
	3.3
	1P3M P
	C11.5 NONS

	P2EP3
	5T2110Z
	F4R11628
	2.5 DPG N2O
	1P3M
	C11.5 NONS

	P2EP4
	45T915Z
	F4R11628
	2.5 DPG N2O
	1P3M
	C11.5 NONS

	P2EP5
	5T9891Z
	F4R11628
	2.5 DPG N2O
	1P3M
	C11.5 NONS

	P2EP6
	5V9885Z
	F4R11645
	3.3 MIM CAP
	1P3M
	C11.5 NONS

	P2EP7
	AV277HXXXZ
	F4R11679
	3.3
	1P4M
	C11.5 NONS

	P2EP8
	AT294HXXXZ
	F4R11680
	2.5 DPG N2O DNW
	1P4M
	C11.5 NONS

	P2EP9
	AV279HXXXZ
	F4R11681
	3.3
	1P3M
	C11.5 NONS

	P2EP10
	AT311HXXXZ
	F4R11687NS
	2.5 DPG N2O
	1P3M
	C11.5 NONS

	P2EP11
	AP377HXXXZ
	F4R11707
	1.8/3.3 OTP
	1P3M
	C11.5 SAC

	P2EP12
	AP318HXXXZ
	F4R11707NS
	1.8/3.3
	1P3M
	C11.5 SAC

	P2EP13
	AP336Hxxx_Z
	F4R11707
	1.8/3.3
	1P3M
	C11.5 SAC

	P2EP14
	AP344Hxxx_Z
	F4R11707
	1.8/3.3
	1P3M
	C11.5 SAC

	P2EP15
	AP343HXXXZ
	F4R11707
	1.8/3.3
	1P3M
	C11.5 SAC

	P2EP16
	AP354HXXXZ
	F4R11713
	1.8/3.3 VERSA
	1P3M
	C11.5 SAC

	P2EP17
	40915NB
	F4R8020
	5
	1P2M
	CEMOS 8

	P2EP18
	40056NB
	F4R8020
	5
	1P2M
	CEMOS 8

	P2EP19
	40048LB
	F4R8020
	5
	1P2M
	CEMOS 8

	P2EP20
	40024PB
	F4R8020CR
	5
	1P2M
	CEMOS 8

	P2EP21
	40026XF
	F4R8021
	5
	1P2M
	CEMOS 8

	P2EP22
	40245XE
	F4R8021
	5
	1P2M
	CEMOS 8

	P2EP23
	47245E
	F4R8021
	5
	1P2M
	CEMOS 8

	P2EP24
	40V056A
	F4R8022
	3.3
	1P2M
	CEMOS 8

	P2EP25
	49F805Z
	F4R8023
	5
	1P2M
	CEMOS 8

	P2EP26
	49F805Z
	F4R8023
	5
	1P2M
	CEMOS 8

	P2EP27
	5991AX
	F4R8030
	5
	1P2M
	CEMOS 8

	P2EP28
	3VHG862Y
	F4R8030
	5
	1P2M
	CEMOS 8

	P2EP29
	4F3805Y
	F4R8044
	5
	1P2M
	CEMOS 8

	P2EP30
	A313HxxxZ
	F4R8047
	5
	1P3M
	CEMOS8

	P2EP31
	4V2528Z
	F4R8504
	3.3
	1P3M
	CEMOS 8.5

	P2EP32
	40V991Z
	F4R8504
	3.3
	1P3M
	CEMOS 8.5

	P2EP33
	40V5928AY
	F4R8508
	3.3
	1P3M
	CEMOS 8.5

	P2EP34
	40V044CG
	F4R8508
	3.3
	1P3M
	CEMOS 8.5

	P2EP35
	42V510Z
	F4R8508
	3.3
	1P3M
	CEMOS 8.5

	P2EP36
	23V08Z
	F4R8508
	3.3
	1P3M
	CEMOS 8.5

	P2EP37
	AP320HXXXZ
	F4R11696
	1.8/5 RTC
	2P3M
	C11.5 NONS

	P2EP38
	AP371HXXXZ
	F4R11706
	1/8/2005
	2P3M Limerick
	C11.5 NONS

	P2EP39
	AP349HZ
	F4R11706
	1.8/5 OTP
	2P3M Ennis
	C11.5 NONS

	P2EP40
	AV359HXXXZ
	F4R11709
	3.3/12 E2
	1P4M
	C11.5 NONS

	P2EP41
	AV387HXXXZ
	F4R11709NS
	3.3/12 E2
	1P4M
	C11.5 NONS

	P2EP42
	AP403HXXXZ
	F4R11715
	1.8/5 RTC
	2P3M
	C11.5 NONS

	P2EP43
	AP361HXXXZ
	F4R11720
	1.8/5 MIM
	2P3M Clomel Test Chip
	C11.5 NONS

	P2EP44
	Av329HxxZ
	F4R11704
	3.3V +MIM
	1P3M,  F4R11681+MIM
	C11.5 NONS










Exhibit D-Transfer Products







	
						
	Phase 3 Process Qualification Vehicles (2 Total)
	 
	 

	 
	IDT Part #
	IDT Flow
	#P/M Layers
	IDT Process Name
	Technology

	P3QV1
	QS3861Y
	F4R8025
	5
	1P2M
	CEMOS 8

	P3QV2
	AV340HXXXZ
	F4R9033CR1
	3.3
	1P3M
	CEMOS 9

	 
	 
	 
	 
	 
	 

	Phase 3 Extension products (29 total)
	 
	 

	 
	IDT Part #
	IDT Flow
	#P/M Layers
	IDT Process Name
	Technology

	P3EP1
	QS3390X
	F4R8025
	5
	1P2M
	CEMOS 8

	P3EP2
	QS3245Y
	F4R8025
	5
	1P2M
	CEMOS 8

	P3EP3
	QS3257X
	F4R8025CR
	5
	1P2M
	CEMOS 8

	P3EP4
	72V7084Z
	F4R9020
	3.3
	1P3M
	CEMOS 9

	P3EP5
	72V7164Z
	F4R9020
	3.3
	1P3M
	CEMOS 9

	P3EP6
	72V8985Z
	F4R9020
	3.3
	1P3M
	CEMOS 9

	P3EP7
	72V7082Z
	F4R9020
	3.3
	1P3M
	CEMOS 9

	P3EP8
	821054AZ
	F4R9030
	5
	2P3M
	CEMOS 9

	P3EP9
	CV145Z
	F4R9033
	3.3
	1P3M
	CEMOS 9

	P3EP10
	CV126Y
	F4R9033
	3.3
	1P3M
	CEMOS 9

	P3EP11
	CV110NU
	F4R9033
	3.3
	1P3M
	CEMOS 9

	P3EP12
	CV179Z
	F4R9033
	3.3
	1P3M
	CEMOS 9

	P3EP13
	CV183HXXXZ
	F4R9033
	3.3
	1P3M
	CEMOS 9

	P3EP14
	CV125Y
	F4R9033
	3.3
	1P3M
	CEMOS 9

	P3EP15
	CV128Z
	F4R9033
	3.3
	1P3M
	CEMOS 9

	P3EP16
	CV141Z
	F4R9033
	3.3
	1P3M
	CEMOS 9

	P3EP17
	CV163Z
	F4R9033
	3.3
	1P3M
	CEMOS 9

	P3EP18
	Cv166Z
	F4R9033
	3.3
	1P3M
	CEMOS 9

	P3EP19
	AV303HXXXZ
	F4R9033CR1
	3.3
	1P3M
	CEMOS 9

	P3EP20
	AV400HXXXZ
	F4R9033NS
	3.3
	1P3M
	CEMOS 9

	P3EP21
	A252HXXXZ
	F4R9040
	5
	1P3M
	CEMOS 9

	P3EP22
	A268HXXXZ
	F4R9040
	5
	1P3M
	CEMOS 9

	P3EP23
	A267HxxxZ
	F4R9040
	5
	1P3M
	CEMOS 9

	P3EP24
	A280HXXXZ
	F4R9043
	5
	1P4M
	CEMOS 9

	P3EP25
	AV299xxxZ
	F4R9042
	3.3
	1P4M
	CEMOS 9

	P3EP26
	AV263HXXXZ
	F4R9042
	3.3
	1P4M
	CEMOS 9

	P3EP27
	AV414HXXXZ
	F4R9700
	3.3
	1P3M+MIM
	CEMOS9.5

	P3EP28
	40V024SA
	F4R8503
	3.3
	1P2M Schottky
	CEMOS 8.5

	P3EP29
	3CVG800Z
	F4R8503
	3.3
	1P2M Schottky
	CEMOS 8.5
































Exhibit E





Transfer Schedule