# Patent

## Title
High-voltage normally-off field effect transistor with channel having multiple adjacent sections

## Abstract

A device having a channel with multiple voltage thresholds is provided. The channel can include a first section located adjacent to a source electrode, which is a normally-off channel and a second section located between the first section and a drain electrode, which is a normally-on channel. The device can include a charge-controlling electrode connected to the source electrode, which extends from the source electrode over at least a portion of the second section of the channel. During operation of the device, a potential difference between the charge-controlling electrode and the channel can control the on/off state of the normally-on section of the channel.

## Background
REFERENCE TO RELATED APPLICATIONS
The present patent application is a continuation-in-part application of U.S. application Ser. No. 13/622,379, entitled “High-Voltage Normally-Off Field Effect Transistor Including a Channel with a Plurality of Adjacent Sections,” which was filed on 19 Sep. 2012, which claims the benefit of U.S. Provisional Application No. 61/536,335, entitled “High-Voltage Normally-Off Field Effect Transistor,” which was filed on 19 Sep. 2011, each of which is hereby incorporated by reference in its entirety to provide continuity of disclosure.


TECHNICAL FIELD
The disclosure relates generally to semiconductor devices, and more particularly, to a channel having a non-uniform voltage threshold.
BACKGROUND ART
Current high-power field effect transistors, such as gallium nitride (GaN)-based heterostructure field effect transistors (HFETs), feature record high powers and breakdown voltages. Although these features make HFETs extremely promising for various applications in power electronics, certain material and device characteristics significantly limit the performance characteristics of the HFETs.
For example, FIG. 1 shows an illustrative schematic structure of a GaN-based HFET according to the prior art. The GaN-based HFET is essentially a normally-on device. In particular, the device channel (two-dimensional electron gas (2DEG)) is conducting between the source and drain of the HFET in the absence of a voltage bias applied to the gate. Such a characteristic is an important limitation for many power electronics applications since a gate voltage source failure can result in extremely high currents flowing through the power transistors and other connected circuit elements and result in partial or total damage to some of the components of the circuit.
One approach to achieve a normally-off condition in a GaN-based HFET removes a portion of the area under the gate, e.g., via etching or the like. For example, FIG. 2 shows an illustrative schematic structure of a recessed gate GaN-based HFET according to the prior art. A circuit-based approach uses a combination of GaN-based HFETs with normally-off silicon (Si)-based devices forming cascode connections, or Baliga pairs. For example, FIG. 3 shows an illustrative comparison of an AlGaN/GaN-based HFET with a cascode circuit according to the prior art.
However, both of these approaches lead to significant performance degradation. In particular, the recessed gate HFET shown in FIG. 2 has higher leakage current, a lower breakdown voltage, and a lower reliability as compared to the HFET shown in FIG. 1. Furthermore, the circuit of FIG. 3 includes significant parasitic parameters and adds additional series resistance of the Si-based devices to the overall circuit.
SUMMARY OF THE INVENTION
This Summary Of The Invention introduces a selection of certain concepts in a brief form that are further described below in the Detail Description Of The Invention. It is not intended to exclusively identify key features or essential features of the claimed subject matter set forth in the Claims, nor is it intended as an aid in determining the scope of the claimed subject matter.
Aspects of the invention provide a device having a channel with multiple threshold voltages. The channel can include a first section having a gate connected thereto and located adjacent to a source electrode, which is a normally-off channel, and a second section located between the first section and a drain electrode, which is a normally-on channel. The device can include a charge-controlling electrode connected to the source electrode, which extends from the source electrode over the gate and at least a portion of the second section of the channel. During operation of the device, a potential difference between the charge-controlling electrode and the channel can control the on/off state of the normally-on section of the channel. The device can further include another section located between the second section and the drain electrode, which can be normally-on or normally off, with another gate connected thereto. This additional section can also include one or more sub-sections with a corresponding gate located on top of each sub-section.
A first aspect of the invention provides a field effect transistor, comprising: a source electrode, a drain electrode, and a gate disposed there between; a gap-filling material separating the gate from the drain electrode, wherein the gap-filling material is connected to the drain electrode without contacting the gate; a channel extending from the source electrode to the drain electrode, wherein the channel includes a plurality of adjacent sections, the plurality of adjacent sections including: a first section connected to the gate and located adjacent to the source electrode without contact thereof, wherein the first section is a normally-off channel; and a second section located adjacent the first section and connected to the drain electrode and the gap-filling material, wherein the second section has a surface that completely contacts the drain electrode and the gap-filling material, and wherein the second section is a normally-on channel; and a charge-controlling electrode connected to the source electrode, wherein the charge-controlling electrode extends from the source electrode over the gate without contact thereof and over at least a portion of the gap-filling material with contact thereof.
A second aspect of the invention provides a field effect transistor, comprising: a source electrode, a drain electrode, and a first gate and a second gate each disposed between the source electrode and the drain electrode; a channel extending from the source electrode to the drain electrode, wherein the channel includes a plurality of adjacent sections, the plurality of adjacent sections including: a first section connected to the first gate and located adjacent to the source electrode, wherein the first section is a normally-off channel; a second section located between the first section and the drain electrode, wherein the second section is a normally-on channel; and a third section connected to the second gate and located between the second section and the drain electrode; a gap-filling material separating the first gate from the second gate without contacting either of the gates; and a charge-controlling electrode connecting the source electrode to the gap-filling material while physically isolated from the first gate and the second gate, wherein the charge-controlling electrode extends from the source electrode over the first gate and over at least a portion of the gap-filling material.
A third aspect of the invention provides a method of fabricating a device, the method comprising: forming a source electrode, a drain electrode, and a gate disposed there between; forming a gap-filling material separating the gate from the drain electrode, wherein the gap-filling material is connected to the drain electrode without contacting the gate; forming a channel extending from the source electrode to the drain electrode, wherein the channel includes a plurality of adjacent sections, the plurality of adjacent sections including: a first section connected to the gate and located adjacent to the source electrode without contact thereof, wherein the first section is a normally-off channel; and a second section located adjacent the first section and connected to the drain electrode and the gap-filling material, wherein the second section has a surface that completely contacts the drain electrode and the gap-filling material, and wherein the second section is a normally-on channel; and forming a charge-controlling electrode connected to the source electrode, wherein the charge-controlling electrode extends from the source electrode over the gate without contact thereof and over at least a portion of the gap-filling material with contact thereof.
The illustrative aspects of the invention are designed to solve one or more of the problems herein described and/or one or more other problems not discussed.



BRIEF DESCRIPTION OF THE DRAWINGS
These and other features of the disclosure will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various aspects of the invention.
FIG. 1 shows an illustrative schematic structure of a gallium nitride-based heterostructure field effect transistor according to the prior art.
FIG. 2 shows an illustrative schematic structure of a recessed gate gallium nitride-based heterostructure field effect transistor according to the prior art.
FIG. 3 shows an illustrative comparison of an AlGaN/GaN-based HFET with a cascode circuit according to the prior art.
FIG. 4 shows a cross-section view of an illustrative semiconductor device according to a first embodiment.
FIG. 5 shows a cross-section view of an illustrative semiconductor device according to a second embodiment.
FIG. 6 shows a cross-section view of an illustrative semiconductor device according to a third embodiment.
FIG. 7 shows a cross-section view of an illustrative semiconductor device according to a fourth embodiment.
FIG. 8 shows a perspective view of an illustrative semiconductor device according to a fifth embodiment.
FIG. 9 shows a top view of an illustrative semiconductor device according to a sixth embodiment.
FIG. 10 shows a cross-section view of an illustrative semiconductor device according to a seventh embodiment.
FIG. 11 shows a cross-section view of an illustrative semiconductor device according to an eighth embodiment.
FIG. 12 shows a cross-section view of an illustrative semiconductor device according to a ninth embodiment.
FIG. 13 shows a cross-section view of an illustrative semiconductor device according to a tenth embodiment.
FIG. 14 shows a cross-section view of an illustrative semiconductor device according to an eleventh embodiment.
FIG. 15 shows a cross-section view of an illustrative semiconductor device according to a twelfth embodiment.
FIG. 16 shows a cross-section view of an illustrative semiconductor device according to a thirteenth embodiment.
FIG. 17 shows a cross-section view of an illustrative semiconductor device according to a fourteenth embodiment.
FIG. 18 shows an illustrative flow diagram for fabricating a circuit according to an embodiment.



It is noted that the drawings may not be to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.
DETAILED DESCRIPTION OF THE INVENTION
As indicated above, aspects of the invention provide a device having a channel with multiple threshold voltages. The channel can include a first section having a gate connected thereto and located adjacent to a source electrode, which is a normally-off channel, and a second section located between the first section and a drain electrode, which is a normally-on channel. The device can include a charge-controlling electrode connected to the source electrode, which extends from the source electrode over the gate and at least a portion of the second section of the channel. During operation of the device, a potential difference between the charge-controlling electrode and the channel can control the on/off state of the normally-on section of the channel. The device can further include another section located between the second section and the drain electrode, which can be normally-on or normally off sections with another gate connected thereto. This additional section can also include one or more sub-sections having normally-on or normally-off channels with a corresponding gate located on top of each sub-section. The use of the third section with a gate attached thereto, including embodiments in which it includes one or more sub-sections with a corresponding gate attached to each sub-section, enables the devices to achieve high voltage operation that is necessary for most power electronics applications.
As used herein, it is understood that the phrase “normally-on channel” means a channel that is in a conducting state when no external voltage or electric field is applied to the channel. Similarly, it is understood that the phrase “normally-off channel” means a channel that is in the non-conducting state when no external voltage or electric field is applied to the channel. It also is understood that: an “insulating material” is a material having a resistivity above 1010 Ohm×cm; a “semi-insulating material” is a material having a resistivity in the range of 105-1010 Ohm×cm; a “semiconductor material” is a material having a resistivity in the range of 10−3-105 Ohm×cm; and metals and semi-metals are materials having a resistivity below 10−3 Ohm×cm. Unless otherwise noted, the term “set” means one or more (i.e., at least one) and the phrase “any solution” means any now known or later developed solution.
Returning to the drawings, FIG. 4 shows a cross-section view of an illustrative semiconductor device 10A according to a first embodiment. The device 10A is shown including a substrate 12, a buffer 14, a channel 16, a barrier 18, a source electrode 20A, a drain electrode 20B, and a gate 22, each of which can be manufactured and fabricated using any solution. For example, the buffer 14 can comprise a single layer or a multi-layer structure, such as an initiation layer and/or a buffer layer. Additionally, the channel 16 can be formed by an active layer and/or the device 10A can include multiple channels 16, each of which is formed by a distinct layer. The barrier 18 also can comprise a single layer or a multi-layer structure. However, it is understood that the heterostructure shown for device 10A is only illustrative of various possible configurations for the device. For example, an embodiment of the device 10A can be formed without the barrier 18. Regardless, the heterostructure of the device 10A can include various layers made from any of a plurality of materials systems. Furthermore, one or more of the layers in a heterostructure described herein can include one or more attributes to alleviate strain. For example, a layer can be formed of a superlattice structure.
In an embodiment, the substrate 12 is formed of SiC, the channel 16 is formed of a gallium nitride (GaN) layer, and the barrier 18 is formed of an aluminum gallium nitride (AlGaN) layer. However, it is understood that this is only illustrative of various possible group III nitride based devices. To this extent, one or more layers forming the buffer 14, channel 16, and/or barrier 18 can be formed of any combination of various types of group III nitride materials comprising one or more group III elements (e.g., boron (B), aluminum (Al), gallium (Ga), and indium (In)) and nitrogen (N), such that BWAlXGaYInZN, where 0≦W, X, Y, Z≦1, and W+X+Y+Z=1. Illustrative group III nitride materials include AlN, GaN, InN, BN, AlGaN, AlInN, AIBN, InGaN, GaBN, AlGaInN, AlGaBN, AlInBN, and AlGaInBN with any molar fraction of group III elements. Furthermore, it is understood that the device 10A can be formed from other semiconductor materials, including: other types of group III-V materials, such as GaAs, GaAlAs, InGaAs, indium phosphorus (InP), and/or the like; group II-VI materials, such as zinc oxide (ZnO), and/or the like; silicon (Si); germanium (Ge); silicon carbide (SiC); and/or the like. Similarly, the substrate 12 can be formed of any of various types of compound semiconductor or dielectric materials, including, for example: sapphire; diamond; mica; ceramic; germanium (Ge); various types of group III nitride substrates including GaN, AlN, BN, AlGaN, AlGaInN, GaBN, AIBN, AlInBN, AlGaBN, and/or the like; LiGaO2, LiNbO2, ZnO; Si; SiC; GaAs; and/or the like. Furthermore, the substrate 12 can comprise a conducting and/or semiconducting substrate.
Additionally, the device 10A includes a charge-controlling electrode 24A. The charge-controlling electrode 24A includes a first portion connected to the source electrode 20A, a second portion extending over/above the gate 22, and a third portion located on gap-filling material 26A. In an embodiment, each of the gate 22, the source electrode 20A, the drain electrode 20B, and the charge-controlling electrode 24A is formed of metal. However, it is understood that each of the gate 22, the source electrode 20A, the drain electrode 20B, and the charge-controlling electrode 24A can be formed of any type of conducting material, including for example, a semiconductor, a crystalline material, a polycrystalline material, and/or the like. The gap-filling material 26A can comprise any type of material, including a dielectric, a semi-insulating material, a semiconducting material, a conducting material, and/or the like. Furthermore, the gap-filling material 26A can comprise a single layer of material and/or a multilayer material including any combination of material layers. In an embodiment, the gap-filling material 26A comprises a layer of low conducting (e.g., semi-insulating) material. The low conducting material can have a surface resistance that is significantly higher than that of metal electrodes, but is also much lower than that of a dielectric material. The practical values of the surface resistance of the low-conducting layer range from 103 to 107 Ohm/square. Illustrative low conducting materials include, for example: InGaN; a semiconductor; a low conducting dielectric single crystal material; a textured, polycrystalline or amorphous material; a semi-metal material; oxides of Ni and other metals and/or the like. Furthermore, in an embodiment, the charge-controlling electrode 24A is electrically isolated from the gate 22 via a spacing that is filled with an insulating material, such as air, and/or the like.
The device 10A includes a channel 16 having a plurality of adjacent sections 30, 32 in a direction between the source electrode 20A and the drain electrode 20B. Each section 30, 32 can include a corresponding threshold voltage that is distinct from the section(s) 30, 32 immediately adjacent thereto. In an embodiment, at least one of the sections, such as section 32, is a normally-on channel (e.g., threshold voltage less than or equal to zero) and at least one of the sections, such as section 30, is a normally-off channel (e.g., threshold voltage greater than zero). In this case, a side of the channel 16 closest to the source electrode 20A can comprise a normally-off section 30, while a side of the channel 16 between the gate 22 and the drain electrode 20B can comprise a normally-on section 32.
The gate 22 can be located near the source electrode 20A between the normally-off section 30 of the channel 16 and the charge-controlling electrode 24A. A voltage applied to the gate 22 can control the on/off state of the normally-off section 30. The charge-controlling electrode 24A can extend over at least a portion of or all of the normally-on section 32 of the channel 16. A potential difference between the charge-controlling electrode 24A and the channel 16 can control the on/off state of the normally-on section(s) 32 of the channel located between the normally-off section 30 and the drain electrode 20B. To this extent, unlike a field-modulating plate, which is widely used in high-voltage devices and is designed to have a minimal capacitance with respect to a channel, the charge-controlling electrode 24A can have a strong capacitive coupling with the channel 16, and therefore be capable of efficiently controlling the concentrations of mobile carriers in the channel 16. As used herein, the charge-controlling electrode 24A has a “strong capacitive coupling” with the channel 16 when the capacitance between the charge-controlling electrode 24A and the channel 16 is greater than or equal to a channel charge under the charge-controlling electrode 24A divided by the threshold voltage.
The different threshold voltages for the sections 30, 32 can be formed using any solution. For example, a threshold voltage for the normally-off section 30 can be adjusted using a recessed gate technique. Furthermore, the threshold voltage of a section 30, 32 can be adjusted by changing one or more of: a conductivity, polarization charges, a doping level, a semiconductor material composition, a surface potential, and/or the like, of the corresponding section of the channel 16. Still further, a device described herein can include one or more back gates, each of which is located on an opposing side of the channel 16 from the gate 22. In this case, during operation of the device in a circuit, a potential applied to a back gate can be used to adjust the corresponding threshold voltage using any solution.
When implemented in a circuit, the device 10A can operate as a field-effect transistor (FET) having both a normally-off channel 16 and a high operating voltage. In particular, when a voltage applied to the gate 22 is zero or below the threshold voltage for the normally-off section 30, the normally-off section 30 is in the non-conducting state. A potential of the normally-on section 32 is high, and a voltage between the charge-controlling electrode 24A and the normally-on section 32 can deplete this section 32. As a result, the entire device 10A is in the off state and the device 10A can absorb a high voltage applied to the drain electrode 20B. Furthermore, when a voltage applied to the gate 22 is above the threshold voltage for the normally-off section 30, the normally-off section 30 is in the conducting state. A potential of the normally-on section 32 is low, and a voltage between the charge-controlling electrode 24A and the normally-on section 32 is above the threshold voltage corresponding to the normally-on section 32. As a result, all of the sections 30, 32 of the channel 16 are in a conducting state and the device 10A has a low resistance. Consequently, the device 10A can operate as a low on-resistance, high-voltage power switch.
When the channel 16 is an n-type channel, the normally-off section 30 has a positive threshold voltage and the normally-on section 32 has a negative threshold voltage. As discussed herein, an external voltage applied to the gate 22 controls the on/off state of the normally-off section 30. Typically, the normally-off section 30 is depleted at zero gate bias. The potential difference between the charge-controlling electrode 24A and the channel 16 controls the on/off state of the normally-on section 32. In a typical application with the n-type channel, when the voltage potential at the gate 22 is zero or below threshold voltage for the normally-off section 30, the normally-off section 30 is in the non-conducting state and a significant portion of the drain voltage drops across the normally-off section 30. As a result, the potential of the normally-on section 32 is significantly higher than that of the source electrode 20A. Therefore, in a typical application when the voltage at the drain electrode 20B is higher than an absolute value of the threshold voltage for the normally-on section 32, a voltage between the charge-controlling electrode 24A and the normally-on section 32 turns the normally-on section 32 into the off state. Consequently, the entire channel 16 is in the off state when the gate voltage 22 is zero or below the threshold voltage of the normally-off section 30. It is understood that the device 10A as well as other devices described herein can have a p-type channel, but operate in a manner according to the difference in polarity.
Since a high drain voltage is distributed over the entire channel 16, a peak electric field along the channel 16 can be kept sufficiently low to achieve high-voltage operation. In an embodiment, the gap-filling material 26A comprises a layer of low-conducting (semi-insulating) material, which can further increase a breakdown voltage of the device 10A. In this case, a finite conductance of the gap-filling material 26A can lead to a quasi-linear potential distribution along the gap-filling material 26A, and therefore along a surface of the semiconductor above the normally-on section 32 of the channel 16. A linear potential distribution leads to a quasi-uniform electric field in and above the channel 16, and therefore reduces/eliminates electric field peaks.
When a voltage applied to the gate 22 is above the threshold voltage for the normally-off section 30, the normally-off section 30 is in the conducting state and a voltage across the normally-off section 30 is low. As a result, a voltage between the charge-controlling electrode 24A and the normally-on section 32 is above the threshold voltage corresponding to the normally-on section 32. Therefore, all of the sections 30, 32 of the channel 16 are in a conducting state and the device 10A has a low resistance. Consequently, the device 10A can operate as a low on-resistance, high-voltage power switch.
It is understood that various embodiments of a device, such as a field effect transistor, can include one or more additional features. For example, FIG. 5 shows a cross-section view of an illustrative semiconductor device 10B according to a second embodiment. In this case, the channel 16 of the device 10B includes a plurality of normally-on sections 32A-32D between the gate 22 and the drain electrode 20B. Each of the normally-on sections 32A-32D can have a threshold voltage that differs from the threshold voltages for the other normally-on sections 32A-32D. A different threshold voltage can be achieved, for example, by: one or more layers in the heterostructure, such as the barrier 18, having a non-uniform thickness, composition, and/or doping along the channel 16; a non-uniform thickness and/or composition of the gap filling material 26B, and/or the like. In an embodiment, an absolute value of the threshold voltage for each of the plurality of normally-on sections 32A-32D increases from the gate 22 to the drain electrode 20B. However, it is understood that any type of variation of the threshold voltages can be implemented, e.g., depending on the circuit requirements for a target circuit in which the device 10B can be incorporated.
In an embodiment, the charge-controlling electrode 24B and the gap-filling material 26B are configured, e.g., using a step arrangement as shown, to provide a different metal-channel separation for each of the normally-on sections 32A-32D. Use of the step arrangement can provide the variable threshold voltage, and enable adjustment (e.g., optimization) of a potential profile in an active regions of the device 10B, e.g., to achieve a higher breakdown voltage. Furthermore, it is understood that a composition, thickness, doping, and/or the like, of the gap-filling material 26B located between the charge-controlling electrode 24B and each normally-on section 32A-32D can differ between the normally-on sections 32A-32D. While the device 10B is shown including a plurality of normally-on sections 32A-32D, it is understood that a device can include any number of one or more normally-off sections and normally-on sections, each of which is formed using any solution.
FIG. 6 shows a cross-section view of an illustrative semiconductor device 10C according to a third embodiment. In the device 10C, the charge-controlling electrode 24C includes a portion 28, which extends through the gap-filling material 26C and forms an internal contact with the normally-on section 32 of the channel 16. In an embodiment, the internal contact is a nonlinear contact, such as for example, a Schottky contact, a metal-insulator-semiconductor contact, and/or the like, with the normally-on section 32 of the channel 16. The internal contact formed by the portion 28 can provide a lower absolute value of the threshold voltage (e.g., typically down to between approximately three volts and approximately six volts) and thereby reduce the voltage required to turn the device 10C off. It is understood that when the channel 16 includes multiple normally-on sections, such as the sections 32A-32D shown in FIG. 5, the charge-controlling electrode 24C can form an additional contact with any number of zero or more of the sections.
FIG. 7 shows a cross-section view of an illustrative semiconductor device 10D according to a fourth embodiment. In the device 10D, the normally-off section 30 of the channel is shown being formed using a recessed gate 22. Furthermore, similar to the device 10C (FIG. 6), the charge-controlling electrode 24D includes a portion 28, which extends through the gap-filling material 26D toward the normally-on section 32 of the channel 16. However, the device 10D includes insulating layers 40A, 40B, which are located between the channel 16 and the gate 22 and the portion 28, respectively. As a result, both the gate 22 and the portion 28 form a metal-insulator-semiconductor structure with the channel 16 using the insulating layers 40A, 40B, respectively. The insulating layers 40A, 40B can significantly reduce the gate leakage currents for the device 10D, and thereby further reduce loss due to the device 10D, increase an operating voltage for the device 10D, improve reliability of the device 10D, and/or the like. It is understood that each insulating layer 40A, 40B can be formed of any type of dielectric material including, for example, silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, and/or the like.
FIG. 8 shows a perspective view of an illustrative semiconductor device 10E according to a fifth embodiment. In this embodiment, the device 10E includes a pair of insulating layers 42A, 42B, each of which can be configured similar to the insulating layers 40A, 40B of FIG. 7. Furthermore, the device 10E includes a charge-controlling electrode 24E, which is formed of a plurality of subsections 44A-44C. In particular, the subsection 44A is connected to the source electrode 20A, the subsection 44B extends over the gate 22, and the subsection 44C is located on the gap-filling material 26E. As illustrated, the insulating layer 42B extends below the entire width and length of the gap-filling material 26E, which can allow for a reduced parasitic capacitance and leakage between the subsection 44C and the channel 16. Furthermore, the subsection 44B of the charge-controlling electrode 24E can have a reduced width as measured in a direction perpendicular to the direction from the source electrode 20A to the drain electrode 20B. The reduced width of the subsection 44B corresponds to an area where the charge-controlling electrode 24E crosses the gate 22. In this case, the reduced width of the subsection 44B can decrease an amount of capacitance between the charge-controlling electrode 24E and the gate 22.
FIG. 9 shows a top view of an illustrative semiconductor device 1 OF according to a sixth embodiment. The semiconductor device 10F includes a pair of charge controlling electrodes configured similar to the charge-controlling electrode 24E of the device 10E of FIG. 8. To this extent, each charge-controlling electrode includes multiple subsections 44A-44C where each subsection 44A is located over a source electrode 20A (FIG. 8) of the device 10F, each subsection 44B has a reduced width and extends over a gate 22 of the device 10F, and each subsection 44C is located on a portion of the gap-filling material 26E located between a gate 22 and a drain electrode 20B. The device 10F comprises an interdigitated, multi-finger geometry, which can achieve a larger active area, a lower on-resistance, and a higher peak current than the device 10E.
FIG. 10 shows a cross-section view of an illustrative semiconductor device 10G according to a seventh embodiment. The semiconductor device 10G is configured similar to the device 10D of FIG. 7. However, the charge-controlling electrode 24G is also connected to a field-modulating electrode 46A. Similarly, the drain electrode 20B also is connected to a field-modulating electrode 46B. Inclusion of the field-modulating electrodes 46A, 46B can provide further control over the electric field uniformity for the device 10G. In an embodiment, each field-modulating electrode 46A, 46B is formed of metal or a low conducting material as described herein. Furthermore, each field-modulating electrode 46A, 46B can be located on an insulating layer 48 formed of, for example, a dielectric material.
FIG. 11 shows a cross-section view of an illustrative semiconductor device 10H according to an eighth embodiment. As shown in FIG. 11, the channel 16 of device 10H includes a third section 50 located between the second section 32 of the channel 16 and the drain electrode 20B. In one embodiment, the third section 50 can be a normally-on section, however, it is understood that this third section 50 of the channel 16 can also be a normally-off section. The device 10H can further include a second gate 52 attached to the third section 50 of the channel 16 through the barrier 18. As shown in FIG. 11, a gate 52 to the third section 50 is disposed on a top surface of the barrier 18 between the gap-filling material 26H and the drain electrode 20B. In one embodiment, the gate 52 is physically isolated from the gap-filling material 26H and the drain electrode 20B. A voltage applied to the gate 22 enables control of the state of the first section 30 of the channel 16, while a voltage applied to the gate 52 enables control of the state of the third section 50 of the channel 16. As a result, gate 22 and/or gate 52 can be utilized to control the overall device current of the device 10H. For each multi-gate embodiment described herein, it is understood that a circuit can independently adjust the voltages applied to the gates or can adjust the voltages applied to the gates together. To this extent, two or more gates can be operated together to control the on/off state of multiple sections of the channel 16, or one of multiple gates can be operated independently to adjust the on/off state of a single section of the channel 16.
FIG. 12 shows a cross-section view of an illustrative semiconductor device 10I according to a ninth embodiment. In this embodiment, the third section 50 of the channel 16 is shown having a plurality of sub-sections 50A and 50B. It is understood, that for clarity, the third section 50 is only illustrated with two sub-sections, however, the device 10I can have more sub-sections if desired. In one embodiment, the sub-sections 50A and 50B can be both normally-on sections. In another embodiment, the sub-sections 50A and 50B can be both normally-off sections. In still another embodiment, the sub-sections 50A and 50B can be a combination of normally-on sections and normally-off sections. As shown in FIG. 12, the sub-sections 50A and 50B are disposed between the source electrode 20A and the drain electrode 20B. More specifically, the sub-sections 50A and 50B of the third section 50 of the channel 16 can be disposed between the second section 32 of the channel 16 and the drain electrode 20B.
Each of the sub-sections 50A and 50B of the third section 50 can have a corresponding sub-section gate 52A, 52B attached thereto. For example, in FIG. 12, a gate 52A connects to the sub-section 50A of the channel 16 via the barrier 18, while a gate 52B connects to the sub-section 50B of the channel 16 via the barrier 18. Both gates 52A and 52B can be disposed on a top surface of the barrier 18 between the gap-filling material 26I and the drain electrode 20B. In one embodiment, both the gate 52A and the gate 52B are physically isolated from the gap-filling material 26I and the drain electrode 20B. Each of the gates 22, 52A, 52B can be utilized to control current flow through the corresponding sections 30, 50A, 50B, respectively.
In one embodiment, each of the sub-sections 50A and 50B of the third section 50 of the channel 16 of the device 10I can have different threshold voltages. A different threshold voltage for the sub-sections 50A and 50B can be achieved, for example, by: having one or more layers in the heterostructure of the device 10I, such as, for example, the barrier 18; and having a non-uniform thickness, composition, and/or doping along the channel 16. In this manner, not only can the threshold voltages for the sub-sections 50A and 50B of the third section 50 vary, but so can the threshold voltages of the first section 30 and the second section 32 of the channel 16 of the device 10I. It is understood, that the threshold voltages for all of the sections of the channel can be uniform or can be tailored to have some sections with similar threshold voltages while having other sections with different threshold voltages.
FIG. 13 shows a cross-section view of an illustrative semiconductor device 10J according to a tenth embodiment. In this embodiment, a gate isolation layer can be disposed between each sub-section gate and a corresponding sub-section. As shown in FIG. 13, a gate isolation layer 62A can be disposed between the gate 52A and the sub-section 50A, while a gate isolation layer 62B can be disposed between the gate 52B and the sub-section 50B. The gate isolation layers 62A and 62B can be any insulating material such as a dielectric material. A non-exhaustive listing of dielectric material that is suitable for use as a gate isolation layer can include silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, and/or the like.
The gate isolation layers 62A and 62B can be used to configure each of the sub-sections 50A and 50B of the third section 50 of the channel 16 with different threshold voltages. In one embodiment, the thicknesses of the gate isolation layers 62A and 62B can be varied to attain different threshold voltages due to a changing capacitance between the gate 52A, 52B and the channel 16. As shown in FIG. 13, the thickness of the gate isolation layer 62A is less than the thickness of the gate isolation layer 62B. In another embodiment, the composition of the gate isolation layers 62A and 62B can be varied to attain different threshold voltages due to a change in the work function of the device surface. In still another embodiment, different threshold voltages can be attained for the various sections by varying the doping of the channel portions of those sections.
FIG. 14 shows a cross-section view of an illustrative semiconductor device 10K according to an eleventh embodiment. In this embodiment, not all of the sub-section gates have a gate isolation layer disposed between the gate and the corresponding sub-section, such as the embodiment illustrated in FIG. 13. In FIG. 14, there is no gate isolation layer disposed between the gate 52A and the sub-section 50A, while gate 52B has a gate isolation layer 62B disposed between the gate and the sub-section 50B. It is understood that this arrangement is only illustrative of one possible example, and that a gate isolation layer can be disposed between the gate 52A and the sub-section 50A while the gate 52B and the sub-section 50B can contact each other without having a gate isolation layer placed there between.
FIG. 14 also shows that the device 10K can have the gate 22 recessed into the normally-off, first section 30 of the channel 16. A recessed gate 22 serves to decrease the parasitic access resistances of the device 10K. It is understood that the level that the gate 22 is recessed can be varied to attain a desired threshold voltage. It is also understood that the recessed gate 22 may also have a layer or a number of layers of dielectric material beneath it. Each of the insulating layers can be formed of any type of dielectric material including, but not limited to, silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, and/or the like.
FIG. 15 shows a cross-section view of an illustrative semiconductor device 10L according to a twelfth embodiment. In this embodiment, some of the gates connected to the various sections of the channel 16 including the sub-sections of the third section 50 can be formed with a semiconductor heterostructure. For example, FIG. 15, shows the gate 22 of the first section 30 of the channel can be formed with a semiconductor heterostructure 18A. In one embodiment, the heterostructure 18A is a hetero-barrier semiconductor that can be formed of any of the aforementioned materials listed for barrier 18. As shown in FIG. 15, the heterostructure 18A can be disposed underneath the gate 22. In this manner, the heterostructure 18A can be used to control the threshold voltage of the first section 30 of the channel 16 due to altering the capacitive coupling. In addition to controlling the threshold voltage of the first section 30, the heterostructure 18A can be used to control gate leakage current from the gate 22 via a change in the effective input impedance.
It is understood that FIG. 15 is illustrative of only one example in which a semiconductor heterostructure can be used in a device such as a field effect transistor and is not meant to limit the various embodiments described herein. For example, the heterostructure 18A can be formed with any of the gates utilized in any of the various sections of the channel 16. It is also understood, that the heterostructure 18A does not necessarily have to be formed with a gate that has been recessed in a section of the channel as illustrated in FIG. 15. In particular, the heterostructure 18A is suitable for use with gates that are not recessed and that are disposed on a top surface of the barrier 18 or the channel 16 if no barrier is used. It is further understood, that a heterostructure 18A formed with any of the gates 22, 52A, 52B may also have a layer or multiple layers of dielectric on top of it, under the corresponding gate electrode.
FIG. 16 shows a cross-section view of an illustrative semiconductor device 10M according to a thirteenth embodiment. In this embodiment, at least one of the sections 30, 32, and 50 can have a vertically laid out channel portion in addition to, or in place of, a horizontally extending channel portion. For example, FIG. 16 shows that the third section 50 of the channel 16 of the device 10M can have a horizontally extending channel portion 16A with a vertically laid out channel portion 16B. As shown in FIG. 16, the horizontally extending channel portion 16A has a top surface that can contact the drain electrode 20B via the barrier 18. The vertically laid out channel portion 16B can extend vertically out of the horizontally extending channel portion 16A. In one embodiment, the vertically laid out channel portion 16B extends vertically downward from the horizontally extending channel portion 16A such that a portion of its bottom surface contacts an additional drain electrode 20C located adjacent to a portion of both the substrate 12 and the buffer 14. A connection drain electrode 20D connects the drain electrode 20B with the additional drain electrode 20C. As shown in FIG. 16, the connection drain electrode 20D can contact side surfaces of the horizontally extending channel portion 16A and the vertically laid out channel portion 16B in addition to contacting a side surface of the drain electrode 20C.
The vertically laid out channel portion 16B enables the device to achieve higher operating voltages and to eliminate the premature surface breakdown. In particular, higher operating voltages are attained by the channel portion 16B spreading the electric field streamlines in two dimensions, which also reduces premature surface breakdown. In this arrangement of the device 10M, the additional drain electrode 20C provides a current path for the vertically laid out channel portion 16B of the channel 16, while its connection to the drain electrode 20B via the connection drain electrode 20D serves to spread the electric field even more.
It is understood that FIG. 16 is illustrative of only one example in which a vertically laid out channel portion can be used in a device such as a field effect transistor and is not meant to limit the various embodiments described herein. For example, the vertically laid out channel portion 16B can be situated in any of the various sections of the channel 16 such as the first section 30 and/or the second section 32. Similarly, it is understood that more than one of the sections of the channel 16 can be formed with the vertically laid out channel portion 16B. Those skilled in the art will appreciate that changing the location of the vertically laid out channel portion or adding additional vertically laid out channel portions may necessitate a change of the location of the drain electrode 20C and the connection drain electrode 20D, and/or the amount of drain electrodes that are used. It is also understood, that the field effect transistor device that is implemented with the vertically laid out channel portion 16B does not necessarily have to be formed with one gate having a gate isolation layer as shown in FIG. 16. As noted above, one or more of the gate isolation layers may be used with any of the gates formed in the sections of the channel 16. It is also understood, that the use of the gate isolation layers can have variable thicknesses and/or composition in order to obtain different threshold voltages. Alternatively, any of the gates formed in the sections of the channel 16 can be formed without gate isolation layers. Furthermore, it is understood that the any of the gates formed in the sections of the channel 16 can be recessed in a section of the channel if desired. Also, it is understood that any of the gates utilized in the various sections of the channel 16 can be formed with a semiconductor heterostructure.
FIG. 17 shows a cross-section view of an illustrative semiconductor device 10N according to a fourteenth embodiment. The device 10N is an alternative to the device 10M depicted in FIG. 16 in that the connection drain electrode 20D is not used to connect the drain electrode 20B with the additional drain electrode 20C. In this manner, the drain electrode 20B and the additional drain electrode 20C have the option to have an independent bias applied thereto. Such a configuration can enable adjustment of the two-dimensional field distribution in a high field region of the device 10N.
Aspects of the invention are shown and described primarily with reference to a heterostructure field effect transistor. However, it is understood that a charge-controlling electrode described herein can be implemented in various types of field-effect transistors, including, for example, a field-effect transistor, a heterostructure field-effect transistor, an insulated gate field-effect transistor, an insulated gate heterostructure field-effect transistor, a multiple channel heterostructure field-effect transistor, a multiple channel heterostructure insulated gate field-effect transistor, an inverted field-effect transistor, an inverted heterostructure field-effect transistor, an inverted insulated gate field-effect transistor, an inverted insulated gate heterostructure field-effect transistor, an inverted multiple channel heterostructure field-effect transistor, an inverted insulated gate multiple channel heterostructure field-effect transistor, and/or the like. Additionally, the charge-controlling electrode described herein can be implemented in other types of semiconductor devices, including for example, a diode of any type, a semiconductor resistor, a semiconductor sensor, a light emitting diode, a laser, an integrated element, a transistor integrated with light emitting diode, a laser with and/or integrated with other circuit components, and/or the like.
It is also understood that the three section device designs of FIGS. 11-17 including the subsections of the third section can be implemented with various types of field-effect transistors, including, for example, a field-effect transistor, a heterostructure field-effect transistor, an insulated gate field-effect transistor, an insulated gate heterostructure field-effect transistor, a multiple channel heterostructure field-effect transistor, a multiple channel heterostructure insulated gate field-effect transistor, an inverted field-effect transistor, an inverted heterostructure field-effect transistor, an inverted insulated gate field-effect transistor, an inverted insulated gate heterostructure field-effect transistor, an inverted multiple channel heterostructure field-effect transistor, an inverted insulated gate multiple channel heterostructure field-effect transistor, and/or the like.
Furthermore, it is understood that the three section device designs of FIGS. 11-17 including the subsections of the third section can be implemented with a variety of gate types connected to the first and the subsections of the third section. A non-exhaustive listing of gate types that are suitable for use in the various embodiments described herein can include, Schottky type gates, recessed Schottky type gates, isolated gates including dielectric material between the gates and a barrier, recessed isolated gate types, hetero-type gates incorporating a heterostructure barrier under the gate metal or under the dielectric material located under the gate metal or recessed hetero-type gate.
In addition, it is understood that the three section device designs of FIGS. 11-17 including the subsections of the third section are suitable for use with any of the field effect transistor device designs illustrated in FIGS. 4-10. For example, the three section device designs of FIGS. 11-17 including the subsections of the third section are suitable for use with the interdigitated, multi-finger pattern device illustrated in FIG. 9.
While shown and described herein as a method of designing and/or fabricating a semiconductor device, it is understood that aspects of the invention further provide various alternative embodiments. For example, in one embodiment, the invention provides a method of designing and/or fabricating a circuit that includes one or more of the semiconductor devices designed and fabricated as described herein.
To this extent, FIG. 18 shows an illustrative flow diagram for fabricating a circuit 126 according to an embodiment. Initially, a user can utilize a device design system 110 to generate a device design 112 for a semiconductor device as described herein. The device design 112 can comprise program code, which can be used by a device fabrication system 114 to generate a set of physical devices 116 according to the features defined by the device design 112. Similarly, the device design 112 can be provided to a circuit design system 120 (e.g., as an available component for use in circuits), which a user can utilize to generate a circuit design 122 (e.g., by connecting one or more inputs and outputs to various devices included in a circuit). The circuit design 122 can comprise program code that includes a device designed as described herein. In any event, the circuit design 122 and/or one or more physical devices 116 can be provided to a circuit fabrication system 124, which can generate a physical circuit 126 according to the circuit design 122. The physical circuit 126 can include one or more devices 116 designed as described herein.
In another embodiment, the invention provides a device design system 110 for designing and/or a device fabrication system 114 for fabricating a semiconductor device 116 as described herein. In this case, the system 110, 114 can comprise a general purpose computing device, which is programmed to implement a method of designing and/or fabricating the semiconductor device 116 as described herein. Similarly, an embodiment of the invention provides a circuit design system 120 for designing and/or a circuit fabrication system 124 for fabricating a circuit 126 that includes at least one device 116 designed and/or fabricated as described herein. In this case, the system 120, 124 can comprise a general purpose computing device, which is programmed to implement a method of designing and/or fabricating the circuit 126 including at least one semiconductor device 116 as described herein.
In still another embodiment, the invention provides a computer program fixed in at least one computer-readable medium, which when executed, enables a computer system to implement a method of designing and/or fabricating a semiconductor device as described herein. For example, the computer program can enable the device design system 110 to generate the device design 112 as described herein. To this extent, the computer-readable medium includes program code, which implements some or all of a process described herein when executed by the computer system. It is understood that the term “computer-readable medium” comprises one or more of any type of tangible medium of expression, now known or later developed, from which a stored copy of the program code can be perceived, reproduced, or otherwise communicated by a computing device.
In another embodiment, the invention provides a method of providing a copy of program code, which implements some or all of a process described herein when executed by a computer system. In this case, a computer system can process a copy of the program code to generate and transmit, for reception at a second, distinct location, a set of data signals that has one or more of its characteristics set and/or changed in such a manner as to encode a copy of the program code in the set of data signals. Similarly, an embodiment of the invention provides a method of acquiring a copy of program code that implements some or all of a process described herein, which includes a computer system receiving the set of data signals described herein, and translating the set of data signals into a copy of the computer program fixed in at least one computer-readable medium. In either case, the set of data signals can be transmitted/received using any type of communications link.
In still another embodiment, the invention provides a method of generating a device design system 110 for designing and/or a device fabrication system 114 for fabricating a semiconductor device as described herein. In this case, a computer system can be obtained (e.g., created, maintained, made available, etc.) and one or more components for performing a process described herein can be obtained (e.g., created, purchased, used, modified, etc.) and deployed to the computer system. To this extent, the deployment can comprise one or more of: (1) installing program code on a computing device; (2) adding one or more computing and/or I/O devices to the computer system; (3) incorporating and/or modifying the computer system to enable it to perform a process described herein; and/or the like.
The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to an individual in the art are included within the scope of the invention as defined by the accompanying claims.

## Claims

1. A field effect transistor, comprising:
a source electrode, a drain electrode, and a gate disposed there between;
a gap-filling material separating the gate from the drain electrode without contacting the gate;
a channel extending from the source electrode to the drain electrode, wherein the channel includes a plurality of adjacent sections, the plurality of adjacent sections including:
a first section connected to the gate and located adjacent to the source electrode without contact thereof, wherein the gate is integrated in the first section, and wherein the first section is a normally-off channel; and
a second section located adjacent the first section and connected to the gap-filling material, wherein the second section has a surface that directly contacts the gap-filling material, and wherein the second section is a normally-on channel; and

a charge-controlling electrode connected to the source electrode, wherein the charge-controlling electrode extends from the source electrode over the gate without contact thereof and over at least a portion of the gap-filling material with direct contact thereof.

2. The field effect transistor of claim 1, wherein the charge-controlling electrode extends horizontally and directly on a top surface of the source electrode to over the portion of the gap-filling material for direct contact thereof.

3. The field effect transistor of claim 1, wherein the charge-controlling electrode comprises a section having a stepped-shape that contacts the gap-filling material, wherein the gap-filling material has a stepped-shape that is complementary to receive the stepped-shape section of the charge-controlling electrode.

4. The field effect transistor of claim 1, wherein the charge-controlling electrode comprises a horizontally extending section and a vertically extending section that extends downward from the horizontally extending section to directly contact the second section of the channel.

5. The field effect transistor of claim 4, wherein the vertically extending section has a first side with complete and direct contact with the gap-filling material and a second side opposite the first side that is adjacent the gate without contact thereof.

6. The field effect transistor of claim 4, wherein the horizontally extending section of the charge-controlling electrode extends beyond the vertically extending section to over a top surface of the gap-filling material with direct contact thereof.

7. The field effect transistor of claim 4, further comprising an isolation material located directly between the vertically extending section of the charge-controlling electrode and the second section of the channel, wherein the isolation material is integrated in the second section of the channel.

8. The field effect transistor of claim 1, further comprising a gate isolation material formed in the first section of the channel, wherein the gate is substantially recessed in the gate isolation material, wherein a top surface of the gate is below a top surface of the source electrode and a top surface of the drain electrode.

9. The field effect transistor of claim 1, wherein the plurality of adjacent sections further includes a third section located between the first section and the drain electrode, wherein the third section has a surface that is in complete contact with the gap-filling material, and wherein the third section is a normally-on channel having a different threshold voltage than a threshold voltage of the second section.

10. A field effect transistor, comprising:
a source electrode, a drain electrode, and a first gate and a second gate each disposed between the source electrode and the drain electrode;
a channel extending from the source electrode to the drain electrode, wherein the channel includes a plurality of adjacent sections, the plurality of adjacent sections including:
a first section connected to the first gate and located adjacent to the source electrode, wherein the first gate is integrated in the first section, and wherein the first section is a normally-off channel;
a second section located between the first section and the drain electrode, wherein the second section is a normally-on channel; and
a third section connected to the second gate and located between the second section and the drain electrode;

a gap-filling material separating the first gate from the second gate without contacting either of the gates; and
a charge-controlling electrode connecting the source electrode to the gap-filling material while physically isolated from the first gate and the second gate, wherein the charge-controlling electrode extends from the source electrode over the first gate and over at least a portion of the gap-filling material.

11. The field effect transistor of claim 10, wherein the third section of the channel comprises a plurality of sub-sections each having one of a normally-on channel and a normally-off channel, each sub-section having a corresponding sub-section gate attached thereto.

12. The field effect transistor of claim 11, further comprising a plurality of sub-section gate isolation layers, where each sub-section gate isolation layer is disposed between one sub-section gate and a corresponding sub-section.

13. The field effect transistor of claim 12, wherein each of the plurality of sub-section gate isolation layers has a variable thickness and/or composition of material, and wherein each of the plurality of sub-section gate isolation layers attain different threshold voltages due to the variable thickness and/or composition of material.

14. The field effect transistor of claim 11, further comprising a sub-section gate isolation layer disposed between at least one sub-section gate and a corresponding sub-section.

15. The field effect transistor of claim 11, further comprising a semiconductor heterostructure disposed underneath at least one of the first gate and the sub-section gates to control threshold voltages of the sections forming the channel.

16. The field effect transistor of claim 11, wherein at least one of the plurality of sub-sections comprises a horizontally extending channel portion with a vertically laid out channel portion, the horizontally extending channel portion having a top surface that contacts the drain electrode and the vertically laid out channel portion having a bottom surface that contacts an additional drain electrode.

17. The field effect transistor of claim 16, further comprising a connection drain electrode that connects the drain electrode with the additional drain electrode, wherein the connection drain contacts side surfaces of the horizontally extending channel portion and the vertically laid out channel portion.

18. The field effect transistor of claim 10, wherein the channel is formed from one of: silicon, silicon carbide, or a group III-V material.

19. The field effect transistor of claim 10, wherein the source electrode, the first gate, the second gate, the drain electrode, and the charge-controlling electrode form an interdigitated, multi-finger pattern.

20. A method of fabricating a device, comprising:
forming a source electrode, a drain electrode, and a gate disposed there between;
forming a gap-filling material separating the gate from the drain electrode without contacting the gate;
forming a channel extending from the source electrode to the drain electrode, wherein the channel includes a plurality of adjacent sections, the plurality of adjacent sections including:
a first section connected to the gate and located adjacent to the source electrode without contact thereof, wherein the gate is integrated in the first section, and wherein the first section is a normally-off channel; and
a second section located adjacent the first section and connected to the gap-filling material, wherein the second section has a surface that directly contacts the gap-filling material, and wherein the second section is a normally-on channel; and

forming a charge-controlling electrode connected to the source electrode, wherein the charge-controlling electrode extends from the source electrode over the gate without contact thereof and over at least a portion of the gap-filling material with direct contact thereof.