# Patent

## Title
Voltage-controlled oscillator

## Abstract

A voltage-controlled oscillator includes two first inductors having a common node, two varactors respectively coupled to the first inductors, a cross-connected pair coupled to the first inductors, and a reversely tunable source degeneration module coupled to the cross-connected pair. The reversely tunable source degeneration module cooperates with the cross-connected pair to form a negative equivalent capacitance seen into the cross-connected pair from the common node of cross-connected pair and each first inductor. An oscillatory signal pair is provided at the first terminals of the first and second transistors.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation-in-part of U.S. patent application Ser. No. 14/964,081, filed by the applicant on Dec. 9, 2015, which claims priority of Taiwanese Patent Application No. 103145257 filed on Dec. 24, 2014, and the entire disclosure of which is incorporated herein by reference.


FIELD
The disclosure relates to a voltage-controlled oscillator, and more particularly to a voltage-controlled oscillator adapted for a radio frequency (RF) circuit.
BACKGROUND
Voltage-controlled oscillators (VCO) are critical components in wireless communication systems. As an example, signals of different channels may be selected by changing the output frequency of the VCO. Recently, due to the increasing demand for data transmission, it is important to effectively improve on the operating frequency and the adjustable frequency range.
Referring to FIG. 1, a conventional VCO includes two inductors (Lg), two varactors (Cd), a cross-coupled pair of transistors (M1, M2), and a current source 11.
A common node of the inductors (Lg) is coupled to a voltage source (VDD), the varactors (Cd) are respectively coupled to the inductors (Lg) and have a common node coupled to a bias voltage source (Vtune) the drain terminal and the gate terminal of each of the transistors (M1, M2) are respectively coupled to the varactors (Cd), and the current source 11 is coupled between a common source node of the transistors (M1, M2) and ground.
In application, the voltage provided by the bias voltage source (Vtune) may be adjusted to change capacitances of the varactors (Cd), thereby adjusting an output frequency of the VCO.
However, the operating frequency and the adjustable frequency range of the conventional VCO may be limited due to effective parasitic capacitance of the transistors (M1, M2). In addition, the voltage provided by the voltage source (VDD) has to be raised for enabling the transistors (M1, M2) to operate in the saturation region while maintaining sufficient output voltage swing, resulting in higher power consumption.
SUMMARY
Therefore, an object of the disclosure is to provide a voltage-controlled oscillator that may have a relatively higher operating frequency and a relatively wider range of frequency adjustment.
According to the disclosure, the voltage-controlled oscillator includes two first inductors, two first varactors, a cross-connected pair that includes a first transistor, a second transistor, and two second inductors, and a reversely tunable source degeneration module. The two first inductors have a common node. Each of the first inductors has a first terminal coupled to the common node, and a second terminal. Each of the two varactors has a first terminal disposed to receive a first bias voltage, a second terminal coupled to the second terminal of a respective one of the first inductors, and a capacitance associated with a magnitude of the first bias voltage. Each of the first transistor and the second transistor has a first terminal coupled to the second terminal of a respective one of the first varactors, a second terminal and a control terminal. One of the second inductors is coupled between the control terminal of the first transistor and the first terminal of the second transistor, and the other one of the second inductors is coupled between the control terminal of the second transistor and the first terminal of the first transistor. The reversely tunable source degeneration module is coupled to the second terminals of the first and second transistors, is configured for source degeneration of the first and second transistors, and cooperates with the first and second transistors and the second inductors to form a negative equivalent capacitance seen into the cross-connected pair from the first terminal of each of the first and second transistors. A first oscillatory signal is provided at the first terminal of the first transistor, and a second oscillatory signal is provided at the first terminal of the second transistor.



BRIEF DESCRIPTION OF THE DRAWINGS
Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiments with reference to the accompanying drawings, of which:
FIG. 1 is a schematic circuit diagram illustrating a conventional voltage-controlled oscillator;
FIG. 2 is a schematic circuit diagram illustrating an embodiment of a voltage-controlled oscillator according to this disclosure;
FIG. 3 is a schematic circuit diagram illustrating a small signal equivalent circuit model of the embodiment;
FIG. 4 is a schematic circuit diagram illustrating a single-side circuit of the small signal equivalent circuit model;
FIG. 5 is a schematic circuit diagram illustrating an equivalent circuit model of the embodiment seen into drain terminals of a first transistor and a second transistor of the embodiment;
FIG. 6 is a schematic diagram illustrating effective parasitic capacitance and resistance of the equivalent circuit model; and
FIG. 7 is a plot showing comparison between equivalent capacitances of the embodiment and a conventional VCO.



DETAILED DESCRIPTION
Before the disclosure is described in greater detail, it should be noted that like elements are denoted by the same reference numerals throughout the disclosure, and that the reference numerals used for the elements may also be used to represent property values of the elements, such as a resistance of a resistor, a capacitance of a capacitor/varactor, an inductance of an inductor, etc.
Referring to FIG. 2, an embodiment of a voltage-controlled oscillator (VCO) according to this disclosure is shown to include two first inductors (Ld), two varactors (Cd), a first transistor (M1), a second transistor (M2), two second inductors (Lg), a reversely tunable LC source degeneration module 5, a push-push circuit 6, and two buffer amplifier circuits 7.
The first inductors (Ld) have a common node 2 to which a first terminal of each first inductor (Ld) is coupled.
Each of the varactors (Cd) has a first terminal receiving a first bias voltage (VT1), a second terminal coupled to a second terminal of a respective one of the first inductors (Ld), and a capacitance associated with a magnitude of the first bias voltage (VT1). The capacitances of the varactors (Cd) may be changed by adjusting a magnitude of the first bias voltage (VT1).
The first transistor (M1) has a first terminal coupled to the second terminal of one of the varactors (Cd) and serving as a first output terminal 3, a second terminal, and a control terminal.
The second transistor (M2) has a first terminal coupled to the second terminal of the other one of the varactors (Cd) and serving as a second output terminal 4, a second terminal, and a control terminal.
In this embodiment, the first, second and control terminals of each of the first and second transistors (M1, M2) are respectively drain, source and gate terminals thereof.
One of the second inductors (Lg) is coupled between the control terminal of the first transistor (M1) and the first terminal of the second transistor (M2), which is the second output terminal 4. The other one of the second inductors (Lg) is coupled between the control terminal of the second transistor (M2) and the first terminal of the first transistor (M1), which is the first output terminal 3. Accordingly, the first transistor (M1), the second transistor (M2) and the second inductors (Lg) form a cross-connected pair.
The reversely tunable LC source degeneration module 5 is coupled between the second terminals of the first and second transistors (M1, M2) and ground, and includes two source inductors (Ls) and two source varactors (Cs) for source degeneration of the first and second transistors (M1, M2).
One of the source inductors (Ls) is coupled between the second terminal of the first transistor (M1) and a reference node (e.g., ground). The other one of the source inductors (Ls) is coupled between the second terminal of the second transistor (M2) and the reference node.
In such architecture, this embodiment of VCO may generate at the common node of the first inductors (Ld) an oscillating signal that has a carrier frequency of f0, and harmonics with frequencies of 2f0, 3f0, 4f0, etc. Accordingly, the common node of the first inductors (Ld) serves as an oscillating signal source node. In addition, this embodiment of VCO may also generate a first oscillatory signal and a second oscillatory signal respectively at the first and second output terminals 3, 4, and the first and second oscillatory signals form a differential signal pair in this embodiment.
The source varactors (Cs) have a common node to which a first terminal of each source varactor (Cs) is coupled and which receives a second bias voltage (VT2). Each source varactor (Cs) further has a second terminal coupled to the second terminal of a respective one of the first and second transistors (M1, M2), and a capacitance associated with a magnitude of the second bias voltage (VT2). The capacitances of the source varactors (Cs) may be changed by adjusting a magnitude of the second bias voltage (VT2).
The push-push circuit 6 is coupled to the oscillating signal source node 2 for receiving the oscillating signal therefrom, and to a first direct-current (DC) voltage source (VDD) to receive a first voltage for provision to the oscillating signal source node 2, and outputs an oscillatory output signal (Vout) having a frequency twice the carrier frequency of the oscillating signal.
In this embodiment, the push-push circuit 6 includes a power terminal 61 coupled to the first DC voltage source (VDD), an output terminal 62, a transmission line (Z), a DC blocking capacitor (C1), and a by-pass capacitor (Cp). It is noted that a resistor (R1) shown in FIG. 2 represents an output impedance of a load (e.g., a measuring instrument, not shown), which is generally 50 ohms.
The transmission line (Z) is coupled between the power terminal 61 and the oscillating signal source node 2, and has an impedance associated with one-quarter wavelength of a second harmonic of the oscillating signal (usually denoted as λ/4 (@2f0)). Accordingly, the second harmonic of the oscillating signal that has a frequency of 2f0 is not transmitted toward the left direction (i.e., toward the power terminal 61), and is only transmitted toward the right direction (i.e., toward the output terminal 62) to serve as the oscillatory output signal (Vout). On the other hand, other harmonics of the oscillating signal, which have the frequencies of f0, 3f0, 4f0, etc., may be transmitted toward the left direction.
The by-pass capacitor (Cp) is coupled between the power terminal 61 and the reference node for stabilizing input of the first voltage.
The DC blocking capacitor (C1) is coupled between the oscillating signal source node 2 and the output terminal 62 for blocking the DC component and allowing passage of the alternating current (AC) component only.
Each of the buffer amplifier circuits 7 has an amplifier input terminal 71 coupled to a respective one of the first and second output terminals 3, 4 for receiving therefrom and amplifying a respective one of the first and second oscillatory signals, and an amplifier output terminal 72 at which a respective one of a first amplified oscillatory signal, which serves as a first output signal (Vo1), and a second amplified oscillatory signal, which serves as a second output signal (Vo2), is outputted.
In this embodiment, each of the buffer amplifier circuits 7 includes an amplifier transistor (M3), a first DC blocking capacitor (C2), a high-frequency blocking inductor (L1) and a second DC blocking capacitor (C3). It is noted that each of resistors (R2) shown in FIG. 2 represents an output impedance of a load (e.g., a measuring instrument, not shown), which is generally 50 ohms.
The amplifier transistor (M3) has a first terminal coupled to a second DC voltage source (VDD2) and to the amplifier output terminal 72, a second terminal, and a control terminal coupled to the amplifier input terminal 71, and receiving a third voltage (VG) that causes the amplifier transistor (M3) to operate in a saturation region.
In this embodiment, the first, second and control terminals of each amplifier transistor (M3) are respectively drain, source and gate terminals thereof.
The first DC blocking capacitor (C2) is coupled between the control terminal of the amplifier transistor (M3) and the amplifier input terminal 71 for blocking the DC component and allowing passage of the AC component only.
The high-frequency blocking inductor (L1) has a first terminal coupled to the second voltage source (VDD2), and a second terminal coupled to the first terminal of the amplifier transistor (M3), thereby blocking the AC component and allowing passage of the DC component only.
The second DC blocking capacitor (C3) is coupled between the amplifier output terminal 72 and the first terminal of the amplifier transistor (M3) for blocking the DC component and allowing passage of the AC component only.
Since the operation principle for oscillation of the VCO should be familiar by persons with ordinary skills in the art, detail thereof is not described herein for the sake of brevity.
Referring to FIGS. 2 to 4, in order to facilitate description and reduce complexity of calculation, a portion of the circuit is omitted in FIGS. 3 and 4. FIG. 3 shows a small signal equivalent circuit model of the first inductor (Ld), the varactor (Cd), the second inductor (Lg), the first transistor (M1) and the second transistor (M2). FIG. 4 shows a small signal equivalent circuit model of a single-side circuit (the side of the first transistor (M1)) shown in FIG. 3 at resonance, where Rd represents a parasitic resistance of the first inductor (Ld) and the varactor (Cd). In the small signal equivalent circuit model, the first terminals of the first inductors (Ld) and the varactors (Cd) may be deemed to be virtually grounded. The corresponding first inductor (Ld) and varactor (Cd) may be characterized as an open circuit at resonance (jωLd=1/jωCd, where ω is a resonant frequency of the corresponding first inductor (Ld) and varactor (Cd)), and are thus omitted in FIG. 4.
In FIG. 4, the voltage gain (G1) of the single-side circuit may be derived as follows:




  
    
      
        
          V
          
            gs
            ⁢
            
              
            
            ⁢
            1
          
        
        =
        
          
            
              
                1
                ⁢
                
                  /
                
                ⁢
                j
                ⁢
                
                  
                
                ⁢
                ω
                ⁢
                
                  
                
                ⁢
                
                  C
                  
                    gs
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
              
              
                
                  1
                  ⁢
                  
                    /
                  
                  ⁢
                  j
                  ⁢
                  
                    
                  
                  ⁢
                  ω
                  ⁢
                  
                    
                  
                  ⁢
                  
                    C
                    
                      gs
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                
                +
                
                  j
                  ⁢
                  
                    
                  
                  ⁢
                  ω
                  ⁢
                  
                    
                  
                  ⁢
                  
                    L
                    g
                  
                
              
            
            ⁢
            
              v
              i
            
          
          =
          
            
              1
              
                1
                -
                
                  
                    ω
                    2
                  
                  ⁢
                  
                    L
                    g
                  
                  ⁢
                  
                    C
                    
                      gs
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                
              
            
            ⁢
            
              v
              i
            
          
        
      
    
    
      
        (
        1
        )
      
    
  
  
    
      
        
          v
          o
        
        =
        
          
            
              -
              
                g
                m
              
            
            ⁢
            
              V
              
                gs
                ⁢
                
                  
                
                ⁢
                1
              
            
            ⁢
            
              R
              d
            
          
          =
          
            
              
                
                  -
                  
                    g
                    m
                  
                
                ⁢
                
                  R
                  d
                
              
              
                1
                -
                
                  
                    ω
                    2
                  
                  ⁢
                  
                    L
                    g
                  
                  ⁢
                  
                    C
                    
                      gs
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                
              
            
            ⁢
            
              v
              i
            
          
        
      
    
    
      
        (
        2
        )
      
    
  
  
    
      
        
          G
          1
        
        =
        
          
            
              v
              o
            
            
              v
              i
            
          
          =
          
            
              
                
                  -
                  
                    g
                    m
                  
                
                ⁢
                
                  R
                  d
                
              
              
                1
                -
                
                  
                    ω
                    2
                  
                  ⁢
                  
                    L
                    g
                  
                  ⁢
                  
                    C
                    
                      gs
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                
              
            
            =
            
              G
              2
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




In the above, Vgs1 represents a gate-source voltage of the first transistor (M1), Cgs1 represents a gate-source capacitance of the first transistor (M1), vi, vo are respectively assumed equivalent input and output voltages, gm represents a transconductance of the first transistor (M1), G2 represents a voltage gain of the single-side circuit of the second transistor (M2). As shown below, the total gain (G) of the entire circuit is a product of the gains (G1, G2) of both sides of the circuit:





  
    
      
        G
        =
        
          
            
              G
              1
            
            ·
            
              G
              2
            
          
          =
          
            
              
                g
                m
                2
              
              ⁢
              
                R
                d
                2
              
            
            
              
                (
                
                  1
                  -
                  
                    
                      ω
                      2
                    
                    ⁢
                    
                      L
                      g
                    
                    ⁢
                    
                      C
                      
                        gs
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                  
                
                )
              
              2
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




According to equation (4), in absence of the second inductors (Lg), the total gain (G) will be gm2Rd2. The addition of the second inductors (Lg) can increase the total gain (G) of the circuit loop, which increases the likelihood that the oscillator satisfies the condition for oscillation: total gain (G)≧1. When the total gain (G) of the circuit has been determined, the addition of the second inductors (Lg) may reduce the requirement for the transconductance (gm) of each of the first and second transistors (M1, M2) resulting in lower power consumption.
Referring to FIGS. 2, 5 and 6, FIG. 5 shows an equivalent circuit model seen into the drain terminals of the first and second transistors (M1, M2).
An equivalent capacitance (CEQ) and an equivalent resistance (REQ) seen into the cross-connected pair from the first terminal of each of the first and second transistors (M1, M2) (that is, the common node of the gate terminal of the first transistor (M1) and the drain terminal of the second transistor (M2) or the common node of the gate terminal of the second transistor (M2) and the drain terminal of the first transistor (M1)) may be derived as follows:




  
    
      
        
          R
          EQ
        
        =
        
          
            2
            
              -
              
                g
                m
              
            
          
          ·
          
            
              1
              +
              
                
                  
                    (
                    
                      ω
                      
                        ω
                        T
                      
                    
                    )
                  
                  2
                
                ⁢
                
                  
                    (
                    
                      1
                      +
                      
                        
                          C
                          s
                        
                        
                          C
                          gs
                          ′
                        
                      
                    
                    )
                  
                  2
                
              
              -
              
                2
                ⁢
                
                  
                    (
                    
                      
                        ω
                        1
                      
                      
                        ω
                        2
                      
                    
                    )
                  
                  2
                
                ⁢
                
                  (
                  
                    1
                    +
                    
                      
                        C
                        s
                      
                      
                        C
                        gs
                        ′
                      
                    
                  
                  )
                
              
              +
              
                
                  ω
                  1
                  4
                
                
                  
                    ω
                    2
                  
                  ⁢
                  
                    ω
                    T
                    2
                  
                
              
            
            
              
                
                  
                    (
                    
                      ω
                      
                        ω
                        T
                      
                    
                    )
                  
                  2
                
                ⁢
                
                  
                    C
                    s
                  
                  
                    C
                    gs
                    ′
                  
                
                ⁢
                
                  (
                  
                    2
                    +
                    
                      
                        C
                        s
                      
                      
                        C
                        gs
                        ′
                      
                    
                  
                  )
                
              
              -
              
                2
                ⁢
                
                  
                    (
                    
                      
                        ω
                        1
                      
                      
                        ω
                        T
                      
                    
                    )
                  
                  2
                
                ⁢
                
                  (
                  
                    1
                    +
                    
                      
                        C
                        s
                      
                      
                        C
                        gs
                        ′
                      
                    
                  
                  )
                
              
              +
              
                
                  ω
                  1
                  4
                
                
                  
                    ω
                    2
                  
                  ⁢
                  
                    ω
                    T
                    2
                  
                
              
            
          
        
      
    
    
      
        (
        5
        )
      
    
  
  
    
      
        
          C
          EQ
        
        =
        
          
            
              C
              s
            
            2
          
          ·
          
            
              
                
                  ω
                  2
                  2
                
                
                  ω
                  2
                
              
              +
              
                
                  
                    ω
                    1
                    2
                  
                  
                    ω
                    T
                    2
                  
                
                ⁢
                
                  
                    ω
                    2
                    2
                  
                  
                    ω
                    2
                  
                
              
              +
              
                
                  
                    ω
                    2
                  
                  
                    ω
                    T
                    2
                  
                
                ⁢
                
                  (
                  
                    1
                    +
                    
                      
                        C
                        s
                      
                      
                        C
                        gs
                        ′
                      
                    
                  
                  )
                
              
              -
              
                
                  ω
                  1
                  2
                
                
                  ω
                  T
                  2
                
              
              -
              
                
                  
                    ω
                    2
                    2
                  
                  
                    ω
                    T
                    2
                  
                
                ⁢
                
                  (
                  
                    1
                    +
                    
                      
                        C
                        s
                      
                      
                        C
                        gs
                        ′
                      
                    
                  
                  )
                
              
              -
              1
            
            
              
                
                  ω
                  1
                  4
                
                
                  
                    ω
                    2
                  
                  ⁢
                  
                    ω
                    T
                    2
                  
                
              
              +
              
                
                  
                    ω
                    2
                  
                  
                    ω
                    T
                    2
                  
                
                ⁢
                
                  
                    (
                    
                      1
                      +
                      
                        
                          C
                          s
                        
                        
                          C
                          gs
                          ′
                        
                      
                    
                    )
                  
                  2
                
              
              -
              
                2
                ⁢
                
                  
                    ω
                    1
                    2
                  
                  
                    ω
                    T
                    2
                  
                
                ⁢
                
                  (
                  
                    1
                    +
                    
                      
                        C
                        s
                      
                      
                        C
                        gs
                        ′
                      
                    
                  
                  )
                
              
              +
              1
            
          
        
      
    
    
      
        (
        6
        )
      
    
  




where ω=1/√{square root over (LdCd)}, ω1=1/√{square root over (LsCgs′)}, ω2=1/√{square root over (LsCs)}, ωT=gm/Cgs′,





  
    
      C
      gs
      ′
    
    =
    
      
        C
        gs
      
      
        (
        
          1
          -
          
            
              ω
              0
              2
            
            ⁢
            
              L
              g
            
            ⁢
            
              C
              gs
            
          
        
        )
      
    
  
  ,




Cgs is a gate-source capacitance of each of the first and second transistors (M1, M2), ω0 is a frequency of each of the first and second oscillatory signals, ω is a resonant frequency of the first inductor (Ld) and the varactor (Cd), ω1 is a resonant frequency of the source inductor (Ls) and the gate-source capacitance (Cgs) of the corresponding transistor (M1, M2), ω2 is a resonant frequency of the source inductor (Ls) and the corresponding source capacitor (Cs), ωT is a current-gain cut-off frequency of each of the first transistor (M1) and the second transistor (M2). When ωT>>ω1 and ωT>>ω2, equations (5), (6) may be simplified as:





  
    
      
        
          R
          EQ
        
        =
        
          
            2
            
              -
              
                g
                m
              
            
          
          ·
          
            
              1
              +
              
                
                  
                    (
                    
                      ω
                      
                        ω
                        T
                      
                    
                    )
                  
                  2
                
                ⁢
                
                  
                    (
                    
                      1
                      +
                      
                        
                          C
                          s
                        
                        
                          C
                          gs
                          ′
                        
                      
                    
                    )
                  
                  2
                
              
            
            
              
                
                  (
                  
                    ω
                    
                      ω
                      T
                    
                  
                  )
                
                2
              
              ⁢
              
                
                  C
                  s
                
                
                  C
                  gs
                  ′
                
              
              ⁢
              
                (
                
                  2
                  +
                  
                    
                      C
                      s
                    
                    
                      C
                      gs
                      ′
                    
                  
                
                )
              
            
          
        
      
    
    
      
        (
        7
        )
      
    
  
  
    
      
        
          C
          EQ
        
        =
        
          
            
              C
              s
            
            2
          
          ·
          
            
              
                
                  
                    ω
                    2
                  
                  
                    ω
                    T
                    2
                  
                
                ⁢
                
                  (
                  
                    1
                    +
                    
                      
                        C
                        s
                      
                      
                        C
                        gs
                        ′
                      
                    
                  
                  )
                
              
              -
              1
            
            
              
                
                  
                    ω
                    2
                  
                  
                    ω
                    T
                    2
                  
                
                ⁢
                
                  
                    (
                    
                      1
                      +
                      
                        
                          C
                          s
                        
                        
                          C
                          gs
                          ′
                        
                      
                    
                    )
                  
                  2
                
              
              +
              1
            
          
        
      
    
    
      
        (
        8
        )
      
    
  




It is known from equation (8) that Cs/Cgs is reduced when Cs becomes small, thereby reducing the equivalent capacitance (CEQ).

In the VCO, since the corresponding first inductor (Ld), varactor (Cd) and equivalent capacitance (CEQ) form an LC resonant structure, reducing the equivalent capacitance (CEQ) may result in a smaller total capacitance (C) (i.e., an equivalent capacitance of the varactor (Cd) and the equivalent capacitance (CEQ) that are coupled in parallel), which may lead to higher operation frequency (f0) of the VCO because the operating frequency (f0) of the VCO is determined according to the total inductance (L) and the total capacitance (C) of the LC resonant structure:




  
    
      
        
          f
          o
        
        =
        
          1
          
            2
            ⁢
            π
            ⁢
            
              
                
                  L
                  d
                
                ⁡
                
                  (
                  
                    
                      C
                      d
                    
                    +
                    
                      2
                      ⁢
                      
                        C
                        EQ
                      
                    
                    +
                    
                      C
                      other
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        9
        )
      
    
  




where Cother represents an equivalent capacitance of source-drain capacitance of the first transistor (M1) and the second transistor (M2) and a capacitance seen into the third transistor (M3) from the corresponding one of the first output terminal 3 and the second output terminal 4. According to equations (6) and (9), in some embodiments, the inductors (Lg, Ls), the capacitor (Cs) and dimensions (e.g., channel widths) of the transistors (M1, M2) which are associated with the transconductance (gm) and the gate-source capacitance (Cgs) may be appropriately designed such that





  
    [
    
      
        
          ω
          2
          2
        
        
          ω
          2
        
      
      +
      
        
          
            ω
            1
            2
          
          
            ω
            T
            2
          
        
        ⁢
        
          
            ω
            2
            2
          
          
            ω
            2
          
        
      
      +
      
        
          
            ω
            2
          
          
            ω
            T
            2
          
        
        ⁢
        
          (
          
            1
            +
            
              
                C
                s
              
              
                C
                gs
                ′
              
            
          
          )
        
      
    
    ]
  
  <
  
    
      [
      
        
          
            ω
            1
            2
          
          
            ω
            T
            2
          
        
        +
        
          
            
              ω
              2
              2
            
            
              ω
              T
              2
            
          
          ⁢
          
            (
            
              1
              +
              
                
                  C
                  s
                
                
                  C
                  gs
                  ′
                
              
            
            )
          
        
        +
        1
      
      ]
    
    .
  




In this case, the numerator of equation (8) would be negative, thereby resulting in a negative equivalent capacitance (CEQ), and thus a higher operating frequency (f0).

In addition, when the equivalent capacitance (CEQ) becomes smaller, the varactor (Cd) occupies a relatively larger proportion of the total capacitance (C) of the LC resonant structure. Therefore, adjustment of the capacitance of the varactor (Cd) can have a larger effect on the total capacitance (C), thereby resulting in a larger adjustable range of the operating frequency.
A phase noise of this embodiment may be derived using the Lesson's formula as follows:




  
    
      
        
          L
          ⁡
          
            (
            
              Δ
              ⁢
              
                
              
              ⁢
              f
            
            )
          
        
        =
        
          10
          ⁢
          log
          ⁢
          
            {
            
              
                
                  [
                  
                    1
                    +
                    
                      
                        (
                        
                          
                            f
                            o
                          
                          
                            2
                            ⁢
                            Δ
                            ⁢
                            
                              
                            
                            ⁢
                            fQ
                          
                        
                        )
                      
                      2
                    
                  
                  ]
                
                ⁢
                
                  (
                  
                    1
                    +
                    
                      
                        f
                        c
                      
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        f
                      
                    
                  
                  )
                
                ⁢
                
                  FkT
                  
                    2
                    ⁢
                    
                      P
                      av
                    
                  
                
              
              +
              
                
                  2
                  ⁢
                  
                    kTRK
                    VCO
                    2
                  
                
                
                  
                    (
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      f
                    
                    )
                  
                  2
                
              
            
            }
          
        
      
    
    
      
        (
        10
        )
      
    
  




where L(Δf) represents the phase noise (unit: dBc/Hz) when a frequency offset from a carrier frequency (f0) is Δf, fc represents a flicker noise corner frequency (unit: Hz), Q represents a loaded quality factor, F represents a noise factor, k is the Boltzmann constant (unit: J/K), T represents a temperature (unit: K), Pav represents an average power at the output of the VCO, R represents an equivalent noise resistance of each source varactor (Cs), and Kvco represents an oscillator voltage gain (unit: Hz/V).

It is known from equation (9) that the phase noise (L(Δf)) may be reduced by reducing the oscillator voltage gain (Kvco). When the inductors (Ls) have been determined, the oscillator voltage gain (Kvco) is a ratio dC/dV of the source varactor (Cs), which means that it is better to bias the source varactors (Cs) in a low Kvco mode rather than a high Kvco mode, thereby obtaining better phase noise (L(Δf)). Biasing in the Kvco mode refers to biasing at a voltage-frequency conversion mode, wherein the low Kvco mode refers to a configuration corresponding to a C-V curve with a low steepness slope the high Kvco mode refers to a configuration corresponding to a C-V curve with a high steepness slope, and the slope of the C-V curve refers to a ratio (dC/dV) of each source varactor (Cs).
Referring back to FIG. 2, in this embodiment, the first transistor (M1) and the second transistor (M2) can form the oscillating signal with a carrier frequency




  
    f
    o
  
  =
  
    1
    
      2
      ⁢
      π
      ⁢
      
        
          
            L
            d
          
          ⁡
          
            (
            
              
                C
                d
              
              +
              
                2
                ⁢
                
                  C
                  EQ
                
              
              +
              
                C
                other
              
            
            )
          
        
      
    
  




at the oscillating signal source node 2 (in this embodiment, the carrier frequency (f0) is designed to be 30 GHz). Since the transmission line (Z) has an impedance of λ/4 (@2f0), the transmission line (Z) serves as an open circuit when a signal transmitted thereon has a frequency of 2f0, and has a relatively low impedance with respect to the other high-harmonic frequencies. Accordingly, only the oscillatory output signal (Vout) with the frequency of 2f0 (i.e., 60 GHz for this embodiment) may be provided at the output terminal 62. By virtue of the push-push circuit 6, the signals that respectively have the two frequencies of f0 and 2f0 may be outputted at the same time.

FIG. 7 shows comparison between the equivalent capacitances (CEQ) of the embodiment and a conventional VCO which does not include the inductors (Lg, Ls) and the varactors (Cs) of the embodiment. It can be seen from FIG. 7 that in a case that the equivalent capacitance (CEQ) of the conventional VCO is configured to be 0.5Cgs, the equivalent capacitance (CEQ) of this embodiment is adjustable according to the capacitor (Cs), and may even be adjusted to be negative. By virtue of such design, a VCO of 94 GHz may be realized using a relatively cheaper process of 90 nm CMOS technology.
In summary, the embodiment of the VCO according to this disclosure has the following advantages:
1. The reversely tunable source degeneration module 5 may contribute to reduce the equivalent capacitance (CEQ) of the first and second transistors (M1, M2), thereby significantly improving upon the operating frequency and the adjustable frequency range.
2. The second inductors (Lg) at the gate terminals of the first and second transistors (M1, M2) can improve the total gain (G) of the circuit loop, and increase the likelihood that the oscillator satisfies the condition for oscillation: total gain (G)≧1. When the total gain (G) of the circuit has been determined, the addition of the second inductors (Lg) may reduce the requirement for the transconductance (gm) of each of the first and second transistors (M1, M2), resulting in lower power consumption.
3. The first inductors (Ld) and the source inductors (Ls) are added so that a DC voltage drop between the oscillating signal source node 2 and ground may be omitted, thereby significantly reducing the supply voltage required by the entire circuit, and reducing power consumption in comparison to conventional techniques.
4. The reversely tunable source degeneration module 5 may contribute to reduce the phase noise (L(Δf)) via reducing the oscillator voltage gain (Kvco) by changing the second bias voltage (VT2) to adjust Kvco mode in which the source varactors (Cs) are biased.
5. The push-push circuit 6 may contribute to provide outputs with two different frequencies, thereby achieving a dual-band output.
While the disclosure has been described in connection with what is considered the exemplary embodiment, it is understood that this disclosure is not limited to the disclosed embodiment but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.

## Claims

1. A voltage-controlled oscillator comprising:
two first inductors having a common node, each of said first inductors having a first terminal coupled to said common node, and a second terminal;
two first varactors, each having a first terminal disposed to receive a first bias voltage, a second terminal coupled to said second terminal of a respective one of said first inductors, and a capacitance associated with a magnitude of the first bias voltage;
a cross-connected pair including:
a first transistor and a second transistor, each having a first terminal coupled to said second terminal of a respective one of said first varactors, a second terminal and a control terminal; and
two second inductors, one of which is coupled between said control terminal of said first transistor and said first terminal of said second transistor, and the other one of which is coupled between said control terminal of said second transistor and said first terminal of said first transistor; and

a reversely tunable source degeneration module coupled to said second terminals of said first and second transistors, configured for source degeneration of said first and second transistors, and cooperating with said first and second transistors and said second inductors to form a negative equivalent capacitance seen into said cross-connected pair from said first terminal of each of said first and second transistors,
wherein a first oscillatory signal is provided at said first terminal of said first transistor, and a second oscillatory signal is provided at said first terminal of said second transistor,
wherein said reversely tunable source degeneration module includes:
two source inductors, one of which is disposed to couple said second terminal of said first transistor to a reference node, and the other one of which is disposed to couple said second terminal of said second transistor to the reference node; and
two source varactors having a common node disposed to receive a second bias voltage, each of said source varactors having a first terminal coupled to said common node of said source varactors, a second terminal coupled to said second terminal of a respective one of said first and second transistors, and a capacitance associated with a magnitude of the second bias voltage,

the voltage-controlled oscillator further satisfying





  
    
      [
      
        
          
            ω
            2
            2
          
          
            ω
            2
          
        
        +
        
          
            
              ω
              1
              2
            
            
              ω
              T
              2
            
          
          ⁢
          
            
              ω
              2
              2
            
            
              ω
              2
            
          
        
        +
        
          
            
              ω
              2
            
            
              ω
              T
              2
            
          
          ⁢
          
            (
            
              1
              +
              
                
                  C
                  s
                
                
                  C
                  gs
                  ′
                
              
            
            )
          
        
      
      ]
    
    <
    
      [
      
        
          
            ω
            1
            2
          
          
            ω
            T
            2
          
        
        +
        
          
            
              ω
              2
              2
            
            
              ω
              T
              2
            
          
          ⁢
          
            (
            
              1
              +
              
                
                  C
                  s
                
                
                  C
                  gs
                  ′
                
              
            
            )
          
        
        +
        1
      
      ]
    
  
  ,



where ω=1/√{square root over (LdCd)}, ω1=1/√{square root over (LsCgs′)}, ω2=1/√{square root over (LsCs)}, ωT=gm/Cgs′,





  
    
      C
      gs
      ′
    
    =
    
      
        C
        gs
      
      
        (
        
          1
          -
          
            
              ω
              0
              2
            
            ⁢
            
              L
              g
            
            ⁢
            
              C
              gs
            
          
        
        )
      
    
  
  ,



ω0 represents a frequency of each of the first and second oscillatory signals, Cs represents a capacitance of each of said source varactors, Ld represents an inductance of each of said first inductors, Cd represents a capacitance of each of said first varactors, Ls represents an inductance of each of said second inductors, gm represents a transconductance of each of said first and second transistors, and Cgs represents a gate-source capacitance of each of said first and second transistors.

2. The voltage-controlled oscillator of claim 1, wherein said common node of said first inductors serves as an oscillating signal source node at which an oscillating signal is provided, said voltage-controlled oscillator further comprising:
a push-push circuit coupled to said oscillating signal source node for receiving the oscillating signal therefrom, and configured to output an oscillatory output signal having a frequency that is twice a frequency of the oscillating signal.

3. The voltage-controlled oscillator of claim 2, wherein said push-push circuit includes:
a power terminal to be coupled to a first voltage source; and
a transmission line coupled between said power terminal and said oscillating signal source node, and having an impedance associated with one-quarter wavelength of a second harmonic of the oscillating signal.

4. The voltage-controlled oscillator of claim 3, wherein said push-push circuit further includes:
an output terminal at which the oscillatory output signal is outputted;
a by-pass capacitor disposed to couple the power terminal to the reference node; and
a direct-current (DC) blocking capacitor coupled between said oscillating signal source node and said output terminal.

5. The voltage-controlled oscillator of claim 3, further comprising:
two buffer amplifier circuits, each being coupled to said first terminal of the respective one of said first and second transistors for receiving therefrom and amplifying a respective one of the first and second oscillatory signals, and being configured to output a respective one of a first amplified oscillatory signal and a second amplified oscillatory signal.

6. The voltage-controlled oscillator of claim 5, wherein each of said buffer amplifier circuits includes:
an amplifier output terminal at which the respective one of a first amplified oscillatory signal and a second amplified oscillatory signal is outputted; and
an amplifier transistor having a first terminal that is to be coupled to a second voltage source and that is coupled to said amplifier output terminal, a second terminal, and a control terminal that is coupled to said first terminal of the respective one of said first and second transistors, and that is disposed to receive a third voltage that causes said amplifier transistor to operate in a saturation region.

7. The voltage-controlled oscillator of claim 6, wherein each of said buffer amplifier circuits further includes:
a first direct-current (DC) blocking capacitor coupled between said control terminal of said amplifier transistor and said first terminal of the respective one of said first and second transistors;
a high-frequency blocking inductor having a first terminal to be coupled to the second voltage source, and a second terminal coupled to said first terminal of said amplifier transistor; and
a second DC blocking capacitor coupled between said amplifier output terminal and said first terminal of said amplifier transistor.

8. The voltage-controlled oscillator of claim 1, wherein said common node of said first inductors serves as an oscillating signal source node at which an oscillating signal is provided, said voltage-controlled oscillator further comprising:
a push-push circuit coupled to said oscillating signal source node for receiving the oscillating signal therefrom, and configured to output an oscillatory output signal having a frequency that is twice a frequency of the oscillating signal.

9. The voltage-controlled oscillator of claim 8, wherein said push-push circuit includes:
a power terminal to be coupled to a first voltage source; and
a transmission line coupled between said power terminal and said oscillating signal source node, and having an impedance associated with one-quarter wavelength of a second harmonic of the oscillating signal.

10. The voltage-controlled oscillator of claim 9, wherein said push-push circuit further includes:
an output terminal at which the oscillatory output signal is outputted;
a by-pass capacitor disposed to couple the power terminal to the reference node; and
a direct-current (DC) blocking capacitor coupled between said oscillating signal source node and said output terminal.

11. The voltage-controlled oscillator of claim 9, further comprising:
two buffer amplifier circuits, each being coupled to said first terminal of the respective one of said first and second transistors for receiving therefrom and amplifying a respective one of the first and second oscillatory signals, and being configured to output a respective one of a first amplified oscillatory signal and a second amplified oscillatory signal.

12. The voltage-controlled oscillator of claim 11, wherein each of said buffer amplifier circuits includes:
an amplifier output terminal at which the respective one of a first amplified oscillatory signal and a second amplified oscillatory signal is outputted; and
an amplifier transistor having a first terminal that is to be coupled to a second voltage source and that is coupled to said amplifier output terminal, a second terminal, and a control terminal that is coupled to said first terminal of the respective one of said first and second transistors, and that is disposed to receive a third voltage that causes said amplifier transistor to operate in a saturation region.

13. The voltage-controlled oscillator of claim 12, wherein each of said buffer amplifier circuits further includes:
a first direct-current (DC) blocking capacitor coupled between said control terminal of said amplifier transistor and said first terminal of the respective one of said first and second transistors;
a high-frequency blocking inductor having a first terminal to be coupled to the second voltage source, and a second terminal coupled to said first terminal of said amplifier transistor; and
a second DC blocking capacitor coupled between said amplifier output terminal and said first terminal of said amplifier transistor.