# Patent

## Title
Integrated circuit devices including source/drain extension regions and methods of forming the same

## Abstract

Integrated circuit devices may include a stack that includes channel regions and gate electrodes stacked in an alternating sequence in a vertical direction. The channel regions may include impurities having a first conductivity type. The integrated circuit devices may also include source/drain regions on respective opposing sides of the stack, and the source/drain regions may be spaced apart from each other in a horizontal direction and may include impurities having a second conductivity type that is different from the first conductivity type. The integrated circuit devices may further include extension regions that may be between respective ones of channel regions and one of the source/drain regions and may include impurities having the second conductivity type. Each of the extension regions may have a thickness in the vertical direction that is less than those of the channel regions and the one of the source/drain regions.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority of U.S. Provisional Application Ser. No. 62/092,179, entitled HIGH PERFORMANCE FINFET AND NANOSHEET DEVICES WITH LOW BAND TO BAND TUNNELING, filed in the USPTO on Dec. 15, 2014, the disclosure of which is hereby incorporated by reference in its entirety.


FIELD
The present disclosure generally relates to the field of electronics and, more particularly, to methods of forming integrated circuit devices.
BACKGROUND
Field-Effect Transistors (FETs) including high mobility channel materials have been developed to increase carrier mobility. However, those high mobility channel materials may cause higher leakage currents due to a larger band-to-band tunneling (BTBT) current in a drain region.
SUMMARY
An integrated circuit device may include a stack on a substrate. The stack may include a plurality of channel regions and a plurality of gate electrodes stacked in an alternating sequence in a vertical direction that is perpendicular to a surface of the substrate, and the plurality of channel regions may include impurities having a first conductivity type. The integrated circuit device may also include source/drain regions on respective opposing sides of the stack. The source/drain regions may be spaced apart from each other in a horizontal direction that is parallel to the surface of the substrate and may include impurities having a second conductivity type that is different from the first conductivity type. The integrated circuit device may further include a plurality of extension regions that may be between respective ones of the plurality of channel regions and one of the source/drain regions and may include impurities having the second conductivity type. Each of the plurality of extension regions may have a thickness in the vertical direction that is less than those of the plurality of channel regions and the one of the source/drain regions.
In various embodiments, a width of the plurality of gate electrodes in the horizontal direction may be less than a width of the plurality of channel regions in the horizontal direction.
According to various embodiments, each of the plurality of channel regions may overlap with the plurality of gate electrodes in plan view, and the thickness of the plurality of channel regions in the vertical direction may be uniform.
According to various embodiments, the thickness of each of the plurality of extension regions may decrease in the horizontal direction toward the one of the source/drain regions.
According to various embodiments, the thickness of each of the plurality of extension regions may decrease and then increase in the horizontal direction toward the one of the source/drain regions.
In various embodiments, the plurality of gate electrodes may be spaced apart from the one of the source/drain regions, and the device may further include a plurality of insulation layers between respective ones of the plurality of gate electrodes and the one of the source/drain regions. The plurality of insulation layers may have a dielectric constant lower than silicon oxide.
In various embodiments, an impurity concentration of the source/drain regions may be greater than an impurity concentration of the plurality of extension regions.
According to various embodiments, the source/drain regions and the plurality of extension regions may include a same material and composition.
An integrated circuit device may include a channel region extending from a substrate in a vertical direction that is perpendicular to a surface of the substrate. The channel region may include impurities having a first conductivity type and opposing sides spaced apart from each other in a first horizontal direction that is parallel to the surface of the substrate. The integrated circuit device may also include a gate electrode on the channel region and source/drain regions on the respective opposing sides of the channel region. The source/drain regions may include impurities having a second conductivity type that is different from the first conductivity type. The integrated circuit device may further include an extension region between the channel region and one of the source/drain regions. The extension region may include impurities having the second conductivity type and may have a width in a second horizontal direction that is perpendicular to the first horizontal direction less than those of the channel region and the one of the source/drain regions.
In various embodiments, a width of the gate electrode in the first horizontal direction may be less than a width of the channel region in the first horizontal direction.
According to various embodiments, the channel region may overlap with the gate electrode in plan view, and the width of the channel region in the second horizontal direction may be uniform.
In various embodiments, the width of the extension region in the second horizontal direction may be uniform.
In various embodiments, the width of the extension region in the second horizontal direction may decrease and then increase in the first horizontal direction toward the one of the source/drain regions.
According to various embodiments, the extension region may have a recessed upper surface when viewed in a cross section that is perpendicular to the second horizontal direction.
In various embodiments, an impurity concentration of the source/drain regions may be greater than an impurity concentration of the extension region.
In various embodiments, the source/drain regions and the extension region may include a same material and composition.
An integrated circuit device may include a channel region on a substrate, and the channel region may include impurities having a first conductivity type. The integrated circuit device may also include a gate electrode on the channel region and source/drain regions on respective opposing sides of the channel region. The source/drain regions may be spaced apart from each other in a first direction and may include impurities having a second conductivity type that is different from the first conductivity type. The integrated circuit device may further include an extension region between the channel region and one of the source/drain regions, and the extension region may include impurities having the second conductivity type and may have a cross-sectional area perpendicular to the first direction that is less than those of the channel region and the one of the source/drain regions.
In various embodiments, the channel region may overlap with the gate electrode in plan view, and the cross-sectional area of the channel region perpendicular to the first direction may be uniform.
According to various embodiments, the cross-sectional area of the extension region may decrease along the first direction toward the one of the source/drain regions.
According to various embodiments, an impurity concentration of the source/drain regions may be greater than an impurity concentration of the extension region.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view illustrating an integrated circuit device according to some embodiments of the present inventive concepts.
FIGS. 2 and 3 are cross-sectional views, taken along the line A-A′ of FIG. 1, illustrating integrated circuit devices according to some embodiments of the present inventive concepts.
FIGS. 4A, 5 and 6 are plan views of FIG. 1 illustrating integrated circuit devices according to some embodiments of the present inventive concepts.
FIG. 4B is a cross-sectional view taken along the line B-B′ of FIG. 4A.
FIG. 7A is a perspective view and FIGS. 7B and 8 through 13 are cross-sectional views, taken along the line C-C′ of FIG. 7A, illustrating intermediate structures provided as portions of a method of forming an integrated circuit device according to some embodiments of the present inventive concepts.
FIG. 14 is a perspective view and FIGS. 15 through 20 are cross-sectional views, taken along the line D-D′ of FIG. 14, illustrating intermediate structures provided as portions of a method of forming an integrated circuit device according to some embodiments of the present inventive concepts.
FIGS. 21A and 22A are perspective views and FIGS. 21B, 22B and 23 through 26 are plan views illustrating intermediate structures provided as portions of a method of forming an integrated circuit device according to some embodiments of the present inventive concepts.
FIGS. 27, 28, 29A and 30 through 34 are plan views and FIG. 29B is a cross-sectional view, taken along the line E-E′ of FIG. 29A, illustrating intermediate structures provided as portions of a method of forming an integrated circuit device according to some embodiments of the present inventive concepts.
FIGS. 35, 36, 37A, 38 and 39 are plan views and FIG. 37B is a cross-sectional view, taken along the line F-F′ of FIG. 37A, illustrating intermediate structures provided as portions of a method of forming an integrated circuit device according to some embodiments of the present inventive concepts.



DETAILED DESCRIPTION
Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the spirit and teachings of this disclosure and so the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout.
Example embodiments of the present inventive concepts are described herein with reference to cross-sectional or perspective views that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the present inventive concepts should not be construed as limited to the particular shapes illustrated herein but include deviations in shapes that result, for example, from manufacturing.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of the stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element is referred to as being “coupled,” “connected,” or “responsive” to, or “on,” another element, it can be directly coupled, connected, or responsive to, or on, the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly coupled,” “directly connected,” or “directly responsive” to, or “directly on,” another element, there are no intervening elements present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the teachings of the present embodiments.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.
Using high mobility channel materials may not improve device performances as anticipated due to a higher leakage current in a drain region. As appreciated by the present inventors, localized confinement in a high gate-drain field region may increase a bandgap and may decrease Band to Band Tunneling (BTBT) leakage current in a drain region. In some embodiments according to the present inventive concepts, integrated circuit devices may include a source/drain extension region that has a portion having a cross-sectional area smaller than a cross-sectional area of a channel region, and junctions may be formed adjacent the portion of the source/drain extension region that has a cross-sectional area smaller than a cross-sectional area of the channel region.
FIG. 1 is a perspective view illustrating an integrated circuit device according to some embodiments of the present inventive concepts. FIGS. 2 and 3 are cross-sectional views, taken along the line A-A′ of FIG. 1, illustrating an integrated circuit device according to some embodiments of the present inventive concepts. FIGS. 4A, 5 and 6 are plan views of FIG. 1 illustrating an integrated circuit device according to some embodiments of the present inventive concepts, and FIG. 4B is a cross-sectional view, taken along the line B-B′ of FIG. 4A.
Referring to FIGS. 1 and 2, an integrated circuit device may include a substrate 100. The substrate 190 may be a bulk silicon substrate, a semiconductor on insulator (SOI) substrate or an insulator (e.g., buried oxide) on a substrate. In some embodiments, the substrate 100 may include one or more semiconductor materials, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs) or silicon germanium carbon (SiGeC).
The device may include channel regions 150-1 on the substrate 100. The channel regions 150-1 may include, for example, indium gallium arsenide (InGaAs), indium antimonide (InSb), silicon (Si), silicon germanium (SiGe) and/or germanium (Ge). Each of the channel regions 150-1 may have opposing sides that are spaced apart from each other in a first horizontal direction (X direction). The X direction may be substantially parallel to a surface of the substrate 100. Each of the channel regions 150-1 may have a middle portion in the X direction that has a substantially uniform thickness in a vertical direction (Z direction) along the X direction as illustrated in FIG. 2. The Z direction may be substantially perpendicular to the surface of the substrate 100. The thickness of the middle portion of the channel regions 150-1 in the Z direction may be greater than about 6 nm. The thickness of the middle portion of the channel regions 150-1 may be determined to provide sufficient carrier mobility. Although FIG. 2 shows two channel regions 150-1, the inventive concepts are not limited thereto. In some embodiments, the device may include more than three channel regions stacked on the substrate 100 in the Z direction.
The device may also include source/drain regions 410 on the opposing sides of the channel regions 150-1 and source/drain extension regions 400-1 between the channel regions 150-1 and the source/drain regions 410. In some embodiments, the source/drain regions 410 and the source/drain extension regions 400-1 may include materials substantially same as the channel regions 150-1. In some embodiments, the source/drain regions 410 and the source/drain extension regions 400-1 may include the same material and composition. The source/drain regions 410 an the source/drain extension region 400-1 may include first impurities having a first conductivity type, and a first impurity concentration of the source/drain regions 410 may be greater than a first impurity concentration of the source/drain extension regions 400-1. The channel regions 150-1 may include second impurities having a second conductivity type that is different from the first conductivity type.
The source/drain extension regions 400-1 may have a portion having a thickness in the Z direction that is less than the thickness of the the middle portion of the channel regions 150-1 in the Z direction to suppress Band to Band Tunneling (BTBT) current between the channel regions 150-1 to the source/drain regions 410. The source/drain extension regions 400-1 may have a varying thickness in the Z direction that decreases along the X direction from the channel regions 150-1 to the source/drain regions 410 and may have a minimum thickness adjacent the source/drain regions 410 as illustrated in FIG. 2. The minimum thickness of the source/drain extension regions 400-1 in the Z direction may be about 2 nm to about 4 nm. In some embodiments, a portion of the channel regions 150-1 adjacent the source/drain extension regions 400-1 may have a thickness in the Z direction that is less than the thickness of the middle portion of the channel regions 150-1 in the Z direction.
In some embodiments, the channel regions 150-1 and the source/drain extension regions 400-1 may have substantially the same width in a second horizontal direction (Y direction) and a cross-sectional area of the channel regions 150-1 (e.g., the middle portion of the channel regions 150-1) perpendicular to the X direction may be greater than a cross-sectional area of the source/drain extension regions 400-1 perpendicular to the X direction. The Y direction may be substantially parallel to the surface of the substrate 100 and may be substantially perpendicular to the X direction. For example, the channel regions 150-1 and the source/drain extension regions 400-1 may have a width in the Y direction of greater than about 6 nm.
Each of the source/drain regions 410 may be disposed on sides of the source/drain extension regions 400-1 and may be connected to the channel regions 150-1 through the source/drain extension regions 400-1. The source/drain regions 410 may have a thickness in the Z direction of greater than about 4 nm. In some embodiments, the source/drain regions 410 and the source/drain extension regions 400-1 may have substantially the same width in the Y direction, and a cross-sectional area of the source/drain regions 410 perpendicular to the X direction may be greater than the cross-sectional area of the source/drain extension regions 400-1 perpendicular to the X direction.
Contact regions 430 may be disposed on the respective source/drain regions 410. The contact regions 430 may contact upper surfaces of the source/drain regions 410. For example, the contact regions 430 may include metal silicide. The contact regions 430 may contact a conductive layer, which electrically connects the source/drain regions 410 to various components of the integrated circuit device, for example, a bit line or a capacitor. The conductive layer may include a metal or a metal alloy. Source/drain spacers 290 may be disposed on the source/drain regions 410.
Still referring to FIG. 2, the device may further include a gate insulating layer 310 and a gate electrode 330 sequentially disposed on the channel regions 150-1. The gate electrode 330 may wrap around the individual channel regions 150-1 to form a gate-all-around (GAA) FET. In some embodiments, the gate electrode 330 may have a width in the X direction that is not greater than a width of the channel regions 150-1 in the X direction. In some embodiments, a junction (e.g., P-N junction) may be formed outside of an edge of the gate electrode 330 such that the gate electrode 330 may not overlie the junction. The junction may be formed in the source/drain extension regions 400-1. The junction may be formed in a portion of the source/drain extension regions 400-1 that has a thickness in the Z direction less than the thickness of the channel regions 150-1. In some embodiments, portions of the channel regions 150-1 that vertically overlap with the gate electrode 330 may have a substantially uniform thickness in the Z direction.
The gate insulating layer 310 may be disposed between the gate electrode 330 and the channel regions 150-1 and on sides of the gate electrode 330. In some embodiments, the gate insulating layer 310 may include a high-k material having a higher dielectric constant than silicon oxide such as, for example, hafnium oxide (HfO2), lanthanum oxide, (La2O3), zirconium oxide, (ZrO2) and/or tantalum oxide (Ta2O5). The gate electrode 330 may include first and second gate electrodes stacked sequentially. For example, the first gate electrode may include one of TiN, TaN, TiC and TaC, and the second gate electrode may include W or Al.
Insulation layers 250 may be disposed between the gate electrode 330 and the source/drain regions 410. The insulation layers 250 may include, for example, a low-k material having a lower dielectric constant than silicon oxide. Gate spacers 210 may be disposed on the insulation layers 250. In some embodiments, the gate spacers 210 may overlie an interface between the channel regions 150-1 and the source/drain extension regions 400-1, and the channel regions 150-1 and the source/drain extension regions 400-1 have a thickness in the Z direction, adjacent the interface between the channel regions 150-1 and the source/drain extension regions 400-1, that is less than the thickness of the middle portion of the channel regions 150-1 in the Z direction.
FIG. 3 is a cross-sectional view, taken along the line A-A′ of FIG. 1, illustrating an integrated circuit device according to some embodiments of the present inventive concepts. Referring to FIG. 3, channel regions 150-2 may be disposed on the substrate 190. Each of the channel regions 150-2 may have a middle portion in the X direction that has a substantially uniform thickness in the Z direction along the X direction as illustrated in FIG. 3. The thickness of the middle portion of the channel regions 150-2 in the Z direction may be greater than about 6 nm.
The source/drain extension regions 400-2 may have a varying thickness in the Z direction that decreases and then increases along the X direction and may have a minimum thickness adjacent a midpoint of the source/drain extension regions 400-2 in the X direction as illustrated in FIG. 3. The minimum thickness of the source/drain extension regions 400-2 in the Z direction may be about 2 nm to about 4 nm. Insulation layers 250 may include portions protruding toward the gate electrode 330 and the gate electrode 330 and may have recessed sides as illustrated in FIG. 3.
In some embodiments, a portion of the channel regions 150-2 adjacent the source/drain extension regions 400-2 may have a thickness in the Z direction that is less than the thickness of the middle portion of the channel regions 150-2 in the Z direction. In some embodiments, the gate spacers 210 may overlie an interface between the channel regions 150-2 and the source/drain extension regions 400-2, and the channel regions 150-2 and the source/drain extension regions 400-2 have a thickness in the Z direction, adjacent the interface between the channel regions 150-2 and the source/drain extension regions 400-2, that is less than the thickness of the middle portion of the channel regions 150-2 in the Z direction.
In some embodiments, the channel regions 150-2 and the source/drain extension regions 400-2 may have substantially the same width in the Y direction, and a cross-sectional area of the channel regions 150-2 (e.g., the middle portion of the channel regions 150-2) perpendicular to the X direction may be greater than a cross-sectional area of the source/drain extension regions 400-2 perpendicular to the X direction. For example, the channel regions 150-2 and the source/drain extension regions 400-2 may have a width in the Y direction of greater than about 15 nm. In some embodiments, the source/drain regions 410 and the source/drain extension regions 400-2 may have substantially the same width in the Y direction, and a cross-sectional area of the source/drain regions 410 perpendicular to the X direction may be greater than the cross-sectional area of the source/drain extension regions 400-2 perpendicular to the X direction.
FIG. 4A is a plan view of FIG. 1 illustrating an integrated circuit device according to some embodiments of the present inventive concepts, and FIG. 4B is a cross-sectional view, taken along the line B-B′ of FIG. 4A. Referring to FIG. 4B, a channel regions 150-3 may have a fin-shape that protrudes from the substrate 100 in the Z direction. The channel regions 150-3 may have a substantially uniform thickness in the Z direction along the X direction. The gate insulating layer 310 may be conformally disposed on the channel regions 150-3 as illustrated in FIG. 4B. The gate insulating layer 310 may have a substantially uniform thickness on the channel regions 150-3. The gate electrode 330 may be disposed on the gate insulating layer 310.
Referring to FIG. 4A, the channel regions 150-3 may have a substantially uniform width in the Y direction along the X direction. The width of the channel regions 150-3 in the Y direction may be greater than about 15 nm. Source/drain extension regions 400-3 may be disposed on opposing sides of the channel regions 150-3 that are spaced apart from each other in the X direction. The Source/drain extension regions 400-3 may be disposed between the substrate 100 and the gate spacers 210. The source/drain extension regions 400-3 may have a width in the Y direction that is less than the width of the channel regions 150-3 in the Y direction. The source/drain extension regions 400-3 may have a substantially uniform width in the Y direction along the X direction as illustrated in FIG. 4A. A width of the source/drain extension regions 400-3 may be greater than about 6 nm. In some embodiments, the channel regions 150-3 and the source/drain extension regions 400-3 may have the substantially same thickness in the Z direction, and a cross-sectional area of the channel regions 150-3 perpendicular to the X direction may be greater than a cross-sectional area of the source/drain extension regions 400-3 perpendicular to the X direction. For example, the channel regions 150-3 and the source/drain extension regions 400-3 may have a thickness in the Z direction of greater than about 6 nm.
Each of the source/drain regions 410 may be disposed on sides of the source/drain extension regions 400-3 and may be connected to the channel regions 150-3 through the source/drain extension regions 400-3. The source/drain regions 410 may have a width in the Y direction that is greater than the width of the source/drain extension regions 400-3 in the Y direction as illustrated in FIG. 4A. For example, the source/drain regions 410 may have the width in the Y direction of greater than about 6 nm. In some embodiments, the source/drain regions 410 may have a thickness in the Z direction that is substantially the same as or greater than the thickness of the source/drain extension regions 400-3 in the Z direction, and a cross-sectional area of the source/drain regions 410 perpendicular to the X direction may be greater than the cross-sectional area of the source/drain extension regions 400-3 perpendicular to the X direction.
FIG. 5 is a plan view of FIG. 1 illustrating an integrated circuit device according to some embodiments of the present inventive concepts. Referring to FIG. 5, the device may include fin spacers 280 and fin barriers 285 disposed on sides of the source/drain extension regions 400-4. The gate spacers 210 may be formed on upper surfaces of the source/drain extension regions 400-4, the fin spacers 280 and the fin barriers 285.
The channel regions 150-4 may have a substantially uniform width in the Y direction along the X direction. The width of the channel regions 150-4 in the Y direction may be greater than about 6 nm. The source/drain extension regions 400-4 may have a width in the Y direction that is less than the width of the channel regions 150-4 in the Y direction. The source/drain extension regions 400-4 may have a substantially uniform width in the Y direction along the X direction as illustrated in FIG. 5, and a width of the source/drain extension regions 400-4 may be about 2 nm to about 4 nm. In some embodiments, the channel regions 150-4 and the source/drain extension regions 400-4 may have the substantially same thickness in the Z direction, and a cross-sectional area of the channel regions 150-4 perpendicular to the X direction may be greater than a cross-sectional area of the source/drain extension regions 400-4 perpendicular to the X direction. For example, the channel regions 150-4 and the source/drain extension regions 400-4 may have a thickness in the Z direction of greater than about 6 nm.
Each of the source/drain regions 410 may be disposed on sides of the source/drain extension regions 400-4 and may have a width in the Y direction that is greater than the width of the source/drain extension regions 400-4 in the Y direction as illustrated in FIG. 5. For example, the source/drain regions 410 may have the width in the Y direction of greater than about 15 nm. In same embodiments, the source/drain regions 410 may have a thickness in the Z direction that is substantially the same as or greater than the thickness of the source/drain extension regions 400-4 in the Z direction, and a cross-sectional area of the source/drain regions 410 perpendicular to the X direction may be greater than the cross-sectional area of the source/drain extension regions 400-4 perpendicular to the X direction.
FIG. 6 is a plan view of FIG. 1 illustrating an integrated circuit device according to some embodiments of the present inventive concepts. Referring to FIG. 6, the channel regions 150-5 may have a substantially uniform width in the Y direction along the X direction. The width of the channel regions 150-5 in the Y direction may be greater than about 6 nm.
The source/drain extension regions 400-5 may have a portion having a width in the Y direction that is less than the width of the channel regions 150-5 in the Y direction. The source/drain extension regions 400-5 may have a varying width in the Y direction along the X direction as illustrated in FIG. 6. The width of the source/drain extension regions 400-5 in the Y direction may decrease and then increase along the X direction and may have a minimum width adjacent a midpoint of the source/drain extension regions 400-5 in the X direction. The minimum width of the source/drain extension regions 400-5 in the Y direction may be about 2 nm to about 4 nm. In some embodiments, the channel regions 150-5 and the source/drain extension regions 400-5 may have the substantially same thickness in the Z direction, and a cross-sectional area of the channel regions 150-5 perpendicular to the X direction may be greater than a cross-sectional area of the source/drain extension regions 400-5 perpendicular to the X direction. For example, the channel regions 150-5 and the source/drain extension regions 400-5 may have a thickness in the Z direction of greater than about 6 nm.
Each of the source/drain regions 410 may be disposed on sides of the source/drain extension regions 400-5 and may have a width in the Y direction that is greater than the width of the source/drain extension regions 400-5 in the Y direction as illustrated in FIG. 6. For example, the source/drain regions 410 may have the width in the Y direction of greater than about 10 nm. In some embodiments, the source/drain regions 410 may have a thickness in the Z direction that is substantially the same as or greater than the thickness of the source/drain extension regions 400-5 in the Z direction, and a cross-sectional area of the source/drain regions 410 perpendicular to the X direction may be greater than the cross-sectional area of the source/drain extension regions 400-5 perpendicular to the X direction.
FIG. 7A is a perspective view and FIGS. 7B and 8 through 13 are cross-sectional views, taken along the line C-C′ of FIG. 7A, illustrating intermediate structures provided as portions of a method of forming an integrated circuit device according to some embodiments of the present inventive concepts. Referring to FIGS. 7A and 7B, stacks including sacrificial layers 110 and channel layers 130 may be formed on the substrate 100. The sacrificial layers 110 may have etch selectivity with respect to the channel layers 130. The channel layers 130 may be nanosheets having a thickness in the Z direction in a range of about 6 nm to about 10 nm. The stacks may have a line shape extending in the X direction. A dummy gate electrode 230 may be formed on the stacks, and gate spacers 210 may be formed on sides of the dummy gate electrode 230. The dummy gate electrode 230 may have a line shape extending in the Y direction and may cross the stacks. For example, the dummy gate electrode 230 may include poly-silicon, and the gate spacers 210 may include silicon nitride.
Referring to FIG. 8, the sacrificial layers 110 and the channel layers 130 may be etched using the dummy gate electrode 230 and the gate spacers 210 as an etch mask until the substrate 100 is exposed. Sides of the sacrificial layers 110 may be selectively etched to form recesses and then insulation layers 250 may be formed in the recesses. In some embodiments, the insulation layers 250 may be formed by forming a preliminary insulation layers that fill the recesses and on sides of the channel layers 130 and performing an anisotropic etching process to remove portions of the preliminary insulation layers formed on the sides of the channel layers 130. The insulation layers 250 may include a low-k material that has a dielectric constant lower than silicon oxide.
Referring to FIG. 9, source/drain regions 410 may be formed on the sides of the channel layers 130. In some embodiments, the source/drain regions 410 may be formed by performing an epitaxial growth process using the channel layers 130 a seed layer. In some embodiments, the source/drain regions 410 may be formed by performing an epitaxial growth process using the substrate 100 a seed layer. The source/drain regions 410 may include first impurities having a first conductivity type that is different from a second conductivity type of second impurities in the channel layers 130. In some embodiments, an ion implantation process and/or a plasma doping process may be performed to include first impurities having the first conductivity type in side portions of the channel layers 130 before forming the source/drain regions 410.
Referring to FIG. 19, a process (e.g., an anneal process) may be performed to form preliminary source/drain extension regions 400 between the channel layers 130 and the source/drain region 410. The first impurities in the source/drain regions 410 may diffuse into the channel layers 130 by the process (e.g., anneal process) to form the preliminary source/drain extension regions 400. Protecting layers 270 may be formed on the source/drain regions 410. The protecting layers 270 may include, for example, silicon oxide.
Referring to FIG. 11, the dummy gate electrode 230 and the sacrificial layers 110 may be removed. The sacrificial layers 110 may have etch selectivity with respect to the channel layers 130 and may be selectively removed. The protecting layers 270 may protect the source/drain regions 410 during removing the dummy gate electrode 230 and the sacrificial layers 110.
Referring to FIG. 12, an epitaxial growth process may be performed using the channel layers 130 as seed layer to form channel regions 150-1 and source/drain extension regions 400-1. A thickness of the channel regions 150-1 in the Z direction may be greater than a thickness of the source/drain extension regions 400-1. The channel regions 150-1 may have a middle portion in the X direction that has a substantially uniform thickness in the Z direction along the X direction, and the source/drain extension regions 400-1 may have a varying thickness in the Z direction as illustrated in FIG. 12. The source/drain extension regions 400-1 may have an impurity concentration less than an impurity concentration of the source/drain region 410.
Referring to FIG. 13, a gate insulating layer 310 that wraps around the individual channel regions 150-1 may be formed, and a gate electrode 330 may be formed on the gate insulating layer 310 such that a gate-all-around (GAA) FET structure may be formed. Referring again to FIG. 2, the protecting layers 270 may be removed, and source/drain spacers 290 may be disposed on the source/drain regions 410. The source/drain regions 410 may be etched using the source/drain spacers 290 as an etch mask and contact regions 430 may be formed on upper surfaces of the source/drain regions 410.
FIG. 14 is a perspective view and FIGS. 15 through 20 are cross-sectional views, taken along the line D-D′ of FIG. 14, illustrating intermediate structures provided as portions of a method of forming an integrated circuit device according to some embodiments of the present inventive concepts. Referring to FIG. 14, stacks including sacrificial layers 110 and channel layers 130 may be formed on the substrate 100. The stacks may have a line shape extending in the X direction. A dummy gate electrode 230 may be formed on the stacks and gate spacers 210 may be formed on sides of the dummy gate electrode 230. The dummy gate electrode 230 may have a line shape extending in the Y direction and may cross the stacks.
Referring to FIG. 15, the sacrificial layers 110 and the channel layers 130 may be etched using the dummy gate electrode 230 and the gate spacers 210 as an etch mask until the substrate 100 is exposed. Channel protecting layers 240 may be formed on sides of the channel layers 130. The channel protecting layers 240 may have etch selectivity with respect to the sacrificial layers 110 and the channel layers 130.
Referring to FIG. 16, sides of the sacrificial layers 110 may be selectively etched. The sacrificial layers 110 may be etched in the X direction by a distance lspacer. The sacrificial layers 110 may have recessed sides as illustrated in FIG. 16.
Referring to FIG. 17, portions of the channel layers 130 that are disposed under the gate spacers 210 may be etched. The channel layers 130 may be etched in the Z direction by a distance lch. It will be understood that lspacer and lch may be independently determined since the sacrificial layers 110 and the channel layers 130 are etched using two separate etching processes. The portions of the channel layers 130 may have recessed upper and lower surfaces as illustrated in FIG. 17.
Referring to FIG. 18, the channel protecting layers 240 may be removed, and insulation layers 250 may be formed on the recessed sides of the sacrificial layers 110 and the recessed upper and lower surfaces of the channel layers 130. Source/drain regions 410 may be formed on the sides of the channel layers 130. The source/drain regions 410 may include first impurities having a first conductivity type. A process (e.g., an anneal process) may be performed to form source/drain extension regions 400-2 and channel regions 150-2. The first impurities in the source/drain regions 410 may diffuse into the channel layers 130 by the process (e.g., anneal process) to form the source/drain extension regions 400-2. In some embodiments, an ion implantation process and/or a plasma doping process may be performed to include first impurities having the first conductivity type in side portions of the channel layers 130 before forming the source/drain regions 410.
Referring to FIG. 19, the dummy gate electrode 230 and the sacrificial layers 110 may be removed. The sacrificial layers 110 may have etch selectivity with respect to the channel layers 130 and may be selectively removed.
Referring to FIG. 20, a gate insulating layer 310 that wraps around the individual channel regions 150-2 may be formed, and a gate electrode 330 may be formed on the gate insulating layer 310. Referring again to FIG. 3, source/drain spacers 290 may be disposed on the source/drain regions 410. The source/drain regions 410 may be etched using the source/drain spacers 290 as an etch mask and contact regions 430 may be formed on upper surfaces of the source/drain regions 410.
FIGS. 21A and 22A are perspective views and FIGS. 21B, 22B and 23 through 26 are plan views illustrating intermediate structures provided as portions of a method of forming an integrated circuit device according to some embodiments of the present inventive concepts. Referring to FIGS. 21A and 21B, the channel layers 140 may have a line shape that extends in the X direction. A dummy gate electrode 230 may be formed on the channel layers 140 and gate spacers 210 may be formed on sides of the dummy gate electrode 230. The dummy gate electrode 230 may have a line shape extending in the Y direction and may cross the channel layers 140.
Referring to FIGS. 22A and 22B, channel protecting layers 260 may be formed on portions of the channel layers 140 exposed by the dummy gate electrode 230 and the gate spacers 210. In some embodiments, the channel protecting layers 260 may include silicon oxide and may have a substantially uniform thickness along surface of the channel layers 140 as illustrated in FIG. 22A.
Referring to FIG. 23, the dummy gate electrode 230 may be removed. An epitaxial growth process may be performed using the channel layers 140 as a seed layer to form channel regions 150-3 as illustrated in FIG. 24. Referring to FIG. 25, the dummy gate electrode 230 may be formed again between the gate spacers 210 and then the channel protecting layers 260 may be removed.
Referring to FIG. 26, the portions of the channel layers 140 exposed by the dummy gate electrode 230 and the gate spacers 210 may be etched and then the source/drain regions 410 may be formed. The source/drain regions 410 may include first impurities having a first conductivity type. A process (e.g., an anneal process) may be performed to form source/drain extension regions 400-3. The first impurities in the source/drain regions 410 may diffuse into the channel layers 140 by the process (e.g., anneal process) to form the source/drain extension regions 400-3. In some embodiments, an ion implantation process and/or a plasma doping process may be performed to include first impurities having the first conductivity type in side portions of the channel layers 140 to form the source/drain extension regions 400-3 before forming the source/drain regions 410.
Referring again to FIGS. 4A and 4B, the dummy gate electrode 230 may be removed and then a gate insulating layer 310 may be formed on sides and upper surfaces of the channel regions 150-3, and a gate electrode 330 may be formed on the gate insulating layer 310.
FIGS. 27, 28, 29A and 30 through 34 are plan views and FIG. 29 is a cross-sectional view, taken along the line E-E′ of FIG. 29A, illustrating intermediate structures provided as portions of a method of forming an integrated circuit device according to some embodiments of the present inventive concepts. Referring to FIG. 27, channel layers 140 may be formed on the substrate 100. The channel layers 140 may have a line shape that extends in the X direction. Fin spacers 280 may be formed on sides of the channel layers 140 and a fin barrier 285 may be formed on the fin spacers 280. The fin barrier 285 may fill a space between the channel layers 140.
Referring to FIG. 28, a dummy gate electrode 230 may be formed on the channel layers 140, the fin spacers 280 and the fin barrier 285. Gate spacers 210 may be formed on sides of the dummy gate electrode 230. The dummy gate electrode 230 may have a line shape extending in the Y direction and may cress the channel layers 140. Channel protecting layers 265 may be formed on portions of the channel layers 140 exposed by the dummy gate electrode 230 and the gate spacers 210. In some embodiments, the channel protecting layers 265 may include silicon oxide and may have a substantially uniform thickness along sides and an upper surface of the channel layers 140.
Referring to FIGS. 29A and 29B, the dummy gate electrode 230 may be removed, and upper portions of the channel layers 140 may be removed to leave portions of the channel layers 140′. The fin spacers 280 may be removed such that spaces defined by the fin barrier 285 may be formed as illustrated in FIG. 29B.
Referring to FIG. 30, an epitaxial growth process may be performed using the portions of the channel layer 140′ as a seed layer to form channel regions 150-4. In some embodiments, the channel regions 150-4 may fill the spaces defined by the fin barrier 285. Referring to FIG. 31, the fin barrier 285 between the gate spacers 210 may be removed to expose sides of the channel regions 150-4.
Referring to FIG. 32, the dummy gate electrode 230 may be formed again between the gate spacers 210, and the fin spacers 280 and the fin barrier 285 that are exposed by the dummy gate electrode 230 and the gate spacers 210 may be removed. Referring to FIG. 33, portions of the channel regions 140 exposed by the dummy gate electrode 230 and the gate spacers 210 may be removed and then source/drain regions 410 may be formed by performing, for example, an epitaxial growth process using portions of the channel regions 140 under the gate spacers 210 as a seed layer. The source/drain regions 410 may include first impurities having a first conductivity type. A process (e.g., an anneal process) may be performed to farm source/drain extension regions 400-4. The first impurities in the source/drain regions 410 may diffuse into the channel layers 140 by the process (e.g., anneal process) to form the source/drain extension regions 400-4. In some embodiments, an ion implantation process and/or a plasma doping process may be performed to include first impurities having the first conductivity type in side portions of the channel layers 140 to form source/drain extension regions 400-4 before forming the source/drain regions 410.
Referring to FIG. 34, source/drain protecting layers 267 may be formed on the source/drain regions 410, and the dummy gate electrode 230 may be removed. Referring again to FIG. 5, a gate insulating layer 310 may be formed on sides and upper surfaces of the channel regions 150-4, and a gate electrode 330 may be formed on the gate insulating layer 310. The source/drain protecting layers 267 may be removed after the gate insulating layer 310 and the gate electrode 330 are formed.
FIGS. 35, 36, 37A, 38 and 39 are plan views and FIG. 37B is a cross-sectional view, taken along the line F-F′ of FIG. 37A, illustrating intermediate structures provided as portions of a method of forming an integrated circuit device according to some embodiments of the present inventive concepts. Referring to FIG. 35, channel layers 140 may be formed on the substrate 100. The channel layers 140 may have a line shape that extends in the X direction. A dummy gate electrode 230 may be formed on the channel layers 140, and gate spacers 210 may be formed on sides of the dummy gate electrode 230. The dummy gate electrode 230 may have a line shape extending in the Y direction and may cross the channel layers 140.
Referring to FIG. 36, channel protecting layers 260 may be formed on portions of the channel layers 140 that are exposed by the dummy gate electrode 230 and the gate spacers 210. In some embodiments, the channel protecting layers 260 may include silicon oxide and may have a substantially uniform thickness along sides and an upper surface of the channel layers 140. The gate spacers 210 may be removed after forming the channel protecting layers 260 to expose the underlying channel layers 140.
Referring to FIGS. 37A and 37B, an etch process may be performed to partially etch the channel layers 140 to form channel regions 150-5. Sides of the channel layers 140 may be etched, and the channel layers 140 may have a varying width in the Y direction along the X direction as illustrated in FIG. 37A. The width of the channel layers 140 in the Y direction may decrease and then increase in the first direction. Upper surface of the channel layers 140 may be etched and may have recesses as illustrated in FIG. 37B. In some embodiments, the etch process may have some orientation dependence such that the sides of the channel layers 140 may be etched faster than the upper surface of the channel layers 140. For example, the upper surface of the channel layers 140 may be in (100) crystal planes, the sides of the channel layers 140 may be in (011) crystal planes, and the etch process may have a faster etch rate in the [110] direction than the [100] direction.
Referring to FIG. 38, the gate spacers 210 may be formed again on the sides of the dummy gate electrode 230. According to FIG. 39, the channel protecting layers 260 may be removed to expose the channel layers 140 underlying the channel protecting layers 260. The exposed channel layers 140 may be etched and then source/drain regions 410 may be formed by performing, for example, an epitaxial growth process using portions of the channel regions 140 under the gate spacers 210 as a seed layer. The source/drain regions 410 may include first impurities having a first conductivity type. A process (e.g., an anneal process) may be performed to form source/drain extension regions 400-5. The first impurities in the source/drain regions 410 may diffuse into the channel layers 140 by the process (e.g., anneal process) to form the source/drain extension regions 400-5. In some embodiments, an ion implantation process and/or a plasma doping process may be performed to include first impurities having the first conductivity type in side portions of the channel layers 140 to form source/drain extension regions 400-5 before forming the source/drain regions 410.
Referring again to FIG. 6, the dummy gate electrode 230 may be removed, and a gate insulating layer 310 may be formed on sides and upper surfaces of the channel regions 150-5. A gate electrode 330 may be formed on the gate insulating layer 310.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the inventive concepts. Thus, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

## Claims

1. An integrated circuit device comprising:
a stack on a substrate, the stack comprising a plurality of channel regions and a plurality of gate electrodes stacked in an alternating sequence in a vertical direction that is perpendicular to a surface of the substrate and the plurality of channel regions comprising impurities having a first conductivity type;
source/drain regions on respective opposing sides of the stack, the source/drain regions being spaced apart from each other in a horizontal direction that is parallel to the surface of the substrate and comprising impurities having a second conductivity type that is different from the first conductivity type; and
a plurality of extension regions between respective ones of the plurality of channel regions and one of the source/drain regions and comprising impurities having the second conductivity type, each of the plurality of extension regions having a thickness in the vertical direction that is less than those of the plurality of channel regions and the one of the source/drain regions,
wherein each of the plurality of channel regions overlaps with the plurality of gate electrodes in plan view, and the thickness of the plurality of channel regions in the vertical direction is uniform.

2. The device of claim 1, wherein a width of the plurality of gate electrodes in the horizontal direction is less than a width of the plurality of channel regions in the horizontal direction.

3. The device of claim 1, wherein the thickness of each of the plurality of extension regions decreases in the horizontal direction toward the one of the source/drain regions.

4. The device of claim 1, wherein the thickness of each of the plurality of extension regions decreases and then increases in the horizontal direction toward the one of the source/drain regions.

5. The device of claim 1, wherein the plurality of gate electrodes are spaced apart from the one of the source/drain regions, and
wherein the device further comprises a plurality of insulation layers between respective ones of the plurality of gate electrodes and the one of the source/drain regions, and the plurality of insulation layers has a dielectric constant lower than silicon oxide.

6. The device of claim 1, wherein an impurity concentration of the source/drain regions is greater than an impurity concentration of the plurality of extension regions.

7. The device of claim 1, wherein the source/drain regions and the plurality of extension regions comprise a same material and composition.

8. An integrated circuit device comprising:
a channel region on a substrate, the channel region comprising impurities having a first conductivity type;
a gate electrode on the channel region;
source/drain regions on respective opposing sides of the channel region, the source/drain regions being spaced apart from each other in a first direction and comprising impurities having a second conductivity type that is different from the first conductivity type; and
an extension region between the channel region and one of the source/drain regions, the extension region comprising impurities having the second conductivity type and having a cross-sectional area perpendicular to the first direction that is less than those of the channel region and the one of the source/drain regions,
wherein the cross-sectional area of the extension region decreases along the first direction toward the one of the source/drain regions.

9. The device of claim 8, wherein the channel region overlaps with the gate electrode in plan view, and the cross-sectional area of the channel region perpendicular to the first direction is uniform.

10. The device of claim 8, wherein an impurity concentration of the source/drain regions is greater than an impurity concentration of the extension region.