I NAME OR Tm.I 

!"\R. ltAl f...., 

CIRCULATE 

DATE 

& I 

3 

• 

FILI 

INfORMAnOll 

NOTE AND 

REnlRN 

IEIMI 

&IGINATURE 

eclassified and approved for release by NSA 

n 09-05-2013 ursuant to E.O. 13526 

DD FORM 91:: RepJaeelD.A..A.OOl'orm.llll,1.A.pr48,lllldil'HQ ~ - • _ 1. FEBIJO ~ l'aim~~HO't''7,w~~~.1JIMI. . ., , .. ~-"- .- : . f •• 

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Office Memorandum · UNITED STATES GOVERNMENT 

-

TO ~ ~/~~ -DATB/~H.r)' 

1'1'0J< 1M ~ I ¥' u-.J \ _ 

SUBJECT Pc~ v1 s.1-1 

.. vC,_ ~ r~/N~~~~ 

--'-?\. ~ti~ tr' tJ-W... ~ ~ ~ J.) _;_;( ~,-t; ~ 

-Q, ~ r "- 4l(J- ff' ~ Pt:~ VIS I/~ ..,,._,...,-~ 

~ ..t+e tA., .-...4 ~ - "'-d/ ~ t, r ~~~~~;r~ 

l~/~ 

--------~~~~==== 
REF ID: A 7174,3D"' -

DERVISH 

General Description 

Volume 1 1 June 1954 

Copy No. 6 

-

Task No. 353-7406 

By:~~~ i&L. Bowman 

ll/D-353 

Control No. 346/6 

30 775 
PREFACE 

The purpose of this document is to disseminate to interested and key 

personnel the general philosophy of DERVISH and descriptions of units 

developed thus far The aim is two-fold (1) To acquaint machine-minded 

analysts with some of the applications and programming aspects of the 

DERVISH units, and (Z) To acquaint technical personnel briefly with the 

theory and logic of operation 

The units discussed in this volume represent a result of ideas advanced 

1n NSA-35 and NSA-06 They follow one hne of development mostly, although other lines are being considered on a lower priority because of the 

emphas1s being placed upon getting a few assemblies of units into operation 

Local effort ts being augmented by a time and materials contract 

The author gratefully acknowledges the efforts of and contributions 

to this task by C J Sch1erlmann, R E Gordon, W McGough, Jr , and 

L W Lathroum of NSA-35, D A Shepard and E D Marston of NSA-06 

RLB 
TABLE OF CONTENTS 

Chapter 1 - General Descr1pt1on - IZ April 1954 

Chapter 2 - Definitions, Gates and Symbols - 12 April 1954 

Chapter 3 - The Visual Unit (VU) - lZ April 1954 

Chapter 4 - The Mod-Counter (MC) - 14 April 1954 

Chapter 5 - The Mod-Adder (MA) - 14 AprU 1954 

Chapter 6 - The Subst1tut1on Unit (SU) - ZO April 1954 

Chapter 7 - The Adder-Selector (AS) - 24 May 1954 
REF ID:A717~ 

ta TOP SECRE t e 

CHAPTER I 

GENERAL DESCRIPTION 

I Introduction 

DERVISH, a sub-proJect approved 4 December 1951 by DIRAFSA, ii 

directed toward a building block plulosophy of analytic machine assembly 

and re -assembly with particular emphasis on rotor solution devices These 

bu1ld1ng blocks are not necessarily assumed to be repetitive circuits or 

modules designed to !ac1htate production hne construction and standardize 

plug-in units, but are to be considered more as functional blocks which may 

be assembled in most any arrangement to perform a set or sequence of 

logical operations and yet possess many desirable maintenance features 

Each block is to have facility for performing a specific unique function 

This idea 1s not new, neither has 1t been fully exploited Engineering effort 

devoted to the development of a family of building blocks has indicated a 

favorable degree of practicability of this philosophy The growth of DERVISH 

stems from the construction and demonstration during July - November 1951 

of a unit applying dynamic circuit techniques to an arithmetic representation 

of a wired rotor which handled charact~·rs at a rate of 167, 000 per second. 

From this, it was evident that other functional blocks could be built to perform functions of addition, subtraction, star.age, substitution, selection, 

etc • at the same rate of speed 

This building block philosophy has a number of distinct advantages over 

present approaches to machine design and construction in that a new special 

purpose device can be assembled in a matter of weeks by no more than a 

half dozen laboratory technicians As soon as the device has served its 

purpose, it can be readily changed, modiflf"d or dismantled and the units 

made available for the hssembly of another device In this manner the 

normal two to three years' delay encountered between a request for a 

machine and its realization would be effectively eliminated 

II. ObJectives 

One of the maJor obJectives in the development of these units 1s to make 

them of such nature that an analyst with a general knowledge of machine aid 

techniques can make a functional layout of a machine in block diagram form. 

By use of the building blocks, the engineering effort required for the realization of the device can be narrowed down to a smaller scope than would be 

possible normally and the time required to construct a piece of equipment 

and get 1t into operation is substantially reduced 

l 

NSA Form 781 C JO 6 Jul 51 TOP SECRET 
REF ID:A71743 

e TOP SECRET e 

Another ob3ecbve is to make the units mutually compatible circu1t .. wis• 

and yet be flexible and adaptable to a variety of applications. To achieve 

this, a pulse timing standard has been established for the input and output 

of units and extra control leads are provided where possible so their versatility may be increased. 

In order that equipment down time be minunized and maintenance and 

repair s1mphfied, the chassis are of a plug-in design which permits rapid 

replacement of faulty ones The component layout has been made in such 

a manner that all elements are readily accessible for trouble shooting and 

replacement 

III Notation and Representation 

In the DERVISH units characters, numbers and quantities are represented in a serial binary form. Some units utilize 5-bit quantities and 

others 6-bit quantities but all are based on a 6-bit cycle In the normal 

concept a binary quantity of l's and O's is represented by pulses and no 

pulses respectively, but a one's complement or dual representation 1s 

employed in these umts In effect, this means that normal logic l's are 

represented by no pulses and O's are represented by pulses. The following example shows sample quantities in both logics and the pulse patterns 

Quantity Normal Dual Pulse Patterns 

T6 I Ts T4 T3 

I 

Tz T1 I 

A or 0 000000 11 ll ll 

B or l 000001 111110 

C or z 000010 111101 

Dor 3 000011 111100 

6Z 111110 000001 rl 

I 

63 111111 000000 I 

t 

Any character or number not exceeding 63 can be represented on a 

6 microsecond cycle and those quantities ranging from 64 through 4095 

can be represented in the same time cycle through the use of an additional 

c1rcu1t. Although five binary bits are suff1c1ent to represent alphabetic 

z 

NSA Form 781 ClO 6 Jul 51 TOP SECRET 
eTOP SECRET 

characters, some units require six microseconds to process or operate 

on one character, therefore, a cycle of six micro•Jeconds has been chosen 

as a basic time cycle The six time positions in this cycle are referred 

to as T 1, T 2 , T 3 , T4, T 5 and T 6 in ascending order with respect to time. 

In a 6-bit quantity or character, the six pulse positions arc referred to 

as P1, Pz, P 3 , P 4 , P 5 and P6 in ascending order with respect to the 

power of z. These two terminologies are not to be confused The pulses 

are packets of energy which travel through the circuits with a finite speed 

and they do not always appear at an observation'. point 1n phase with the 

respective time positions For example, a bus schedule represents the 

times at which a bus may be observed at indicated points along the bus 

route. An analogous concept is used to designate pulse schedules 1n the 

c1rcu1ts operating 1n a serial mode 

IV C1rcu1try and T1m1ng 

At present the circuit elements employed are of the dynamic type 

operating at a 1 mc/s pulse repetition frequency These circuits utilize 

crystal diodes for gating and sw1tch1ng, vacuum tubes for amplifiers and 

pulse regeneration, pulse transformer~1 for a-c coupling, and delay hnes 

for storage and time pos1tloning elements 

In order to synchronize all parts of a machine two types of timing are 

necessary one for microsecond timing and one for cycle timing. 

A. Microsecond Timing 

For the microsecond timing a 1 rnc/s sine wave clock pulse u distributed to ill clock pulse a.mphflers which in turn generate the four phases 

to be used 1n timing the circuit gates Their relationship 1s thus 

NSA Form 781 CJO 6 Jul 51 TOP 

Tz 

3 

SECRET 

Synchron1z1ng 

Clock Pulse 
TOP SECRETe 

B. Cycle Timing 

Prov1s1on for cycle timing and basic control for several units is made 

in the form of T pulses, T pulses and fixed pulse patterns. AT pulse 18 

defined as one pulse occurring at a prescribed hme position in the 6 microsecond cycle There are 24 of these T pulses identified as 1

Tl' zTl' 3T1, 

4T1, 1T2 , zTz, 3T2 , • • • •• 3T6, and 4T6 The subscript on the left of 

the T indicates the phase of clock pulse used to generate the pulse and the 

subscript on the right designates the time position. A T pulse may be 

defined as a single blank occurring at a prescribed time position while a 

pulse occurs in each of the other five hme positions There are Z4 of these 

T pulses identified as 1T1, z!l' 3T1, 4T1, 1T2 , zTz• • 3T6• and 4T6 The 

subscript on the left of the T indicates the phase of clock pulse used to 

generate the five pulses present and the subscript on the right designates 

the time position of the blank All possible T and T pulses are generated 

because 1t was, and still is, impossible to predict which ones will be used 

but the fact that they are all available, whether used or not, certainly 

simplifies test setups. 

A fixed pulse pattern may be defined as a pattern of pulses and blanks 

which is repeated every cycle and remains unchanged from cycle to cycle 

Out of a possible 32 unique 5-bit patterns, two (00000 and 11111) can be 

represented by d-c voltages, five (00001, 00010• 00100, 01000 and 10000) 

can be represented by T pulses, and five ( 11110, 11101, 11011, 10111 

and 01111) can be represented by T pulses All 3Z patterns are needed to 

designate rotor output points as described in chapter 6, The Adder-Selector 

(AS), so the remaining ZO are generated on a pattern generator chassis 

The follo• •1ng sketch shows examples of T pulses and T pulses• 

Tz T1 I 

I 

n lTl 

I 

I I nJ zT1 

I 

I 3T3 

I 

I 2T5 I 

I lTl 

4T5 

4 

NSA Form 78 l C 10 6 Jul 51 TOP SECRET 
~ An effort has been ma.de to standardize unit input and output timing 

Thu standard was arbitrarily chosen as Pt at 1T1 which means that the 

first pulse position of a character, or number, coincides with 1Tt time 

This simplifies the problem of tying units together 

V Chassu 

Based on optimum arrangements of functional circuits and their 

probable usage, a rather large standard plug-in chassis design has been 

chosen which measures approximately 17 inches high, ZS inches long, 

3 inches wide, and weighs around ZS pounds filled Two plugs, each 

with 36 connections, are located on the back of the chassis Provuion is 

made for 24 electron tubes on the chassis front with capacity on the side 

panels for the associated circuitry up to a maximum of 39 components 

and 8 microseconds of delay hnes or 18 components and 10 microseconds 

of delay hnes per tube The self-contained filament transformer Slmplifiea 

the problem of filament power distribution Thu size chassis appears to 

be about the desirable size since it has capacity for accommodating one 

complete Adder-Selector, one Substitution Unit, four Mod-Counters, four 

Mod-Adders, the Z4 T generators or the Z4 T generators 

VI Cabinetry 

Three types of cabinetry are contemplated for housing the DERVISH 

chassis The first is a sort of a laboratory test set up variety of which 

there are two sizes, 6 chassis capacity and 10 chassis capacity Each is 

equipped with its own clock pulse amphers and a blower for cooling by room 

air but is dependent upon an external power supply These cabinets are 

designed primarily for testmg individual chassis or very small groups of 

chassis 

The second type is more of a breadboard assembly type of cabinet 

capable of accommodatmg 24 chassis It 18 also equipped with clock pulse 

amphfiers and coohng blower but is dependent upon external power supplies 

It's primary purpose is to permit the testing and demonstration of moderate sized assembhes or groups of chassis Inter-chassu connections are 

made in the form of soldered wires on the plugs on the back of the cabinet. 

The third type is a complete self-contained cabinet system designed for 

operational use It is to be complete with power supplies, heat exchanger and 

cooling system, capacity for 7Z DERVISH chassis, and an optional manual 

control console Inter-chassis connections are to be plug-in wires which 

will permit relatively rapid d1smanthng of one assembly and setting up of a 

new one Multiple cabinet systems are contemplated as being possible for 

very large problems 

5 

NSA Form 761 C!O 6 Jul 51 TOP SECRET 
VII Future Work 

Although the work on DERVISH during 195Z and 1953 was concerned 

mainly with units operating at a l mc/s pulse repetition rate which handled 

data in serial form, one model of an Adder-Selector (rotor) was constructed 

to operate 1n the parallel mode at a 1 mc/s rate. ThlB represents an effective speed increase by a factor of 6 TblS is to be pursued further with 

respect to other units provided an 1nd1cated need warrants 1t 

There is the poss1b1hty of increasing the pulse repehbon rate to 3 or 4 

me/ s or higher m order to achieve greater overall speed and yet utilize the 

practical aspects of serial operation New circuit techniques, developments 

of components such as transistors, magnetic elements and ferroelectric 

materials (barium titanate) may well have a bearing on the direction of 

future effort and are not to be overlooked 

In the immediate future the ma in emphasis u to be placed on the construction of a sufficient quantity of units to permit assembly of some 

demonstratlonal and operational equipment utilizing the techniques now 

considered eng1neer1ngly sound Operational requirements will dtctat~ 

the extent to which this is carried before higher speeds and parallel 

operation are more actively exploited 

cS 

NSA Form 781 CJO 6 Jul 51 TOP SECRET 
REF ID:A71743 
REF ID:A71743 
REF ID:A71743 
REF ID:A71743 
REF ID:A71743 
REF ID:A71743 
REF ID:A71743 

C~-. i...;.; Delinitfo-~sl _-- ,____ - - - - .. - --""..$ - - ,,,.......,,___ 
CHAPTER 2 

DEFINITIONS, SYMBOLS AND GATES 

I. Scope 

The purpose and scope of this chapter is to define the terms and 

symbols used 1n the foll owing chapters and to show the component values 

and structures of gates used on the logical diagrams Although a number 

of these may appear to be rather abstract or common 1n some instances, 

1t is felt that thu "d1ct1onary" should include most of the very baste terms 

as well as those peculiar to the type circuitry actually employed 

II. Defimtiona 

Accumulator 

Adder 

"AND" Gate 

Binary Number 

Borrow 

- A device which stores a number, or quantity, 

and upon reception of a new number, or quantity, adds it to the previous contents and 

stores the sum 

- A device which can form the sum of two or 

more numbers, or quantities, impressed 

upon it 

- A circuit having an output and a mulbphcity 

of inputs so designed that the output is 

energized when and only when a certain prescribed set of input conditions are met 

- A d1g1t of a binary number 

- A number of the binary system wh1ch uses 

two symbols {usually denoted by 11 011 and "1 ") 

and has 2 as its base ThlB 1S analogous to 

a decimal number of the decimal system 

which uses 10 symbols {"0, 1, 2, - 911 ) and 

the base 10 

( 1) A condition occurring in subtraction when 

the difference (minuend minus the subtrahend) 

Qf two digits in the same column 1s negative 

(2) The digit to be extracted from the next 

column of the minuend (3) The action of 

extracting 1t 

7 
Buffer 

Carry 

Character 

Character Cycle 

Clocked 

Clock Pulse 

Complement 

Counter 

Cycle 

Delay Line 

An isolating circuit used to avoid reaction of 

a driven circuit upon the corresponding driving 

circuit 

( 1) A condition occurring in addition when the 

sum of two digits in the same column equals 

or exceeds the base of the number system in 

use (Z) The digit to be forwarded to the next 

column (3) The action of forwarding it 

- A letter 1 or symbol, of an alphabet It may 

be represented by a specific binary number 

The time required for the transmission of 

one character 1 including the space between 

characters 

Characteristic 1 or property, of having been 

timed with a reference timing signal 

A primary timing signal with which circuits 

are synchronized 

A number whose representation 1s derived 

from the finite positional notation of another 

by one of the following rules (a) True Complement (twos complement) - Subtract each 

digit from the radix less one, then add one 

to the least significant digit, executing any 

carries required (b) (Radix - l)'s Complement (ones complement) - Subtract each 

digit from the radix less one 

A device capable of changing from one to 

the next of a sequence of distinguishable states 

upon each receipt of a discrete input •ngnal 

An interval of time 1n which 1s completed one 

round of events, or phenomena, that recur 

regularly and in the same sequence 

A circuit component wherein a finite time is 

required for a pulse of electrical energy to 

traverse its physical length 

8 
Diode 

Enabler 

Dynamic Fhp-Flop 

Inhibitor 

Memory 

Number 

"OR" Gate 

Preset 

Pulse 

A non-linear circuit component which exhibits 

a high resistance to current flow in one di -

rection and a low resistance in the opposite 

direction 

- Any input to an "AND" gate that is actuated 

by positive going signals, the presence of such 

a signal being required for the 11AND11 gate to 

operate. 

An electronic circuit which has two operational states and ordinarily two types of input 

signals (turn ON and turn OFF) Its output 

is a continuous stream of pulses when ON and 

no pulses when OFF 

Any input to an "AND" gate that is actuated 

by negative going signals, the absence of such 

a signal being required for the "AND" gate to 

operate 

A device into which information may be introduced and then extracted at a later time 

A representation of an abstract mathematical 

entity defined by the rules governing the 

relations and operations to which it is susceptible such as a binary number, or a decimal 

number, or a sequence of pulses. 

A circuit having an output and one or more 

inputs so designed that the output is energized 

whenever one or more inputs are energized 

Thus an 110R11 gate is frequently considered 

as a buffer or isolating circuit 

Commonly refers to a condition 1n a counter 

whereby the counter's beginning point 1s 

estabhshed at some value other than zero 

A signal of electrical energy normally of 

short duration 

9 
Pulse Timing 

Radix (or Base) 

Read 

Reset 

Rotor 

Selector 

Shift 

Stage 

Staticize 

Storage Loop 

T Pulse 

T Pulse 

- A system 0£ de s1 gnat1ng a time schedule of 

specified pulse positions 

- The integer of whose successive powers the 

digits of a number are the coeff1c1ents 

- To extract information 

- (1) The action of an electronic circuit being 

returned to its normal initial condition 

(Z) The control function which effects this 

return 

- A due de signed to rotate within an electrical 

cipher machme with a set of input contacts 

and a set of output contacts connected by any 

prearranged scheme 

- A device capable of choosing any one of a 

multiphcity of items In DERVISH, it is an 

electronic switching circuit capable of choosing 

for an output any one of a number of inputs 

- Displacement of an ordered set of digits (bits) 

one or more columns to the right or left 

- Commonly refers to one set of electron tube 

elements and their associated circuit components 

- To take one or more d1g1ts (bits) normally 

movmg through a series of circuit stages and 

store them in individual storage elementb 

- A specific type of memory device normally 

of delay hne s with its ends connected thereby 

allowing its content of digits to circulate 

within 1t on a cychc basis 

- A single pulse occurring at a prescribed time 

position of a repetitive time cycle 

- A single blank, or no pulse, occurring at a 

precribed time position 1n a repetitive cycle 

while pulses occur at all other time positions 

to 
Tim1ng Numbers 

Tolerance 

Translator 

Write 

III Symbols 

REF ID:A71743 

- A set of numbers used to define the corners 

of the unhzed trapezoidal portion of an 

electrical pulse 

- An indication (normally by a set of numbers) 

of the allowable deviation of pulses which are 

driving a gate and yet maintain reliable 

operation of that gate 

- A device capable of accepting information in 

one number system or code and changing that 

information into another number system or 

code "Encoder" u frequently used to identify a device capable of translating information 

in one number system to a machine code and 

"decoder" to identify a device capable of translating information in a machine code to a 

number system 

- Insert Information 

The set of symbols adopted in DERVISH is normally the same as that 

used with SEAC by the National Bureau of Standards and with ABNER by 

NSA-35 No set of symbols has been standardized for comparable circuit 

or logical diagrams as yet in the electronics field since the recent rapid 

growth of the fields of computation and data processing has produced a 

wide variety of symbols and notations 

Item Logical symbol Component diagram 

Delay bne 

-IOV 

+1V 

11 
Item 

Tube 

"OR" gate 

"AND" gate 

"AND" gate 

(with 1nh1b1tor) 

REF ID:A71743 

Logical symbol Component diagram 

Q,___:: 

D 

-65V 

+62V 

----iD,___~ 

JZ 
Item 

Normal Gating 

Arrangement 

Flip-Flop 

REF ID:A71743 

Logical symbol 

OP 

13 

Component diagram 

+ 

-65V 

[) ) 

~v 

~r -65V 

-65V 
REF ID :A71743. 

IV Timing Numbers and Gate Tolerances 

A. Timing Numbers 

In dynamic circuitry 1t is very important that pulses be well defined 

with respect to time in order that circuit components affecting pulse shape 

and delay may be ptoperly chosen to give reliable operation at every point I 

in the circuit especially where a number of signals are combined in some 

manner to perform l 1og1cal function A system of timing numbers has been 

adopted which provides a way of describing the shape and time location of 

the utlhzable portio~ of any pulse at any point in a circuit The portion of 

a pulse that is really\ utilized is that portion lying between -5 V. d-c and 

+2 V. d-c The tuning numbers designate the times within a microsecond 

period when these two voltage levels intersect the leading and trailing edges 

of a pulse and this is represented by the expression 

~Lg__ 

AID 

A, B, C and D are expressed in hundredthsof a microsecond where A indicates the time when the leadmg edge or rising voltage is -5 V , B 1nd1cates 

the time when the rlSing voltage is +2 V , C indicates the time when the 

trailing edge or falling voltage is +2 V , and D indicates the time the trailing 

edge is down to -5 V The amount of pulse above the +2 volt level 1s not 

indicated normally but 1s +4 V or higher which gives a considerable amplitude margin of safety. 

The clock pulses are the basic tlmlng and synchronizing signals The 

first one was arb1trar1ly chosen and the others fall in hne thusly 

~1~ 

20f77 

CP2• 50 97 

45 102 

75 122 

70 127 

100 147 

95 152 

The following sketch shows the t1m1ng number points and the utilized 

trapezoidal portion of a clock pulse• 

r / .. --..' =-! .. --,, - 1 - , lusec /' \ I \ /" I \ 

' I f \ ,' , B~/ \.t°C 

---' \\ --; ______ \ ____ / __ --L _ -- . ·--- \ /\A D_..i"\ / 

\ I \ J ' ; " ,' ,..., __ ,,,,." ' ... -~"'"' 

+zv 

-SV 

14 
REF ID:A71743 

A certain amount of delay is incurred when a clocked signal passes 

through a gate structure, tube and transformer The aggregate delay for 

all these components for all conditions of pulse (first through Nth) ha.s been 

combined into one set of numbers thus 

_!_<tll_ 

419 

The numbers 4, 10, 3 and 9 indicate the maximum delay under any condition 

for points A, B, C and Din going through one stage Therefore, the output 

pulse from a stage clocked with CPz 1s 

CPz 

Output 

'C_--

+zv. 

.. sv. 

-IOV 

+zv 

-sv. 

When a tube drives a pulse through a delay line, the pulse would ideally 

be shifted in time but for practical considerations it is also distorted due to 

attenuation which is a function of the length 0£ line The pulse 1s narrowed 

at the top and broadened at the bottom since the frequency band pass of the 

delay hne 1s considerably below 5 Mc/s thereby seriously attenuating the 

harmonics 1n a pulse Timing numbers are modified to accomodate this 

distortion according to the following 

0 to 0 33/sec 

0 67 to 0 9~sec 

±!l:l 

:-rr+T 

+3,-3 

-3 +3 

o. 34 to 0 66~sec 

1. 00 JA'sec and over ~ 

~ 

The pulse output of a 50 microsecond delay line driven by a stage 

clocked with CP1 is 

= 

15 

87 123 

72 138 
REF ID:A71743 

B. Gate Tolerances 

In the normal sense tolerance 1s understood to mean a specified allowance for error in we1gh1ng, mcasur1ng, etc., or variations from the standard 

or given d11nens1ons, weight, or the hke In the sense as apphed to dynamic 

circuitry, it indicates the maximum allowable deviation a pulse or set of 

pulses may vary in f!hapc or time position without affecting the reliable 

operation of a gate. This usually apphes to the "AND" gate of a stage and 

is calculated for both enabling and inh1b1tlng cond1t1onfii 

(1) Enabling Tdlerance 

Assume the simple case of one stage clocked with CP1 driving another 

stage clocked with CPz ~ 

--------~~"--_+ Rec1rculahon 

Input from stage _ 

clocked with GP 1 CPa. 

The recirculation is used as a method of ma1nta1ning an input pulse for 

the full duration of the clock pulse in order to get a fully regenerated and 

reshaped output pulse The following sketch shows the time relat1onsh1p of 

the pulses 97 50 97 

\102 45 ~ 45/

0 

Input 

Output 

I 

I 35 75 

__ ;_-=-Z4;;;J) 

I 

I 

: ~~8~6~~~~ I I 

I 6,_o __ l __ 1 ___ 00 

49~: ~Ill ~A~-, -~-B1 ~C~ ~D~ \ . \j_ ~ ffl34 ttt:------

Enabhng tolera~ 

16 
REF ID:A71743 ....... 

-

The ideal case is to get the B and C tolerances equal In the system where 

four phases of clock pulse are employed this 1s quite easily achieved When 

more than one input pulse is used, the A tolerance is determined by the input 

having the earhest A point, the B tolerance 1s determined by the input having 

the latest B point, the C tolerance by the input having the earliest C point, 

and the D tolerance by the output pulse D point 

(Z) lnlub1ting Tolerance 

When an inhibitor 1s used, it must be remembered that an "AND" gate 

can operate only when all inputs are enabled, therefore, to 1nh1b1t an "AND" 

gate the inh1b1tor pulse needs to be wide enough to prevent gate action during 

the composite overlap of all the inputs Take the following simple case with 

one enabler and one clock pulse to be 1nhib1ted. 

Enabler from a CP 1 stage 

Inh1b1tor from a CP1 stage 

+ 

50 75 CPz 

I

r----'-"'\ Overlap of CPz and the input 

45 _s_6 __ e_n_a_bler to be mh1b1ted 

The 1nh1b1tor and enabler time rel ationsh1p 1s as follows• 

1\102 50 75 50 

45/ \s6 45/: 

Enabler overlap 

I I I 

I I I 2f\ I 186 

I 

75/1 

I Direct 1nh1b1tor 

I 1351 I 

I I I I I I 

I 148 I I 113 I 

I I :\61 I I 98/! Delayed 1nh1b1tor 

I I I 

I I I I I ! I I 

14 ~ 

~ r7 1~ )'I 

10 14 13 

2.7 37 Inh1b1ting tolerance 

17 
- REF ID :A71743-

It can be seen that the inhibitor pulse is not wide enough to completely 

prevent gate action, therefore, it is effectively broadened by a·. ZS microsecond delay line to provide inhibition over the entire overlap period of the 

enablers plus a margin of safety. · 

The following example shows a simple arrangement of a fiip-fiop with 

timing numbers for all the leads and the "AND" gate tolerances: 

60 ~~ 100 .---...._ ......... 75 _ _. 

49 111) 

2T4 ---------

**2~ 

-1T2 / 

35175 

24 86 

87 

7Z 

85 125 

~ 74 136 

---+ 

75 122 

70 127 

Enabling tolerance = (75-63) (97-85) 

(46-27) (70-36) 

= 12112 

19 34 

Inhibiting tolerance = (70-61) (99-87) (Zl-14) 

(48-22) (75-38) 

V. Ciate Resistor Calculations. 

= 

ill ill 

Z6f37 

Gating circuits may take any of a large number of forms depending on 

function and type of circuit components. An "OR-AND-OR" arrangement 

has been adopted as normal practice in dynamic circuitry for a gating 

structure associated with a tube. The following example shows this 110RAND-OR11 arrangement: 

"OR" "AND" "OR" 

18 
REF ID: A71 74.lThis arrangement not only allows for a wide variety of ways to combine 

signals but also isolates all input signals from each other and the tube grid. 

The following sketch shows the component arrangement of the "OR-AND-OR" 

structure: 

I .. 

---1l..~-

-----:' . ,.._ __ _____ ; ( 

. -~-

I 

... L I I•••• • If ' 

·---~·' • T .. .,,. 

---~;t: .. ____ .. >J---- .... 

·· ·•·:i.·~ ---------t ...__....., _ _.,------ .. ,:~ 

~~ . -~-c 

ii~ R3 ].::' I•~'_ •IO'lf. 

·- _..,__ ) 1---- I 

1 _,S'v, -1 .. 

-5v. 

----! ,_ 

·--1 t:. ... 

---;c..-

---~<:. ... 

! 

I 

I 

I 

f 

•• L. 19 ·r"'' 

........ 

The. resistor values are calculated to provide pulse· rise and fall times 

of O. 1 microsecond or less when up to five inputs are connected into each 

resistor. The voltage'excursions on the grid are between -5. 5 V. and +z V. 

with the -5. 5 V. limit provided by a bumper diode with a half volt drop to 

-5 V. and the +z V. limit provided by grid current although in practice this 

does go a little higher, R1 is calculated first. It must supply sufficient 

current to discharge C1 from +z V. to -5. 5 V. in 0, l microsecond. C1 consists of 9 mmfd tube input capacitance plus 6 mmfd for wiring capacitances 

making a total of 15 mmfd. The average rate of discharge of C 1 is therefore 

75 volts per microsecond. The actual shape of the curve is not linear but 

rather exponential whose slop at any· point is: ~ = /;;:, E -,Q-, where 

e is the voltage across R1 at time t, and E is tile initial voltage across R1. 

Bute = E c ·,i\, , therefore,~= ~ • The steepest part of the curve 

is.at the +z V. level where C1 is just 'slarting to discharge so a conservative 

method is to choose the -5. 5 V. level as having a 75 volt!,Psec slope at 

which point 

de 59.5 

= dt R1 C1 

75 59.5 

10-6 = R 10-JZ 1 ~ 15 x 

19 
- REF ID :A7174§... 

59. 5 x 106 

15 x 75 

= 5Z,888 ohms 

. Allowing for 10 fl. tolerance R 1 = SZ, 888 x }I-- = 48, 080 

R1 is then chosen a• 47K. 

The formula usin1 voltage doesn 1t apply easily for calculatin1 Rz but 

the formula for current is more easily used. R 1 can also be calculated from 

the current flow. 

i = 

Substituting q = Ce i = de 

c dt 

This formula applies to R 1 as well as the one used above. 

Current through R 1 = 15 x io-1 2 x 7.f x 103 

10-6 

= 15 x 15 x io-3 

= 1. 125 ma 

R1 = 59. 5 = 5Z, 888 ohms 

1. 125 

Allowing for 10 % tolerance R 1 = 5Z, 888 x ~ = 48, 080 ohms 

tt 

Use R 1 = 47K 

.In calculating Rz it is pointed out that R2 must supply three separate 

currents: (l) the maximum current that can exist in R 1, (Z) the current to 

charge c 1 and c2 , and (3) the back current for the remainin1 diodes connected to R 1• The charging current for C1 and Cz is not exactly constant 

but is maximum at the start and minimum at the finish. Also the diode back 

current is not constant but is zero at the start and a finite value at the 

finish. These two currents overlap in time but not when both are maximum, 

therefore, the assumption is made that,on the average, one half of the diode 

back current is concurrent with the charge cu.rrent. c2 = 5 1nmfd and the 

20 
·--· ·--.. "-..... - REF ID: A71 74§.. 

-... ~·- .. 

"•i. ... 

diode back resistance is allowed to be as low as SOK. Allowing O. 5 volts 

drop across the diode connecting Rz and Ri the following expression applies: 

Current throuah Rz = 65 + Z + (Cl + CC)75 + 1 /Z x 10 

0.9R1 10- l/5x50 

Rz. 

= 67 

42.3 

= 1.58~ + 1.500 + .500 

= 3. 584 ma 

= 59. 5 

3.584 

= 16,60Z ohms 

Allowin& for 10 % tolerance Rz = 16, 602 x 10 = 15, 093 TI 

Use Rz = 15K 

R3 must also supply three separate currents: ( 1) the maximum current 

that can exist in R2, (Z_) the current to discharge Cz and C3, and (3) the back 

current for the remaining diodes connected to Rz. C3 = 5 mmfd. Allow one 

half volt drop across thp diode connecting R3 to Rz. 

Cur:rent through R 3 = 62 + 9 + (CZ + C~) 75 + l /Z x lZ 

0.9Rz 10- l/5x50 

= .!!_ + 10 x 10-lZ x 75 x 103 + L 

13.5 10-6 10 

= 5. 259 + o. 750 + o. 600 

= 6.609 ma 

= 65 - 9 = 

6.609 

8,473 ohms 

Allowing for 10% tolerance R3 

10 = 8,473 x IT = 

21 

7, 703 ohms 
- REF ID:A71743-

There are several methods for calculating these gate resistors depending 

upon the assumptions made and the results vary over a rather wide ranae such 

as this: 

R 1 ranges from 36K to S lK 

Rz ranges from 13K to 20K 

R3 ranges from 7. SK to 12.K 

In practice, however, crystal diodes ha.ve a finite back resistance which 

assists R 3 in discharging Cz and C3 and the tube grid assists R1 in discharging 

C1. It is also true that the greater the ratio of Rz to R1 the lower the permissible back resistance of the "AND" gate crystals. 

The following tables show current values in milliamperes for the gate 

• resistors: 

For R 1 = 47K · at top of swing +2. V. • at bottom of swing -S. S V. 

51. 7K 

47K 

42.. 3K 

minimum 

design center 

maximum 

I. 296 

1.426 

1.584 

I. 151 

1. 266 

1.407 

For R2 = 15K at top of swing +2. 5 V. at bottom of swing -8. S V. 

16. SK 

!SK 

13. SK 

minimum 

design center 

maximum 

3.606 

3.967 

4.407 

For R3 = 7. SK at top of swing +6 V. 

8. 25K 

7. SK 

6. 7SK 

minimum 

design center 

maximum 

8.'606 

9.467 

10.519 

zz 

4.273 

4.700 

s.zzz 

at bottom of swing -9 V. 

6.788 

7.467 

8.296 
REF ID:A71743 

• • 
CHAPTER 3 

THE VISUAL UNIT (VU) 

I Function 

The function of the Vuual Unit is to accept a 6-bit binary pattern of 

pulses and display it on lights along with its decimal interpretation This 

will fulfill the need for evaluating bmary patterns of pulses quickly during 

both testing and operation 

II Symbolic Representation 

The following sketch shows how the Visual Untt may be represented 

in a block diagram· 

~ va 1 

vaz 

: va3 

: va4 

va5 

va6 vu vc 1 · va 7 VCz -

vaa VC3' 

va9 vc4 

vc5 VC6 _ 

. vb1 vc 7 

vbz vca 

vb3 vc9 vb4 

vb5 ·vb 6 

vb7 vb8 . vb9 

The functions of the leads may be defined as follows. 

va1 to va9 - Inputs associated with switch S1 Each may have 

P1 at any time within the range 1

T5 through 1

T1 

Z3 
- REF ID: A71 74~ 

vb1 to vb9 - Inputs associated with switch Sz. Each may have 

P 1 at any time within the range 1T1 through 1T3. 

vc 1 to vc9 - Inputs associated with switch 53. Each may have 

P 1 at any time within the range 1T5. 

III. Application 

There is only one logical application for the Visual Unit. It is a means 

whereby a quick visual interpretation of a pattern of six pulses may be obtained directly without the aid of an oscilloscope. When built into a machine 

or an assembly of units. its chief purpose would be to permit an operator to 

display visually quantities present in counters, adders, storage units, etc. 

On problems where recording time is of no great significance this makes 

poseible a quick visual recording facility without providing necessary circuitry to operate a page printer or typewriter. It has obvious advantages 

during system testing and trouble shooting as well. 

IV. Operation 

The main portion of the Visual Unit consists of a six microsecond storage loop with three input points and a translator to convert its contents to an 

easily readable form. The three input points are associated with the three 

tubes in the storage loop. At each point a 10 position Z gang switch selects 

one of nine inputs or allows the loop to be closed. For example: switch 51 

associated with tube l, is used to select inputs on lead va1 on position 1, 

lead va~ on position Z, etc. through position 9. In its zero position nothing 

comes in and the loop is closed for pulse circulation at that point. In order 

to position input patterns properly each input is supplied with places for delay 

lines in increments of . ZS microseconds from zero up to and including 2. 00 

microseconds. The three tubes in the storage loop are spaced two microseconds apart in time. This in conjunction with the variable delays for each 

input signal makes it possible to accept a 6-bit pattern-timed at any time in 

the six microsecond cycle. For proper operation two of the three switches 

must be set on their zero positions in order to insure a full six microseconds 

of storage for a pulse pattern entering via the third switch. 

The six pulse positions of the storage loop are sampled every six microseconds and stored on six detectors each of which drive a two position relay 

through a triode to control the translator. One contact of each relay operates 

a neon light in addition. 

Z4 
REF ID:A71743 

The following sketch shows pulse patterns !or the value 44 timed P 1 

at 4T5 fed m on lead va1 

T41 T31 Tzl T\1 1 T6j T 51 T4j T31 Tzl T 1 I T61 Ts I 

I I I I 

I I I I 

I I I I lva1 I I I r 

I I 

1

Tube l 

I 

1Tube Z 

I 

1Tube 3 

I 

1Gate 4a 

I 

n IOate 4b 

I 

IGate Sa 

I 

'Gate Sb 

I n, 1

Gate 6a 

I 

n I Gate 6b 

The translation is done in two parts The first part consists of two 3 to 

8 translators and the second part is an 8 x 8 matrix The three low order 

bits P1. Pz and P3 operate a 3 to 8 translator tied to -65 volts and the three 

high order bits P4, P5 and P6 operate a 3 to 8 translator tied to +62 volts 

The two sets of 8 outputs thus derived are used to drive the two sets of 

coordinates of the 8 x 8 matrix containing a neon at each intersection At 

the intersection where one coordinate is high from the +62 volt translator 

and the other coordinate is low fro1n -65 volt translator one neon is illuminated which 1nd1cates the decimal value of the 6-b1t pattern The 6-bit pattern 

is displayed on the set of 6 naons For example, the value 44 causes neons 

32, 8 and 4 of the set of 6 neons to be illuminated and neon 44 of the set of 

64 to be illuminated The relays 1n the Visual Umt forbid its use as a continuous mom tor for patterns that are constantly changing at a rapid rate, however 1 

it may be used as a monitor for patterns that remain constant for several seconds such as thos~ encountered in a slow running Mod Counter 

'25 
REF ID: A71 743"" 

IV. Physical Characterictics 

The Visual Unit is built on one chassis with an approximate circuit component requirements as follows: 

Vacumm tubes: 

Pulse transformers: 

Crystal diodes: 

Delay lines: 

Resistor al 

Filament 1lransforme r: 

Relays: 

Neons: 

Switches: 

3 type 6AN5, 3 type 12AT7 

3 plug-in ferrite tyJ>e 

158 Kemtron type K-345 

6 sticks minimum, 60 sticks maximum 

172 

l Thordarson type T21Fl2 

6 type SM5LO (Potter-Brumfield) 

70 type NEZ 

3 Graybill miniature 10 poa. 2 decks 

The power consumption on the more important voltages for one chassis 

h approximately as follows: 

Current Watts 

+200 v. O. 18 amps 36 

+62 v. 0. Z6 amps 16 

-8 v. -0. 03 amps -.24 

-65 v. 0. 39 amps 25 

110 v. a. c. . 14 amps 15 

The total power consumption is approximately 90 to 100 watts which 

represents a heat dissipation of 5 to 6 B. T. U. per minute. 

Z6 
-66V 

+62V 

' 

NOTE 

r:i'O 

"'a 

in- • (\J ie 

SIMILAR SWITr 

ARE ASSOCIA H STRUCTURES 

2 a 3 TEO WITH TUBES 

+ 7V 

+ 235V 

va2 ¢ va3 ¢ va v ¢• l' va, va, va, va, 

tg\ ,, ' '' I r ¢ ' 1 J I : I I~ 'O' r,;1 r : e, , ' y r-9 

va 1 

¢ 

,..i., 

,-1 I -I rO' , 101 I I I r1 I r'., .,. 9 1iJ I-~ 101 IOI I o, 101 I I 

..,., L;> c;J ' 1~, : 101 I ~11 -6 l I 'T I <;" I c-1 I 

1 1 ~ f : u· ; :-1 ~ 1· ~" , 

I- t I I I I I I 

r-1 r-1 I- I I I 1 I I 

,1,,~,n·r~ f' ' ' 

I : I ' " ' • ' I " I ' I I l r'- ! I l[' > 'J' > I : I > : ' I > I I I I I T : r< I ,4-

;5: 

9 

1 I 

nrQ--~ __ 9C I 9 

518 

VISUAL UNIT 
REF ID:A71743 
REF ID:A11143 

.. 
:.., 

REF ID:A71743 
I. Function 

REF ,IQ...:~ ll '.L~ 

e TOP ~hbK:b l e 

CHAPTER 4 

THE MOD-COUNTER (MC) 

Counting is a very common operation in the functioning of analytical 

machines, but frequently counters are designed around a fixed modulus 

such as 10 or some power of 2. In DERVISH, however, the object was 

to design a counter with a settable modulus and enough flexibilities for a 

number of applications. 

The Mod-Counter now designed to count at a maximum rate of 167, 000 

counts per second operates on a six microsecond time cycle. It is suitable 

for a variety of applications and may be adjusted for any modulus up to and 

including 64. It is also capable of counting at a rate of either +l or +z. 

II. Symbolic Representation 

The following sketch shows how the Mod-Counter may be represented 

in a block diagram: 

ca 1 

~ caz 

. cb cd1 ~ 

MC 

;. cc cdz 

cez cg ~ 

~ 

Mod M 

cez 

;. cf 

·ch 

Leads caz and cb have facility for one microsecond plug-in delay lines 

to permit counting at a +z rate. Also, leads caz, cc, ce, and cf have plugin delay lines up to 1. 00 microsecond to permit the use of signals which may 

occur early by that amount with respect to the prescribed time. These delays 

are ignored 1n the following discussion except where specifically noted. 

Z7 

NSA Form 78l·C10 6 Jul 51 TOP SECRET 
The functions of the leads may be defined as follows: 

cb - Count Input. This lead must have pulses at all times when no count 

is being made. For each count a blank must occur at 3T6. 

caj\·Count Control. The signals on these leads determine when counts are 

cal) made. If neither lead is used, a count is made solely by the blank at 

3T6 on lead ch. If ca1 is used, a count is made when both cb and ca1 

have a blank at 3T6. If both control leads are used, a count is made 

only when blanks occur at 3T6 on leads cb, ca1 and caz simultaneously. 

cc - Reset. This lead must have pulses at all times normally. Reset takes 

place when a blank occurs at 3T6. The blank may be followed by 1 to 5 

additional blanks during the reset cycle without harm. 

ch - Reset Control. The signal of this lead controls the reset action of the 

signal on lead cc. When this lead is not used, a reset i~ effected for 

each occurrence of a blank at 3T6 on lead cc. When this lead is used 

a reset is effected only when blanks occur on both ch and cc at 3T6. 

cf - Mod Input. This lead must have a pattern of negative going pulses 

timed P 1 at zT1 for the value of the modulus minus one. 

cefi-Preset Count. For normal reset to zero, one of these two leads rece~ quires a constant stream of pulses during the reset cycle. For a reset 

to some other value such as 5, the lead that is used must have a pattern 

of pulses for the value 5 timed Pt at 4T6 during the reset cycle. Both 

leads can be used in the case where the Mod-Counter is preset to some 

value within its operating range then resets to zero each tim\ thereafter. 

For example, ce l could be supplied with a continuous stream of pulses 

(representing zero) and cez supplied with a preset pattern representing 

some other value. The cyclic reset would always be to zero since the 

pattern on ce1 would over-ride that one cez but when an initial reset is 

made, the pulses on c~1 could be stopped, thereby allowing a preset to 

the value of the pattern on cez. 

cdi- Output. This output is timed P1 at 4T6 and could be considered as the 

value of the count just prior to the next count. 

cdz- Output. This output lt timed Py at 1

T1 and is always the newly formed 

count whether reset or just after the most recent count is added. 

cg - Carry Indicator. This lead is not a true carry indicator but rather it 

indicates that the content of the counter has built up to its highest value 

ZS 

NSA Form 781-CIO 6 Jul 51 TOP SECRET 
as evidenced by a comparison match with the mod input on lead of. 

This means that when the next count is added the contents of the counter 

must return to zero on a preset value. This is the same as indicating 

when the counter has reached the end of a cycle. 

It is not necessary to use all input leads at all times, especially those 

put in for control purposes. For example: the count control leads ca1 and 

caz are not required for counting but are provided so as to make the process 

ol counting subject to conditions. The application will determine how many 

of these leads are to be utilized. 

III. Applications a.nd programming considerations 

A. Simple Counting 

For simple straight counting, a minimum set of connections to the 

counter need to be used. The following sketch shows this representation: 

Coun t Input ~cb cd 1 -

MC 

t . cc cd2 . Mod 64 Rese 

Zero · ce cg carry indicator . 1 

Totals not in excess of 63 will accumulate in the counter and be available for output on lead cd2 with P 1 at 1

T1 or 5 3/4 microseconds later on 

lead cd 1 with P 1 at 4

T6 • The indication that the count has reached 63 is 

provided by the occurrence of a blank on lead cg at 3

T6 . 

B. Cascade Counting 

( 1) For Moduli up to 64: 

When it is desired to count items whose total exceeds 63, two or more 

Mod-Counters may be operated in series or cascade. When this is done, 

the connections to each counter are similar to those used when a counter 

is used by itself. The main difference occurs in the control of the successive units. 

Z9 

l'l~A rorm 781-GlO 6 .;ul 51 TOP SECRET 
The following example shows three counters in cascade: 

..-~~~~~~~~~~-.--~~~~~~~~.---~~~~~~Count input 

--~~~~~~~~4--~.-.~~~~~~-+~~..-~~~~~~~Reset 

..0 u nl - ..0 u .D u 

u u u u u u u 

MC3 MCz MC1 

Mod M Mod M Mod M 

N 

- N - N 

"C 

u u 

Q) 

u 

bl) "C 

u u 

G) 

u 

bO "C 

u u 

Q) - Zero 

This is a good example of a straightforward metric arrangement 

regardless of the modulus. By using a modulus of 10, however, a normal 

decade is represented. 

(Z) For moduli greater than 64. 

(a) Factorable moduli. 

In the above example of counters used in cascade, the same modulus 

may be used for each counter to produce a regular counting sequence but 

a different modulus may be just as easily applied to each counter to produce 

a somewhat irregular counting sequence. In either case, the evaluation 

of the total count in the cascade is the sum of the products of the contents 

of each counter times the modulus applied to its controling predecessor. 

The following example shows how the product of two different moduli 

can be used to effect or simulate a large modulus: 

-

-

, •It ~ .i;- ~I- w 

u ,D ,...N 

u u nl nl u u 

.D 

u nl - u u u 

MC5 MC4 

Mod 10 ModlC 

N - N,... 

"C dl bO "C Q) 

u u u u u 

l 'f _J t 

t 

NSA Form 78l·C JO 6 Jul 51 

·~ . l • ' I •• 

u ..0 ,... N u ,..0 .... u ..0 

u u nl nl u u nl u u u u u 

MC3 MCz MC1 

Mod 10 ModZl Mod 29 

N - - .... bO"C Q) bO G) bO G) 

u u u u u u u 

u ,___j t _J r - -

30 

TOP SECRET 

Reset 

Count input 

Zero 
In this normal cascade arrangement MC 1 counts every item, MCZ 

counts every 29th item, and MC3 counts every 209th item, This is an 

easy means of obtaining a large modulus provided none of its factors are 

greater than 64. 

(b) Non-factorable moduli 

It is also possible to obtain a non-factorable modulus between 64 and 

128 such as 89 using an external flip-flop in conjunction with a Mod-Counter. 

The following sketch shows this: 

' 

l rL l 

ii 'I •• l 1 

() .0 .-. N U .0 ..-! N 

u () IV <II uunlro 

u () u () 

MC4 MC3 

Mod 10 Mod 10 

N ..... N ..... "ti 41) b.O "ti Q} 

u u u u () 

t L-l t 

' • 

l 

u 

() .0 

u u 

nl -

MCz 

Mod 10 

N ..... b.O '"Cl cu () u () 

i--l i 

,, 

~ 

... - • --i I I I 

I FFl 

I I 

I I 

I I 

I I 

L_j-- -

Zero 

' 

u .0 

u u 

MC 1 

Mod 64 

'"""N 

bl) ., ti 

u u () 

j T 

Cou 

Reset 

nt input 

Pattern 

f or 39 

The flip-flop has two functions: ( l) to control the counting of MCz 

in such a mann~r that MC1 counts up to its upper limit twice for each 

count entered into MC2 ; (2) to control the ce 1 input to MC1 in such a 

manner that MC1 alternates between two counting ranges 0 - 63 and 

39 - 63. 

The sum of the lengths of the two ranges would, therefore, represent 

a modulus of H9 (64 + 25) or a rate at which MCz would be allowed to count. 

The two ranges might just as well be 0 - 44 and l - 44 giving lengths of 45 

and 44 or any other two lengths whose sum is 89 provided they both have 

the same top value and not greater than 63. 

C. Rotor Position Indicator 

The process of indicating consecutive positions of a cipher machine 

rotor is really nothing more than counting the successive times it has been 

stepped from some starting point. The Mod-Counter is ideally suited 

31 

NSA f-orm 78l•CIO 6 Jul 51 TOP SECRET 
for this purpose. A Z6-point rotor has positions that can be represented 

by 0, 1, Z, 3, •.... 25, 0, 1, ••.•. etc. This represents successive 

counts on a modulus of 26. The stepping of the rotor can be controlled 

since the counting is subject to conditions on leads ca1 and ca2 • It can be 

seen that a rotor ensemble may be represented by a group of mod•counters 

whose stepping may be controlled according to some motion pattern applied 

to their various ca leads. They can be reset to any position from which to 

start a stepping sequence since the Mod-Counter can be reset to zero if 

lead cc 1 contains a continuous stream of pulses or to some other value 

represented by the pulse pattern on lead cez if lead eel has no pulses. 

The pulse pattern source for lead cez may be sorne fixed pattern, another 

Mod-Counter controlled to provide consecutive reset values, or some 

other generator source. 

The following sketch shows how rotor positions of a 4 rotor ensemble 

may be generated: 

' ~ . 1 

u ,.0 ...... u ,.0 ...... u u cd u u cd u u 

MC4 MC3 

Mod26 Mod 26 

N ...... N ...... 'U v "Cl v u u u u 'f' 1' 

'v 1V 

. l 

u ,.0 ...... u u "' u 

MCz 

Mod 26 

N ...... 'U v 

u u 

1' 

. ~ 

, ' J, 

u ,.0 ...... u u "' u 

MC1 

Mod 26 

N ...... 'U v u u 

T 

.~ 

.- - - - i• - J .... - .., 

I Motion I 

I I 

I Control I 

I I 

I l I Li--.-, -·r--:; - --l 

Cou 

Reset 

nt input 

The Motion Control in the foregoing sketch is shown merely to 

indicate the connections to the Mod-Counters, especially the ca1 leads. 

In the normal sense the positions of a rotor may control the stepping 

of another so the cd leads are shown going into the Motion Control. 

The ce 2 leads shoula be supplied with patterns of pulses representing 

the positions to which the rotors reset. 

NSA Form 781-C10 6 Jul 51 TOP SECRET 
Since the Mod-Counter has a basic cycle period of 6 microseconds it 

is pos::iible to produce 167, 000 successive rotor positions per second. The 

time for res~tting to a new position is the same as for stepping. The following ske-tch shows how seven Mod-Counters can be connected to represent 

rotor positions in an array of three 26-point rotors which step 19 positions 

in their motion cycle from every possible starting point or setting: 

.. ~T l .r;-- J.b T J: I 

u .0 ,...... N .D ,_. N u ,.!) ..... Ill Ill u ro u u u u Ill ro u u u u u u u 

MC3 MCz MC1 

Mod 26 Mod 26 Mod 26 

- - .... ...... ..... ..... 'ti ., bO'O ti OD 'U ti 

u u u u u u (J (,' 

--1 L--J 

-

. • 1 .~ ,, 

N~ U .0 ..... N~ u .a ..... N~ 0 .0 8 u u u nl 8 u u u nj ~ u u u u u 

Mr6 MC5 MC4 

Mod 26 Mod 26 Mod 26 

N ..... N ..... N 

'ti t> '"cl ti '"cl 

u u u u u ... .. 

I ' 

J. 

..... 

rd 

u 

..... 

ti 

u 

"' 

" l 

u ,.0 

u u 

MC7 

Mod 19 

..... bO ti 

u u 

1 

l 

rj_ - -----1 

r--•• -...l•..J~ I I I I: Motion I l F F l 1 Control I 

I I -- __ ...J 1 I L-,-.-r--.J 

R eset 

3T6 

Zero 

The foregoing sketch may be considered to consist of three parts: ( 1) 

a metric type counter consisting of MC I• MC2 and MC3 ; (2) the position 

indicators MC4 , MC5 and MC6; and (3) the controling units consisting of 

MC7 , FF and the Motion Control. The function of the first part is to 

supply the second part with a new reset value every cycle• and to do this 

it must count one position e-ach 19 cycles. MC7 provides an easy method 

of deriving a 19 character cycle. The function of the second part is to 

generate the 18 succeeding positions from each starting point of the three 

:n 

NSA Form 781·C10 6 Jul 51 TOP SECRET 
rotors whose stepping is controlled by the Motion Control. The third control element is a flip-flop normally generating a continuous stream of pulse• 

but is turned off for 6 pulse times every 19th cycle allowing MC4 • MC5 and 

MC6 to be reset to the respective values in Mc 1, MCz and MC3 which then 

advance to the next position. This means that after a reset of MC 1, MC2 

and MC3 successive starting points 000, 001, 002, 003, etc., will each be 

used as the first position of a 19 step cycle of the rotors. 

IV. Operation 

The heart of the counter consists of an add-one circuit in a 6 microsecond delay line storage loop. Three tubes with associated gates accomplish this function but two more tubes are used in order to provide the 

functions of reset and carry indication. The timing in this unit is chosen 

so the output of tube 3 is P1 at 11'1 as shown on the first logical diagram. 

An alternate timing may be used whereby the output of tube 4 is P1 at 1 T1 

as shown on the second logical diagram. In the following description the 

negative signals are omitted. 

In normal operation, according to the first logical diagram, tubes 1 and 

Z put out continuous pulse trains and the six bits representing the count N 

circulate in a closed loop consisting of tubes 3, 4 and a 5. 50 microsecond 

delay line. Tube l puts out a blank, or no pulse, in the P1 position when 1 

is to be added to the count circulating through tube 4 and puts out one additional blank for easy carry over into a next higher pulse position. Tube 3 

forms the sum N + 1. Tube Z, while running continuously, enables the 

count to be held in the loop but turns off for six microseconds when the 

counter is reset. The reset can be effected either by a blank signal on lead 

cc and lead ch or when tube 5 is off and l is added to N. The comparison 

tube 5 is off at 3T6 only when the circulating count has grown until it has 

become equal to one less than the mod capacity of the counter. This indicates that on the next count added, N should return to zero or some other 

preset bottom value as determined by the signals on leads ce 1 and ce2 • It 

is not necessary to use both these leads at the same time and in cases where 

only one is needed either one may be chosen since they both drive the same 

"OR" gate. How they can be used to select zero or some other number for 

presetting is more fully demonstrated in Par. III C. 

A provisional count control is made possible by leads ca1 and ca and 

provisional reset by lead ch. Their patterns of pulses are not criticl\. 

except at 3 T6 when they must be correct. At all other times they have no 

effect on the circuit. An example of the use of one of these leads may be 

shown when two or more counters are cascaded as covered in Par. III B. 

34 

NSA Form T81•CIO 6 Jul 51 TOP SECRET 
The following sketch shows pulse patterns at various points in the counter 

through four cycles with a modulus of 26 and a circulating count of 23: 

r 

T6 I 

lea 

L-------1 l 

I I cb .._...;.._ _ ___,: 

I 

I cc 

I 

I tube 4 

I 

I tube l 

I 

I tube Z 

I 

tube 3 

I cf 

I 

I tube S 

I I ~----~~:__~~------J~__:..------r---7~----_;..----;...~I 

1 I ca 1 

• I 

35 

NSA Form 781·CIO 6 Jul 51 TOP SECRET 

I 

1--...:.--~' c b 

I 

I cc 

I tube 2 

I 

l eel 

tube 3 
It can be seen in the foregoing example that on the fourth cycle the output of tube 3 could have been a pattern of pulses from lead cez provided the 

stream on ce 1 had been made blank for those six microseconds. Since ce t 

had a continuous pattern during that cycle no existing pattern on cez could 

have had any effect on tube 3. By controlling the pattern on ce 1 to be OFF 

or ON at the proper t~me, the counter can be preset to some value, within 

its counting range, other than zero. 

In order to demonstrate how the "AND" gate of tube 5 detects when the 

count in the counter has built up to its top value, assume a modulus of 10 

which means lead cf should contain a pattern of negative going pulses timed 

P1 at 2T1 which represents ( l 0-1 ) or 9. The pattern for the value 9 will fail 

to inhibit the "AND" gate action during at least one pulse position for all 

counts 0 through 8 causing the flip-flop of tube 5 to turn ON. Whett the count 

of 9 is reached the inhibition pulses on lead cf coincide with all the enabling 

puhes in the count pattern and the flip-flop of tube 5 does not turn ON, 110 

the signal on lead cg is blank at 3T6 indicating that the full count is reached. 

The next occurrence of a count will cause tube Z to turn OFF for 6 microseconds thereby enabling tube 3 to put out the reset value.· 

Pulse patterns on the "AND" gate of tube 5: 

Tube 5 

turns ON 

Tube 5 doe S) I 

not turn o~_.r-41 

NSA Form 781·CIO 6 Jul 51 

T4 Tz T1 

TOP-~ECRET 

Pattern for 9 

Count of 0 

" II 1 

II II 2 

II II 3 

" II 4 

II II 5 

II ti 6 

" II 7 

II II 8 

II II 9 .... 
V. Physical Characteristics 

Four complete and separate Mod-Counters are built on one chassis with 

all input and output leads available on the two plugs at the back of the chassis. 

The four units are functionally independent but are tied together electrically. 

The circuit component requirement for one chassis of four Mod-Counters is 

approximately as follows: 

Vacuum tubes: 

Pulse transformers: 

Crystal diodes: 

Delay li:nes: 

Resistors: 

Filament transformers: 

ZO type 6AN5 

ZO plug-in ferrite type 

42.~ type 1N34, CK705, or comparable type 

52 sticks of one microsecond or fraction 

Z32 

1 Thordarson type TZlFlZ 

The power requirement for one chassis varies somewhat due to -resistor 

values used but an average approxima.tion for the power consumption on the 

more important voltages is as follows: 

Current Watts 

+zoov o. 4 amp. 80 

+6ZV O. 5 amp. 31 

-BY -0. 25 amp. -1 

-65V O. 9 amp. 58 

llOV a-c o. 55 amp. 60 

The total power dissipation is approximately 230 to 250 watts wbidh 

represents a heat dissipation of 13 to 14 B. T. U. per minute. 

37 

NSA Form 781·CIO 6 Jul 51 TOP SECRET 
4Ts __ ----

r 

._____ ~ ' --~------ ~--t-1 

t, 

ALTER'\JATE 

ce2 

PRESET 

COUNT 

TIMING P1@1Ti 

I 

ch 

CP 4 

cf 

, COUNT l'lPUT @ 

{RESET @ - 4T6J 

4Ts1 

lRESET c ONTROL 

@ 4TsJ 

3T1 

' 

, l ___ _:_+/ 

l 

MOD INPUT 

P1@3T1 

cg 

CARRY 

l"IDICATOR 

@ 4Ts 

NOTE 

3Ts 

I I I I 1

q--,r-,~-zs 

I I _.7 

40 • ~~ 

: I I 

I 9 

I 

I 

I 

I 

11~~ f • 

c__!J 

cd 1 

OUTPUT 

P1~4Ts 

COvNTING 

FCR + 2 COUNTING 

;91 ~ --· I 

I 

i 

I 

1- +I " 

I I 

: , . ,.l, I 

i""}I l 

~I I 

I I I . ~ I 

I 

~ I 

~ 

,ce, ce2 

P'lESET 

C.CUN~ 

I 

co.., 11 I

' l CJlJi'IT ca2"' ' CCNTRCi..@ 3T6) 

---ch iiESET CONTRC' 

@ 3TsJ ~ 

I ' 

r-'~~ 

·-~~ ' I y ' 25~~! ~:' ' '5 ' 

fo-,,01 ' :l\1 : : 

: ! l ' 

I I I 

cf 

i 

cg 

CARRY 

INDICATOR 

NCiitl A! P. @4T6 __ ..:...:.::-:___~T~l M~I ttJJ GG I 

cd 2 

OUTPUT 

P1@1T1 

"1CD •NPUT 

P,@2T1 

@ 3r6 

MOD-COUNTER 
REF ID:A71743 
REF ID:A71743 
REF ID:A71743 

M.C. 
REF ID:A71743 
REF ID:A71743 

CHAPTER 5 

THE MOD-ADDER (MA) 

I. Function 

The Mod-Addet" performs three independent functions with equal ease 

and facility. Notes. 1, Z, and 3 on the logical diagram indicate the arrangement of five plug-in delay line sticks or connecting links to be used to rnake 

the unit function as a Mod-Adder, a Mod-Subtractor or an Absolute Differencer. When the'. function of modular addition is being done, the sum of 

two numbers is for~ed and adjusted according to some preset modulus and 

the result is supplied as an output. When the function of modular subtrattion 

is being performed, the difference of two numbt•rs is formed and adjusted 

according to a preset modulus and the result supplied as an output. When 

the function of forming an absolute difference is performed, the smaller 

of two quantities is subtracted from the larger and this difference provided 

as an output, 

In all three modes of operation, the same general characteristics apply, 

in that one 6 microsec<tnd cyle is consumed in each operation, each data 

input consists of a 6-bit quantity represented in serial binary form timed 

with P 1 at 1 T1, and the output is a 6-bit quantity in serial binary form timed 

P1 at 1 T1• In all cases, no input quantity can be equal to or greater than 

the modulus, which in turn, must be equal to or less than 64. 

II. Symbolic Representation 

The following sketch shows how the Mod-Adder may be rep.resented in 

a block diagram: 

• aa 

: af MA 

ad . 

·ab (aa + ab) 

ae . 

ag Mod M 

ac 

38 
REF ID:A71743 

The functions of the leads may be defined as follows: 

aa\ - Inputs. These leads are to be used for supplying the two operands to 

al?} the Mod-Adder. The pulse patterns should be timed Pi at iT1. 

af 1 agJ - Input controls. When these leads are not used, the inputs on leads aa 

and ab feed in normally. When they are us~d. they paos or stop the signals on leads aa and ab respectively. For example, when af is used, it 

must be supplied with pulses all times that the input on aa is to be prohibited from entering the adder and blanks when the input on aa is allowed 

to enter the adder. 

ac - Mod inp11t. This input is for the modulus and must be timed P 1 at zT1• 

ad - Output. This lead provides the output result timed Pt at 1

T1. 

ae - Exceed indicator. This lead indicates when the result of the modular 

addition or subtraction required adjustment to be correct. For example, 

during the output cycle, lead ae will have six pulses if the sum of the 

input quantities is less than the modulus or it will have six blanks if the 

sum of the input quantities is equal to or greater than the modulus. 

HI. Application and Program Considerations 

A. Nominal Use 

The simplest application of the Mod-Adder is that of just forming a 

sum, or difference, of two 6-bit quantities and adjusting the result to some 

modulus. It was first designed to fulfill one specific requirement, namely 

to represent the relative displacement of two items when the absolute displace -

rnent or position of each is known. For example, if item A was moved lZ 

miles due west from a given starting point and item B was moved 3 miles due 

west from the same starting point the relative displacement of A with respect 

to Bis (12-3} or 9 miles due west. 

B. Accumulation 

(1} For totals less than 64. 

The Mod-Adder is readily adaptable for use as a 6-bit modular accumulator so long as each quantity being accumulated is less than the modulus. 

By using its output on lead ad as an input on lead aa, the growing sum circ.&.tlates around on a six microsecond cycle and quantities fed in on lead ab 

39 
REF ID:A71743 

are added into this sum. Lead af provides an erae:e or reset to zero feature 

while lead ag can be used as a suitable control to add zero or some quantity 

from lead ab. The fol lowing sketch shows this arrangement: 

aa 

MA 

Input ab 

(aa+ab) 

Erase oi Reset af ae ....,_-~Exceed Indicator 

Mod 64 

Input control ag 

{Z) For totals equal to or greater than 64. 

When it is desired to accumulate quantities whose total is 64 or greater, 

an arrangement consisting of one Mod-Adder and some Mod-Counters ran be 

made to form an accumulator whose capacity is more than 6 bi.nary places. 

In this use the alternate tin.ing for the Mod-Counter needs to be used. The 

following sketch shows an example of an accumulator with a 24 binary place 

capacity: 

_ .. 

h 

• ii .r-- ', l ' u .a - N U ,0 - N 

u u "' u "' u u u "' u"' u

MC3 MCz 

Mod 64 Mod 64 

..... ..... ..... .... 'tj Q) OO"'CS Q) 

u u u u u 

1" .___, f' 

" • 

'' '~ 

u 

u .a 

u -

"' u 

MC1 

Mod 64 

00 

u 

'1j 

u - Q) 

u 

- ~ t 

w 

4T6 

Iii ' r 

.0 00 "' "' "' "' 

MA 

(aa+ab) 

Mod 64 

Q) 'tj 

'----' "' "' Zero -

Co 

Eras 

Reset 

unt Input 

The counters serve to count the number of times that the Mod-Adder 

accumulated over its modulus. 

40 
REF ID:A71743 

C. Bi-Directional Counting 

On certain occasions it is desirable to have a counter which will go 

backward ..ts well as forward and counters havE" been built with that fadlity 

although they are not in great demand. 'The Mod-Adder is capable of performing that function when an external electronic switch is provided so lhat 

a ~·hoice of I or 63 may be added to give the effect of +l or -1. The output 

must be tied back to one of the inputs as in ar.cumulation. The followi n!!-

sketch clemon~trates the idea: 

aa adi--------+ Output 

MA 

Erase or Reset af 

(aa+ab) 

Jnput control ag 

Mod 64 r-------, 

ae ' s· 1gn ' ~ s· 1gn 

1 Indicator I L _____ _i r- - ---, I~ I 

I Switch 1----' 

63-1 : .___ __.J 

Control----------------------------~ 

A sign indicator could easily show whether the count in the adder is 

positive or negative. The circuit condition to control the sign indication 

would exist when 63 is added into the Mod-Adder and the signal on lead ae 

shows that the sum (63 - N) < 64. This would only occur when N = 0, or 

when the counter goei:1 from 0 to -1. When the count is negative, the pulse 

pattern 1s not the correct value but 64 minus the correct value. One way 

of getting around this ambiguity is to have another control on the electronic 

&witch to r~verse its selection function when the sign is negative. 

D. Generation of Number Sequences 

By appropriate arrangements of Mod-Adders and Mod-Counters some 

rather interesting number sequences can be generated. This is facilitated 

by the fact that the modulus for a mod-counter may be generated by another 

Mod-Counter or Mod-Adder. The variety of arrangements is practically 

41 
REF ID:A71743 

unlimited particularly when they employ units described in next chapters. 

The following sketch shows a simple arrangement~ 

Ze 

Re 

ro 

set .... __, 

'--! 

'-I 

ch 

ce1 

cb 

ce1 

MC1 

cg cf cdz · aa MA ad . Ot..ttput 

T (aa-ab) 

" Mod 64 

ca1 cdz ab 

MCz 

In this example MC1 is the faster stepping counter. MCz is stepped 

each time MC1 steps past its top "-&lue back to zero. Since the output of 

MCz is the modulus input for MC1 the top value for MC1 is periodically 

increased by one. When both MC1 and MCz start at zero the following 

sequences of numbers are generated: 

MC1 O, O, 1, O, 1,Z, O, 1, Z,3, O, I, Z, 3,4, O, 1, Z, 3, 4,5, 

MCz. O, 1, l, Z, Z,Z, 3, 3, 3,3, 4, 4, 4, 4,4, 5, 5, 5, 5, 5,5, 

)AA 0,63,0,62,63,0,61,62.,63,0,60,61,62.,63,0,59,60,61,62.,63f 0, 

E. Other 

There are undoubtedly other uses for the Mod-Adder which may be 

evident to the reader or which may arise as problem applications are exploited. The example• that have been given are merely suggestive and not 

limiting. 

4Z 
REF ID:A71743 

IV. Operation 

In normal operation of the Mod-Adder three input pulse patterns are 

utilized and two outputs are produced. All pulse patterns are used in both 

polarities (+)and(-), so hereafter references to pairs of leads will be made 

in the singular. Two of the input patterns timed P1 at 1 T 1 are the operands 

fed in on leads aa and ab and the third pulse pattern timed P1 at 2 T1 is the 

correcting modulus fed in on lead ac. The result or output pulse pattern. 

timed P1 at 1T11 one character cycle later than the inputs• is available on 

lead ad, Leads af and ag are provided to permit control of the input quantities 

on leads aa and ab, respectively. An auxiliary output is available on lead ae 

which indicates that the modulus correction had to be made for addition or 

subtraction or that a 2 's C'omplement had to be formed in the case of minor 

diffebencing, A Z •s complement of N when 6-bit quantities are used is equal 

to (2 - N). 

There are three distinct sections of the circuit which are: (1) the first 

section made up of tube 11 an adder-subtractor tube, and tube Z. a carryborrow tube; (2) the second section made up of tube 3, an adder-complementer 

tube, and tube 4, a carry tube; and (3) the output section composed of tubes 5 

and 6. In the first section, a sum or difference is formed from the signals 

on leads aa and ab. This result is added in the second adder to a pulse pattern 

on lead ac to form a second result. One of these two results is correct, the 

other incorrect and tube 5 selects the correct one for tube 6 to send out as 

an output. The condition of carry at the 6th bit position determines which 

result is correct. The three functions will now be considered in turn assuming 

a quantity P fed in on lead aa and a quantity Q fed in on lead ab, and a correcting 

modulus fed in on lead ac. 

A. Modular Addition (P + Q) Mod M 

The Mod-Adder performs this function when the appropriate arrangement of plug-in delay line sticks or links referred to by Notes 1, 2 and 3 on 

the logical diagram. When tube 2 is on, the addition rule for tube 1 is: 

0 + 0 = 1, l + 1 = 1, 0 + 1 = 0, and 1 + 0 = O. When tube 2 is off, the rule is: 

0 + 0 = 0, 1 + 1 = 0, 0 + 1 = 1, and 1 + 0 = l. The same rules apply to tubes 3 

and 4. The two quantities to be added, P and Q, can be any quantities smaller 

than modulus chosen, but the pulse pattern representing the modulus fed in on 

lead ac must not be the modulus but rather 64 minus the modulus, For example, 

to represent a modulus of 10, this pulse pattern should be for the quantity 

(64 - 10) or 54. The first section of the circuit forms the sum (P + Q) Mod 64 

and the second section forms the sum [ (P + Q) Mod 64 + (64 - M)] Mod 64. 

These sums represent (P + Q) and (P + Q - M), respectively, Three distinct 

ca.sea need to be considered. 

43 
REF ID:A71743 

Case 1: (P + Q) < M 

In this case the sum is formed by the first section of the circuit which 

now functions as an adder, and since M cannot be greate1· than 64, the sum 

P + Q cannot exceed 63. Therefore, no carry will be propagated beyond the 

6th bit position in the first adder. At the sam.e time, the sum [CP + Q) + 

(64 - M)] Mod 64 formed in the second section, or adder, of the circuit is 

also never greater than 63, so no carry will be propagated beyond the 6th bit 

position, tube 5 will be enabled at the 3T6 sampling time and turned on for the 

next six microseconds thereby selecting the result from the first adder for 

tube 6 to provide as an output. For example, let P = 18, Q = 7 and (64 - M = 38) 

where M = 26, The first sum 18 + 7 = 25 which is less than 26 and 25 + 38 = 63 

which is less than 64. The following sketch shows pulse patterns at the main 

points in the circuit for P = l~, Q = 7 and M = 26, 

T6! Tsl T41 T31 Tz Tl T6 T51 T4 T3 Tz Tl I 

I I I I I I I I I I I I 

I I ~__flaa I I I I 

I lab I I I 

u-: ITube 2 

I I 

_!Tube 1 

~ ac 

I 

I Tube 3 

I 

I - ITube 5 

I 

1ad 

I I I 

Case 2: M '(P = Q) < 64 

In this case, the sum formed by the first adder is equal to or greater 

than the modulus, therefore, the corrected sum formed by the second adder 

is the proper result and the indication of this is the fact that a carry is propagated beyond the 6th bit position in the second adder. Tube 5 is caused to 

be in the off condition for 6 microseconds because one of its enabling gates 

has no pulse at the 3 T6 sampling time, therefore, it selects the sum formed 

by the second adder for tube 6 to provide as the output. The first adder can 

44 
REF ID :A717439 

not produce a carry past the 6th bit position since {P + Q) cannot exceed 63 

but the second adder does because [(P + Q) + (64 - M)] ) 64. For example, 

let P = 21, Q = 8 and (64 - M = 38) where M = 26. The first sum (21 + 8) = 29 

which is greater than 26 and the second sum 29 + 38 = 67 which is greater than 

64. The result is (67 - 64) = 3. The following sketch shows pulse patterns 

at the main points in the circuit for P = 21, Q = 8 and M. = 26: 

I , I 

I 

I I I 

Case 3: M ~ (P + Q) ~ 64 

I 

I I 

I 

ab 

1 Tube 2 

I 

~ __________ ,_n 1 I Tube i 

nJn h I 

I 

: : I ac 

ii I 

.._ _______ _, I I I I Tube 4 I I 

I I I Tube 3 

I I 

I I Tube 5 

I 

1ad 

In this case the correct sum is formed by the second adder and the indication of this is the fact that a carry digit is propagated beyond the 6th bit 

position in the first adder. Therefore, tube 5 is caused to be in the off condition for 6 microsecbnds just as it was in Case Z, thereby selecting the result 

formed in the second adder for tube 6 to provide as the output. The second 

adder cannot produce a carry past the 6th bit position because the maximum 

possible value for the sum formed in the first adder is 64 - 2 (64 - (M - 1 >] 

which is then added to (64 - M}, so the maximum possible value formed by 

the second adder is 64 - 2 [64 - (M - l)] + (64 - M) and Z (64 - (M - l)] > 

(64 - M). Therefore, the maximum possible value of the sum formed in the 

second adder is M - 2. For example, let P = 39, Q = 39 and (64 - M = 24) 

where M = 40. (39 + 39) = (78 - 64) = 14 and 14 + (64 - 40) = 38 which is equal 

to (40 - 2). The chief difference between Case Zand Case 3 is the source of 

the indication which controls the output selection since in both cases, the output of the second adder is the correct result. 

45 
REF ID:A71743 

B. Modular Subtraction (P - Q) Mod M 

When the function of modular subtraction is to be performed, the appropriate arrangement of the plug-in delay line sticks or links referred to by 

Notes 1, 2 and 3 on the logical diagram must be made. The first section of 

the circuit, involving tubes 1 and Z, now functions as a Mod 64 subtracter and 

the second l:iection as a Mod 64 adder. When tube Z is ON, the subtraction 

rule ior tube 1 is: 0 - 0 = 1, 1 - 1 = 1, 0 - 1 = 0 and 1 ... 0 = 0, When tube Z 

is OFF, the rule is: 0 - 0 = 0, 1 - 1 = 0, 0 - 1 = 1 and 1 - 0 = 1. The correct 

rnodulus is used and not 64 minus the modulus. The subtractor forms (P - Q) 

Mod 64 and the adder forms (<P - Q) Mod 64 + M] Mod 64. These two results 

correspond to (P - Q} and (P - Q + M) respectively. Two cases need to be 

considered. 

Case 1: P;.;r:Q 

In this case the output of the subtractor is always positive c.nd correct. 

A borrow can never be propagated beyond the 6th bit position arad the result 

thus formed will be (P - Q). This is added to M in the adder to form a second 

and incorrect result (P - Q + M) Mod 64. The indication for controling tube 5 

to select the correct result is provided by the condition of borrow over the end 

in the subtracter only. Th•~refore. when P ~ Q, tube 5 is always enabled at 

the 3 T6 sampling time and will be ON for the following six microseconds so 

that tube 6 uses the result from the subtractor to supply as the output. The 

following sketch shows pulse patterns for P = 18 • Q = 16 and M = Z6: 

46 

aa 

ab 

'Tube 2 

I 

I Tube 1 

I 

I ac 

I 

I Tube 4 

I 

1 Tube 3 

I 

I Tube 5 

ad 
REF ID:A71743 

Case 2: P < Q 

In this case the result formed in the subtractor is negative and incorrect. 

A borrow is always propagated past the 6th bit position which causes tube 5 

to be OFF for 6 microseconds following the 3T6 sampling time thereby selecting 

the result formed in the adder for tube 6 to supply as an output. The first 

result. (P • Q) Mod 64. is added to the modulus in the adder to form the correct result, [(P- Q) Mod 64 + M] Mod 64, which in effect (P - 0 + M). For 

example, assume P = 16, Q = 22 and M = 26. The subtractor produces 

(16 - 22) Mod 64 = 58 and the adder produces (58 + 26) Mod 64 = 20. The 

following sketch shows pulse patterns for P = 16, Q = 22 and M = 26. 

Ts I 

I 

T4 I 

I 

I 

I 

I 

Tz I 

I 

l 

C. Absolute Differencing 

aa 

r I 

~--,----n~ ___ nab 

I I 

1--~~~~~~~~_.ril__fjTubeZ I I 

!---------~n._ __ __.~ Tube l 

(P - Q), (Q - P) 

I 

I Tube 4 

I 

1 Tube 3 

1 Tube 5 

I 

I ad 

For this function the appropriate selection of the plug-in delay sticks or 

links must be made according to Notes 1, 2 and 3 on the logical diagram and 

a modulus of zero must be used. The first section functions as a Mod 64 subtracter t and the second section functions as a 2 •s complementer. When tube 4 

is ON. the complementing rule for tube 3 is: 0 = 0 and 1 = 1. When tube 4 is 

0 FF, the rule is: 0 = 1 and 1 = 0. Tube 4 is turned on at the beginning of the 

cycle and stays on until tube 3 puts out a blank, or no pulse, and then it turns 

off for the rest of the 6 microsecond cycle. Since the desired result may be 

either (P - Q) or (Q - P), two cases need to be considered: 

47 
REF ID:A71743 

Case 1: P;;::: Q 

ln this case the subtractor forms the correct result (P - Q) just as it 

<lid in Gase 1 for modular subti~action. The indication to control tube 5 is 

also the same as in subtraction and since no borrow can be propagated past 

the 6th bit position, the result formed by the subtractor is selected for tube 6 

to supply as the output. 

Case Z: P < Q 

In this case the subtractor forms the incorrect result (P - Q + 64) and 

a harrow is propagated past the 6th bit position just same as in Case Z for 

:modular subtraction. The Z1s complementer forms the correct result [(64 -

(P - Q 1 64}] = 64 - P + Q - 64 = (O - P) and because the subtractor propagated a borrow over the end tube 5 is caused to be in the off condition so the 

result from tube 3 is selected for tube 6 to supply as the output. The following 

sketch shows pulse patterns for P = 10 and Q :: 18: 

T 6 

i I 

:_n 

t j 

T 3 

V. Physical Characteristics 

aa 

ab 

!Tube Z 

I 

I 

'Tube 1 

I ac 

I 

I Tube 4 

I 

Tube 3 

Tube 5 

ad 

Four complete and separate Mod-Adders are built on one plug-in chassis 

with all the input and output leads available on the two plugs at the back of the 

chassis. The four units are functionally independent but are interconnected 

48 
REF ID:A71743 

E•lectrically. The circuit component requirement for one chassis of four 

Mod-Adders is approximately as follows: 

Vacuum tubes: 

Pulse transformers: 

Crystal diodes: 

Delay lines: 

Resistors: 

Filament transformer: 

Z4 type 6AN5. 

24 plug-in ferrite type. 

820 type 1N34, CK705, or comparable type. 

140 sticks of one microsecond or fraction. 

468 

l Thordarson type T21Fl2. 

An average approximation of the power consumption on the more important voltages is as follows: 

Current Watts 

+zoo v. O. 48 amp. 96 

+62 v. O. 84 amp. 5Z. 

-8 v. -0.7 atnp. -5.6 

-65 v. 1. 04 amp, 68 

110 v. a-c O. 65 amp. 7Z 

The total power dissipation is approximately 300 to 3ZO watts which 

represents a heat dissipation of 17 to 18 B. T. U. per minute. 

,; 

49 
ll\IPUTS 

1 aa ~ 

I I 

-; 

I fl., 

I !~I I~ I I 

I 

I 

I ---<>--' 

!SEE NOTE I I 

* (SEE NOTE 21 

OUTPUT P I @1T1 

OCI 

~ - .. 

NOTES 

I R ADDIT.ON LONG LINKS FO R SUBTRACTION HORT LINKS FO 

: DIFFERENCl~~R AODITIOl\I a 2 BOTH L.INKS 

SUBTRACTION DIFFERENCING LINICS FOR 

3 :~ SHORT L.INK L.INK FJR F~~D~"J~fRACTION 8 DIFFERENCING 

MOD-ADDER 

---~-
REF ID:A71743 

.A. 
REF ID:A71743 
REF ID:A71743 
REF ID:A71743 ·-;s 

Chapter 6 - (SU) 
CHAPTER 6 

THE SUBSTITUTION UNIT (SU) 

I. Function 

---

The function of the Substitution Unit ii to substitute one of 3Z values, 

or 5 ·bit patterns, for another. This ii accomplished at the rate of 16 7, 000 

per second. The relationship between the pattern fed into the unit and the 

substituted pattern is purely arbitrary and can be changed either automatically with additional circuitry, or manually. 

II. ~!'.21~! Representation 

The following sketch shows how the Substitution Unit may be represented in a block diagram: 

- sa 

se 

·sbo SC ~ 

eb1 SU ad . 

sbz 

- sb3 

• • • • . sb31 

The functions of the leads may be defined as follows: 

aa - Input pattern for which substitution is to be made. lb timing 

of P 1 may be anytime in the range 3T6 to 31'1 • 

sbo to sb31 - Input patterns for substitution timed Pt at 1T6• 

sc - Early output timed Pt at 3T6. 

1e - Input control. May be timed anytime from P1 at 3T6 to 3T1. 

50 

NSA Form 781-ClO 6 Jul 51 TOP SECRET 
Ill. Application and Programming Considerations 

A. Simple Substitution 

The primary purpose of the Substitution Unit is to provide a convenient 

means whereby one value or 5-bit pattern can be changed to or replaced by 

another. Three analytical use• of this type are (1) to repre•ent·the endplate aequence of rotor cipher device, (Z) to change from one 5-hit coding to 

another such as binary to letterwriter, etc., and (3) table look-up. 

B. Selector Switch 

l. With 3Z po•ition• or le•• 

The Substitution Unit can be used as an electronic •elector switch 

with up to 32 positions capable of being switched from one position to any 

other position in 6 microseconds. One eimpl e mean• of accomplhhing 

sequential switching h to supply the input from a Mod Counter as follow•: 

l 

ch cdz 

MC 

Mod 32 

St epping Sig n al at Ti 3 6 

l 

ea •ho 

sbt .-

ebz 

sb3 .- SU 

sd 

•h31 

l 

Output 

... 

. 

Inputs 

to be 

switched 

The Mod Counter aupplie• a sequence of numbers such as O, 1, 2, 3, 

4, 5, 6, 7, etc., to represent the position of the switch. The output of the 

Substitution Unit will be the pulse pattern on lead ah0 , sb1, ab2 , sb3, sb4, 

sb5 , etc. , corresponding to the reapective switch position•. Thh h quite 

useful in ca•e• where a fixed stream of data up to 3Z elements is to be sequenced or scanned. Automatic homing can be accomplished from any position. 

51 

NSA Form 781- C 10 6 Jul 51 TOP SECRET 
2. With many more than 32 poeitions. 

By using ·a cascade arrangement of Z Mod Counters and up to 33 

Substitution Units, an extra large electronic selector switch with a• many 

ae 1024 positions can be elmulated. The following sketch show• a block 

diagram of such a ewitch: 

3T6 

~ cb cdz --- ---1 1 ! MC1 la •• sa 

Mod 32 •ho 14- •ho It- •ho .,._ 

cg 

eb 1 II- sb 1 If- •bi It-

... •bz ~ sbz It- abz ....... 

.. cb ca.1 SU 1 SU2 SU3z 

&b3 ~ ab3 It- 11b3 ~ 

MCz ' I I 

I I I 

I I I Mod 3Z I I I I I 

sb31 It- •b31 4-- •b31 14-

cdz ad ed ed 

1 

sa 

•ho "" 

•b1 

SU33 ~ 

0 

I 

eb31 . 

sd 

1 

Output 

MCz keeps SU33 in one position while MC1 drive• SU1 1 SUz,SU3, ••••• 

su32 all through 3Z position~. In thia manner all 32 input• to SU1 can be 

switched in turn through SU33. Then the 32 inputs to SUz are ewitched in 

turn through SU33, etc.• up through those of SU3z• 

52 

NSA Form 781-C10 6 Jul 51 TOP SECRET 
C. Rotor Notch Ring 

The aimulation of a rotor notch ring for controlling the atepping 

of other rotors is an item of major importance in an electronic representation of a rotor ensemble particularly in complex motions. There are 

several methods by which notch ring• may be simulated when a set of rotor• 

are stepped through a sequence of successive positions and the use of a 

Substitution Unit ii just one of them. The following sketch is an example: 

Notch pattern 0 0 1 0 0 0 1 - -- - 0 

sb0 sbl shz sb3 •h4 •h5 sb6----ab:H 

Stepping MC a 

Control SU 

ad 

Output (Notch or no notch) 

Thie acheme ii not very economical but it does provide a. rather flexible· 

notch ring. With the addition of a 6-position time awitch on the output as 

many as six notch rings can be applied to a rotor. The number of notch ring• 

can be increased by the use of more Substitution Unite and switche•. An 

example ahowtng up to 12 notch rings is given in this next aketcb: 

ea,------... sa SUz 

'---------------------------•--d ~ard=--------------------~-------~ 

Switch 

Driver 

NSA Form 781-ClO 6 Jul 51 

1 bit delay units..._. ti' ~ ~ 

Output 

53 

TOP SECRET 
One notch ring h represented by the Pi bits of the pulse patterns of 

SU l • another by the Pz bite, etc. The condition• of the 2-position and the 

6-poeition switches determine which notch pattern is to be used. 

IV. Ope ratio!!. 

The operation of the Substitution Unit h ba•ed on a alx microsecond 

time cycle. The input on lead ea occur• during one cycle and the output on 

lead ed occurs during the following cycle. Lead se b provided to permit an 

input control. When a continuous stream of pulse• ia on lead ae, the signal 

on lead ea has no effect. When no pulses appear on lead ae, the signal on 

lead ea controls the operation of the circuit. As an example, assume the 

value 13 is being replaced by 22. 

The pulae pattern for the value 13 (13 = l 00 J 0) h fed in on lead ea in 

eerial form and is held in tubes 18, 19 and associated delay lines until all 

five bits are received. The timing of the input may be as e_arly as Pi' at 

,, 

3T6 requiring a I. 00 microsecond delay line or may be as late as P1 at 3T1 

requiring no delay line. When all 5 bits of the input pattern have been re• 

ceived, they a.re used to appropriately tJet the selector drive flip-flops 

consisting of tubes 3, 4, 13, 14, 15, 16, and 17. Tubes 4, 3, 13, 15, and 

16 a.re turned ON when pulses occur in positions Pl' P.z, P3, P4, and P5 

respectively. Tubesl4 and 17 (complements of tubes t'3 end 16) turn ON 

when no pulses occur in position• P3 and P5, respectively. For the pattern 

representing 13 (10010) tubes 3, 14, mid 16 are turned ON and tubes 4, 13, 

15, and 17 are turned OFF. 

The mechanism which selects 1 of 3Z patterns for the output is divided 

into several parts which may be shown in functional block form as follows; 

Z-pos aw Z-poa •w 2-po• aw 

output 

54 

NSA Form 781-ClO 6 Jul 51 TOP SECRET 
' . For circuit consideration• each of the 2-poeition •witches a.re combined 

with their two respective 4 .. poiition switches to form the gating 1tructure · 

for one tube. To follow the example further the 4-position 1witch a••oclated 

with tube Z lets through the 1ignal from tube 5 when tube 4 la OFF and tube 3 

h ON. When tube 14 is ON one of the "AND" gates of tube 5 h enabled and 

when tube 15 h OFF the other "AND" 1ate of tube 5 it not inhibited. The condition of tube1 4 and 3 determine• the •election of 1 of 4 inputl for each of the 

"AND" 1ate1 of tubes 5, 7, 9 and 11. Therefore, input pattern 13 1et1 up 

the appropriate •election drivers to •elect the signal on lead ab 13 for the 

output. Thia 1ignal 1hould be the pattern for ZZ (01001) in order to aatilfy 

the example. The followin1 •ketch ahowt pulse pattern• at variou1 points 

in the circuit for the above example: 

T61 Ts I T4 j T31 Tz T 1 I T6 I Ts I T4 I T3 1 T I I' z, Tl 

I I I I I I I 

I I I faa I I 

f l•e 

f l . 

I I 1Tube 19 

I 

-I I " . I 1

Tube1 18 

I I I 

1_Tube 4; 

I 

., 1Tube 3 

I 

1Tube 13 

I 

1Tube 14 

I I 

LTube lS 

I_ 

I I 

1

Tube 16' 

I 

tTube 17 

I 

I 1

•b13 

1-

I 

ITub~ 5 

I. i 

I 

. I ... c 

I 

1ed 

I 

55 

NSA Form 781-ClO 6 Jul 51 TOP SECRET 
V. Physical Characterhtlc• 

The Substitution Unit h built on one chaa1h with a little •pace to spare. 

All the input and output lead• are available on the plug• at the back of the 

chas1h. The circuit component requirement for one chaa1h le approximately a1 follows: 

Vacuum tubes: 

Pulse tran•formere: 

C.-yatal diode•: 

Delay line•: 

Re1lator1: 

Filament tran1formeta: 

15 type 6AN5 

15 plu1-ln ferrite type 

3 77 kemtron type 345 

24 atick1 of 1 mlcro1econd or 

fraction 

188 

l type TZ1P12 

The approximate power requirement for the more important voltage• 

is aa i'ollow •: 

Current Watt. 

+zoo v. • 29 amps 58 

+ 62 v. .42 amps 26 

8 v. -.28 amp• - 2 

- 65 v. .9 amp• 58 

110 v. a.c. • 41 amps 45 

The total power dhalpatlon la approximately 189 to 205 watts which 

repre1ent1 a heat dh1ipation of 10. 7 to I t..6 B. T. U. per minute . 

. 56 

NSA Form 781·CIO 6 Jul 51 TOP SECRET 
4 Ts 

4 Ts 

REF ID:A71743 

CP ~ 

.. I r;;i 

i '"!: I 

I 

I I 

L

i LQ5. __ , I 

.. -·-- ... ____. 

I 

-

-----····-----------

------·------------------------··---------
REF ID:A71743 

i 

I 

-----·--+·---------+----------------<i-+---------~---

---i.__..-H~-------11f--++-----------4+---------- --··· ---·-----

IL_ L ___ :_ -----···----------·--·· 

CP 

----·-1-

L ... ~-----

---- ___________ ____. 

,___ _____________________ _ ------·--···-·---·-.. ----------- ~---

------------------( -1----<~~----+-+----·-----------·-- ----i@]t---

+ 

SC 

P1 @3Te 

-+-T---------------·--------{ 

+ 

sd 

Pi@ 1T1 
I ---4 

REF ID:A71743 

~---~:~·=-~:~---·~=----------------· -----==---- ·---·-------·---·-·--·-----·--·-· ·-·--··-----··-·-·-~ 

,____ ________ ·-···· ·--- 2 

--------·--·----' 

·----·-------

SUBSTITUTION UNIT 
REF ID:A71743 

.U. 
REF ID:A71743 
REF ID:A71743 

::::) . Cf) 
REF ID:A71743 

S.U. 
s 

REF ID:A71743 

Chapter 7 - (AS) 
CHAPTER 7 

THE ADDER SELECTOR (AS) 

I. Function 

The primary function of the Adder Selector is that of representing a 

wired rotor which may have any number of points up to a maximum of 3Z. 

One limitation is that it is capable or processing only one letter at a time. 

II. Symbolic Representation 

The following sketch shows how the Adder Selector may be represented 

in a block diagram: 

----.ira 

----rb 

---.,.re 

----Mrf 

AS 

Mod M 

rho----

rh1----

rhi----

rh3----

I 

I 

---~rg rd re rh31---- ,__ ____________ ~ 

The function• of the lead1 may be defined a1 follow•: 

ri\ • Input lead1: Tbe1e two leads are for the two primary input 

rb} pattern• one repre1enting a letter and the other repre1entin1 a 

rotor po1ltion. Both must be timed P1 at 1

T1• 

re - Modulu1 input timed P1 at zT1. 

rd - Early output timed P1 a.t 3T6. 

re - Normal output timed P1 at 1

T1• 

r~- Input controls: These two leads are provided to permit control 

rg) of the inputs on leads ra and rb respectively. The pulse patterns 

on theee leads must be timed P1 at 1

T1. 

rho to rh31 • Pattern leads timed P1 at 1T6. These leads provide 3Z 

inputs which represent the rotor output p.oints. 

57 

NSA form 781-ClO 6 Jul 51 TOP SECRET 
III. Application and Programming 

The Adder Selector was designed to perform electronically the functions 

of a wired rotor in the encipherment or decipherment of a letter. This is 

accomplished by the modular addition of two quantities, one representing the 

input letter and the other representing the displacement of the rotor with 

respect to its endplate or preceding rotor, and using that sum to perform a 

table look-up or a substitution function to derive the output letter. These 

two steps can be performed separately by the use of a Mod Adder described 

in Chapter 5 and a Substitution Unit described in Chapter 6 each of which 

requires a 6-microsecond cycle, whereas, the Adder Selector requires only 

one 6-microsecond cycle. Therefore, in !unction the Adder Selector combines the capabilities of a Mod Adder and a Substitution Unit into one unit 

and one character cycle. The descriptions of the above two units also apply 

generally to the Adder Selector so will not be repeated here, but an attempt 

is ma.de to describe the process of representing a wired rotor. 

The operation of a wired rotor can be envi sioned as a substitution table 

in which the table index represents the input points and the values put into the 

table represent the output point•. For example, assume a 26-point rotor 

with input points rho through rh25 arranged consecutively around the rotor 

which serve as a table index and the pulse pattern fed into each of these inputs 

represents the corresponding output point wired to that input point. Assume 

further that this rotor is adjacent to an endplate with a regular sequence of 

inputs 0-2.S around it and that both the rotor and endplate are in position 0 

with respect to a point in space. The adder portion of the Adder Selector must 

operate with a modulus of 26 to do modular addition, or subtraction, depending on which way the rotor moves. With the rotor at position 0 its input 

point is the same as the exit point of the endpl ate. If the rotor is moved N 

positions from 0 its input point is also moved N position with respect to the 

endplate, therefore, the letter must be added ~o, or subtracted from, by an 

amount equal to the distance the rotor has moved from O. One input to the 

adder represents the output of the endplate and the other input represents the 

position of the rotor with respect to the endplate. The result of the addition 

or subtraction which now represents the actual input point to the rotor is used 

to select one of the leads rho through rhz5 on which is a pattern of pulses 

representing the output letter for that corresponding input letter. The selected output letter is now ready to pass through an endplate but must be corrected 

by modular subtraction, or addition, due to the fact that the output points of 

the rotor have been moved in space by the same amount as the input points. 

If, however, the output letter of one rotor is to be utilized as the input letter 

for another it does not have to be modified but the rotor position indication 

for the second rotor must represent the relative position of the second rotor 

with respect to the !irst. 

58 

NSA Form 781-CIO 6 Jul SI 

TOP SECRET 
For fixed wiring, fixed pulse patterns from a pattern generator referred 

to in Chapter 1 may be used to feed the rh leads. A plusging arrangement 

on the chassis itself is provided so that the actual wiring may be plugged up 

manually within the chassis. For non-fixed wiring which is to be changed 

electronically the source of the patterns for the rh leads should be from 

one character storage delay or other circuit elements whose patterns are 

a result of prior analytical tests. 

Several rotors may be represented by several Adder Selectors in cascade. lt takes one character cycle for one letter to go through one rotor in 

serial fashion, therefore, N rotors will consume N character cycles. By 

the use of Mod Counters and Mod Adders to generate rotor positions and 

Adder Selectors to serve as the wired rotors an arrangement of three 26-

point rotors utilizing a metric motion is demonstrated in the following sketch: 

cb 

mod Z6 

I 

• ... cb 

MC2 

mod 26 

cg- cg 

ra 

(ra+rb) 

I. 

... ... ab aa 

(aa .. ab) 

MA 1 

mod 26 

ad 

J 

ra 

(ra+rb) 

... -

.1 

MC3 

mod 26 

cd, 

l 

... .i.. 

ab aa ab 

(aa-ab) (aa-ab) 

MAz MA3 

mod 26 mod 26 

ad aa 

. ~ 

ra 

(ra+rb) 

ad r---+ 

Input--.rb AS1 re~rb ASz rer--;.rb As3 rei----~ 

mod 26 mod 26 mod 26 

• 

rh rh rh 3Z wiring 

·-~------ ~--------~T------~patterns 

59 

NSA Form 781-ClO 6Jul 51 TOP SECRET 

output 
In the foregoing example, it must be assumed that the endplate sequences 

are arranged in the same direction as the rotor points and that the rotor steps 

in such a manner that its successive positions will be in ascending order. The 

two blocks labeled [IQ] and [IQ] represent I -character and 3-character delays 

respectively. MC1 1 MCz, and MC3 generate the absolute positions of the 

three rotors; MA1 derives the relative position of rotor Z with respect to 

rotor l; MAz derives the relative position of rotor 3 with respect to rotor Z; 

AS 1, AS2 and AS3 represent rotors 1, 2 and 3; and MA3 derives the end plate 

output from the position of rotor 3 and its output letter. One cycle of delay ls 

consumed in each rotor and one cycle in MA3 so the output is exactly four 

cycles or Z4 microseconds later than the input. If. the output endplate had a 

plugging arrangement, another Adder Selector would have been needed instead of MA3 and the same time would have been consumed. 

Changes in the wiring of rotors can be made in as little as 6 microseconds 

or up to 32 x 6 microseconds or more depending upon which gives the best 

time -equipment economy. 

IV. Operation 

The operation of the adder portion is identical to that of the Mod Adder 

described in Chapter 4 with three exceptions. It works on 5 bits rather than 

6; instead of one output it provides both the corrected and uncorrected outputs from tubes 15 and 13 respectively; and the carry indicator, tube 17, puts 

out a single pulse or no-pulse timed at 4T6 instead of a set of 6 pulses or 6 

no-pulses. 

The operation of the selector, or subs ti tut ion portion, is identical to 

that of the Substitution Unit described in Chapter 6 with three exceptions. It 

does not have an input control; two inputs, the corrected and uncorrected 

sums are stored in electrical delay lines; and the output of tube 17 is used to 

determine which 5-bit result is stored on flip flops. Tube 17 puts out a pulse 

at 4T5 in all cas..es where the sum is less than the modulus. If a carry bit 

is produced or propagated past the 5th bit is either of the two addition steps 

tube 17 puts out no pulse at 4T5 . When the quantities 9 and 5 are added Mod 

26 the result is 14 which is less than the modulus, therefore, tube 17 produced a pulse at 4T5 to determine the fact that the right result 14 from tube 13 

should be stored in the selector driver tubes (4, 3, 2.4, 2.3, 22, 21, 2.0) instead of the wrong result (9+5+(3Z-2.6)] mod 32 = 20 from tube 15. When the 

sum of two quantities is greater than the modulus tube l 7 puts out no pulse at 

4

T

5 to determine the fact that the result from tube 15 is correct. An example 

of this is the addition of (21+25) mod Z6 where the first result is (2.1+25)-32.=14 

and the second result is ((Zl+Z5)-32+(3Z-Z6)] mod 32 = ZO. 

60 

NSA Form 781-CIO 6 Jul 51 TOP SECllET 
V. Physical Characteristics 

One Adder Selector completely fills one chassis with an approximate 

circuit component requirement as follows: 

Vacuum tubes: 

Pulse transformers: 

Crystal diodes: 

Delay lines: 

Resistors: 

Filament transformer: 

Zl type 6AN5 

Z 1 plug-in ferrite type 

700 type IN34, CK705, or 

comparable type 

73 sticks of one microsecond 

or fraction 

343 

1 Thordarson type TZISlZ 

The power consumption on the more important voltages for one chassis 

is approximately as follows: 

Current Watts 

+zoo v. O. 42 amp. 84 

+62 v. O. 66 amp. 41 

-8 V. -0. 95 amp. .. 7. 6 

-65 v. 1. 28 amp. 83 

110 v. ac 0. 58 amp. 63 

The total power consumption is approximately 270 to 280 watts which 

represents a heat dissipation of 15 to 16 B. T. U. per minute. 

61 

NSA Form 76l·Cl0 6 Jul 51 TOP SECRET 
REF ID:A11143 

t -fj- .... - ~ l' I 

00 z --, 

L/ 

r--. 

\ 

z ·i--

7 _,, 

........ 

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' € --&-,..., 

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r- u - ~-&-r-.-

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J~I 

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------<l- _I '--

(SEE NOTE I) 

NOTE 

(SEE NOTE 2) 

rhn Ill 

N ~ .., C1I 

P1@1T6 ..c:. 

CP2 

f 

----------. 

LONG LINKS FOR ADDITION 

SHORT LINKS FOR SUBTRACTION AND DIFFERENCING 

Z BOTH LINKS FOR ADDITION AND SUBTRACTION 

NO LINKS FOR DIFFERENCING 

3 NO LINK FOR ADDITION 

SHORT LINK FOR SUBTRACTION AND DIFFERENCING 

L...'.... 

(SEE NOTE 3) 

..... IO ..... €) (1\ 

"" 

CPz 
ra 

+ 

INPUTS 

P1 6) 1T1 

rb 

+ + 

rf 

INPUT 

CONTROLS 

rg 

+ 

-, r ~~~..._~~~~~~~~L__--~-~~~~~--~~~L__,___~-

MODULUS INPUT 

P1 I@ 2.T1 

re 

+7V 

GP.,. .J 

+ 3 T5 

+7V 

1 

4T5 

4T5 

Cl 
-

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REF ID:A71743 

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11 

a:: 

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AS.