# Patent

## Title
Device and method for writing data to a resistive memory

## Abstract

The invention relates to a resistive memory including resistive elements, the resistance of each resistive element being capable of alternating between a high value and a low value, the memory further including a device for switching the resistance of at least one selected resistive element between the high and low values. The device includes a first circuit capable of circulating a first current through a first reference resistive component (RLRS), a second circuit capable of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of the voltage across the first reference resistive component with the voltage across the selected resistive element, and a fourth circuit capable of interrupting the second current on detection of the switching.

## Background
BACKGROUND
The present application relates to a device and a method for writing data into a resistive memory.
DISCUSSION OF THE RELATED ART
Resistive memories are non-volatile memories comprising memory cells each having at least one resistive element capable of having at least two different resistance values, for example, a low value, noted Ron, and a high value, noted Roff. As an example, the resistive element may comprise an electrically-insulating material, data being stored in the resistive element by the presence or the absence of a continuous conductive filament in the electrically-insulating material. When the conductive filament is present, resistance Ron of the resistive element is low, while when the filament is broken or is absent, resistance Roff of the resistive element is high. The passing of the resistance of the resistance element of a memory cell from Ron to Roff and conversely is called switching of the memory cell.
The fact of switching the resistance of the resistive element of the memory cell from Roff to Ron is called a memory cell write operation. A write operation corresponds to the forming of the conductive filament in the resistive element of the memory cell. This may be obtained by applying a determined voltage for a determined time between a first terminal and a second terminal of the memory cell. The fact of switching the resistance of the resistive element of the memory cell from Ron to Roff is called memory cell delete operation. A delete operation corresponds to the breaking of the filament of the resistive element of the memory cell. For a bipolar memory cell, this may be obtained by applying a determined voltage for a determined time between the second terminal and the first terminal of the memory cell, that is, with a polarity inverted with respect to the write operation. For a unipolar memory cell, this may be obtained by applying a determined voltage having an amplitude different from that of the voltage applied during the write operation. An initialization operation should generally be provided before the first write operation to form the first filament by applying, between the first and second terminals, a higher voltage than that applied during a write operation. The operation of writing into a resistive memory thus corresponds to the performing of operations of writing into and/or deleting from memory cells of the resistive memory.
A disadvantage of resistive memories is that resistances Ron and Roff obtained after a write operation or a delete operation having a high variability from one memory cell to the other. Further, for a same memory cell, resistance Ron or Roff may vary for two successive write or delete operations. Thereby, the determination of the write or delete voltage and of the duration of application of this voltage is difficult. Indeed, if the write or delete voltage is too low and/or if the duration of application of this voltage is too short, certain memory cells may not switch. However, if the write or delete voltage is too high and/or if the duration of application of this voltage is too long, certain memory cells may deteriorate, which causes a decrease in the lifetime of such memory cells.
SUMMARY
An object of an embodiment is to overcome all or part of the disadvantages of previously-described devices for writing into and deleting from a resistive memory.
Another object of an embodiment is to increase the robustness of the resistive memory, particularly to decrease the dispersion of resistances Ron and Roff of the memory cells of the resistive memory.
Another object of an embodiment is to increase the reliability of the resistive memory, that is, to increase the life expectancy of memory cells and to limit the duration of application to the memory cells of excessive currents and voltages during read and write operations.
Another object of an embodiment is to improve the energetic efficiency of the resistive memory, that is, to decrease the power consumption of the resistive memory while applying conditions sufficient for the read and write operations to occur properly.
Thus, an embodiment provides a resistive memory comprising resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device comprising a first circuit capable of circulating a first current through at least one first reference resistive component, a second circuit capable, during a switching operations, of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of a first voltage which depends on the voltage across the first reference resistive component with a second voltage which depends on the voltage across the selected resistive element or from the comparison of a third current which depends on the first current with a fourth current which depends on the second current, and a fourth circuit capable of interrupting the second current flowing through the selected resistive element on detection of the switching.
According to an embodiment, the first circuit is capable of circulating a fifth current proportional to the first current through at least one second reference resistive component.
According to an embodiment, the memory comprises a current mirror capable of copying the first current flowing through the first reference resistive component, or the fifth current flowing through the second reference resistive component, in said selected resistive element, possibly modified by a multiplication factor.
According to an embodiment, the resistive elements are arranged in rows and in columns, the memory further comprising, for each row, at least one first conductive track connected to each resistive element in the row and, for each column, a second conductive track connected to each resistive element in the column, the memory further comprising at least one third conductive track connected to the first resistive component, each first conductive track being connected to the third conductive track.
According to an embodiment, the memory further comprises, for each resistive element, a first switch series-connected with the resistive element, the first conductive track being connected to each first switch in the row, the memory comprising, for each row, a second switch connected to the first conductive track and to the first reference resistive component.
According to an embodiment, the memory further comprises, for each column, a fourth conductive track, each resistive element being series-connected with the first associated switch between the fourth conductive track and the second conductive track, the memory further comprising a fifth conductive track, each second switch being interposed between the third conductive track and the fifth conductive track.
According to an embodiment, for each column, the second and fourth conductive tracks are connected to the current mirror and the third conductive track is connected to the current mirror.
According to an embodiment, the memory comprises a circuit for supplying a reference voltage connected, for each column, to the second and fourth conductive tracks and connected to the fifth conductive track.
According to an embodiment, the memory comprises, for each row, said first reference resistive component series-connected with the second switch, the fifth conductive track being connected, for each row, to the second switch in the row and the third track being connected, for each row, to the first reference resistive component in the row.
According to an embodiment, the memory comprises a single first reference resistive component, the third and fifth conductive tracks being connected, for each row, to the second switch in the row and the third track being connected to the single first reference resistive component.
According to an embodiment, the memory further comprises sixth and seventh conductive tracks, and for each row, a third switch connecting the sixth and seventh conductive tracks, the sixth and/or the seventh conductive track being connected to the second reference resistive component.
According to an embodiment, the third circuit comprises a comparator receiving the first voltage and the second voltage and providing a binary signal which depends on the sign of the difference between the first voltage and the second voltage.
According to an embodiment, the memory comprises a fourth switch connected to the fourth conductive track and a fifth switch connected to the second conductive track, the fourth and fifth switches being controlled by the binary signal or a signal derived from the binary signal.
An embodiment also provides a method of controlling a resistive memory comprising resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, for the switching of the resistance of a resistive element selected from among the resistive elements between the high and low values, the method comprising the steps of:
circulating a first current through at least one first reference resistive component;
circulating, during a switching operation, a second current proportional to the first current in the selected resistive element;
detecting the switching of the resistance of the selected resistive element from the comparison of a first voltage which depends on the voltage across the first reference resistive component with a second voltage which depends on the voltage across the selected resistive element or from the comparison of a third current which depends on the first current with a fourth current which depends on the second current; and
interrupting the second current flowing through the selected resistive element on detection of the switching.
According to an embodiment, the first current is increasing during the switching operation.



BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, among which:
FIG. 1 is an electric diagram of an embodiment of a device for deleting from a resistive memory;
FIG. 2 shows timing diagrams of signals implemented by the device of FIG. 1 during a delete operation;
FIGS. 3 to 6 are electric diagrams of embodiments of portions of the delete device of FIG. 1;
FIGS. 7 and 8 are partial electric diagrams of other embodiments of a resistive memory delete device;
FIG. 9 is an electric diagram of an embodiment of a device for writing into a resistive memory;
FIG. 10 shows timing diagrams of signals implemented by the device of FIG. 9 during a write operation;
FIG. 11 is an electric diagram of another embodiment of a device for writing into a memory cell of a resistive memory;
FIGS. 12 and 13 are partial electric diagrams of embodiments of a device for deleting from a memory cell of a resistive memory;
FIGS. 14 to 16 are electric diagrams of embodiments of a device for writing into a plurality of memory cells of a resistive memory;
FIG. 17 is an electric diagram of an embodiment of a device for writing into and for deleting from a plurality of memory cells of a resistive memory;
FIG. 18 is a more detailed electric diagram of an embodiment of a device for writing into and for deleting from memory cells of a resistive memory; and
FIGS. 19 to 21 are electric diagrams of embodiments of a device for deleting from/writing into a plurality of memory cells of a resistive memory.



DETAILED DESCRIPTION
For clarity, the same elements have been designated with the same reference numerals in the different drawings. In the following description, expressions “substantially”, “around”, and “approximately” mean “to within 10%”.
In the following description, a signal which alternates between a first constant state, for example, a low state, noted “0”, and a second constant state, for example, a high state, noted “1”, is called “binary signal”. In practice, the binary signals may correspond to voltages or to currents which may not be perfectly constant in the high or low state. The high and low states of binary signals of a same electronic circuit may be different.
According to an embodiment, an operation of writing into a memory cell of a resistive memory and/or of deleting from the memory cell is carried out as follows:

    
    
        application of an increasing voltage or current across the memory cell;
        detection of the memory cell switching; and
        automatic cutting of the current flowing through the memory cell after the detection.
    
    


For each memory cell, the switching of the memory cell occurs when the voltage applied thereacross reaches the voltage necessary for its switching. The switching voltage may thus be different from one memory cell to the other. The memory cell lifetime is advantageously increased since each memory cell is not submitted longer than necessary to the voltage or to the current enabling it to switch. Further, the power consumption of the resistive memory is decreased since the current supplying each memory cell is interrupted as soon as the memory cell has switched.
FIG. 1 shows an embodiment of a resistive cell 5 comprising an array 10 of memory cells Celli,j, for example, with N rows and M columns, where N and M are integers greater than 2 and where i is an integer varying from 1 to N and j is an integer which varies from 1 to M. Memory 5 further comprises a device 14 for deleting from memory cells Celli,j.
Each memory cell Celli,j comprises first and second terminals. For each row of array 10, the first terminals of the memory cells Celli,j in the row are connected to a word line WLi. For each column of array 10, the second terminals of the memory cells Celli,j in the column are connected to a bit line BLj. Each word line WLi, with i varying from 1 to N, is connected to a source of a low reference potential, for example, ground GND, via a switch 16i. Switches 16i are controlled by a word line selection unit 18. As an example, each switch 16i corresponds to a metal-oxide gate field-effect transistor, or MOS transistor, for example, with an N channel, having its drain is connected to word line WLi, having its source connected to ground GND and having its gate controlled by unit 18. Each bit lines BLj, with j varying from 1 to M, is connected to a switch 20j. Switches 20j are controlled by a bit line selection unit 22. As an example, each switch 20j corresponds to a MOS transistor, for example, with a P channel, having its drain connected to bit line BLj, having its source connected to a node A, and having its gate controlled by unit 22.
As an example, each memory cell Celli,j may comprise a resistive element where a conductive filament may be formed, in series with a non-linear component. According to another example, each memory cell Celli,j may comprise a resistive element in series with a MOS transistor. In this case, the gate of the MOS transistor may be connected to word line Wi, one of the terminals of memory cell Celli,j being connected to bit line BLj and the other terminal of memory cell Celli,j being connected to a source of a variable potential.
Delete device 14 comprises a circuit 30 for providing an increasing voltage VRamp at a node B and a circuit 32 receiving voltage VRamp and delivering an increasing reference voltage Vref smaller than voltage VRamp. As an example, circuit 30 is capable of providing a voltage ramp, that is, voltage VRamp is a function linearly increasing along time. As a variation, the first time derivative of voltage VRamp decreases along time. As an example, voltage VRamp successively comprises a first ramp and a second ramp, the first time derivative of voltage VRamp for the second ramp being smaller than the first time derivative of voltage VRamp for the first ramp.
According to an embodiment, voltage Vref is proportional to voltage VRamp with a proportionality ratio smaller than 1.
Delete device 14 comprises a resistor Rm between node B and a node C. Resistor Rm may be formed by a polysilicon track. Call Vrm the voltage between node C and ground GND. A switch 34 controlled by a binary signal Din is provided between node C and a node D. Two switches 36 and 38, assembled in parallel, are provided between nodes D and A. Switch 36 is controlled by a binary signal Rst and switch 38 is controlled by a binary signal G. As an example, each switch 34, 36, 38 is on when the associated control signal is in a first state, for example, in the low state, and is off when the associated control signal is in a second state, for example, in the high state. According to an embodiment, each switch 34, 36, 38 corresponds to a P-channel MOS transistor having its gate controlled by the associated control signal.
Delete device 14 comprises an operational amplifier 40, assembled as a comparator, having its non-inverting input (+) connected to node C and receiving voltage Vrm and having its inverting input (−) connected to circuit 32 and receiving voltage Vref. Comparator 40 provides signal G. As an example, signal G is at “0” when voltage Vrm is smaller than voltage Vref and is at “1” when voltage Vrm is greater than voltage Vref.
When a memory cell Celli,j is selected for a delete operation, memory cell Celli,j and resistor Rm form a voltage dividing bridge. Voltage Vrm is provided by the following relation (1):




  
    
      
        Vrm
        =
        
          
            RCell
            
              RCell
              +
              Rm
            
          
          ⁢
          VRamp
        
      
    
    
      
        (
        1
        )
      
    
  




where Rcell is the resistance of the selected memory cell Celli,j and is equal to Ron or Roff.

Resistance Rm is selected so that voltage Vrm is sufficiently high to be measurable and not too high to avoid hindering memory cell write or delete operations or imposing too high a voltage Vramp. As an example, resistance Rm may be substantially equal to Ron/10. Then, voltage Vref is selected so that, when the resistance of the resistive element of the selected memory cell Celli,j is equal to Roff, voltage Vrm is smaller than voltage Vref and, when the resistance of the resistive element of memory cell Celli,j is equal to Ron, voltage Vrm is greater than voltage Vref.
Memory array 10 may be divided into a plurality of column groups. The columns of each group of columns may be connected to different nodes A and delete device 14 may be partially duplicated for each group of columns. More specifically, resistor Rm, switches 34, 36, 38, and comparator 40 are repeated for each group of columns and circuits 30 and 32 may be common to all the columns groups.
FIG. 2 shows timing diagrams of signals implemented by memory 5 of FIG. 1 during a delete operation. Times t0 to t5 are successive times.
At time t0, memory cell Celli,j where a delete operation should be performed is selected. This is obtained by connecting word line WLi to ground GND and by turning on transistor 20j. Further, signal Rst is set to “0”, which turns on transistor 36. Signal Din is at “0” when a delete operation should be performed in the selected memory cell. Transistor 34 is then conductive.
At time t1, voltage VRamp starts increasing from the zero value. Voltages Vref and Vrm thus start increasing. Further, a current I starts flowing through the selected memory cell Celli,j. The resistance of the resistive element of memory cell Celli,j being equal to Ron, voltage Vrm is smaller than voltage Vref. Signal G delivered by comparator 40 is at “0” as soon as the difference between voltages Vrm and Vref is sufficient. Since the value of signal G may be uncertain as long as voltages Vrm and Vref are not sufficiently different, transistor 36, which is conductive, enables to provide a conduction path between nodes A and D until it is certain that signal G is at “0”.
At time t2, signal Rst switches from “0” to “1”. Transistor 36 switches to the off state.
At time t3, the voltage applied to memory cell Celli,j is sufficiently high to cause the switching of the memory cell. The resistance of the resistive element of memory cell Celli,j switches from Ron to Roff. Voltage Vrm then rises above Vref. Current I decreases.
At time t4, signal G provided by comparator 40 switches to “1”. Transistor 38 switches to the off state. Current I cancels and no voltage is applied to memory cell Celli,j any longer.
A time t5, circuit 30 interrupts the supply of voltage VRamp, for example, after a determined time.
As a variation, transistor 36 may be omitted. Delete device 14 may then comprise means for ensuring that signal G is at “0” at the beginning of a delete operation. As an example, delete device 14 may comprise a storage element of flip-flop type between comparator 40 and transistor 38.
FIG. 3 shows an embodiment of circuit 30 for supplying voltage VRamp. In this embodiment, circuit 30 comprises a capacitor 42 having an electrode connected to ground GND and having its other electrode connected to the non-inverting input (+) of a follower-assembled operational amplifier 44. The inverting input (−) of operational amplifier 44 is connected to the output of operational amplifier 44. Operational amplifier 44 supplies voltage VRamp. Circuit 30 further comprises a P-channel MOS transistor 46 and an N-channel MOS transistor 48. The source of transistor 46 is connected to a source of a high potential VDD. The drains of transistors 46 and 48 are connected to the non-inverting input (+) of operational amplifier 44. The source of transistor 48 is connected to ground GND. The gate of the MOS transistor receives a binary signal Ramp_Cmd and the gate of transistor 48 receives a binary signal Ramp_reset.
Circuit 30 of FIG. 3 operates as follows. Capacitor 42 is discharged by turning on transistor 48, transistor 46 being off. Transistor 48 is then turned on and transistor 46 is off. The conduction properties of transistor 46 are selected so that the charge of capacitor 42 is progressive. The voltage across capacitor 42 corresponds to voltage VRamp. Operational amplifier 44 copies voltage Vramp.
FIG. 4 shows another embodiment of circuit 30 for delivering voltage VRamp. In this embodiment, instead of transistor 46, a current mirror comprising two P-channel MOS transistors 50 and 52, a current source 54 delivering a current Iref, and an N-channel MOS transistor 56 are provided. The sources of transistors 50 and 52 are connected to the source of potential VDD. The drain of transistor 52 is connected to the non-inverting input (+) of operational amplifier 44. The gate of transistor 50 is connected to the gate of transistor 52, to the drain of transistor 50, and to a terminal of current source 54. The other terminal of current source 54 is connected to the drain of transistor 56 and the source of transistor 56 is connected to ground GND.
The current mirror copies current Iref delivered by current source 54 with a multiplication factor equal to the ratio between the gate widths of transistors 52 and 50. When transistor 56 is on and transistor 48 is off, capacitor 42 is charged at constant current with the current copied by the current mirror. The embodiment shown in FIG. 4 enables to obtain a more linear ramp and to better control the duration of the ramp with respect to the embodiment shown in FIG. 3.
FIG. 5 shows another embodiment of circuit 30 for delivering voltage VRamp. As compared with the embodiment shown in FIG. 4, capacitor 42 and operational amplifier 44 are not present. The function of capacitor 42 is fulfilled in the present embodiment by the stray capacitance, illustrated in FIG. 5 by capacitors 58 shown in dotted lines, of the conductive track which transmits voltage VRamp.
FIG. 6 shows another embodiment of circuit 30 for supplying voltage VRamp. In this embodiment, circuit 30 comprises a counter 60 (Counter) rated by a clock signal CK and delivering a digital signal NUM coded over a plurality of bits. Signal NUM is received by a digital-to-analog converter 62 (DAC) which converts digital signal NUM into an analog signal delivered to the non-inverting input (+) of operational amplifier 44. The increase rate of signal VRamp is determined by the frequency of clock signal CK and the number of bits of signal NUM. As a variation, a low-pass filter may be interposed between digital-to-analog converter 62 and operational amplifier 44 to smooth voltage VRamp. In practice, the low-pass filter function may be fulfilled by operational amplifier 44 and the stray capacitance of the conductive track transmitting voltage VRamp.
FIG. 7 shows a more detailed embodiment of delete device 14 where resistor Rm is formed of a diode-assembled P-channel MOS transistor 72. The source of transistor 72 is connected to node B, the drain and the gate of transistor 72 being connected to node C.
Circuit 32 for delivering voltage VRamp comprises a diode-assembled P-channel MOS transistor 74 between a node E and a node F. Node E receives voltage VRamp. The source of transistor 74 is connected to node E, the drain and the gate of transistor 74 being connected to node F. Preferably, transistor 74 is identical to transistor 72. When resistor Rm is formed by a polysilicon track, MOS transistor 74 is preferably replaced with an identical polysilicon resistor.
Circuit 32 further comprises, between node F and ground GND, an assembly of memory cells 76 assembled in series and in parallel so that equivalent resistance Req of the assembly of memory cells 76 is smaller than Roff. As an example, an assembly of six memory cells 72, each having a resistance Roff, is shown in FIG. 7 and the memory cells of this assembly are arranged so that equivalent resistance Req of the assembly of memory cells 76 is equal to 3⁄4*Roff. As a variation, memory cells 76 each having a resistance Ron may be used. Circuit 32 may further comprise, in series with the assembly of memory cells 76, a resistance representative of the parasitic resistances on bit line BLj and word line WLi on selection of memory cell Celli,j. Since memory cells 76 are series-connected, each memory cell 76 does not see a sufficiently high voltage to switch. Circuit 32 plays the role of a voltage divider. Voltage Vref is provided by the following relation (2):




  
    
      
        Vref
        =
        
          
            Req
            
              Req
              +
              Rm
            
          
          ⁢
          VRamp
        
      
    
    
      
        (
        2
        )
      
    
  




FIG. 8 shows another more detailed embodiment of delete device 14 where resistor Rm and transistor 34 shown in FIG. 1 are replaced with a P-channel MOS transistor 78 having its source connected to node B, having its drain connected to node D, having its gate receiving signal Din, and having its substrate connected to the drain. This means that, in the case where the substrate of transistor 78 corresponds to an N-type doped region where P-type doped regions corresponding to the drain and to the source of transistor 78 are formed, the drain and the substrate are substantially taken to the same potential.
The embodiment shown in FIG. 8 advantageously enables to suppress one of MOS transistors 72 and 34 with respect to the embodiment shown in FIG. 7. Since the substrate and the drain of transistor 78 are interconnected, the threshold voltage of transistor 78 is all the smaller as voltage Vrm is low. Thereby, it is avoided to lose the threshold voltage of diode-assembled transistor 72 in voltage VRamp. A lower voltage VRamp may thus be used, which enables to decrease the electric power consumption of delete device 14.
Preferably, circuit 32 for supplying voltage Vref, shown in FIG. 8, comprises, instead of transistor 74 shown in FIG. 7, a P-channel MOS transistor 80 identical to transistor 78, having its source connected to node E, having its drain connected to node F, having its gate connected to ground GND, and having its substrate connected to the drain.
FIG. 9 shows an embodiment of memory 5 where memory 5 comprises a device 90 for writing into memory cells Celli,j, that is, capable of having the resistance of the resistive element of a memory cell Celli,j switch from Roff to Ron. The elements common with delete device 14 shown in FIG. 1 are designated with the same reference numerals.
Each word line WLi, with i ranging from 1 to N, is connected to circuit 30 for supplying voltage VRamp via a switch 92i. Switches 92i are controlled by word line selection unit 18. As an example, each switch 92 corresponds to a P-channel MOS transistor having its drain connected to word line WLi, having its source connected to circuit 30, and having its gate controlled by unit 18. Each bit line BLj, with j varying from 1 to M, is connected to node A via a switch 94j. Switches 94 are controlled by bit line selection unit 22. As an example, each switch 94j corresponds to an N-channel MOS transistor, having its drain connected to bit line BLj, having its source connected to node A, and having its gate controlled by unit 22.
Write device 90 comprises an N-channel MOS transistor 96 having its source connected to ground GND, having its drain connected to a node H, having its gate receiving signal Din, and having its substrate connected to the drain. Call Rm′ the equivalent resistance of transistor 96. Call Vrm′ the voltage between node H and ground GND. A switch 98 is assembled between nodes H and A. Switch 98 is controlled by a binary signal G′. As an example, switch 98 corresponds to an N-channel MOS transistor, having its source connected to node H, having its drain connected to node A, and having its gate controlled by signal G′.
Write device 90 further comprises an operational amplifier 100, assembled as a comparator, having its non-inverting input (+) connected to node H and receiving voltage Vrm′ and having its inverting input (−) connected to circuit 32 and receiving voltage Vref. Comparator 100 provides a binary signal R. As an example, signal R is at “0” when voltage Vrm′ is smaller than voltage Vref and is at “1” when voltage Vrm′ is greater than voltage Vref.
Write device 90 further comprises a flip-flop type storage element 102, which delivers signal G′. Flip-flop 102 comprises an S control input receiving binary signal Rst and a R reset input receiving signal R. Conventionally, when signal Rst on the S control input switches from “0” to “1”, output G′ of flip-flop 102 is set to “1”. When signal R on the R reset input switches from “0” to “1”, output G′ of flip-flop 102 switches to “0”. When signal R on the R reset input switches from “1” to “0” or when signal Rst on the S control input switches from “1” to “0”, output G′ of flip-flop 102 is not modified.
When a memory cell Celli,j is selected for a write operation, memory cell Celli,j and equivalent resistor Rm′ of MOS transistor 96 form a voltage dividing bridge. Voltage Vrm′ is provided by the following relation (3):




  
    
      
        
          Vrm
          ′
        
        =
        
          
            
              Rm
              ′
            
            
              RCell
              +
              
                Rm
                ′
              
            
          
          ⁢
          VRamp
        
      
    
    
      
        (
        3
        )
      
    
  




FIG. 10 shows timing diagrams of signals implemented by memory 5 of FIG. 9 during a write operation. Times t′0 to t′6 are successive times.
At time t′0, signal Rst switches to “1”, which causes the setting to “1” of output signal G′ of flip-flop 102. Transistor 98 thus turns on. Signal Din is at “1” when a write operation should be performed in the selected memory cell. Transistor 96 is then conductive.
At time t′1, voltage VRamp starts increasing from the zero value. Voltages Vref and Vrm′ thus start increasing. Further, a current I starts flowing through the selected memory cell Celli,j. The resistance of memory cell Celli,j being equal to Roff, voltage Vrm′ is smaller than voltage Vref. Signal R output by comparator 100 is at “0”. However, output G′ of the flip-flop remains at “1”.
At time t′2, signal Rst switches from “1” to “0”. Output signal G′ of flip-flop 102 is however not modified.
At time t′3, the voltage applied to memory cell Celli,j is sufficiently high to cause the switching of the memory cell. The resistance of the resistive element of memory cell Celli,j switches from Roff to Ron. Voltage Vrm′ then rises above Vref. Current I decreases and signal R output by comparator 100 switches to “1”.
At time t′5, flip-flop 102 receiving signal R sets signal G′ to “0”. Switch 98 switches to the off state. Current I cancels and no voltage is applied to memory cell Celli,j any longer. During its drop, voltage Vrm′ becomes smaller than voltage Vref and signal R′ switches to “0”. However, signal G′ is maintained at “0”.
At time t′6, circuit 30 interrupts the supply of voltage VRamp.
In the embodiment shown in FIG. 9, to perform a write operation, bit line BLj connected to the selected memory cell Celli,j is set to ground GND and word line WLi connected to the selected memory cell Celli,j receives voltage VRamp. This advantageously enables to use the same circuit 30 for a write operation and for a delete operation. According to another embodiment, to perform a delete operation, word line WLi connected to the selected memory cell Celli,j may be set to high potential VDD and bit line BLj connected to the selected memory cell Celli,j may receive a voltage continuously decreasing, for example, from VDD to 0 V.
According to an embodiment, memory 5 may comprise delete device 14 shown in FIG. 1 and write device 90 shown in FIG. 9. In this case, circuits 30 and 32 may be common to the write and delete devices. Further, in the case where delete device 14 also comprises a flip-flop, flip-flop 102 and operational amplifier 100 may be common to delete device 14 and to write device 90.
According to another embodiment, an operation of writing into a memory cell of a resistive memory and/or of deleting from the memory cell is carried out as follows:

    
    
        circulating of a current through the memory cell;
        comparison of the voltage across the memory cell with a reference voltage;
        detection of the switching of the memory cell from the comparison of the voltage across the memory cell with the reference voltage; and
        automatic cutting of the current flowing through the memory cell after the detection.
    
    


For each memory cell, the power consumption of the memory cell is decreased since the current supplying each memory cell is interrupted as soon as the memory cell has switched. The memory cell lifetime is advantageously preserved since the memory cell is not submitted to the switching voltage longer than necessary. Further, the current flowing through the memory cell is interrupted when the voltage across the memory cell reaches a determined voltage, that is, when the resistance of the memory cell reaches a determined resistance. Advantageously, resistances Ron of the memory cells after a write operation are substantially equal and resistances Roff of the memory cells after a delete operation are substantially equal.
The operating principle of a write device and of a delete device will first be described for a write or delete operation for a single memory cell. This is followed by the description of the use of the write device and of the delete device with a resistive memory comprising a plurality of memory cells.
FIG. 11 shows another embodiment of a device 110 for writing into a resistive element R of a memory cell. Write device 110 comprises a programming circuit 114, an end-of writing detection circuit 116 and a logic feedback circuit 118.
Programming circuit 114 comprises a circuit 120 for providing a programming voltage VProg to a node T. Voltage VProg may be a constant voltage or a stepped monotonous voltage, for example, continuously increasing, for example, a voltage ramp, for part of a write or delete operation, for example the beginning of a write or delete operation at least until the switching of the memory cell, and then decreasing at the end of the write or delete operation. Circuit 120 may have the same structure as previously-described circuit 30. Programming circuit 114 further comprises a reference resistor RLRS between nodes J and K and a switch 122 controlled by a binary signal SET_ACT between node T and node J. Switch 122 may correspond to a P-channel MOS transistor having its source connected to node T, having its drain connected to node J, and having its gate receiving signal SET_ACT. According to an embodiment, reference resistance RLRS is substantially equal to the resistance level Ron desired for resistive element R. Resistor RLRS may be formed by a polysilicon track.
Resistive element R is placed between nodes L and Z. Programming circuit 114 comprises a switch 124 controlled by a binary signal EN_set_H between node T and node L. Switch 124 may correspond to a P-channel MOS transistor having its source connected to node T, having its drain connected to node L, and having its gate receiving signal EN_set_H.
Programming circuit 114 comprises a current mirror which copies the current flowing through resistor RLRS in resistive element R. The current mirror for example comprises a diode-assembled N-channel MOS transistor 126, having its drain connected to node K, having its source connected to ground GND, and having its gate connected to the drain. The current mirror further comprises an N-channel MOS transistor 128, having its drain connected to node Z, having its source connected to ground GND, and having its gate connected to the gate of transistor 126. Call VSET the voltage between node K and ground GND and VR the voltage between node Z and ground GND.
Detection circuit 116 is capable of comparing voltages VSET and VR. It comprises an N-channel MOS transistor 130 having its source connected to a node O, having its drain connected to a node P, and having its gate connected to node K and receiving voltage VSET. Call VCOMP the voltage between node P and ground GND. Node P is connected to the drain of a P-channel MOS transistor 132. Detection circuit 116 further comprises an N-channel MOS transistor 134 having its source connected to node O, having its drain connected to the drain of a P-channel MOS transistor 136, and having its gate connected to node Z and receiving voltage VR. The sources of MOS transistors 132 and 136 are connected to a source of a high reference potential VDD. The gate of transistor 132 is connected to the drain of transistor 136 and the gate of transistor 136 is connected to the drain of transistor 132. Preferably, the gate width of transistor 134 is larger than the gate width of transistor 130. As an example, the gate width of transistor 134 is equal to twice the gate width of transistor 130.
Detection circuit 116 comprises, between node P and ground GND, a switch 138 controlled by binary signal SET_ACT. Switch 138 may correspond to an N-channel MOS transistor having its source connected to ground GND, having its drain connected to node P, and having its gate receiving signal SET_ACT. Detection circuit 116 further comprises, between node O and ground GND, a switch 140 controlled by a binary signal ENb. Switch 140 may correspond to an N-channel MOS transistor having its source connected to ground GND, having its drain connected to node O, and having its gate receiving signal ENb. The gate width of transistor 140 may be equal to the sum of the gate width of transistor 134 and of the gate width of transistor 130.
Logic circuit 118 comprises a block 142 carrying out the “OR” logic function, receiving signals VCOMP and SET_ACT and delivering a binary signal EN. Logic circuit 118 further comprises a block 144 carrying out the “NO” logic function, receiving signal EN and delivering signal ENb. Logic circuit 118 may further comprise a level conversion circuit 146 receiving signal EN and delivering signal EN_set_H. The high state of signal EN_set_H is at a voltage greater than the high state of signal EN and is capable of controlling certain MOS transistors. As an example, the high state of signal EN_set_H corresponds to VProg. As a variation, circuit 146 may be absent.
According to an embodiment, device 110 may further comprise a voltage converter receiving signal SET_ACT and having its output connected to the gate of transistor 138 and to the gate of transistor 122.
Write device 110 operates as follows. Before the beginning of a write operation, signal SET_ACT is at “1”. Transistor 138 is thus conductive, which maintains voltage VCOMP at “0”. Further, transistor 122 is off. No current flows through resistor RLRS. Signal EN is at “1” and signal ENb is at “0”. Transistor 140 is thus off. Signal EN_set_H is at “1”. Transistor 124 is thus off. No current flows through resistive element R.
At the beginning of a write operation, signal SET_ACT is set to “0”. Transistor 122 thus becomes conductive. Since signal VCOMP is at “0”, signal EN switches to “0” and signal ENb switches to “1”. Transistor 140 thus becomes conductive. Signal EN_set_H switches to “0”. Transistor 124 thus becomes conductive. Circuit 120 supplying programming voltage VProg causes the flowing of a current ILRS through resistor RLRS. Current ILRS is copied by the current mirror and flows through resistive element R. Since the resistance of resistive element R can be assumed to be equal to Roff, that is, greater than RLRS, voltage UNVM across resistive element R is greater than voltage ULRS across resistor RLRS. Since the drain-source voltages of transistors 122 and 124 are identical and substantially zero, voltage VR is smaller than voltage VSET. Transistor 130 is thus more conductive than transistor 134. Signal VCOMP remains at “0”, transistor 136 being conductive and transistor 132 being off.
When resistive element R switches, the resistance of resistive element R decreases. When the resistance of resistive element R becomes substantially equal to RLRS, voltage UNVM becomes substantially equal to voltage ULRS and voltage VR becomes substantially equal to VSET. Since the gate width of transistor 134 is greater than the gate width of transistor 130, transistor 134 is more conductive than transistor 130. This causes a switching of VCOMP from “0” to “1”, transistor 132 becoming conductive and transistor 136 turning off. Signal EN, and thus signal EN_set_H, then switch from “0” to “1”. Transistor 124 is turned off, interrupting the current flow in resistive element R. Further, signal ENb switches from “1” to “0”, thus turning off transistor 140.
According to another embodiment, the gate width of transistor 134 may not be larger than the gate width of transistor 130. In this case, reference resistance RLRS is greater than the desired resistance Ron. When resistive element R switches, the resistance of resistive element R decreases from Roff to Ron. When the resistance of resistive element R becomes smaller than resistance RLRS, voltage UNVM becomes smaller than voltage ULRS and voltage VR becomes greater than VSET. Transistor 134 is more conductive than transistor 130. This causes a switching of VCOMP from “0” to “1”.
For each memory cell, the current flowing through the memory cell is interrupted as soon as the memory cell has switched. The memory cell lifetime is advantageously preserved since the memory cell is not submitted longer than necessary to the voltage and to the current enabling it to switch. Further, the memory cell power consumption during a write operation is decreased. Further, in the present embodiment, the current flow in resistive element R is interrupted after the resistance of resistive element R has reached a determined value for which signal VCOMP switches from “0” to “1”. The resistance of resistive element R after the switching is thus controlled.
FIG. 12 shows an embodiment of a device 150 for deleting from a resistive element R.
Delete device 150 comprises a programming circuit 152, a circuit for detecting the end of a delete operation 154, and a logic feedback circuit 156. Detection circuit 154 may be identical to previously-described circuit 116, with the difference that signal SET_ACT is replaced with a binary signal RST_ACT. Logic circuit 156 may be identical to previously-described logic circuit 118, with the difference that signal SET_ACT is replaced with a binary signal RST_ACT and in that signal EN_set_H is replaced with a binary signal EN_rst_H.
Programming circuit 152 comprises certain elements of previously-described programming circuit 114. Programming circuit 152 comprises, in particular, circuit 120 for supplying voltage VProg to node T. Programming circuit 152 comprises a switch 158 controlled by binary signal EN_rst_H between node T and node Z. Switch 158 may correspond to a P-channel MOS transistor having its source connected to node T, having its drain connected to node Z, and having its gate receiving signal EN_rst_H.
Programming circuit 152 comprises an N-channel MOS transistor 160 having its drain connected to node L, having its source connected to ground GND, and having its gate connected to the gate of MOS transistor 126. Call VR′ the voltage between node L and ground GND.
Programming circuit 152 further comprises a reference resistor RHRS between nodes Q and V and a switch 162 controlled by binary signal RST_ACT between node T and node Q. Switch 162 may correspond to a P-channel MOS transistor having its source connected to node T, having its drain connected to node Q, and having its gate receiving signal RST_ACT. In the present embodiment, resistance RHRS is substantially equal to resistance Roff desired for resistive element R. Resistor RHRS may be formed by a polysilicon track. Call UHRS the voltage across resistor RHRS and VRST the voltage between node V and ground GND. Programming circuit 152 further comprises an N-channel MOS transistor 164 having its drain connected to node V, having its source connected to ground GND, and having its gate connected to the gate of transistor 126. Node V is connected to the gate of transistor 134 and node L is connected to the gate of transistor 130.
The gate width of transistor 160 may be larger than the gate width of transistor 126.
Delete device 150 operates as follows. Before the beginning of a delete operation, signal RST_ACT is at “1”. Transistor 138 is thus conductive, which maintains signal VCOMP at “0”. Further, transistors 122 and 162 are off. No current flows through resistors RLRS and RHRS. Signal EN is at “1” and signal ENb is at “0”. Transistor 140 is thus off. Signal EN_rst_H is at “1”. Transistor 158 is thus off. No current flows through resistive element R.
At the beginning of a delete operation, signal RST_ACT is set to “0”. Transistors 122 and 162 thus become conductive. Since signal VCOMP is at “0”, signal EN switches to “0” and signal ENb switches to “1”. Transistor 140 thus becomes conductive. Signal EN_rst_H switches to “0”. Transistor 158 thus turns on. Circuit 120 supplies programming voltage VProg. It results in the flowing of a current ILRS through resistor RLRS. Current ILRS, copied by the current mirror, possibly with a multiplication factor greater than 1, flows through resistor element R and through resistor RHRS. Since the resistance of resistive element is of low level, voltage UNVM across resistive element R is smaller than voltage UHRS across resistor RHRS and voltage VR′ is greater than voltage VRST. Transistor 130 is thus more conductive than transistor 134. Signal VCOMP thus remains at “0”, transistor 136 being conductive and transistor 132 being off.
When resistive element R switches, the resistance of resistive element R increases. When voltage UNVM becomes substantially equal to voltage UHRS, voltage VR′ becomes substantially equal to VRST. Since the gate width of transistor 134 is larger than the gate width of transistor 130, transistor 134 is more conductive than transistor 130. This causes a switching of VCOMP from state “0” to state “1”, transistor 132 becoming conductive and transistor 136 turning off. Signal EN and signal EN_rst_H then switch from “0” to “1”. Transistor 158 is then turned off, interrupting the current flow in resistive element R. Further, signal ENb switches from “1” to “0”, thus turning off transistor 140.
According to another embodiment, the gate width of transistor 134 may not be larger than the gate width of transistor 130. In this case, reference resistance RHRS is smaller than the desired resistance Roff. When resistive element R switches, the resistance of resistive element R increases from Ron to Roff. When the resistance of resistive element R becomes greater than resistance RHRS, voltage UNVM becomes greater than voltage UHRS and voltage VR, becomes smaller than VRST. Transistor 134 is more conductive than transistor 130. This causes a switching of VCOMP from “0” to “1”.
For each memory cell, the current flowing through the memory cell is interrupted as soon as the memory cell has switched. The memory cell lifetime is advantageously preserved since the memory cell is not submitted longer than necessary to the voltage and to the current enabling it to switch. Further, the memory cell power consumption during a delete operation is decreased. Further, in the present embodiment, the current flow in resistive element R is interrupted after the resistance of resistive element R reaches a determined value for which signal VCOMP switches from “0” to “1”. The resistance of resistive element R after the switching is thus controlled.
FIG. 13 shows another embodiment of a device 170 for deleting from a resistive element R.
Delete device 170 comprises a programming circuit 172, a circuit for detecting the end of a delete operation 174, and a logic feedback circuit 176. Programming circuit 172 comprises transistors 122 and 126 and resistor RLRS of circuit 114 previously described in relation with FIG. 11. Programming circuit 172 further comprises transistor 158 of circuit 152 previously described in relation with FIG. 12. Resistive element R is connected in the same way as for circuit 152. Programming circuit 172 further comprises an N-channel MOS transistor 178 having its source connected to ground GND, having its gate connected to the gate of transistor 126, and having its drain connected to node L. The gate width of transistor 178 may be larger, for example, by a factor n greater than 1, than the gate width of transistor 126. Logic circuit 176 may comprise previously-described logic block 142 and level conversion circuit 146 of logic circuit 156.
Detection circuit 174 comprises a P-channel MOS transistor 180 having its source connected to the source of reference potential VDD, having its gate connected to node K and receiving voltage VSET, and having its drain connected to a node X. Detection circuit 174 comprises an N-channel MOS transistor 182 having its source connected to ground GND, having its gate connected to node L and receiving voltage VR′, and having its drain connected to node. Node X delivers signal VCOMP received by “OR” logic gate 142. Detection circuit 174 comprises an N-channel MOS transistor 184 having its source connected to ground GND, having its gate receiving signal RST_ACT, and having its drain connected to node X.
Delete device 170 operates as follows. Before the beginning of a delete operation, signal RST_ACT is at “1”. Transistor 122 is thus off. No current flows through resistor RLRS. Transistor 184 is conductive and signal VCOMP is at “0”. Signal EN is at “1” and signal EN_rst_H is at “1”. Transistor 158 is thus off. No current flows through resistive element R.
At the beginning of a delete operation, signal RST_ACT is set to “0”. Transistor 122 thus becomes conductive and transistor 184 is turned off. Since signal VCOMP is at “0”, signal EN and signal EN_rst_H switch to “0”. Transistor 158 thus becomes conductive. Circuit 120 supplies programming voltage VProg. It results in the flowing of a current ILRS through resistor RLRS. Current ILRS is copied by the current mirror and flows through resistive element R multiplied by multiplication factor n. Since the resistance of resistive element R initially has value Ron, voltage UNVM across resistive element R is in the order of n times voltage ULRS across resistor RLRS. Transistors 180 and 182 are sized so that in this configuration, transistor 182 is more conductive than transistor 180. Signal VCOMP thus remains at “0”.
When resistive element R switches, the resistance of resistive element R increases from Ron to Roff. Voltage UNVM increases and signal VR′ decreases. Transistor 180 is more conductive than transistor 182. This causes a switching of VCOMP from “0” to “1”. Signal EN and signal EN_rst_H then switch from “0” to “1”. Transistor 158 is then turned off, interrupting the current flow through resistive element R and thus the delete operation.
For each memory cell, the current flowing through the memory cell is interrupted as soon as the memory cell has switched. The memory cell lifetime is advantageously preserved since the memory cell is not submitted longer than necessary to the voltage and to the current enabling it to switch. Further, the memory cell power consumption during a delete operation is decreased. Further, in the present embodiment, the current flow through resistive element R is interrupted after the resistance of resistive element R has reached a determined resistance value for which signal VCOMP switches from “0” to “1”. The resistance of resistive element R after the switching is thus controlled.
FIG. 14 shows an embodiment of a memory 190 comprising a write device having an operation which may be similar to what has previously described for write device 110 shown in FIG. 11. Memory 190 comprises an array of resistive elements Ri,j arranged in N rows and M columns, where i varies from 1 to N and j varies from 1 to M. FIG. 14 shows the resistive elements of the first row and of the last row for column “j”. Further, the elements of memory 190 identical to the elements of the write or delete device previously described in relation with FIGS. 11 to 13 are designated with the same reference numerals, to which an index may be added to indicate that the element is repeated for each row “i” and/or for each column “j”.
As an example, two resistive elements R1,j and RN,j of column j are shown in FIG. 14. Each resistive element Ri,j comprises a first terminal (+) and a second terminal (−). Terminal (+) is connected to the source of a P-channel MOS transistor 192i,j. For each row “i”, the gate of each transistor 192i,j in the row is connected to a word line WLi. For each column “j”, the source of each transistor 192i,j in the column is connected to a first bit line BL1j and terminal (−) of each resistive element Ri,j in the column is connected to a second bit line BL2j. Bit line BL1j is connected to the drain of transistor 124j and to the drain of transistor 160j. Bit line BL2j is connected to the drain of transistor 158j and to the drain of transistor 128j.
Memory 190 comprises a circuit for detecting the end of a write and/or delete operation SAj which is connected to bit lines BL1j and BL2j and to the gate of transistor 126. The operation of circuit SAj may be similar to that of previously described circuit 116 or 174 for detecting the end of a write operation. Memory 190 comprises a logic circuit Logicj which is connected to circuit SAj and which provides signals EN_set_Hj and EN_rst_Hj. The operation of circuit Logicj may be similar to that of previously-described logic circuit 118 or 176.
Memory 190 further comprises an N-channel MOS transistor 194j having its source connected to ground GND, having its drain connected to the gate of transistor 128j, and having its gate receiving signal EN_set_Hj. Memory 190 further comprises a P-channel MOS transistor 196j having its source connected to the gate of transistor 126, having its drain connected to the gate of transistor 128j, and having its gate receiving signal EN_set_Hj. Memory 190 further comprises an N-channel MOS transistor 198j having its source connected to ground GND, having its drain connected to the gate of transistor 160j, and having its gate receiving signal EN_rst_Hj. Memory 190 further comprises a P-channel MOS transistor 200j having its source connected to the gate of transistor 126, having its drain connected to the gate of transistor 160j, and having its gate receiving signal EN_rst_Hj.
In the embodiment shown in FIG. 14, a reference resistor RLRSi and a P-channel MOS transistor 202i are provided for each row “i”. The gate of transistor 202i is connected to word line WLi and the drain of transistor 202i is connected to a first terminal of resistor RLRSi. For the first row, the source of transistor 2021 is connected to the drain of transistor 122. For the other rows, the source of transistor 202i of the row is connected to the source of transistor 202i−1 of the previous row. For the last row, the second terminal of resistor RLRSN is connected to the drain of transistor 126. For the other rows, the second terminal of resistor RLRSi is connected to the second terminal of resistor RLRSi+1 of the next row. FIG. 14 shows parasitic resistors 204 which are substantially homogeneously distributed on the conductive tracks connecting switches 202i.
Memory 190 operates as follows. The resistive element Ri,j where a write or delete operation should be performed is selected by the grounding of word line WLi so that transistor 192i,j becomes conductive, the other word lines being maintained at high potential VDD. Further, transistor 122 is conductive so that a current flows through the resistor RLRSi of the same row as the selected resistive element Ri,j.
For an operation of writing into resistive element Ri,j of column “j”, signal EN_set_Hj is set to “0” and signal EN_rst_Hj is set to “1”. Transistor 196j is thus conductive and transistor 194j is off. A current can thus flow through transistor 128j. Transistor 198j is conductive and transistor 200j is off. Transistor 160j is thus off and no current can flow therethrough. Thereby, during the write operation, a current successively flows through transistor 124j, transistor 192i,j, resistive element Ri,j, from terminal (+) to terminal (−), and through transistor 128j. The current path is shown by a stripe-dot line 206.
For an operation of deleting resistive element Ri,j of column “j”, signal EN_set_Hj is set to “1” and signal EN_rst_Hj is set to “0”. Transistor 200j is thus conductive and transistor 198j is off. A current can thus flow through transistor 160j. Transistor 194j is conductive and transistor 196j is off. Transistor 128j is thus off and no current can flow therethrough. Thereby, during the delete operation, a current successively flows through transistor 158j, through resistive element Ri,j, from terminal (−) to terminal (+), through transistor 192i,j, and through transistor 160j. The current path is shown by a dotted line 208.
The arrangement of resistors RLRSi results in that the parasitic resistances seen by current ILRS flowing through resistor RLRSi are substantially the same whatever the selected resistive element Ri,j.
FIG. 15 shows another embodiment of a memory 210. Memory 210 comprises all the elements of memory 190, with the difference that a single resistor RLRS is present and is used whatever the selected resistive element Ri,j. There thus advantageously is a surface area gain with respect to memory 190 and less variability on current ILRS since the same resistor RLRS is used. Further, the parasitic resistances seen by current ILRS crossing resistor RLRS are substantially the same whatever the selected resistive element Ri,j.
FIG. 16 shows another embodiment of a memory 220. Memory 220 comprises all the elements of memory 190 with the difference that transistors 194j, 196j, 198j, and 200j are not present. Memory 220 comprises an N-channel MOS transistor 222j having its source connected to the drain of transistor 128j and to circuit SAj, having its drain connected to line BL2j, and having its gate receiving signal EN_rst_Hj. Memory 220 comprises an N-channel MOS transistor 224j having its source connected to the drain of transistor 160j and to circuit SAj, having its drain connected to line BL1j, and having its gate receiving signal EN_set_Hj. Memory 220 further comprises an N-channel MOS transistor 226 having its source connected to the drain of transistor 126, having its drain connected to a terminal of each resistor RLRSi, and having its gate connected to the drain of transistor 122.
For an operation of writing into resistive element Ri,j of column “j”, signal EN_set_Hj is set to “0” and signal EN_rst_Hj is set to “1”. Transistor 222j is thus conductive and transistor 224j is off. Thereby, the current flows as shown by stripe-dot line 206. For an operation of deleting from resistive element Ri,j of column “j”, signal EN_set_Hj is set to “1” and signal EN_rst_Hj is set to “0”. Transistor 224j is thus conductive and transistor 222j is off. Thereby, the current flows as shown by dotted line 208.
In the embodiment shown in FIG. 16, memory 220 advantageously has a simplified structure with a decreased number of transistors with respect to memory 190.
FIG. 17 shows another embodiment of a memory 230 where delete device 170 previously described in relation with FIG. 13 may be used. Memory 230 has the same structure as memory 210 shown in FIG. 15. Memory 230 further comprises, of each row, a P-channel MOS transistor 232i having its gate connected to word line WLi. For the first row, the source of transistor 2321 is connected to the drain of transistor 158. For the other rows, the source of transistor 232i of the row is connected to the source of transistor 232i−1 of the previous row. For the last row, the drain of transistor 232N is connected to a terminal of resistor RHRS. For the other rows, the drain of transistor 232i of the row is connected to the drain of transistor 232i+1 of the next row. FIG. 17 shows parasitic resistors 234 which are substantially homogeneously distributed on the conductive tracks connecting switches 232i. Of course, a resistor RHRS may be provided for each row similarly to what has been described for resistors RLRSi in FIG. 16. Detection circuit SAj is further connected to the drain of transistor 164. The operation of circuit SAj may be similar to that of previously described circuit 156 for detecting the end of a write operation.
FIG. 18 shows a more detailed embodiment of a write and delete device 240 capable of being used with memory 230 of FIG. 17. The elements common with write device 110 shown in FIG. 11 and delete device 150 shown in FIG. 12 are designated with the same reference numerals, to which an index may be added to indicate that the element is repeated for each row “i” and/or for each column “j”.
The gate of transistor 122 receives a signal ACT and the gate of transistor 162 receives signal RST_ACT.
Circuit SAj for detecting the end of a write and/or delete operation comprises all the elements of circuit 154, with the difference that transistor 140 is replaced with two N-channel MOS transistors 242j, 244j. The drain of transistor 242j is connected to the source of transistor 130j. The source of transistor 242j is connected to ground GND and the gate of transistor 242j receives signal ENbj. The drain of transistor 244j is connected to the source of transistor 134j. The source of transistor 244j is connected to ground GND and the gate of transistor 244j receives high reference potential VDD. Transistor 244j is thus conductive.
Circuit SAj further comprises an N-channel MOS transistor 246j having its drain receiving signal VRj′ and having its gate receiving signal EN_rst_Hbj. Circuit SAj further comprises an N-channel MOS transistor 248j having its drain receiving signal VSET and having its gate receiving signal EN_set Hbj. The sources of transistors 246j and 248j are connected to the gate of transistor 130j. Circuit SAj further comprises an N-channel MOS transistor 250j having its drain receiving signal VRST and having its gate receiving signal EN_rst_Hbj. Circuit SAj further comprises an N-channel MOS transistor 252j having its drain receiving signal VRj and having its gate receiving signal EN_set_Hbj. The sources of transistors 250j and 252j are connected to the gate of transistor 134j.
The control of the write and read operations is performed by binary signals SET_ACT and RST_ACT. Logic circuit Logicj comprises four logic blocks 254j, 256j, 258j, and 260j. Block 254j carries out the “OR” logic function and receives signals SET_ACT and VCOMPj. Block 256j carries out the “OR” logic function and receives signals RST_ACT and VCOMPj. Block 258j carries out the “NAND” logic function, receives the outputs of blocks 254j and 256j, and outputs signal ENbj. Block 260j carries out the “AND” logic function, receives signals SET_ACT and RST_ACT, and outputs signal ACT.
Logic circuit Logicj comprises a level conversion circuit 262j receiving the output of block 254j. The output of level conversion circuit 262j drives an inverter 264j which outputs signal EN_set_Hbj. Signal EN_set_Hbj drives an inverter 266j which outputs signal EN_set_Hj. Logic circuit Logicj comprises a level conversion circuit 268j receiving the output of block 256j. The output of level conversion circuit 268j drives an inverter 270j which outputs signal EN_rst_Hbj. Signal EN_rst_Hbj drives an inverter 272j which outputs signal EN_rst_Hj.
Signals SET_ACT and RST_ACT are at “1” by default. Signal ACT thus is at “1”. Transistor 138 is thus conductive, which maintains signal VCOMPj at “0”. Further, transistors 122, 162 are off. No current flows through resistors RLRS and RHRS. Signal ENbj is at “0”. Transistor 242j is thus off. Signals EN_set_Hbj and EN_rst_Hbj are at “0”. Transistors 246j, 248j, 250j, and 252j are thus off. Signals EN_set_Hj and EN_rst_Hj are at “1”, transistors 124j and 158j are thus off. No current flows through resistive element Ri,j. Signals SET_ACT and RST_ACT are identical for all the columns in the array.
To perform an operation of writing into resistive element Ri,j of column “j”, signal SET_ACT is set to “0”, signal RST_ACT remaining at “1”. Signal ACT thus switches to “0”. Transistor 138j is thus turned off and transistor 122 becomes conductive. Further, signal ENbj switches to “0”. Transistor 242j thus turns on. Signal EN_set_Hj switches to “0”. Transistor 124j thus becomes conductive. Signal EN_set_Hbj switches to “1” while signal EN_rst_Hbj remains at “0”. The gate of transistor 130j receives signal VSET and the gate of transistor 134j receives signal VRj. Circuit SAj then operates like end-of-writing detection circuit 116 previously-described in relation with FIG. 11.
To perform an operation of deleting from resistive element Ri,j of column “j”, signal RST_ACT is set to “0”, signal SET_ACT remaining at “1”. Signal ACT thus switches to “0”. Transistor 138j is thus turned off and transistor 122 becomes conductive. Further, signal ENbj switches to “0”. Transistor 242j thus turns on. Signal EN_rst_Hj switches to “0”. Transistor 124j thus becomes conductive. Signal EN_rst_Hbj switches to “1” while signal EN_set_Hbj remains at “0”. The gate of transistor 130j receives signal VRj′ and the gate of transistor 134j receives signal VRST. Circuit SAj then operates like end-of-deleting detection circuit 154 previously-described in relation with FIG. 12.
FIG. 19 shows another embodiment of a memory 270. The elements common with memory 5 shown in FIG. 1 are designated with the same reference numerals.
Memory 270 especially comprises memory cells Celli,j distributed in rows and in columns. Each bit line BLj, with j varying from 1 to M, is connected via switch 20j to an additional word line DWL. One end of additional word line DWL is connected to a delete and/or write device 272. As an example, each memory cell Celli comprises a reference resistive element Ri,j in series with a non-linear component, for example, a diode Di,j. Memory 270 further comprises an additional column of reference cells DCelli, with i varying from 1 to N. As an example, each reference cell DCelli may have a structure similar to that of memory cell Celli,j and comprise a reference element DRi in series with a non-linear component, for example, a diode DDi. Each reference cell DCelli comprises a first terminal connected to a word line WLi and a second terminal connected to an additional bit lines DBL. Additional bit line DBL is connected to delete and/or write device 272 via a switch DT controlled by bit line selection unit 22. Switch DT for example corresponds to a MOS transistor, for example, with a P channel, having its drain connected to reference bit line DBL, having its source connected to a node A′, and having its gate controlled by unit 22.
As an example, device 272 may operate similarly to delete device 14 previously described in relation with FIG. 1, circuit 32 being then replaced with additional bit line DBL and reference cells DCelli. According to another example, device 272 may operate similarly to end-of-writing detection circuit SAj and logic feedback circuit Logicj previously described in relation with FIG. 14. As an example, to carry out an operation of writing into and/or deleting memory cell Celli,j, device 272 is capable of:
circulating current through reference cell DCelli and through memory cell Celli,j;
detecting the switching of the resistance of memory cell Celli,j, for example, by comparing voltages representative of the voltage across reference cell DCelli and of the voltage across memory cell Celli,j; and
interrupting the current flowing through memory cell Celli,j on detection of the switching.
During the write and/or delete operation, current flows through the selected memory cell Celli,j, through the portion of word line WLi between switch 16i and memory cell Celli,j, the portion of bit line BLj between memory cell Celli,j and switch 20j, and the portion of the additional bit line between switch 20j and device 272. Further, current flows through reference cell DCelli, through the portion of word line WLi between switch 16i and reference cell DCelli and the portion of additional bit line DBL between reference cell DCelli and switch DT which is directly connected to device 272. Thereby, the parasitic resistances seen by the current flowing through memory cell Celli,j are substantially the same as the parasitic resistances seen by the current flowing through reference cell DCelli.
FIG. 20 shows another embodiment of a memory 280. Memory 280 comprises all the elements of memory 270, with the difference that reference resistive elements DRi are replaced with a single resistor DR present at the base of additional word line DBL and which is used whatever the selected memory cell Celli,j. There thus advantageously is a gain in surface area with respect to memory 270 and less current variability since the same resistor DR is used.
FIG. 21 shows another embodiment of a memory 290. Memory 290 comprises all the elements of memory 280, with the difference that certain bit lines BLi are not connected to additional word line DWL but are connected to a second additional word line DWL′ via switch 20j. One end of second additional word line DWL′ is connected to a delete and/or write device 292, for example, identical to device 272, to which additional bit line DBL is also connected. This embodiment enables to simultaneously write into/delete from memory cells of different columns. Second additional word line DWL′ is arranged so that the parasitic resistances seen by the current flowing through the memory cell Celli,j connected to device 292 are substantially the same as the parasitic resistances seen by the current flowing through resistor DR connected to device 292.
Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, the N-channel MOS transistors may be replaced with P-channel MOS transistors and the P-channel MOS transistors may be replaced with N-channel MOS transistors by adapting the control signals of these transistors.
Further, although the previously-described embodiments relate to bipolar memory cells for which the polarity of the voltage applied across the memory cell is inverted between a write operation and a delete operation, it should be clear that these embodiments may be adapted to unipolar memory cells for which the polarity of the voltage applied across the memory cell is the same for a write operation and a delete operation, only the amplitude range of the applied voltage being different between a write operation and a delete operation.
Further, although in the embodiments previously described in relation with FIGS. 11 to 18, each memory cell comprises a resistive element series-connected with a switch, particularly a MOS transistor, these embodiments may be implemented with other types of memory cells. As an example, each memory cell may comprise a diode series-connected with the resistive element.

## Claims

1. A resistive memory comprising resistive elements arranged in rows and in columns, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device comprising a first circuit capable of circulating a first current through at least one first reference resistive component or of applying a first voltage across the first reference resistive component, a second circuit capable, during a switching operations, of circulating a second current proportional to the first current through the selected resistive element or of applying a second voltage proportional to the first voltage across the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of a third voltage which depends on the voltage across the first reference resistive component and of a second voltage which depends on the voltage across the selected resistive element or from the comparison of a third current which depends on the first current with a fourth current which depends on the second current, and a fourth circuit capable of interrupting the second current flowing through the selected resistive element on detection of the switching, the memory further comprising, for each row, at least one first conductive track connected to each resistive element in the row and, for each column, a second conductive track connected to each resistive element in the column, the memory further comprising at least one third conductive track connected to the first reference resistive component, each first conductive track being connected to the third conductive track.

2. The resistive memory of claim 1, wherein the first circuit is capable of circulating a fifth current proportional to the first current through at least one second reference resistive component.

3. The resistive memory of claim 2, comprising a current mirror capable of copying the first current flowing through the first reference resistive component, or the fifth current flowing through the second reference resistive component, in said selected resistive element, possibly modified by a multiplication factor.

4. The resistive memory of claim 1, the first circuit being capable of supplying the first increasing voltage, and wherein the device comprises a circuit for supplying a third increasing voltage and a voltage divider comprising, in series, at least one resistive component and the selected resistive element, the third voltage being applied across the voltage divider, the fourth voltage being measured at a node of the voltage divider between the resistive component and the selected resistive element.

5. The resistive memory of claim 1, further comprising, for each resistive element, a first switch series-connected with the resistive element, the first conductive track being connected to each first switch in the row, the memory comprising, for each row, a second switch connected to the first conductive track and to the first reference resistive component.

6. The resistive memory of claim 5, further comprising, for each column, a fourth conductive track, each resistive element being series-connected with the first associated switch between the fourth conductive track and the second conductive track, the memory further comprising a fifth conductive track, each second switch being interposed between the third conductive track and the fifth conductive track.

7. The resistive memory of claim 5, comprising a current mirror capable of copying the first current flowing through the first reference resistive component, or the fifth current flowing through the second reference resistive component, in said selected resistive element, possibly modified by a multiplication factor, wherein, for each column, the second and fourth conductive tracks are connected to the current mirror and wherein the third conductive track is connected to the current mirror.

8. The resistive memory of claim 5, comprising a circuit for supplying a reference voltage connected, for each column, to the second and fourth conductive tracks and connected to the fifth conductive track.

9. The resistive memory of claim 6, comprising, for each row, said first reference resistive component series-connected with the second switch, the fifth conductive track being connected, for each row, to the second switch in the row and the third track being connected, for each row, to the first reference resistive component in the row.

10. The resistive memory of claim 6, comprising a single first reference resistive component, the third and fifth conductive tracks being connected, for each row, to the second switch in the row and the third track being connected to the single first reference resistive component.

11. The resistive memory of claim 6, wherein the first circuit is capable of circulating a fifth current proportional to the first current through at least one second reference resistive component, and further comprising sixth and seventh conductive tracks, and for each row, a third switch connecting the sixth and seventh conductive tracks, the sixth and/or the seventh conductive track being connected to the second reference resistive component.

12. The resistive memory of claim 1, wherein the third circuit comprises a comparator receiving the first voltage and the second voltage and providing a binary signal which depends on the sign of the difference between the first voltage and the second voltage.

13. The resistive memory of claim 12, comprising, for each column, a fourth conductive track, each resistive element being series-connected with the first associated switch between the fourth conductive track and the second conductive track, the memory further comprising a fifth conductive track, each second switch being interposed between the third conductive track and the fifth conductive track, and further comprising a fourth switch connected to the fourth conductive track and a fifth switch connected to the second conductive track, the fourth and fifth switches being controlled by the binary signal or a signal derived from the binary signal.

14. A method of controlling a resistive memory comprising resistive elements arranged in rows an in columns, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, for the switching of the resistance of a resistive element selected from among the resistive elements between the high and low values, the memory further comprising, for each row, at least one first conductive track connected to each resistive element in the row and, for each column, a second conductive track connected to each resistive element in the column, the memory further comprising at least one third conductive track connected to the first reference resistive component, each first conductive track being connected to the third conductive track, the method comprising the steps of:
circulating a first current through at least one first reference resistive component or applying a first voltage across the first reference resistive component;
circulating, during a switching operation, a second current proportional to the first current in the selected resistive element or applying a second voltage proportional to the first voltage across the selected resistive element;
detecting the switching of the resistance of the selected resistive element from the comparison of a third voltage which depends on the voltage across the first reference resistive component with a fourth voltage which depends on the voltage across the selected resistive element or from the comparison of a third current which depends on the first current with a fourth current which depends on the second current; and
interrupting the second current flowing through the selected resistive element or interrupting the second voltage on detection of the switching.

15. The control method of claim 14, wherein the first current is increasing during the switching operation.

16. The resistive memory of claim 7, comprising, for each row, said first reference resistive component series-connected with the second switch, the fifth conductive track being connected, for each row, to the second switch in the row and the third track being connected, for each row, to the first reference resistive component in the row.

17. The resistive memory of claim 8, comprising, for each row, said first reference resistive component series-connected with the second switch, the fifth conductive track being connected, for each row, to the second switch in the row and the third track being connected, for each row, to the first reference resistive component in the row.

18. The resistive memory of claim 7, comprising, for each row, said first reference resistive component series-connected with the second switch, the fifth conductive track being connected, for each row, to the second switch in the row and the third track being connected, for each row, to the first reference resistive component in the row.

19. The resistive memory of claim 8, comprising, for each row, said first reference resistive component series-connected with the second switch, the fifth conductive track being connected, for each row, to the second switch in the row and the third track being connected, for each row, to the first reference resistive component in the row.