# Patent

## Title
Optimized data transfer utilizing optimized code table signaling

## Abstract

In various embodiments, a computer-implemented method for optimized data transfer utilizing optimized code table signaling is disclosed. In one embodiment, a computer-implemented method comprises receiving, by a processor, a digital bit stream and transforming, by the processor, the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof. The computer-implemented method further comprises providing, by the processor, the encoded digital bit stream to a transmission system for transmission.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application claims the benefit, under 35 U.S.C. §119(e), of U.S. Provisional Application Ser. No. 61/862,745, filed Aug. 6, 2013, the disclosure of which is incorporated herein by reference in its entirety.


TECHNICAL FIELD
The disclosure generally relates to the field of communication systems, particularly to a data communication system utilizing optimized code table signaling.
BACKGROUND
Various data communication schemes are available for radio communication systems. Modulation techniques (e.g., analog or digital modulation) may be utilized in such communication schemes. In addition, encoding and decoding processes may also be utilized to improve the signal integrity of the data being communicated.
SUMMARY
The present disclosure is directed to data communication systems and methods. In various embodiments, the method applies optimized code table signaling (OCTS) to a digital data stream for the purpose of optimizing its transfer; adapting to a digital communications network; and operating independent of industry and regulatory standards for input digital bit stream and transmission methods.
A further embodiment comprises applying OCTS to an analog bit stream that has been digitized for the purpose of optimizing the bit stream's transfer; adapting to a communications method selected for transmission of digitized analog signals; and operating independent of industry and regulatory standards for input digitized analog signal stream and transmission methods.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the present disclosure. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate subject matter of the disclosure. Together, the descriptions and the drawings serve to explain the principles of the disclosure.



BRIEF DESCRIPTION OF THE DRAWINGS
The novel features of the embodiments described herein are set forth with particularity in the appended claims. The embodiments, however, both as to organization and methods of operation may be better understood by reference to the following description, taken in conjunction with the accompanying drawings as follows:
FIG. 1 illustrates a block diagram of one embodiment of a data communication system for transmitting data from one or more senders to one or more receivers.
FIG. 2 illustrates a block diagram of one embodiment of data communication system for transmitting data.
FIG. 3 illustrates one embodiment of an OCTS process.
FIG. 4 illustrates one embodiment of an OCTS table.
FIG. 5 illustrates one embodiment of an OCTS-expanded table.
FIG. 6 illustrates one embodiment of an OCTS-expanded process including an interleaved data vector.
FIG. 7 illustrates one embodiment of an OCTS-expanded table comprising a designated use for each data type.
FIG. 8 illustrates one embodiment of interleaved gateway channel and composite channel vectors.
FIG. 9 illustrates one embodiment of an OCTS-expanded code table servicing an m-element binary input vector.
FIG. 10 illustrates one embodiment of an OCTS-expanded table transmission mode.
FIG. 11 illustrates one embodiment of an OCTS-expanded table receive mode.
FIG. 12 illustrates one embodiment of an OCTS-expanded gateway code table and block.
FIG. 13 illustrates one embodiment of the symbol, frame, and block relationship within a two-message block set.
FIG. 14 illustrates one embodiment of a computing device which can be used in one embodiment of the systems and methods for network monitoring and analytics.



DETAILED DESCRIPTION
Reference will now be made in detail to several embodiments, including embodiments showing example implementations of systems and methods for OCTS-expanded data communications. Wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict example embodiments of the disclosed systems and/or methods of use for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative example embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein.
FIG. 1 illustrates one embodiment of an Optimized Code Table Signaling (OCTS) process. The OCTS process provides encoding of binary inputs to multi-valued vectors that are presented to the modulator and transmitter, and provides the reverse process of converting the received multi-value vector to a binary output vector. By judicious choice of the OCTS table, the parameters of Bit Error Rate (“BER”), realized data throughput, bit energy, and signal range may be managed dynamically to provide optimized performance. OCTS is described in U.S. Pat. No. 8,320,473, issued on Nov. 27, 2012, and entitled “Data Communication System Utilizing Optimized Code Table Signaling,” which is hereby incorporated by reference in its entirety.
FIG. 1 shows a block diagram illustrating steps performed by a data communication system/method 1000 implementing OCTS. The data communication system 1000 is utilized for transmitting data from one or more senders 1002 to one or more receivers 1010. The data communication system 1000 is configured to utilize the mapping of a binary bit stream to real-valued vectors, where the mapping functions are determined based on the characteristics/properties of the communication path/environment.
In one embodiment, upon receiving data from a sender 1002, step 1004 transforms (encodes) the received data into a vector of real numbers (which may be referred to as a real-valued data vector). For example, each n-bit binary word may be transformed into a set of m real-valued numbers. The transformation is calculated in real-time for each binary word based on the mapping function, or performed as a lookup in a pre-computed table. For example, in one embodiment, Trellis coded Modulation (TCM) is utilized for transforming a sequence of n-bit binary words into a sequence of m real-valued numbers based on the pre-computed table.
The number (m) of real-valued numbers utilized to represent an n-bit binary word may vary based on the properties of the communication path/environment. For example, in one embodiment, fewer than 6 real-valued numbers are utilized to represent a 6-bit binary word in a less noisy environment. In another embodiment comprising a noisy environment, a 6-bit binary word may be transformed into a set of 6 (or more) real-valued numbers. Those skilled in the art will understand that a small m value (the number of real-valued numbers used to represent an n-bit binary word) increases transmission capacity, while a larger m value provides better performance in a noisy environment. The specific values of n and m may be determined base on one or more properties of the communication environment, such as, for example, noise level, bit error rate, signal integrity, and/or other properties.
A transmitter 1006 transmits the transformed real-value data vector to a receive side. Standard communication mechanism, such as, for example, radio communication technologies comprising analog and/or digital module and/or spread spectrum techniques, may be utilized for the transmission. For example, in one embodiment, Quadrature Amplitude Modulation (QAM) is utilized for transmission of the transformed real-value data vector from the sender side to the receiver side.
Upon receipt of the real-valued data vector on the receiver side, the received real-valued data vector is transformed (decoded) 1008 into the computer-readable format originally sent by the sender 1002. In one embodiment, the decoding process 1008 is performed as a table lookup for each set of m real-valued numbers to locate the n-bit binary word represented by the given set of m real-valued numbers. For example, for each set of m real-valued numbers, the decoding process 1008 locates an element in the lookup table that has the smallest Euclidian distance away from this set of m real-valued numbers. Thus, the n-bit binary word that corresponds to this element in the lookup table is the n-bit binary word represented by the set of m real-valued numbers.
Once the transformation 1008 of the real-valued data vector into data represented in a computer readable-medium format is completed, the computer-readable data is transmitted to the receiver 1010. It will be appreciated that additional signal integrity is provided by transmitting the encoded real-valued data vectors instead of the original binary data stream. Since the transformation table (or code table) is not shared with a third party, decoding of the intercepted real-valued data vector (by the third party) into the format originally sent by the sender may be prevented and/or deferred. In some embodiments, the sender 1002 and the receiver 1010 both comprise a pool of potential code tables suitable for performing the encoding and decoding. The sender 1002 informs the receiver 1010 of the specific code table utilized for encoding via a table identifier, such as, for example, acknowledging a table identifier as part of a handshake process and/or sending the identifier as part of the data transmission. The table identifier may not be meaningful to the third party intercepting the transmission.
In some embodiments, the performance of the data communication system 1000 is determined by the attributes of the code tables, which may be optimized based on the properties of the communication environment. The code tables may not be unique for mapping an n-bit binary word to a set of real-valued numbers. In one embodiment, the selection criteria for a suitable code table comprises: 1) having a maximum distance between the data vectors while maintaining the maximum power in the data vectors and using the same dynamic range within each column; and 2) providing an acceptable encoding and decoding performance, for example, above a predetermined threshold.
FIG. 2 illustrates a block diagram of a communication system 1100. The data communication system 1100 may comprise: an input module 1102 for obtaining a data vector to be communicated; a code table selecting module 1104 for selecting a code table configured to facilitating said data communication; a vector selecting module 1106 for selecting a vector of real numbers representative of said data vector from said code table, for example, utilizing Trellis Coded Modulation; and a transmitter 1108 for transmitting the vector of real numbers to a receiver. The vector of real numbers is transformed, upon reception, into a best corresponding vector by utilizing the code table as previously described.
In one embodiment, the code table selecting module 1104 comprises a determining module 1110 for determining at least one of a communication characteristic of a communication environment, a desired level of signal integrity, a desired data throughput level, or any combination thereof. The code table selecting module 1104 selects the code table at least partially based upon at least one of said communication characteristic of the communication environment, desired level of signal integrity, desired data throughput level, or any combination thereof.
In some embodiments, the code table selecting module 1104 includes a table generating module 1112 for creating a plurality of candidate code tables, each of the plurality of candidate code tables having real-valued data entries. The code table selecting module 1104 selects the code table from the plurality of candidate code tables based on an evaluation criterion. For example, in one embodiment, the evaluation criterion is based on at least one characteristic of the communication environment, such as, for example, noise level, bit error rate, signal integrity, and/or other properties. In another embodiment, the evaluation criterion comprises a minimum separation distance for a given candidate code table.
In some embodiments, the code table selecting module 1104 comprises a selecting module 1114 for selecting a code table from a set of preconfigured code tables. Each preconfigured code table of the set of preconfigured code tables is associated with a performance metric to facilitate the selection process. Once a selection is made, a coordinating module 1116 coordinates the code table selected with at least one receiver.
In some embodiments, the data communication system 1100 comprises an evaluating module 1118 for evaluating a performance metric of the code table. A determining module 1120 is configured to determine whether the performance can be improved if the current code table is replaced with a new code table. If the performance can be improved, a replacing module 1122 replaces the current code table with the new code table, and the new code table is utilized for subsequent data communications.
As previously mentioned, the receiver is configured for transforming the vector of real numbers received into a best corresponding vector by utilizing the code table. In one embodiment, the receiver comprises: a vector generating module 1124 for creating a set of candidates for the best corresponding vector; an associating module 1126 for associating each candidate of the set of candidates with a confidence value, the confidence value for each candidate is determined based on a separation distance between the candidate and the vector of real numbers calculated utilizing the code table; and a transforming module 1128 for transforming the vector of real numbers into the candidate with the best confidence value. In some embodiments, the receiver comprises a storage device configured for storing the best corresponding vector.
In some embodiments, code table generation algorithms are driven by a seed value passed into a pseudorandom number generator. By using a random number generator that creates an identical string of pseudorandom numbers given an identical seed, the code table generation algorithms will generate an identical code table given an identical seed. A code table may be identified by a unique identifier within a naming scheme and/or by a seed value. In some embodiments, the code table algorithms require two or more seed values, each for unique functions within the code table generation algorithm. When multiple seed values are used, an exhaustive search of a code table space driven by creating an exhaustive list of code tables becomes prohibitively complex. In some embodiments, code table generation comprises a three-step process, consisting of table creation, table evaluation, and table partitioning.
In some embodiments, a full set of code table output vectors is referred to as a code table signal constellation. Given a pair of n-element output vectors x=(x1, x2, . . . , xn) and y=(y1, y2, . . . , yn), the mean free Euclidian distance (MFED) between vectors x and y is given by the equation:




  
    MFED
    ⁡
    
      (
      
        x
        ,
        y
      
      )
    
  
  =
  
    
      
        ∑
        
          i
          =
          1
        
        n
      
      ⁢
      
        
      
      ⁢
      
        
          (
          
            
              x
              i
            
            -
            
              y
              i
            
          
          )
        
        2
      
    
  




The first order driver of the noise rejection properties of a code table is the minimum MFED (min MFED) across all output vector pairs. Given two code tables, the code table with the largest minimum MFED can be predicted to have the fewest errors given identical signal to noise ratio (SNR) environments. In some embodiments, the minimum MFED serves as a table metric. In embodiments comprising sparsely populated tables (qn>>2m), the minimum MFED provides a useful metric. In embodiments comprising fully populated tables, the minimum MFED may be constant from table to table and therefore does not provide a useful metric.

In some embodiments comprising sparsely populated code tables, a table creation process generates a search algorithm to generate candidate code tables and to evaluate each of the candidate code tables with a code table metric. For example, in one embodiment, if a table is very sparsely populated, a table generator spreads the signal constellation apart to generate better candidates as compared to a signal constellation with a more uniform spread. In another embodiment comprising a fully populated code table, the minimum MFED may be identical in all cases. In this embodiment, the table generator is configured to maintain mapping from a single random number seed to a specific and repeatedly generated code table.
FIG. 3 illustrates one embodiment of an OCTS information flow. An analog input is converted 4 to a digital bit stream. A digital frame and additional error control coding (ECC) 6 is applied to the digital bit stream. A binary input vector is provided to an OCTS table lookup 8. The OCTS table lookup 8 produces a multi-valued output vector, which is provided for modulation and transmission 10. The modulated signal is transmitted over a radiofrequency channel and is received and a demodulated 12 at a destination. The demodulated multi-valued output vector is provided for reconstruction of the bit stream 16. In some embodiments, a digital output is provided. In other embodiments, the digital bit stream is converted 18 into an analog output. The multi-valued output vectors that comprise the output of the OCTS table lookup and the input to the reverse OCTS table lookup in FIG. 1 may comprise binary vectors in and out of a conventional digital communications system.
An OCTS-expanded process provides the means to manage many of the tasks of OCTS and expands the utility of OCTS as an industry-standards agnostic interface to an existing digital communications system. In some embodiments, an OCTS-expanded table comprises an addition of a column to the OCTS table indicating the expanded use of each encoded vector. FIG. 4 illustrates one embodiment of a standard OCTS table. FIG. 5 illustrates one embodiment of an OCTS-expanded table comprising an additional column. In some embodiments, one or more internal OCTS-expanded control channels are included for the OCTS-expanded process. As illustrated in FIG. 4, a traditional OCTS table 20 comprises one or more OCTS encoded vectors 22. The OCTS-expanded table 120, illustrated in FIG. 5, comprises one or more OCTS encoded vectors 122 and further comprises a use column 124. The use column 124 identifies the use of a vector within the OCTS-expanded table 120.
In some embodiments, OCTS-expanded processing requires two independent channels, denoted as the Gateway Channel and the Composite Channel. The Gateway Channel allows a member user into the signal stream, and the Composite Channel provides message and control functions. Each channel requires its own code table, denoted as the Gateway Code Table and the Composite Code Table. In some embodiments, the encoded Gateway Channel output vectors are interleaved with the encoded Composite Channel output vectors into a single pipe. The interleaving provides an additional measure of complexity to the signal stream that may be used for additional functions beyond Optimized Data Transfer.
In some embodiments, a data vector is interleaved as illustrated in FIG. 6. A binary input data vector 226 is provided to an OCTS-expanded encoder 230. The OCTS-expanded encoder 230 applies an OCTS-expanded table to the binary input data vector 226. A gateway encoder 228 encodes a gateway channel utilizing a second OCTS-expanded table. The data stream for the OCTS-expanded encoder 230 and the gateway encoder 228 are interleaved 234 into the same output stream to produce a multi-valued output composite vector 236, which is transmitted over a communication channel. In some embodiments, the communication channel may comprise an RF communication channel. In other embodiments, the communication channel may comprise any bound or unbound communication channel. An internal OCTS-expanded controller 232 is configured to control both the OCTS-expanded encoder 230 and the gateway encoder 228.
In various embodiments, a channel is defined as a specifically purposed stream of encoded information. FIG. 7 illustrates one embodiment of an OCTS-expanded table comprising a use column 322 denoting the use type for each vector within the OCTS-expanded table 320. Each data type of the Use Column of an OCTS-expanded encoded vector has a designated use. In some embodiments, control data for the Gateway Channel is used for gateway and code table identification and is denoted “C1.” Control data for the Gateway Channel may be further used for Receive and Transmit (RX/TX) coordination. In some embodiments, additional use column data for the Gateway Channel comprising Error Control Coding (ECC) information, denoted as “E1”, and additional data, denoted as “D1,” may be included in the OCTS-expanded table 320. In some embodiments, the composite channel is used for combination data, RX/TX coordination and/or other possible control information. Control data for RX/TX coordination in the Composite Channel is denoted “C2”, Error Control Coding information is denoted as “E2”, and additional data may be included and is denoted as “D2.” In some embodiments, additional uses may exist for the Composite Channel and may be used for growth and expansion of the OCTS-expanded process. In one embodiment, the additional Composite Channel data defines the function and performance of OCTS-expanded Quality of Service processing.
In various embodiments, a pipe comprises the full set of channels for an RX/TX pair. A symbol comprises one element of an encoded output vector, a frame comprises the full element set of an encoded output vector, and a block comprises the full frame set of encoded vectors included in a message block. Symbol synchronization comprises the identification of the leading edge of single symbol. Frame synchronization comprises the identification of the initial symbol within a frame. Block synchronization comprises the identification of the initial frame within a message block.
In some embodiments, the interleaved encoded multi-valued output vector is created using a mask to identify the locations within the Composite Channel symbol stream to interleave with the Gateway Channel symbol stream. FIG. 8 illustrates one embodiment of a composite channel code block 438, a gateway channel code block 440, a pipe 442 comprising the interleaved composite channel code block 438 and the gateway channel code block 440, and a mask 444 indicating the interleave pattern of the pipe 442. In the illustrated embodiment, the gateway channel block 440 length is dissimilar to the composite code block 438 length, and both are dissimilar to the Interleaved Code Block 442 length. The interleaving of the gateway channel 440 and the composite channel 438 with frame and message synchronization requires symbol synchronization. In some embodiments, the interleaving process sifts the symbols through the de-interleave function. This is detailed in Table 1, and allows full message transmission through the Composite Channel.
FIG. 9 illustrates one embodiment of an OCTS-expanded Code Table, servicing an m-element binary input vector, and generating an n-element multi-value output vector. The OCTS-expanded code table comprises a plurality of code table partitions. Code table partitions comprise the sections of the code table specifically assigned to a single channel. The code table illustrated in FIG. 9 is partitioned to encode additional data D1 and error control coding E1. In some embodiments, table paritioning provides increased minimum MFED within each partition and improves the partition noise rejection properties.
In some embodiments, a number q of symbol elements is available for each element of the output vector. For example, in the case of Multiple Frequency Key Shifting with forty one unique tones, q is equal to 41. The number of binary inputs comprises 2m, where m is the number of elements in the binary input vector, and the total number of possible output vectors is qn, where n is the number of elements in the encoded output vector. For example, the OCTS-expanded table 520 illustrated in FIG. 7 may be used to encode a 16 bit input vector. The number of unique binary inputs is 216=65,536, and the number of unique multi-valued output vectors is 413=68,921. The OCTS-expanded Code Table associated with this input/output pairing is an array of dimension (68921, 3). In this example, the D1 partition of the OCTS-expanded Code Table comprises the first 65,536 rows, leaving 68,921−65,536=3,385 rows to encode 3,385 C1 and E1 vectors.
In various embodiments, an OCTS-expanded process can transmit and receive into an existing digital communications system to integrate robust control features into the digital data stream. FIG. 10 illustrates one embodiment of an OCTS-expanded process integrated into a digital communications system. In this embodiment, a conventional digital bit stream 650 is converted to a composite multi-valued stream, including data, control, and additional error control coding information. The digital bit stream 650 is provided to an input buffer 652. The input buffer 652 passes the digital bit stream 650 to an error control coding process 654. The digital bit stream 650 and the error control coding 654 stream are provided to a multiplexer 656 which is coupled to an input vector mapper 658. The input vector mapper 658 maps the output of the multiplexer 656 to an OCTS-expanded table. The composite channel signal coding 660 process encodes mapped vectors based on a table stored by the composite table manager 668 and the table library manager 666. The encoded data is passed to an interleaver 676 to interleave the data with a gateway channel stream. The gateway channel stream is generated by a transmit controller 662 coupled to a gateway channel formatter 664. The gateway channel formatter 664 provides gateway channel data to a gateway channel mask 670, which in turn passes the data to a gateway channel signal coding 674 process for encoding the gateway channel data. The encoded gateway channel data is provided to the interleave signal processor 676 and is interleaved with the composite channel data provided by the composite channel signal coding 660 process. The interleaved signal is provided to an input buffer 678 and then to the transmission medium 680. In some embodiments, the output of the OCTS-expanded processing transmit module of the digital communications system is one-to-one, that is, a given input to the OCTS-expanded processing transmit module always results in the same output, and the output is unique to the given input.
FIG. 11 illustrates one embodiment of a receive mode of a digital communications system with an integrated OCTS-expanded process. In one embodiment, a composite multi-valued stream is converted to its constituent data, control, and error control coding channels. The decoded binary output data vectors are then passed along to be processed into a digital bit stream. The receive mode of the digital communications system is generally the reverse of the transmit mode, illustrated in FIG. 10. A multi-valued data stream is received from a transmission medium 780 and passed to an input buffer 778. The input buffer is coupled to a de-interleave signal processor 786 configured to de-interleave the received multi-valued data stream. The composite signal portion of the multi-valued data stream is provided to a composite channel signal coding 760 process for decoding. The composite channel signal coding 760 process utilizes an OCTS-expanded table to decode the received composite channel data. The decoded data is provided to an input vector mapper 758 to un-map the decoded data and provide a digital data stream. The output of the input vector mapper 758 is de-multiplexed into a data stream and an error correcting coding stream, which are both provided to an ECC coder 754. The data stream is error corrected and provided to an input buffer 752, which provides the data stream to a digital bit stream source (or destination) 750.
After being de-interleaved, the gateway channel is provided to a gateway channel signal coding 774 block to decode the gateway channel data through an OCTS-expanded table. The output of the gateway channel signal coding 774 block is provided to a gateway channel mask 770 block to remove the mask from the gateway channel data. The de-masked gateway channel data is provided to a gateway channel formatter 764, which removes previously added formatting from the gateway channel data, and provides the gateway channel data to a receive controller 762.
In some embodiments, the gateway code table and message blocks encode and decode the composite code table identifier and provide confidence in the composite code table identifier's correct decoding. In one embodiment, an appropriate number of seeds for pseudorandom number generators are used by the receive function to uniquely generate the Composite Code Table. Multiple methods may be used to establish the Gateway Code Table and Message Blocks, such as, for example, bit position partitioning, table partitioning, or a combination of the two techniques.
In Bit Position Partitioning, both the transmitter and receiver know the location of the encoded bits. Detection of the transmitted message is available to the receiver based on knowledge of the position of the encoded message. An appropriate number of seeds are used to generate the pseudorandom numbers for the unique encoding.
With table partitioning, the partitions can be allocated to increase the Mean Free Euclidian Distance (MFED) between elements of the partition by assigning encoded elements with the smallest MFED to different partitions. This increases the MFED within a partition, thus increasing noise rejection properties in the case where a received signal can be identified as a member of a specific partition.
With the use of table partitioning alone, the gateway channel information can be encoded using the gateway channel's partition elements without the use of bit position partitioning for identification. With bit position partitioning, the process of synchronizing against the first element of a message block can be achieved by recognizing the position of the gateway channel information within the block, and stepping back in bit position with this known offset. In table partitioning, the gateway channel information must carry this offset within its encoding, since the offset from the received Gateway Channel bits and the lead bit of a message block can vary. FIG. 12 illustrates one embodiment of a gateway code table and block configured for table partitioning. As illustrated in FIG. 12, the OCTS-expanded encoded vector for the gateway channel comprises the offset within the channel frames 838.
FIG. 13 illustrates one embodiment of a symbol 888, frame 886, and block 884 relationship within a two-message block set 882. In the illustrated embodiment, both frames 886 and blocks 884 begin on a symbol 888 boundary. In order to perform block message processing, the specific symbol that begins a block must be identified by the OCTS-expanded process.







TABLE 1





Step-by-Step Process for message transmit and receive


Step-by-Step Process
















Preparation
Distribute the necessary shared information to the



subscriber 



Gateway Table Code identifier



RF Specifics: Frequency, BW, modulation, digital



encoding method



Interleaving mask and block length


Signal Acquisition
This is a receiver and demodulator function.


Symbol
The decoding process begins with the identification of


synchronization
symbols


De-interleaving
Search Interleaved message blocks by performing the



masking function against each possible initial symbol



Evaluate each candidate message block using the



Gateway Code Table and the Gateway Block definition



associated with FIG. 7 above.



De-interleaving is successful when the seed checksums



are per the predefined encode.



Use the contents of the Gateway Channel Frame to



determine the symbol offset to align the Composite



Channel


Composite 
Align the Composite Channel message block and begin


Channel decoding
decoding



Continue to decode the Interleaved channel and



maintaining the Composite Code Table









In various embodiments, the interleave and de-interleave functions are configured to act in coordination with each other. The interleave and de-interleave functions are each driven by a controller utilizing the interleave and de-interleave specification and sequencing seeds.
In some embodiments, the gateway channel format and reformat functions are configured to act in coordination with each other. The gateway channel format and reformat functions are each driven by the controller utilizing the gateway channel format and reformat specification and sequencing seeds.
In some embodiments an error correcting code such a Bose, Chaudhuri, and/or Hocquenghem (BCH) code that generates additional bits that are added uniquely to the data stream is included in the OCTS-expanded processing. By adding the use definition to each code, the E1 encoded vectors can be injected into the composite data stream in an arbitrary location, since they can be identified specifically as the generated parity and error correction bits. In various embodiments, the input MUX and output DEMUX are configured to act in coordination with each other. The input MUX and the output DEMUX are each driven by the controller utilizing the MUX/DEMUX specification and sequencing seeds.
In some embodiments, an OCTS-expanded communication system comprises a controller. The controller is responsible for a series of tasks, such as, for example quality of service monitoring and code table selection to meet the needs of a dynamic transmission environment. The controller may be further responsible for specifying, scheduling, and coordinating code table swaps, input remapping, multiplexer and de-multiplexer operations, gateway channel formatting, and/or interleaved operations. In some embodiments, the controller is configured to receive information, such as, for example, code table swap seeds, input remapping seeds, multiplexer and de-multiplexer operation seeds, gate channel formatting seeds, and/or interleaved operation seeds. The received seeds may be generated from the code table generator seeds coded in the gateway channel.
In some embodiments, operational requirements for the controller comprise monitoring the transmission environment and adapting to the transmission environment and maintaining a sufficiently high rate of table swapping to maintain signal integrity. The operational requirements may be driven by a specific application. The controller management may be driven by a requirements matrix, an options matrix defined by the system resources, and/or direct and indirect performance and transmission environment measures. Direct performance and transmission environment measures may comprise, for example, direct quality of service measurements derived using code built into the code table to calibrate against a known signal and receiver-unique measurements. Indirect performance and transmission environment measures may comprise, for example, bit error rate derived from error control coding schemes, SNR estimate derived from miss distance measures used in the decoding process, and/or rule in/rule out measure.
In some embodiments, an indirect performance and transmission environment measure comprises rule in/rule out measure. An OCTS decode process requires comparing the received decoded vector against all of the encoded vectors in a code table. In some embodiments, rather than an exhaustive search of the table, a rule in rule may be implemented. A rule in rule requires that if the MFED between the input vector and a code table vector is less than a predetermined value, the decoded vector is immediately ruled in as the matching vector and the search can cease. In some embodiments, a rule out rule may be implemented. A rule out rule requires that if the accumulated MFED calculated on a vector element-by-vector element basis exceeds a predetermined threshold, the code table vector can be ruled out and the MFED calculation for that vector can cease. In some embodiments, a derived measure is generated in the case where no vector is ruled in, and all but a few vectors are ruled out. In this embodiment, the vectors that are not ruled out are correlated to a signal to noise ratio and the proper match determined.
FIG. 14 illustrates one embodiment of a computing device 900 which can be used in one embodiment of the systems and methods for OCTS-expanded communication. For the sake of clarity, the computing device 900 is shown and described here in the context of a single computing device. It is to be appreciated and understood, however, that any number of suitably configured computing devices can be used to implement any of the described embodiments. For example, in at least some implementation, multiple communicatively linked computing devices are used. One or more of these devices can be communicatively linked in any suitable way such as via one or more networks (LANs), one or more wide area networks (WANs), wireless connections, or any combination thereof.
In this example, the computing device 900 comprises one or more processor circuits or processing units 902, on or more memory circuits and/or storage circuit component(s) 904 and one or more input/output (I/O) circuit devices 906. Additionally, the computing device 900 comprises a bus 908 that allows the various circuit components and devices to communicate with one another. The bus 908 represents one or more of any of several types of bus structures, including a memory bus or local bus using any of a variety of bus architectures. The bus 908 may comprise wired and/or wireless buses.
The processing unit 902 may be responsible for executing various software programs such as system programs, applications programs, and/or module to provide computing and processing operations for the computing device 900. The processing unit 902 may be responsible for performing various voice and data communications operations for the computing device 900 such as transmitting and receiving voice and data information over one or more wired or wireless communication channels. Although the processing unit 902 of the computing device 900 includes single processor architecture as shown, it may be appreciated that the computing device 900 may use any suitable processor architecture and/or any suitable number of processors in accordance with the described embodiments. In one embodiment, the processing unit 900 may be implemented using a single integrated processor.
The processing unit 902 may be implemented as a host central processing unit (CPU) using any suitable processor circuit or logic device (circuit), such as a as a general purpose processor. The processing unit 902 also may be implemented as a chip multiprocessor (CMP), dedicated processor, embedded processor, media processor, input/output (I/O) processor, co-processor, microprocessor, controller, microcontroller, application specific integrated circuit (ASIC), field programmable gate array (FPGA), programmable logic device (PLD), or other processing device in accordance with the described embodiments.
As shown, the processing unit 902 may be coupled to the memory and/or storage component(s) 904 through the bus 908. The memory bus 908 may comprise any suitable interface and/or bus architecture for allowing the processing unit 902 to access the memory and/or storage component(s) 904. Although the memory and/or storage component(s) 904 may be shown as being separate from the processing unit 902 for purposes of illustration, it is worthy to note that in various embodiments some portion or the entire memory and/or storage component(s) 904 may be included on the same integrated circuit as the processing unit 902. Alternatively, some portion or the entire memory and/or storage component(s) 904 may be implemented in an integrated circuit or other medium (e.g., hard disk drive) external to the integrated circuit of the processing unit 902. In various embodiments, the computing device 900 may comprise an expansion slot to support a multimedia and/or memory card, for example.
The memory and/or storage component(s) 904 represent one or more computer-readable media. The memory and/or storage component(s) 904 may be implemented using any computer-readable media capable of storing data such as volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. The memory and/or storage component(s) 904 may comprise volatile media (e.g., random access memory (RAM)) and/or nonvolatile media (e.g., read only memory (ROM), Flash memory, optical disks, magnetic disks and the like). The memory and/or storage component(s) 904 may comprise fixed media (e.g., RAM, ROM, a fixed hard drive, etc.) as well as removable media (e.g., a Flash memory drive, a removable hard drive, an optical disk, etc.). Examples of computer-readable storage media may include, without limitation, RAM, dynamic RAM (DRAM), Double-Data-Rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory (e.g., NOR or NAND flash memory), content addressable memory (CAM), polymer memory (e.g., ferroelectric polymer memory), phase-change memory, ovonic memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic or optical cards, or any other type of media suitable for storing information.
The one or more I/O devices 906 allow a user to enter commands and information to the computing device 900, and also allow information to be presented to the user and/or other components or devices. Examples of input devices include a keyboard, a cursor control device (e.g., a mouse), a microphone, a scanner and the like. Examples of output devices include a display device (e.g., a monitor or projector, speakers, a printer, a network card, etc.). The computing device 900 may comprise an alphanumeric keypad coupled to the processing unit 902. The keypad may comprise, for example, a QWERTY key layout and an integrated number dial pad. The computing device 900 may comprise a display coupled to the processing unit 902. The display may comprise any suitable visual interface for displaying content to a user of the computing device 900. In one embodiment, for example, the display may be implemented by a liquid crystal display (LCD) such as a touch-sensitive color (e.g., 76-bit color) thin-film transistor (TFT) LCD screen. The touch-sensitive LCD may be used with a stylus and/or a handwriting recognizer program.
The processing unit 902 may be arranged to provide processing or computing resources to the computing device 900. For example, the processing unit 902 may be responsible for executing various software programs including system programs such as operating system (OS) and application programs. System programs generally may assist in the running of the computing device 900 and may be directly responsible for controlling, integrating, and managing the individual hardware components of the computer system. The OS may be implemented, for example, as a Microsoft® Windows OS, Symbian OSTM, Embedix OS, Linux OS, Binary Run-time Environment for Wireless (BREW) OS, JavaOS, Android OS, Apple OS or other suitable OS in accordance with the described embodiments. The computing device 900 may comprise other system programs such as device drivers, programming tools, utility programs, software libraries, application programming interfaces (APIs), and so forth.
The computer 900 also includes a network interface 910 coupled to the bus 908. The network interface 910 provides a two-way data communication coupling to a local network 912. For example, the network interface 910 may be a digital subscriber line (DSL) modem, satellite dish, an integrated services digital network (ISDN) card or other data communication connection to a corresponding type of telephone line. As another example, the communication interface 910 may be a local area network (LAN) card effecting a data communication connection to a compatible LAN. Wireless communication means such as internal or external wireless modems may also be implemented.
In any such implementation, the network interface 910 sends and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information, such as the selection of goods to be purchased, the information for payment of the purchase, or the address for delivery of the goods. The network interface 910 typically provides data communication through one or more networks to other data devices. For example, the network interface 910 may effect a connection through the local network to an Internet Service Provider (ISP) or to data equipment operated by an ISP. The ISP in turn provides data communication services through the internet (or other packet-based wide area network). The local network and the internet both use electrical, electromagnetic or optical signals that carry digital data streams. The signals through the various networks and the signals on the network interface 910, which carry the digital data to and from the computer system 900, are exemplary forms of carrier waves transporting the information.
The computer 900 can send messages and receive data, including program code, through the network(s) and the network interface 910. In the Internet example, a server might transmit a requested code for an application program through the internet, the ISP, the local network (the network 912) and the network interface 910. In accordance with the invention, one such downloaded application provides for the identification and analysis of a prospect pool and analysis of marketing metrics. The received code may be executed by processor 904 as it is received, and/or stored in storage device 904, or other non-volatile storage for later execution. In this manner, computer 900 may obtain application code in the form of a carrier wave.
Various embodiments may be described herein in the general context of computer executable instructions, such as software, program modules, and/or engines being executed by a computer. Generally, software, program modules, and/or engines include any software element arranged to perform particular operations or implement particular abstract data types. Software, program modules, and/or engines can include routines, programs, objects, components, data structures and the like that perform particular tasks or implement particular abstract data types. An implementation of the software, program modules, and/or engines components and techniques may be stored on and/or transmitted across some form of computer-readable media. In this regard, computer-readable media can be any available medium or media useable to store information and accessible by a computing device. Some embodiments also may be practiced in distributed computing environments where operations are performed by one or more remote processing devices that are linked through a communications network. In a distributed computing environment, software, program modules, and/or engines may be located in both local and remote computer storage media including memory storage devices.
Although some embodiments may be illustrated and described as comprising functional components, software, engines, and/or modules performing various operations, it can be appreciated that such components or modules may be implemented by one or more hardware components, software components, and/or combination thereof. The functional components, software, engines, and/or modules may be implemented, for example, by logic (e.g., instructions, data, and/or code) to be executed by a logic device (e.g., processor). Such logic may be stored internally or externally to a logic device on one or more types of computer-readable storage media. In other embodiments, the functional components such as software, engines, and/or modules may be implemented by hardware elements that may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth.
Examples of software, engines, and/or modules may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints.
In some cases, various embodiments may be implemented as an article of manufacture. The article of manufacture may include a computer readable storage medium arranged to store logic, instructions and/or data for performing various operations of one or more embodiments. In various embodiments, for example, the article of manufacture may comprise a magnetic disk, optical disk, flash memory or firmware containing computer program instructions suitable for execution by a general purpose processor or application specific processor. The embodiments, however, are not limited in this context.
While various details have been set forth in the foregoing description, it will be appreciated that the various embodiments of the apparatus, system, and method for anonymous sharing and public vetting of content may be practiced without these specific details. For example, for conciseness and clarity selected aspects have been shown in block diagram form rather than in detail. Some portions of the detailed descriptions provided herein may be presented in terms of instructions that operate on data that is stored in a computer memory. Such descriptions and representations are used by those skilled in the art to describe and convey the substance of their work to others skilled in the art. In general, an algorithm refers to a self-consistent sequence of steps leading to a desired result, where a “step” refers to a manipulation of physical quantities which may, though need not necessarily, take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It is common usage to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. These and similar terms may be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
Unless specifically stated otherwise as apparent from the foregoing discussion, it is appreciated that, throughout the foregoing description, discussions using terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
It is worthy to note that any reference to “one aspect,” “an aspect,” “one embodiment,” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the aspect is included in at least one aspect. Thus, appearances of the phrases “in one aspect,” “in an aspect,” “in one embodiment,” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more aspects.
Although various embodiments have been described herein, many modifications, variations, substitutions, changes, and equivalents to those embodiments may be implemented and will occur to those skilled in the art. Also, where materials are disclosed for certain components, other materials may be used. It is therefore to be understood that the foregoing description and the appended claims are intended to cover all such modifications and variations as falling within the scope of the disclosed embodiments. The following claims are intended to cover all such modification and variations.
In summary, numerous benefits have been described which result from employing the concepts described herein. The foregoing description of the one or more embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or limiting to the precise form disclosed. Modifications or variations are possible in light of the above teachings. The one or more embodiments were chosen and described in order to illustrate principles and practical application to thereby enable one of ordinary skill in the art to utilize the various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the claims submitted herewith define the overall scope.
Some or all of the embodiments described herein may generally comprise technologies which can be implemented, individually, and/or collectively, by a wide range of hardware, software, firmware, or any combination thereof can be viewed as being composed of various types of “electrical circuitry.” Consequently, as used herein “electrical circuitry” includes, but is not limited to, electrical circuitry having at least one discrete electrical circuit, electrical circuitry having at least one integrated circuit, electrical circuitry having at least one application specific integrated circuit, electrical circuitry forming a general purpose computing device configured by a computer program (e.g., a general purpose computer configured by a computer program which at least partially carries out processes and/or devices described herein, or a microprocessor configured by a computer program which at least partially carries out processes and/or devices described herein), electrical circuitry forming a memory device (e.g., forms of random access memory), and/or electrical circuitry forming a communications device (e.g., a modem, communications switch, or optical-electrical equipment). Those having skill in the art will recognize that the subject matter described herein may be implemented in an analog or digital fashion or some combination thereof.
The foregoing detailed description has set forth various embodiments of the devices and/or processes via the use of block diagrams, flowcharts, and/or examples. Insofar as such block diagrams, flowcharts, and/or examples contain one or more functions and/or operations, it will be understood by those within the art that each function and/or operation within such block diagrams, flowcharts, or examples can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof. In one embodiment, several portions of the subject matter described herein may be implemented via Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), digital signal processors (DSPs), or other integrated formats. However, those skilled in the art will recognize that some aspects of the embodiments disclosed herein, in whole or in part, can be equivalently implemented in integrated circuits, as one or more computer programs running on one or more computers (e.g., as one or more programs running on one or more computer systems), as one or more programs running on one or more processors (e.g., as one or more programs running on one or more microprocessors), as firmware, or as virtually any combination thereof, and that designing the circuitry and/or writing the code for the software and or firmware would be well within the skill of one of skill in the art in light of this disclosure. In addition, those skilled in the art will appreciate that the mechanisms of the subject matter described herein are capable of being distributed as a program product in a variety of forms, and that an illustrative embodiment of the subject matter described herein applies regardless of the particular type of signal bearing medium used to actually carry out the distribution. Examples of a signal bearing medium include, but are not limited to, the following: a recordable type medium such as a floppy disk, a hard disk drive, a Compact Disc (CD), a Digital Video Disk (DVD), a digital tape, a computer memory, etc.; and a transmission type medium such as a digital and/or an analog communication medium (e.g., a fiber optic cable, a waveguide, a wired communications link, a wireless communication link (e.g., transmitter, receiver, transmission logic, reception logic, etc.), etc.).
One skilled in the art will recognize that the herein described components (e.g., operations), devices, objects, and the discussion accompanying them are used as examples for the sake of conceptual clarity and that various configuration modifications are contemplated. Consequently, as used herein, the specific exemplars set forth and the accompanying discussion are intended to be representative of their more general classes. In general, use of any specific exemplar is intended to be representative of its class, and the non-inclusion of specific components (e.g., operations), devices, and objects should not be taken limiting.
With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations are not expressly set forth herein for sake of clarity.
The herein described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “operably couplable,” to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components, and/or wirelessly interactable, and/or wirelessly interacting components, and/or logically interacting, and/or logically interactable components.
In some instances, one or more components may be referred to herein as “configured to,” “configurable to,” “operable/operative to,” “adapted/adaptable,” “able to,” “conformable/conformed to,” etc. Those skilled in the art will recognize that “configured to” can generally encompass active-state components and/or inactive-state components and/or standby-state components, unless context requires otherwise.
While particular aspects of the present subject matter described herein have been shown and described, it will be apparent to those skilled in the art that, based upon the teachings herein, changes and modifications may be made without departing from the subject matter described herein and its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of the subject matter described herein. It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to claims containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should typically be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations.
In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, typically means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). In those instances where a convention analogous to “at least one of A, B, or C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, or C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). It will be further understood by those within the art that typically a disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms unless context dictates otherwise. For example, the phrase “A or B” will be typically understood to include the possibilities of “A” or “B” or “A and B.”
With respect to the appended claims, those skilled in the art will appreciate that recited operations therein may generally be performed in any order. Also, although various operational flows are presented in a sequence(s), it should be understood that the various operations may be performed in other orders than those which are illustrated, or may be performed concurrently. Examples of such alternate orderings may include overlapping, interleaved, interrupted, reordered, incremental, preparatory, supplemental, simultaneous, reverse, or other variant orderings, unless context dictates otherwise. Furthermore, terms like “responsive to,” “related to,” or other past-tense adjectives are generally not intended to exclude such variants, unless context dictates otherwise.
Those skilled in the art will recognize that it is common within the art to implement devices and/or processes and/or systems, and thereafter use engineering and/or other practices to integrate such implemented devices and/or processes and/or systems into more comprehensive devices and/or processes and/or systems. That is, at least a portion of the devices and/or processes and/or systems described herein can be integrated into other devices and/or processes and/or systems via a reasonable amount of experimentation. Those having skill in the art will recognize that examples of such other devices and/or processes and/or systems might include—as appropriate to context and application—all or part of devices and/or processes and/or systems of (a) an air conveyance (e.g., an airplane, rocket, helicopter, etc.), (b) a ground conveyance (e.g., a car, truck, locomotive, tank, armored personnel carrier, etc.), (c) a building (e.g., a home, warehouse, office, etc.), (d) an appliance (e.g., a refrigerator, a washing machine, a dryer, etc.), (e) a communications system (e.g., a networked system, a telephone system, a Voice over IP system, etc.), (f) a business entity (e.g., an Internet Service Provider (ISP) entity such as Comcast Cable, Qwest, Southwestern Bell, etc.), or (g) a wired/wireless services entity (e.g., Sprint, Cingular, Nextel, etc.), etc.
In certain cases, use of a system or method may occur in a territory even if components are located outside the territory. For example, in a distributed computing context, use of a distributed computing system may occur in a territory even though parts of the system may be located outside of the territory (e.g., relay, server, processor, signal-bearing medium, transmitting computer, receiving computer, etc. located outside the territory).
A sale of a system or method may likewise occur in a territory even if components of the system or method are located and/or used outside the territory. Further, implementation of at least part of a system for performing a method in one territory does not preclude use of the system in another territory.
In summary, numerous benefits have been described which result from employing the concepts described herein. The foregoing description of the one or more embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or limiting to the precise form disclosed. Modifications or variations are possible in light of the above teachings. The one or more embodiments were chosen and described in order to illustrate principles and practical application to thereby enable one of ordinary skill in the art to utilize the various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the claims submitted herewith define the overall scope. Various aspects of the subject matter described herein are set out in the following numbered clauses:
1. A computer-implemented method comprising: receiving, by a processor, a digital bit stream; transforming, by the processor, the digital bit stream to an encoded digital bit stream, wherein the encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof; and providing, by the processor, the encoded digital bit stream to a transmission system for transmission.
2. The computer-implemented method of clause 1, wherein transforming the digital bit stream comprises applying, by the processor, an m-element vector table to the digital bit stream.
3. The computer-implemented method of clause 2, wherein applying the m-element vector table to the digital bit stream comprises performing, by the processor, a table lookup for the digital bit stream.
4. The computer-implemented method of clause 2, wherein applying the m-element vector table to the digital bit stream comprises mapping, by the processor, the m-element table to the digital bit stream according to a mapping function.
5. The computer-implemented method of clause 1, comprising employing, by the processor, the m-element vector table to manage at least one of a bit error rate (BER), realized data throughput, bit energy, or signal range, and any combination thereof, to provide optimized performance.
6. The computer-implemented method of clause 1, comprising managing, by the processor, one or more tasks to enhance data transfer performance to provide an industry-standards agnostic interface to an existing digital communications system.
7. The computer-implemented method of clause 1, comprising, interleaving, by the processor, a data vector and the composite channel utilizing the gateway channel and a gateway mask.
8. The computer-implemented method of clause 1, comprising: generating, by the processor, a plurality of additional bits, wherein the plurality of additional bits are generated by error correcting code; and adding, by the processor, the plurality of additional bits to the encoded digital bit stream.
9. The computer-implemented method of clause 1, comprising implementing, by the processor, at least one of bit position partitioning, table partitioning, or a combination thereof, to generate blended partitioning for the m-element vector table to optimize data transfer.
10. A system comprising: a communications interface; a processor; and a non-transient memory medium operatively coupled to the processor, wherein the memory medium is configured to store a plurality of instructions configured to program the processor to: receive a digital bit stream; transform the digital bit stream to an encoded digital bit stream, wherein the encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof; and provide the encoded digital bit stream to the communications interface for transmission.
11. The system of clause 10, wherein transforming the digital bit stream comprises applying an m-element vector table to the digital bit stream.
12. The system of clause 11, wherein applying the m-element vector table to the digital bit stream comprises performing a table lookup for the digital bit stream.
13. The system of clause 10, wherein the processor is further configured to employ the m-element vector table to manage at least one of a bit error rate (BER), realized data throughput, bit energy, or signal range, and any combination thereof, to provide optimized performance.
14. The system of clause 10, wherein the processor is further configured to manage one or more tasks to enhance data transfer performance to provide an industry-standards agnostic interface to an existing digital communications system.
15. The system of clause 10, wherein the processor is further configured to interleave a data vector and the composite channel utilizing the gateway channel and a gateway mask.
16. The system of clause 10, wherein the processor is further configured to: generate a plurality of additional bits, wherein the plurality of additional bits are generated by error correcting code; and add the plurality of additional bits to the encoded digital bit stream.
17. The system of clause 10, wherein the communications interface comprises a radio frequency (RF) communication system.
18. A non-transitory computer-readable memory medium configured to store instructions thereon that when loaded by a processor cause the processor to: receive a digital bit stream; transform the digital bit stream to an encoded digital bit stream, wherein the encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof; and provide the encoded digital bit stream to the communications interface for transmission.
19. The non-transitory computer-readable memory medium of clause 18, wherein transforming the digital bit stream comprises applying an m-element vector table to the digital bit stream.
20. The non-transitory computer-readable memory medium of clause 19, wherein applying the m-element vector table to the digital bit stream comprises performing a table lookup for the digital bit stream.
21. The non-transitory computer-readable memory medium of clause 18, wherein the instructions stored thereon further cause the processor to employ the m-element vector table to manage at least one of a bit error rate (BER), realized data throughput, bit energy, or signal range, and any combination thereof, to provide optimized performance.

## Claims

1. A computer-implemented method comprising:
receiving, by a processor, a digital bit stream;
interleaving, by the processor, an initial composite channel with a data vector to create a composite channel, wherein the data vector is based on a gateway channel;
transforming, by the processor, the digital bit stream to an encoded digital bit stream, wherein the encoded digital bit stream comprises the gateway channel, the composite channel, and a data channel; and
providing, by the processor, the encoded digital bit stream to a transmission system for transmission.

2. The computer-implemented method of claim 1, wherein transforming the digital bit stream comprises applying, by the processor, an m-element vector table to the digital bit stream.

3. The computer-implemented method of claim 2, wherein applying the m-element vector table to the digital bit stream comprises performing, by the processor, a table lookup for the digital bit stream.

4. The computer-implemented method of claim 2, wherein applying the m-element vector table to the digital bit stream comprises mapping, by the processor, the m-element vector table to the digital bit stream according to a mapping function.

5. The computer-implemented method of claim 2, further comprising employing, by the processor, the m-element vector table to manage at least one of a bit error rate (BER), realized data throughput, bit energy, or signal range.

6. The computer-implemented method of claim 1, further comprising managing, by the processor, one or more tasks to modify data transfer performance in an existing digital communications system.

7. The computer-implemented method of claim 1, wherein the transmission system comprises at least one of a bounded or an unbounded communication system.

8. The computer-implemented method of claim 1, further comprising:
generating, by the processor, a plurality of additional bits, wherein the plurality of additional bits are generated by error correcting code; and
adding, by the processor, the plurality of additional bits to the encoded digital bit stream.

9. The computer-implemented method of claim 1, wherein the transforming, by the processor, further comprises utilizing at least one of bit position partitioning or table partitioning.

10. A system comprising:
a communications interface;
a processor; and
a non-transient memory medium operatively coupled to the processor, wherein the non-transient memory medium is configured to store a plurality of instructions configured to program the processor to:
interleave an initial composite channel with a data vector to create a composite channel, wherein the data vector is based on a gateway channel;
receive a digital bit stream;
transform the digital bit stream to an encoded digital bit stream, wherein the encoded digital bit stream comprises the gateway channel, the composite channel, and a data channel; and
provide the encoded digital bit stream to the communications interface for transmission.

11. The system of claim 10, wherein transforming the digital bit stream comprises applying an m-element vector table to the digital bit stream.

12. The system of claim 11, wherein applying the m-element vector table to the digital bit stream comprises at least one of performing a table lookup for the digital bit stream or mapping the m-element vector table to the digital bit stream according to a mapping function.

13. The system of claim 11, wherein the processor is further configured to employ the m-element vector table to manage at least one of a bit error rate (BER), realized data throughput, bit energy, or signal range.

14. The system of claim 10, wherein the processor is further configured to manage one or more tasks to modify data transfer performance in an existing digital communications system.

15. The system of claim 10, wherein the processor is further configured to implement at least one of bit position partitioning or table partitioning.

16. The system of claim 10, wherein the processor is further configured to:
generate a plurality of additional bits, wherein the plurality of additional bits are generated by error correcting code; and
add the plurality of additional bits to the encoded digital bit stream.

17. The system of claim 10, wherein the communications interface comprises at least one of a bounded or an unbounded communication system.

18. A non-transitory computer-readable memory medium configured to store instructions thereon that when loaded by a processor cause the processor to:
receive a digital bit stream;
interleave an initial composite channel with a data vector to create a composite channel, wherein the data vector is based on a gateway channel;
transform the digital bit stream to an encoded digital bit stream, wherein the encoded digital bit stream comprises the gateway channel, the composite channel, and a data channel; and
provide the encoded digital bit stream to a communications interface for transmission.

19. The non-transitory computer-readable memory medium of claim 18, wherein transforming the digital bit stream comprises applying an m-element vector table to the digital bit stream.

20. The non-transitory computer-readable memory medium of claim 19, wherein applying the m-element vector table to the digital bit stream comprises performing a table lookup for the digital bit stream.

21. The non-transitory computer-readable memory medium of claim 19, wherein the instructions stored thereon further cause the processor to employ the m-element vector table to manage at least one of a bit error rate (BER), realized data throughput, bit energy, or signal range.

22. The non-transitory computer-readable memory medium of claim 19, wherein applying the m-element vector table to the digital bit stream comprises mapping the m-element vector table to the digital bit stream according to a mapping function.

23. The non-transitory computer-readable memory medium of claim 18, wherein the processor is further configured to manage one or more tasks to modify data transfer performance in an existing digital communications system.

24. The non-transitory computer-readable memory medium of claim 18, wherein the processor is further configured to implement at least one of bit position partitioning or table partitioning.

25. The non-transitory computer-readable memory medium of claim 18, wherein the processor is further configured to:
generate a plurality of additional bits, wherein the plurality of additional bits are generated by error correcting code; and
add the plurality of additional bits to the encoded digital bit stream.

26. The non-transitory computer-readable memory medium of claim 18, wherein the communications interface comprises at least one of a bounded or an unbounded communication system.

27. A computer-implemented method comprising:
receiving, by a processor, a digital bit stream;
transforming, by the processor, the digital bit stream to an encoded digital bit stream,

wherein the encoded digital bit stream comprises a gateway channel and a data channel, by applying an m-element vector table to the digital bit stream and using at least one of bit position partitioning or table partitioning; and
providing, by the processor, the encoded digital bit stream to a transmission system for transmission.

28. The computer-implemented method of claim 27, wherein applying the m-element vector table to the digital bit stream comprises performing, by the processor, a table lookup for the digital bit stream.

29. The computer-implemented method of claim 27, wherein applying the m-element vector table to the digital bit stream comprises mapping, by the processor, the m-element vector table to the digital bit stream according to a mapping function.

30. The computer-implemented method of claim 27, further comprising employing, by the processor, the m-element vector table to manage at least one of a bit error rate (BER), realized data throughput, bit energy, or signal range.

31. The computer-implemented method of claim 27, further comprising managing, by the processor, one or more tasks to modify data transfer performance in an existing digital communications system.

32. The computer-implemented method of claim 27, wherein the transmission system comprises at least one of a bounded or an unbounded communication system.

33. The computer-implemented method of claim 27, further comprising:
generating, by the processor, a plurality of additional bits, wherein the plurality of additional bits are generated by error correcting code; and
adding, by the processor, the plurality of additional bits to the encoded digital bit stream.

34. The computer-implemented method of claim 27, wherein the encoded digital bit stream further comprises a composite channel, wherein the composite channel comprises an initial composite channel interleaved with a data vector, wherein the data vector is based on gateway channel.

35. A system comprising:
a communications interface;
a processor; and
a non-transient memory medium operatively coupled to the processor, wherein the non-transient memory medium is configured to store a plurality of instructions configured to program the processor to:
receive a digital bit stream;
transform the digital bit stream to an encoded digital bit stream by applying an m-element vector table to the digital bit stream and using at least one of bit position partitioning or table partitioning, wherein the encoded digital bit stream comprises a data channel and a gateway channel; and
provide the encoded digital bit stream to the communications interface for transmission.

36. The system of claim 35, wherein applying the m-element vector table to the digital bit stream comprises at least one of performing a table lookup for the digital bit stream or mapping the m-element vector table to the digital bit stream according to a mapping function.

37. The system of claim 35, wherein the processor is further configured to employ the m-element vector table to manage at least one of a bit error rate (BER), realized data throughput, bit energy, or signal range.

38. The system of claim 35, wherein the processor is further configured to manage one or more tasks to modify data transfer performance in an existing digital communications system.

39. The system of claim 35, wherein the processor is further configured to interleave a data vector with an initial composite channel to create a composite channel, wherein the data vector is based on the gateway channel, and to include the composite channel in the encoded digital bit stream.

40. The system of claim 35, wherein the processor is further configured to:
generate a plurality of additional bits, wherein the plurality of additional bits are generated by error correcting code; and
add the plurality of additional bits to the encoded digital bit stream.

41. The system of claim 35, wherein the communications interface comprises at least one of a bounded or an unbounded communication system.

42. A non-transitory computer-readable memory medium configured to store instructions thereon that when loaded by a processor cause the processor to:
receive a digital bit stream;
transform the digital bit stream to an encoded digital bit stream by applying an m-element vector table to the digital bit stream and using at least one of bit position partitioning or table partitioning, wherein the encoded digital bit stream comprises a gateway channel and a data channel; and
provide the encoded digital bit stream to a communications interface for transmission.

43. The non-transitory computer-readable memory medium of claim 42, wherein applying the m-element vector table to the digital bit stream comprises performing a table lookup for the digital bit stream.

44. The non-transitory computer-readable memory medium of claim 42, wherein the instructions stored thereon further cause the processor to employ the m-element vector table to manage at least one of a bit error rate (BER), realized data throughput, bit energy, or signal range.

45. The non-transitory computer-readable memory medium of claim 42, wherein applying the m-element vector table to the digital bit stream comprises mapping the m-element vector table to the digital bit stream according to a mapping function.

46. The non-transitory computer-readable memory medium of claim 42, wherein the processor is further configured to manage one or more tasks to modify data transfer performance in an existing digital communications system.

47. The non-transitory computer-readable memory medium of claim 42, wherein the processor is further configured to interleave a data vector with an initial composite channel to generate a composite channel, wherein the data vector is determined in part based on the gateway channel, and to include the composite channel in the encoded digital bit stream.

48. The non-transitory computer-readable memory medium of claim 42, wherein the processor is further configured to:
generate a plurality of additional bits, wherein the plurality of additional bits are generated by error correcting code; and
add the plurality of additional bits to the encoded digital bit stream.

49. The non-transitory computer-readable memory medium of claim 42, wherein the communications interface comprises at least one of a bounded or an unbounded communication system.