# Patent

## Title
Data pattern generation for I/O testing

## Abstract

One feature pertains to a single data pattern being read from a pattern register located within a memory circuit or device. At least one of the plurality of data patterns is derived from the single data pattern, and the plurality of data patterns may be used in a test and sent to an output driver of the memory circuit. The plurality of data patterns may include a first data pattern and a second data pattern. The first data pattern may be derived from the single data pattern. The second data pattern is one of either a true copy of the single data pattern, an inverse copy of the single data pattern, an all zero bits data pattern, or an all one bits data pattern.

## Background
BACKGROUND
1. Field
Various features relate to Data Pattern Generation for Input/Output (I/O) Testing, and in particular to Pattern Generation for (I/O) Testing for a memory device in which the memory is fully usable during the I/O testing.
2. Background
As data-rates continue to rise, off-chip input/output (I/O) characterization becomes increasingly critical. In the field, and even in test environments, I/O characterization is facilitated through built-in self-test (BIST) methods and hardware.
A BIST may serve to test the functionality of a device, characterized the device, and/or ascertain whether problems exist in the device. Sometimes, a BIST may incorrectly indicate a functional failure. For instance, there could be errors in a memory mechanism of a device itself that shows up as errors in the output, corrupting any analysis of the output performance. Traditionally, during some BIST tests, a write operation to the memory may be performed and then the memory is read out and tested to make sure the read/write operations worked correctly. The read and write functions may be correct, but a particular memory cell (e.g., a memory cell under test/use), is bad. Some internal structure along the data path to the memory cell may be bad. For example, a particular BIST test may measure data speed and accuracy across a data line and the BIST test may indicate a failure of the data line when actually the failure may be due to a faulty memory cell.
Therefore, a method and/or device are needed that provide data pattern generation flexibility to enable to run a built-in self-test for a device (e.g., a data acquisition or memory device) without necessarily activating all the internal workings of the device.
SUMMARY
Methods and apparatus are herein described for generating common and complex I/O characterization data patterns using limited circuitry. These methods and/or circuitry may enable, for example, generation of at least some of the following common types of patterns: pulse response measurements, pseudo-random bit sequences, in phase and out of phase crosstalk evaluation, and power distribution network (PDN) resonance excitation.
One feature provides a method operable on a memory circuit to generate a plurality of data patterns from a single data pattern. A first data pattern may be read from a pattern register located within the memory circuit. A plurality of data patterns are then generated, wherein at least one pattern of the plurality of data patterns is derived from the first data pattern. In one example, at least one of the first data pattern and plurality of data patterns may be a binary data pattern. An input/output (I/O) test operation may then be performed using the generated plurality of data patterns. For instance, the plurality of data patterns may be sent to output drivers located within the memory circuit while performing the I/O test operation.
According to one example, the plurality of data patterns may include a true copy of the single data pattern and an inverse copy of the first data pattern. According to another example, the plurality of data patterns may include a true copy of the single data pattern and at least one pattern of all zero bits or all one bits.
In one implementation, the plurality of data patterns may be stored in a plurality of registers coupled proximate to output drivers for the memory circuit. The input/output (I/O) test operation may serve to at least partially characterize a performance of the output drivers using the plurality of data patterns.
The plurality of data patterns may be inserted into data lines extending between a memory cell array and a plurality of output drivers for the memory circuit. However, the memory cell array remains accessible even while the input/output test operation is performed. In one example, the plurality of data patterns may be stored in a plurality of registers separate from the memory cell array.
At least one of the plurality of data patterns may be mapped on a bit by bit basis to output drivers of the memory circuit. A mapping register may be used to map the generated plurality of data patterns to a plurality of data lines. Additionally, or alternatively, a shift-register may be used to manipulate and randomize the first data pattern.
In some implementations, the pattern register within the memory circuit may be a read-only register with the first data pattern pre-stored in the pattern register. In another example, the pattern register may be defined from a plurality of memory cells within a memory cell array located within the memory circuit.
In one implementation, a memory circuit is provided comprising a memory cell array, a plurality of output drivers coupled to the memory cell array via a plurality of data lines, and a built-in self-test circuit operationally coupled to the plurality of data lines. The built-in self-test circuit may be configured to: (a) read a first data pattern from a pattern register located within the memory circuit, (b) generate a plurality of data patterns, wherein at least one pattern of the plurality of data patterns is derived from the first data pattern; and/or (c) perform an input/output (I/O) test operation using the generated plurality of data patterns. The memory circuit may perform one or more of the functions of the method described above.
The speed of accessing the pattern register, which is physically located proximate to the data line, is much faster than the speed of accessing a data pattern in the memory of the memory cell array, and therefore, a more efficient I/O testing is hereby achieved in comparison to when the data pattern is stored in the memory of a memory array. Additionally, higher I/O speeds may be tested than otherwise possible with traditional approaches since the speed of accessing the data pattern stored in the memory of the memory array is one limiting factor in performing I/O testing by a BIST in traditional approaches. However, with the herein described methods and apparatus, that limiting factor is eliminated. Additionally, the data pattern is coming from the memory side of the memory circuitry, as opposed to from the bus side of the memory circuitry, which further facilitates high-speed I/O testing.



BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 illustrates an exemplary electronic device that includes a memory device or circuit.
FIG. 2 illustrates a block diagram of a register data line circuit including a plurality of pattern registers connected to a data line between a first device and a second device.
FIG. 3 illustrates a block diagram of a register data line circuit wherein a plurality of pattern registers are connected to a plurality of exemplary data lines via a plurality of mapping registers.
FIG. 4 illustrates a block diagram of a circuit including two 8-bit registers, one 8-bit pattern register and one 8-bit mapping register for a total of 16 bits.
FIG. 5 illustrates three 8-bit registers, one 8-bit pattern register and two 8-bit mapping registers for a total of 24 bits.
FIG. 6 illustrates a block diagram of a circuit including a linear-feedback-shift-register pattern register (LFSR) coupled to a mapping register.
FIG. 7 illustrates a block diagram of a circuit including two 8-bit registers, one 8-bit pattern register and one 8-bit mapping register for a total of 16 bits.
FIG. 8 illustrates a block diagram of a memory circuit including a built-in self-test (BIST) circuit that uses a pattern register and mapping registers to test a plurality of output drivers.
FIG. 9 illustrates an exemplary implementation of the memory device of FIG. 8 and a built-in self-test (BIST) circuit that uses a pattern register and mapping registers to test a plurality of output drivers.
FIG. 10 illustrates a block diagram of a first alternative memory circuit including a built-in self-test (BIST) circuit that uses one or more test patterns loaded in a memory device to test a plurality of output drivers.
FIG. 11 illustrates a block diagram of a second alternative memory circuit including a built-in self-test (BIST) circuit that uses one or more test patterns loaded in a memory device to test a plurality of output drivers.
FIG. 12 illustrates an exemplary block diagram of a hardware implementation for an electronic device that includes a RAM array.
FIG. 13 illustrates a method operational within a memory circuit including a memory cell array, at least one data line, and at least one output driver for I/O output.
FIG. 14 illustrates a method for implementing built-in self-test operations within a memory circuit.



DETAILED DESCRIPTION
In the following description, specific details are given to provide a thorough understanding of the various aspects of the disclosure. However, it will be understood by one of ordinary skill in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail in order not to obscure the aspects of the disclosure.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation.
Overview
Methods and apparatuses are described herein that implement data pattern generation for I/O testing. A single data pattern is read from a pattern register, and a pair of data patterns is generated, wherein at least one of the pair is derived from the read single data pattern, and the pair of data patterns may be used in a test. The pairs may be generated by using a true copy and an inverse copy making a first pair, all zeroes (i.e., a nothing copy) and a true copy making a second pair, all ones and a true copy making a third pair, a nothing copy and an inverse copy making a fourth pair, all ones and an inverse copy making a fifth pair, wherein the true and inverse copies are in reference to the single data pattern.
Exemplary Data Pattern Generation for I/O Testing and Methods for Implementing the Same
Heretofore, the characterization(s) of I/O properties of electrical devices coupled to a memory were limited by the speed of the memory itself. In other words, one or more data patterns would be stored in a memory and then retrieved for use in the testing or characterization of devices coupled to the output driver of the memory. However, the data pattern retrieval from the memory was the bottleneck in the I/O testing. Alternatively, the one or more data patterns capable of being used in BISTs were stored remote from the memory array and across the main bus and on the controller side of the main bus. That also caused a delay and potential I/O-related errors in data pattern retrieval. Therefore described herein are structure(s) (i.e., apparatus) and methods wherein pattern registers are positioned on the memory side of the bus and physically proximate to at least one output driver of the memory array.
FIG. 1 illustrates an exemplary electronic device that includes a memory device or circuit. In various examples, the electronic device 100 may be a mobile phone, smartphone, tablet, portable computer, and/or any other electronic device having circuitry. The device 100 includes a main bus, a system bus, or bus 102 separating or defining a memory side 104 of the device 100 and a non-memory side 106 (i.e., a bus side of device 100) of the device 100. The device 100 includes a memory device 108 including a matrix of memory cells 110, which in one embodiment is dynamic random-access memory (DRAM) memory, and an associated output driver 112. The output driver 112 is coupled to the system bus 102 to which other device circuits 120a, 120b, 120c, and 120d may also be coupled. An input driver 122 is also coupled to the bus 102 and to the matrix of memory cells 100. Typical other device circuitry 120a and 120b includes a camera, a speaker, a microphone, and/or a display object, etc. Notably, a data pattern register 124 is positioned on the memory side 104 of the device, as opposed to being on the bus side 106. The proximity of the data pattern register 124 to the output driver 112 enables a relatively fast initialization of any desired BIST I/O testing by speeding up the amount of time consumed in providing the output driver 112 with a pair of data patterns as described herein. In other words, what has been known is to provide the output driver 112 with a data pattern from either the bus side 106 of the device or from the memory cells 110 themselves. However, each of these implementations cause delays and unrelated errors, which are eliminated by sending one or more data patterns to the output driver 112 from the memory side 104, but without using any of the memory cells of the matrix or memory array 110. Therefore, no reading of the memory array 110 is necessary, resulting in a much quicker initiation of the I/O testing.
FIG. 2 illustrates a block diagram of a register data line circuit 200 including a plurality of pattern registers 202a, 202b, 202c, and 202d coupled to a data line 204 (Data line Q) between a first device 206 and a second device 208. In one embodiment, the data line 204 is an output or read data line. A distance 210 (i.e., “D” in FIG. 2) exists between pattern registers 202 and the read data line 204. In one example, the first device 206 may be memory cell array while the second device 208 may be output driver for a memory circuit. In various exemplary implementations, the distance D 210 may between 10 millimeters and 50 mm, between 1 mm and 10 mm, less than 10 mm, less 5 mm, less than 1 mm, less than 300 nm, less than 200 nm, and/or less than 100 nm. Ideally with a via size defined as two lambda, the distance is between two to four lambda. In other words, no matter what the process size for the manufacturing of an integrated circuit (IC) is (e.g., 20 nm or 65 nm process size), the smallest sized elements on the chip are typically vias and they are deemed to be two lambda by two lambda square. Therefore, any element distanced from between two and four lambda away from another element on the chip is very close to the other element. It is desirable that the pattern registers 202 be relatively close to the output/read data line 204 (e.g., within the same semiconductor die, within the same chip, within the same memory module, etc.). Alternatively, the distance between a pattern register 202 and the data line 204 may be twenty lambdas or less.
When the first device 206 is a memory cell array, accessing any of the pattern registers 202a, 202b, 202c, and 202d does not affect access to any of the memory cells of the first device 206. In other words, a device accessing the memory cell array of the first device 206 may have full access to the entire memory cell array while the pattern register is being read. Therefore, a controller (e.g., a processing circuit) controlling the first device 206 and all the pattern registers 202 and the second device 208 can access a data pattern from one or more pattern registers 202 and send it to an output driver (e.g., second device 208) to test the output driver, and/or any peripheral devices connected to the memory cell array (e.g., first device 206). In one example, the pattern register reading and associated I/O testing (i.e., characterization) is performed without using any of the memory in the memory cell array (e.g., in the first device 206).
Also in some examples, a mapping register is located between the pattern register 202 and the data line 204, and the distances recited herein may be between the pattern register 202 and the mapping register and also the distance between the mapping register and the data line 204. Therefore, in those cases the distance between the pattern register 202 and the read data line 204 may be twice the dimensions recited herein. In one embodiment, the circuit 200 facilitates trying to characterize the maximum performance of a device (e.g., memory device or circuit) during a built-in-self-test (BIST). Traditionally, during some BISTs, a write to the memory is performed and then the memory is read out and tested to make sure the read/write operations worked correctly. However, there could be errors in the memory mechanism itself that show up as errors in the output corrupting any analysis of the output performance. In other words, the read and write functions are correct, but a particular memory cell or element in the data path is bad. Put differently, some internal structure to the memory cell is bad. Herein described are methods and apparatus that provide data pattern generation flexibility in a way to enable a user to run a memory device or some other device (e.g., a data acquisition device) BIST without activating all the internal workings of the device in case some of the internal workings are faulty.
Toward that end, FIG. 2 illustrates a series of pattern registers 202a, 202b, 202c, and 202d located proximate the output/read data line path 204. The multi-bit pattern registers 202a, 202b, 202c, and 202d may each store a single data pattern. The pattern registers 202a, 202b, 202c, and 202d can be write-able or read-only with hard coded values. As illustrated in FIG. 3 a multi-bit mapping register 322a stores values used to map true or complement versions of data held in a plurality of pattern registers 302a, 302b, 302c, and 302d to one or more of a plurality of DQ-specific output/read data line paths 304a, 304b, and 304c. A plurality of mapping registers 322a and 322b may be utilized to map specific pattern sequences to different data channels. Although illustrated in FIG. 3 as four pattern registers 302a, 302b, 302c, and 302d, two mapping registers 322a and b, and three data lines 304a and 304b, there may be any number of pattern registers, mapping registers, and/or data lines. The specific pattern sequences may be utilized in performing one or more BISTs useful for characterization of circuit elements such as devices coupled to an I/O input or output driver. More specifically, specific pattern sequences can be used to make pulse response measurements, as pseudo-random bit sequences, to do in phase and out of phase crosstalk evaluation, and for power distribution network (PDN) resonance excitation. For example, crosstalk can be evaluated in terms of in and out of phase aggressors versus victims.
Additionally, the BIST patterns can be used to train. In other words, the circuits described herein are part of a much larger device such a memory device or some other device (e.g., a cell phone, or a data acquisition device, such as a camera), and the BIST returns an evaluation (e.g., a crosstalk evaluation) that can be used by the larger device to improve operations therein. The BIST may be altered in cases where training took place. For example, an initial BIST could be generally mild, but after training and reconfiguring based upon the training, another BIST may be more robust than the initial BIST was. Accordingly, this is self-adaptive and/or self-correcting and/or self-healing. The more robust BIST may have higher expectations than the initial BIST because of improvements achieved by the training, and can trigger an error flag, or return to being the initial BIST and trigger a retraining possibly because of detrimental process drift occurring after the initial training. The BIST may be part of a power-on-self-test (POST) BIST, as opposed to a POST which is not built-in but initiated by or assisted by another device. In a multi-device environment, this BIST can be part of a larger BIST engine. In addition, the device that contains the circuits illustrated and described herein may not be in control of the data bus that the device is connected to (or on an interface with), the device can be a slave device or a master device.
FIG. 3 illustrates a block diagram of a register data line circuit 300 wherein a plurality of pattern registers 302a, 302b, 302c, and 302d are connected to a plurality of exemplary data lines 304a, 304b, and 304c. The pattern registers 302a, 302b, 302c, and 302d may be flip flop or latch registers and can be one bit, one byte, or any desired size. As illustrated in FIG. 3, when each pattern register 302a, 302b, 302c, and 302d is single bit, 24 different values can be sent to the output/read data lines 304a, 304b, and 304c. The pattern registers 302a, 302b, 302c, and 302d can be write-able or read-only with hard coded values. One or more multi-bit mapping registers 322a and 322b stores values used to map the data held in the pattern registers 302a, 302b, 302c, and 302d to one or more of the DQ-specific read data line paths 304a, 304b, and 304c. The plurality of mapping registers 322a and 322b may be utilized to map specific pattern sequences to different data channels. The specific pattern sequences can be used to do the BIST or other tests. More specifically, specific pattern sequences can be used to make pulse response measurements, as pseudo-random bit sequences, and to do in phase and out of phase crosstalk evaluation.
As described below in more detail having at least one mapping register increases the variability of the data supplied to the data lines 304a, 304b, and 304c by sending true copies of patterns within each pattern register 302a, 302b, 302c, and 302d as well as complementary copies (i.e., the logical complement) of the patterns in the pattern registers 302a, 302b, 302c, and 302d. For example, a pattern generator block diagram 300 may use only two pattern registers 302a and 302b which hold data called DATA1 (e.g., in a first register 302a) and hold data called DATA2 (e.g., in a second register 302b). One or more of the mapping registers 322a and 322b can send to the data line a zero or nothing (first value), or can combine DATA1 and DATA2 and send that combined value (second value), or can combine the DATA1's complement (DATA1) with DATA2 (third value), or can combine the DATA2's complement (DATA2) with DATA1 (fourth value), and lastly, can combine both DATA 1's and DATA2's complement (fifth value). Each mapping register 322 may include an interface that couples to the pattern registers 302a and 302b and to one or more of the data lines 304a, 304b, 304c, and 304d. The interface enables the mapping register to read the pattern registers and to write to the data lines. The interface can be internal or external to the mapping register 322. In one feature, the mapping register interface can write to the pattern registers 302a and 302b. Alternatively, other devices can write to the pattern registers or the pattern registers can be implemented as fixed and read-only.
In one exemplary embodiment, only one pattern register (e.g., a “PRX”) 302a is available with a plurality of mapping registers 322a and 322b. The PRX holds one bit or byte and the two mapping registers can alter the data before mapping the data. For example, using an eight bit pattern register (e.g., 302a) the data stored can be sent to any of the data lines 304a, 304b, 304c as a true copy by mapping register 1 (e.g., register 322a) and the complement of the data in the PRX can be sent by mapping register 2 (e.g., register 322b) to one or more of the data lines 304a, 304b, and 304c. Any and all of the various outputs described herein may be used in built-in-self-tests.
FIG. 4 illustrates a block diagram a circuit 400 including two 8-bit registers (i.e., one 8-bit pattern register 402 and one 8-bit mapping register 422) for a total of 16 bits. Each bit of the mapping register (MR) 422 corresponds to a data line (DQx), and the contents of each bit determine if a true copy of the pattern register (PR) is being sent to the respective data line or if a complement copy is being sent. In the illustrated example, a zero (0) indicates the complement is being mapped while a one (1) indicates a true copy is being mapped. In alternative implementations, those roles may be reversed. An alternative circuit 401, e.g., using an inverse pattern may serve to map to one or more other data lines (e.g., DQ5, etc.). In one example, each register in the mapping register 422 directs the bits from the pattern registers to specific output drivers or data lines 304a, 304b, 304c coupled to such output drivers. As illustrated, the “mapping” first and second circuits 400 and 401 (e.g., multiplexers or switches) may select between two inputs (e.g., pattern register bits or inverse pattern register bits) as indicated by the value of each mapping register (MR).
FIG. 5 illustrates a block diagram a 24-bit extension of FIG. 4. More specifically, FIG. 5 conceptually illustrates three 8-bit registers (e.g., one 8-bit pattern register 502, and two 8-bit mapping registers A 522 and B 524) for a total of 24 bits. Each bit of the mapping registers A 522 and B 524 corresponds to a data line (DQx), and the contents of each individual bit register may determine if a true copy of the pattern register is being sent to the respective data line or if a complement/inverse copy is being sent.
In the illustrated example, a zero (0) bit in an individual bit register of a mapping register may indicate the complement (of the pattern register) is sent (e.g., input “0” of the multiplexer 404/406) while a one (1) may indicate a true copy (of the pattern register) is sent (e.g., input “1” of the multiplexer 404/406). Note that those roles can be reversed. In one example, the individual bit registers of the pattern register 502 may be mapped according to the individual bit registers of the first mapping register A 522 to data lines DQ0-DQ3 and DQ8-DQ11 while the complement/inverse of the individual bit registers of the pattern register 502 may be mapped according to the individual bit registers of the second mapping B 524 to data lines DQ4-DQ7 and DQ12-DQ15.
FIG. 6 illustrates a block diagram a circuit 600 including a linear-feedback-shift-register pattern register (LFSR) 602 coupled to a mapping register 622. The LFSR 602 is a shift register whose input bit is a linear function of its previous state. The LFSR 602 can send random data to all of the data lines (e.g., DQs), the LSFR 602 can send shifted data, so each bit is shifted one place. For example, the LSFR 602 sends data to the first data line DQ0, the LSFR 602 shifts the data one place and sends the single shifted data to the second data line DQ1 and so forth for all eight lines when the pattern register is an 8-bit LSFR pattern register. The LFSR 8 bit register 602, can have 28 combinations of patterns so there are 63 bit patterns although the pattern register is only 8 bits.
Moreover, in addition to the LSFR shifting the data, the LSFR can be “seeded” differently (i.e., re-seeded either self re-seeded or by another device or element (physical or logical)). The different logic connectivity between the shift register stages can produce distinct, yet still pseudo-random data streams. Upon reading an end bit of the LFSR multi-bit register, a wraparound can be done to start a next read at the other end of the register. The mapping register 622 again uses a 1 for mapping a true copy of the pattern register's content and a 0 for mapping an inverse copy (complement) of the pattern register's content. In addition, other embodiments use other sizes of LFSR 602, such as a 4-bit register that uses LFSR to have 24−1 patterns. The output values are used in built-in-self-tests.
FIG. 7 illustrates a block diagram a circuit 700 including two 8-bit registers (e.g., one 8-bit pattern register 702 and one 8-bit mapping register 722) for a total of 16 bits. Instead of using the true and inverse as illustrated in FIG. 4, FIG. 7 illustrates combining logic gates and logic levels with multiplexing to provide a wider variety of output combinations. For example, a first circuit 700 includes a first multiplexer or switch 704 having a first input (“0”) coupled to ground (GND) or logical zero (0) and a second input (“1”) coupled to the pattern register (PR). Similarly, a second circuit 701 may include a second multiplexer or switch 706 having a first input (“0”) coupled to voltage source VDD or logical one (1) and a second input (“1”) coupled to the pattern register (PR). In one example, the first and second circuits 700 and 701 may be the same circuit, with a switch prior to the first input (“0”) to selectively couple first input (“0”) to either GND (e.g., logical zero) or VDD (e.g., logical one). The use of a pattern register 702, mapping register 722, and mapping circuit 700 or 701 facilitates the ability to quickly write 8-bits to an 8-bit register, a zero copy (i.e., all zeroes), a true copy, an inverse copy, and all ones, and all permutations thereof. Put differently, a single data pattern (e.g., pattern register 702) can be utilized to create distinct pairs of data patterns.
As illustrated, the “mapping” circuits 700 and 701 may include multi-input multiplexers or switches 704 and 706, respectively. The mapping register (MR) may serve to select between two or more inputs (e.g., pattern register bits or inverse pattern register bits) as indicated by the value of each register of the mapping register (MR). For instance, if a first bit register of the mapping register is zero (0), then the first (“0”) input line to the multiplexers or switches 704 and 706 may be selected. Similarly, if a second bit register of the mapping register 722 is one (1), then the second (“1”) input line to the multiplexers or switches 704 and 706 may be selected. Each individual bit register may be configured to output to a particular data line (e.g., DQ0, DQ1, . . . DQ7) or corresponding output driver.
According to various possible examples, a true copy of the pattern and an inverse copy of the pattern make a first pair, all zeroes (a nothing copy) and a true copy make a second pair, all ones and a true copy make a third pair, a nothing copy and an inverse copy make a fourth pair, all ones and an inverse copy make a fifth pair, and lastly, all ones and a nothing copy form a sixth pair. All of these pairs can be used in BISTs. However, because the sixth pair does not utilize the single data pattern at all, there are only five pairs actually derived from the single data pattern. Although a nothing copy and an all ones copy are really not copies per se, rather they are versions or variations, however, these versions of the data with all ones or all zeroes are herewith termed copies for ease of understanding and readability. Alternatively viewed, a corrupted or changed copy is still a copy. Moreover, in the 8-bit example, all eight bits being zeroes or ones qualifies as a copy (e.g., as being a changed or altered copy). Put differently, multiplexing can be used to output something other than the “true” and “complements” of the pattern. Additionally, logic gates (not shown) may also be added to further manipulate the output pattern.
FIG. 8 illustrates a block diagram of a memory circuit including a built-in self-test (BIST) circuit that uses a pattern register and mapping registers to test a plurality of output drivers. The memory circuit 800 may include a plurality of input drivers 802 coupled to a plurality of memory cell arrays 806, and a plurality of output drivers 804 coupled to the plurality of memory cell arrays 806. A BIST circuit 808 includes an output driver testing circuit 810, one or more pattern registers 812, and one or more mapping registers 814. The BIST circuit 808 is coupled to the output drivers 812. The input drivers 802 and output drivers 812 may be coupled to a bus through which data is written into and read from the memory cell arrays 806. The memory circuit 800 may be integrated into such devices as a cellular phone, a display circuit, a camera device, an audio device, and/or a transmitter/receiver device.
The output driver testing circuit 810 may obtain/read a first pattern (e.g., of fixed length binary pattern) from the pattern registers 812 and may send the first pattern to one or more mapping registers 814 that then map one or more patterns to the output drivers 804. The mapping registers 814 may send a true copy of the first pattern from the pattern register 812, an inverse copy of the first pattern read from a pattern register 812, or altered copy such as a bit shifted of the pattern read from the pattern register 812. The circuitry and/or logic (e.g., within the BIST circuit 808 and/or output driver testing circuit 810) may then use the patterns provided by the mapping register(s) 814 to test (i.e., characterize) the output drivers 804 and/or devices coupled to the output drivers 804. Additionally, the BIST circuit in at least one embodiment is able to alter at least one parameter involving the memory cell arrays 806 and/or output drivers 804 in response to the results of the characterization of an I/O component (e.g., the output drivers 804 and/or any device coupled to an output driver 804). In various implementations, the BIST circuit 808, the pattern register 812 and mapping register(s) 814 may implement one or more of the features illustrated in FIGS. 2, 3, 4, 5, 6, and/or 7.
FIG. 9 illustrates an exemplary implementation of the memory cell arrays of FIG. 8 and a built-in self-test (BIST) circuit that uses a pattern register and mapping registers to test a plurality of output drivers. In this example, the memory cell arrays 806 may include a plurality of memory banks 902 and 904. Each memory bank 902 and 904 may include a plurality of bit cells 906 and 908 coupled to input/output drivers 910 and 912. The input/output drivers 910 and 912 may be coupled to device output drivers 804 via an output bus 916. The BIST circuit 808, comprising the output driver testing circuit 810, pattern register(s) 812, and/or mapping register(s) 814, may be coupled to the output bus 816 between the input/output drivers 910, 912 and the device output drivers 804.
FIG. 10 illustrates a block diagram of a first alternative memory circuit including a built-in self-test (BIST) circuit that uses one or more test patterns loaded in the memory circuit to test a plurality of output drivers. The memory circuit 1000 may include a plurality of input drivers 1002 coupled to a plurality of memory cell arrays 1006. A plurality of output drivers 1004 may be selectively coupled to the plurality of memory cell arrays 1006. A BIST circuit 1008 includes an output driver testing circuit 1010. In this example, an output bus 1016 between the memory cell arrays 1006 and output drivers 1004 may include a switch 1018 that may be selectively switched so that output from the memory cell arrays 1006 goes either directly to the output drivers 1004 or through the BIST circuit 1008. In this example, the BIST circuit 1008 may enable or disable the switch 1018 to obtain (e.g., read) one or more test patterns 1012 stored in the memory cell arrays 1006 via output bus 1016. The output driver testing circuit 1010 may then use the obtained test pattern(s) 1012 to test the output driver performance. Once finished, the BIST circuit 1008 may enable or disable the switch 1018 to allow the memory cell arrays to send output directly to the output drivers 1004. Note that the test patterns 1012 may be loaded from an internal source or from an external source (e.g., loaded by an external loader). The test pattern 1012 may be removed or overwritten during normal operation of the memory circuit 1006. In one example, the test pattern(s) 1012 may be used directly as the output pattern or output value sent to the output drivers 1004 over the output bus 1016. Alternatively, one or more mapping registers 1014 may map the test pattern(s) 1012 to generate the output pattern or output value.
FIG. 11 illustrates a block diagram of a second alternative memory circuit including a built-in self-test (BIST) circuit that uses one or more test patterns loaded in a memory circuit/device to test a plurality of output drivers. The memory circuit 1100 may include a plurality of input drivers 1102 coupled to a plurality of memory cell arrays 1106. A plurality of output drivers 1104 may be selectively coupled to the plurality of memory cell arrays 1106. A BIST circuit 1108 includes an output driver testing circuit 1110. In this example, an output bus 1116 extends between the memory cell arrays 1106 and output drivers 1104. In this example, a dedicated bus 1118 may extend between the BIST circuit 1108 and the memory cell arrays 1106 to allow the BIST circuit 1108 to obtain (e.g., read) one or more test patterns 1112 stored in the memory cell arrays 1106. The output driver testing circuit 1110 may then use the obtained test pattern(s) 1112 to test the output driver 1104 performance. Note that the test patterns 1112 may be loaded from an internal source or from an external source (e.g., loaded by an external loader). The test pattern 1112 may be removed or overwritten during normal operation of the memory cell arrays 1106. The test pattern 1112 may be removed or overwritten during normal operation of the memory circuit 1106. In one example, the test pattern(s) 1112 may be used directly as the output pattern or output value sent to the output drivers 1104 over the output bus 1116. Alternatively, one or more mapping registers 1114 may map the test pattern(s) 1112 to generate the output pattern or output value.
While the examples in FIGS. 8 and 9 may serve to characterize the output driver performance for a device, the examples in FIGS. 10 and 11 may serve to characterize data path performance. Additionally, the memory circuits of FIGS. 8, 9, 10, and 11 allow an external host system to access (e.g., write) the memory cell arrays 806, 1006, 1106 even while a BIST test operation is occurring. For instance, since the BIST test operation may be inserted directly onto the output data lines, the input drivers and the memory cell arrays may remain accessible by the external host system. In various examples, the BIST circuit 810, 1008, and 1108 may perform its input/output test operations independent of operations performed by a memory controller that writes or reads data from the memory cell array.
Exemplary Electronic Device
FIG. 12 illustrates an exemplary block diagram of a hardware implementation for a built-in self-test circuit 1203 within an electronic device 1200 that includes a memory cell array 1202. The electronic device 1200 may be a mobile phone, smartphone, tablet, portable computer, system-on-a-chip, multi-layer chip, memory module, memory chip, and or any other electronic device having circuitry. The electronic device 1200 may include the memory cell array 1202 coupled to an output/read data bus 1205, the built-in self-test circuit 1203 also coupled to the data bus 1205 and/or the memory cell array 1202, and/or I/O drivers comprising an input driver 1216 and output driver 1218 coupled to a host memory bus 1207. In one example, the output driver 1218 may be an off-chip driver, which provides data output off the chip or module on which the memory cell array resides. The output driver 1218 may be distinct from drivers located within memory cell arrays.
The built-in self-test circuit 1203 may include a processing circuit 1206, a storage device 1210, and/or one or more registers 1212 and 1214. The storage device 1210 may include output driver test instructions 1222 and data path test instructions 1224 that allow the processing circuit to characterize the output drive 1218 and/or the data path from the memory cell array 1202 to the host memory bus 1207, respectively.
The processing circuit 1206 may include a pattern generator circuit/module 1226 that serves to generate data patterns as described herein and can store the data patterns within pattern registers 1212. In some implementations, the pattern generator circuit/module 1226 may be adapted to dynamically generate a fixed or random pattern on boot-up of a host system or upon request from the BIST circuit 1203. Alternatively, in other implementations, the pattern register(s) 1212 may be pre-loaded with a pattern (e.g., read-only registers) and the pattern generator circuit/module 1226 may be omitted.
The processing circuit 1206 may also include a pattern mapping circuit/module that serves to map the data pattern from the pattern registers 1212. In some implementations, the pattern mapping circuit/module 1228 may be adapted to dynamically generate a fixed or random mapping pattern on boot-up of a host system or upon request from the BIST circuit 1203. Alternatively, in other implementations, the mapping register(s) 1212 may be pre-loaded with a mapping pattern (e.g., read-only registers) and the mapping generator circuit/module 1226 may be omitted. The mapping register(s) 1214 may serve to map a pattern (or part thereof) from the pattern register(s) 1212 to generate an output pattern or output value for a one or more data lines. Such an output pattern or output value may be sent sequentially or in parallel over the one or more data lines.
In some examples, the BIST circuit 1203 may be part of, or integrated with, a local memory controller (e.g., on the same chip) that controls operations of the memory cell array 1202 by controlling currents and voltages applied to individual memory cells, by reading and writing to the memory cells and, in general, managing the memory cells and all data flows into and out of the memory cell array 1202. The processing circuit 1206 may be programmable and may be configured to (e.g., programmed to) do the functions recited herein.
The processing circuit 1206 may execute one or more of a plurality of routines to read a pattern from a pattern register 1212 and then utilize the mapping registers 1214 to calculate one or more data patterns from a single pattern read. This one or more data patterns, wherein at least one data pattern is derived from the single pattern read or is an all zeros or all ones data pattern, is then sent to the output driver 1218.
Artificial intelligence based systems (e.g., explicitly and/or implicitly trained classifiers) can be employed in connection with performing inference and/or probabilistic determinations and/or statistical-based determinations as described herein. The built-in self-test circuit may employ various inference schemes and/or techniques in connection with the present approach. As used herein, the term “inference” refers generally to the process of reasoning about or inferring states of the system, environment, and/or user from a set of observations as captured via events and/or data. Inference can be employed to identify a specific context or action, or can generate a probability distribution over states, for example. The inference can be probabilistic, that is, the computation of a probability distribution over states of interest based on a consideration of data and events. Inference can also refer to techniques employed for composing higher-level events from a set of events and/or data. Such inference results in the construction of new events or actions from a set of observed events and/or stored event data, whether or not the events are correlated in close temporal proximity, and whether the events and data come from one or several event and data sources. Various classification schemes and/or systems (e.g., support vector machines, neural networks, expert systems, Bayesian belief networks, fuzzy logic, data fusion engines, etc.) can be employed in connection with performing automatic and/or inferred action in connection with the features described herein.
For example, the BIST storage component 1210 may include a specific BIST for a cold start on power up, another BIST for after a certain error condition, another BIST for after a different error condition, and many BISTs for many different temperature conditions. In addition, based upon measured current conditions and stored past prior conditions and past prior BIST results, the BIST circuit 1203 may make several inferences and select among the many currently available BISTs in an attempt to select an optimal BIST for that point in time, and in the current set of conditions (i.e., current environment, such as, for example, current temperature, time since boot up, results of last BIST, and the like).
An input interface 1219 may also be coupled to the processing circuit 1206 and/or BIST circuit 1203 to provide inputs to the processing circuit 1206 from a host system. Many of the components illustrated in FIG. 12, if not all, may be a combination of software and hardware.
Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside on a computer-readable storage medium within memory cell array 1202, processing circuit 1206, and/or BIST storage device 1210. The computer-readable storage medium may be a non-transitory computer-readable storage medium. A non-transitory computer-readable storage medium includes, by way of example, a magnetic storage device (e.g., hard disk, floppy disk, magnetic strip), an optical disk (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a smart card, a flash memory device (e.g., a card, a stick, or a key drive), a random access memory (RAM), a read only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing software and/or instructions that may be accessed and read by a computer. The computer-readable storage medium may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. The computer-readable storage medium may be embodied in a computer program product.
Moreover, a storage medium may represent one or more devices for storing data, including read-only memory (ROM), random access memory (RAM), magnetic disk storage mediums, optical storage mediums, flash memory devices and/or other machine-readable mediums and, processor-readable mediums, and/or computer-readable mediums for storing information. The terms “machine-readable medium”, “computer-readable medium”, and/or “processor-readable medium” may include, but are not limited to non-transitory mediums such as portable or fixed storage devices, optical storage devices, and various other mediums capable of storing, containing or carrying instruction(s) and/or data. Thus, the various methods described herein may be fully or partially implemented by instructions and/or data that may be stored in a “machine-readable medium”, “computer-readable medium”, and/or “processor-readable medium” and executed by one or more processors, machines, and/or devices.
Herein described are apparatus and methods for storing a single data pattern in a pattern register physically located very close to a data line (e.g. a write data line), wherein the data pattern is read and a second data pattern is generated (e.g., derived from the read data pattern or not), and then the two data patterns are sent to an output driver for I/O testing of I/O capabilities of a memory array. Because the data pattern is not contained in memory of the memory array, all of the memory of the memory array is available for normal use. Additionally, the speed of accessing the pattern register physically located close to the data line is much faster than the speed of accessing a data pattern in the memory of the memory array, and therefore, a more efficient I/O testing is hereby achieved in comparison when the data pattern is stored in the memory of the memory array. Additionally, higher I/O speeds may be tested than heretofore. Because heretofore the speed of accessing the data pattern stored in the memory of the memory array was the limiting factor in performing an I/O testing such as a BIST. However, now with the present approach, that limiting factor is eliminated. Additionally, the data pattern is coming from the memory side, as opposed to from the bus side which further facilitates high-speed I/O testing.
Exemplary BIST Methods
FIG. 13 illustrates a method 1300 operational with a memory circuit including a memory cell array, at least one data line, and at least one output driver for I/O output. The method 1300 may include locating a pattern register proximate to a data line before reaching the output driver for the memory circuit 1302. The pattern register may be hard coded and not writable or it may be writable wherein a single data pattern is written to it. When it is desirable to perform an I/O testing, either user initiated or software initiated based upon certain events happening or in accordance with a boot-up process for a host system, a first pattern is read from the pattern register 1304. After the first pattern is read, a second pattern is generated 1306. The second pattern may be derived from the first pattern, for example, it may be an inverse (i.e. the complement), or may be a shifted version, or the second pattern may somehow otherwise derived, or the second pattern may be independent, for example, it may be all zeroes or all ones. However, in all embodiments, a plurality of distinct data patterns are obtained. The plurality of data patterns may be sent to the output driver prior to or while performing an I/O test operation 1308.
FIG. 14 illustrates a method 1400 for implementing built-in self-test operations within a memory circuit. The method 1400 may include reading a first data pattern from a pattern register located on a memory side of a bus of the device 1402. A plurality of data patterns may be generated, wherein at least one pattern of the pair of data patterns is derived from the first data pattern 1404. A BIST operation may be performed using the generated plurality of data patterns 1406. A true copy of the single data pattern and an inverse copy of the single data pattern may be used to obtain the plurality of data patterns 1408. A true copy of the single data pattern and a nothing copy may be used to obtain the plurality of data patterns 1410. Lastly, a true copy of the single data pattern and an all ones copy may be used to obtain the plurality of data patterns 1412. Regardless of how the distinct plurality of data patterns are generated, the data pattern register, the output driver, and the circuitry generating the plurality of data patterns are all on the memory device (e.g., proximate the memory cell arrays, before the memory device output drivers), as opposed to the external to the memory device (e.g., after the output drivers). This physical proximity facilitates a relatively quick reading of the data pattern register, a relatively quick generation of the second pattern to form a plurality (e.g., pair), and/or a relatively quick bit shifting, or other convolution of the original pattern to generate a derived pattern, and lastly a relatively quick providing of the plurality of data patterns to the output driver. Collectively, all these improvements in process speed provide for performing I/O testing that is quicker, more responsible at higher speeds than other methods, wherein test patterns are either stored in the memory of the memory array or on the bus side of the memory device. Additionally, by not using the memory cells of the memory device, the memory array is fully functional, as opposed to BISTs that must consume memory making an allocation of memory unavailable to normal processes.
One or more of the components, steps, features, and/or functions illustrated in the Figures may be rearranged and/or combined into a single component, step, feature, or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from novel features disclosed herein. The apparatus, devices, and/or components illustrated in the Figures may be configured to perform one or more of the methods, features, or steps described in the Figures. The novel algorithms described herein may also be efficiently implemented in software and/or embedded in hardware.
In addition, it is noted that the embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process is terminated when its operations are completed. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination corresponds to a return of the function to the calling function or the main function.
Moreover, a storage medium may represent one or more devices for storing data, including read-only memory (ROM), random access memory (RAM), magnetic disk storage mediums, optical storage mediums, flash memory devices, and/or other machine-readable mediums for storing information. The term “machine readable medium” includes, but is not limited to portable or fixed storage devices, optical storage devices, wireless channels and various other mediums capable of storing, containing, or carrying instruction(s) and/or data.
Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine-readable medium such as a storage medium or other storage(s). A processor may perform the necessary tasks. A code segment may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.
The various illustrative logical blocks, modules, circuits, elements, and/or components described in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing components, e.g., a combination of a DSP and a microprocessor, a number of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The methods or algorithms described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executable by a processor, or in a combination of both, in the form of processing unit, programming instructions, or other directions, and may be contained in a single device or distributed across multiple devices. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
Those of skill in the art would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.
The various features described herein can be implemented in different systems without departing from the described approaches. It should be noted that the foregoing embodiments are merely examples and are not to be construed as limiting. The description of the embodiments is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.

## Claims

1. A method operable on a memory circuit, comprising:
reading a first data pattern from a pattern register located within the memory circuit;
generating a plurality of data patterns, wherein at least one pattern of the plurality of data patterns is derived from the first data pattern; and
performing an input/output (I/O) test operation using the generated plurality of data patterns.

2. The method of claim 1, further comprising:
sending the plurality of data patterns to output drivers located within the memory circuit while performing the I/O test operation.

3. The method of claim 1, wherein the plurality of data patterns include a true copy of the first data pattern and an inverse copy of the first data pattern.

4. The method of claim 1, wherein the plurality of data patterns include a true copy of the first data pattern and at least one pattern of all zero bits or all one bits.

5. The method of claim 1, wherein said memory circuit includes a memory cell array, and
wherein the plurality of data patterns is stored in a plurality of registers coupled proximate to output drivers for the memory cell array.

6. The method of claim 5, wherein the input/output (I/O) test operation serves to at least partially characterize a performance of the output drivers using the plurality of data patterns.

7. The method of claim 1, wherein the plurality of data patterns are inserted into data lines extending between a memory cell array and a plurality of output drivers for the memory cell array.

8. The method of claim 1, wherein the memory cell array remains writeable even while the input/output test operation is performed.

9. The method of claim 1, wherein the plurality of data patterns are stored in a plurality of registers separate from the memory cell array.

10. The method of claim 1, further comprising:
using a mapping register to map the generated plurality of data patterns to a plurality of data lines.

11. The method of claim 1, further comprising:
using a shift-register to manipulate and randomize the first data pattern.

12. The method of claim 1, wherein at least one of the first data pattern and plurality of data patterns is a binary data pattern.

13. The method of claim 1, wherein the pattern register within the memory circuit is a read-only register with the first data pattern pre-stored in the pattern register.

14. The method of claim 1, wherein at least one of the plurality of data patterns is mapped on a bit by bit basis to output drivers of the memory circuit.

15. The method of claim 1, wherein the pattern register is defined from a plurality of memory cells within a memory cell array located within the memory circuit.

16. A memory circuit, comprising:
a memory cell array;
a plurality of output drivers coupled to the memory cell array via a plurality of data lines; and
a built-in self-test circuit operationally coupled to the plurality of data lines, the built-in self-test circuit configured to:
read a first data pattern from a pattern register located within the memory circuit;
generate a plurality of data patterns, wherein at least one pattern of the plurality of data patterns is derived from the first data pattern; and
perform an input/output (I/O) test operation using the generated plurality of data patterns.

17. The memory circuit of claim 16, wherein the built-in self-test circuit is further configured to:
send the plurality of data patterns to the output drivers while performing the I/O test operation.

18. The memory circuit of claim 16, wherein the pattern register within the memory circuit is a read-only register with the first data pattern pre-stored in the pattern register.

19. The memory circuit of claim 16, wherein the built-in self-test circuit further comprises a mapping register, wherein the built-in self-test circuit is further configured to:
use the mapping register to map the generated plurality of data patterns to a plurality of data lines.

20. The memory circuit of claim 19, wherein said mapping register comprises a plurality of individual bit registers, and
wherein each of said individual bit registers in the mapping register corresponds to a specific one of the plurality of data lines and selects a bit from the plurality of patterns to be sent to said specific data line.

21. The memory circuit of claim 16, wherein the plurality of data patterns is stored in a plurality of registers within the same semiconductor die as the plurality of output drivers and the memory cell array.

22. The memory circuit of claim 16, wherein the input/output (I/O) test operation serves to at least partially characterize a performance of the output drivers using the plurality of data patterns.

23. The memory circuit of claim 16, wherein the plurality of data patterns generated are inserted into the plurality of data lines.

24. The memory circuit of claim 16, wherein the plurality of data patterns are stored in a plurality of registers separate from the memory cell array.

25. The memory circuit of claim 16, wherein the pattern register is defined from a plurality of memory cells within the memory cell array located within the memory circuit.

26. The memory circuit of claim 16, wherein the memory cell array remains writeable even while the input/output test operation is performed.

27. The memory circuit of claim 16, wherein at least one of the plurality of data patterns is mapped on a bit by bit basis to the plurality of output drivers of the memory circuit.

28. The memory circuit of claim 16, wherein a minimum distance between the pattern register and said plurality of data lines is not greater than twenty times a width of a via of said memory circuit.

29. The memory circuit of claim 16, wherein said built-in self-test circuit is within the same chip as a memory controller configured to control currents and voltages applied to individual memory cells of the memory cell array.

30. A memory circuit, comprising:
means for reading a first data pattern from a pattern register located within the memory circuit;
means for generating a plurality of data patterns, wherein at least one pattern of the plurality of data patterns is derived from the first data pattern; and
means for performing an input/output (I/O) test operation using the generated plurality of data patterns.

31. A non-transitory machine-readable storage medium, having instructions stored thereon which when executed by at least one processor causes the at least one processor to:
read a first data pattern from a pattern register located within a memory circuit;
generate a plurality of data patterns, wherein at least one pattern of the plurality of data patterns is derived from the first data pattern; and
perform an input/output (I/O) test operation using the generated plurality of data patterns.