# Patent

## Title
Ultra-low-voltage current-reuse voltage-controlled oscillator and transconductance-capacitor filter

## Abstract

According to one aspect of the present disclosure, an ultra-low voltage current reused voltage-controlled oscillator and transconductance-capacitor filter is provided. The circuit includes a voltage-controlled oscillator stacked atop a transconductance-capacitor filter. The voltage-controlled oscillator includes a node one, a node two, a node three, a node four, an inductance, a variable capacitor, a first switched element, a second switched element, a third switched element, and a fourth switched element. The transconductance-capacitor filter includes a first resistor, a second resistor, a fifth switched element, a sixth switched element, a seventh switched element, and an eighth switched element.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit, especially relates to an ultra-low voltage current reused voltage-controlled oscillator and transconductance-capacitor filter.
2. Description of the Prior Art
With the continued maturation of the Internet of Things (IoT), a huge market has been opening up for short-range ultra-low-power (ULP) wireless connectivity. The IoT market will be close to hundreds of billion dollars (annually  ̃16 billions) in 2020. To bring down the hardware cost of such massive inter-connections, sub-GHz ULP wireless products compliant with the existing wireless standard such as the IEEE 802.15.4c/d (ZigBee) will be of great demand, especially for those that can cover all regional ISM bands [e.g., China (433 MHz), Europe (860 MHz), North America (915 MHz) and Japan (960 MHz)]. Together with the obvious goals of small chip area, minimum external components and ultra-low-voltage (ULV) supply (for possible energy harvesting), the design of such a receiver poses significant challenges.
The tradeoffs among multi-band operation, power, area and noise figure (NF) are described in FIG. 1. A multi-band receiver [FIG. 1(a)] can be resorted from multiple low-noise amplifier (LNAs) with shared I/Q mixers and baseband (BB) lowpass filters (LPFs). As such, each LNA and its input matching network can be specifically optimized for one band using passive-LC resonators, improving the NF, selectivity and gain. Although a single wideband LNA with zero LC components is preferred to reduce the die size [FIG. 1(b)], the NF and power requirements of the LNA are much higher. Moreover, when the output noise of the LNA is wideband, more harmonic-folding noise will be induced by its subsequent mixers (under hard switching). All these facts render wideband receivers generally more power hungry than its narrowband counterparts.
In contrast, a wide-range-tunable narrowband RF front-end is of greater potential to realize a multi-band ULP receiver. While sub-GHz passive LC resonators are area hungry, the N-path switched-capacitor (SC) network appears as a prospective alternative to replace them. It behaves as a tunable lossy LC resonator with its center frequency accurately defined by the clock. Inspired by it, present invention introduces a function-reuse RF front-end with signal orthogonality, and a gain-boosted N-path SC network for tunable RF filtering and input impedance matching. External components are avoided, while multi-band operation, stronger RF filtering, smaller physical capacitor size, and lower LO power are concurrently achieved when compared with the traditional designs. Together with a low-voltage current-reuse VCO-filter, the described multi-band receiver exhibits comparable performances with respect to other single-band-optimized designs.
SUMMARY OF THE INVENTION
According to one aspect of the present disclosure, an ultra-low voltage current reused voltage-controlled oscillator and transconductance-capacitor filter is provided. The circuit includes a voltage-controlled oscillator and a transconductance-capacitor filter. The voltage-controlled oscillator includes a node one, a node two, a node three, a node four, an inductance, a variable capacitor, a first switched element, a second switched element, a third switched element, and a fourth switched element. The inductance is coupled between the node one and the node two. The variable capacitor is coupled between the node one and the node two. Each of the first switched element, the second switched element, the third switched element, and the fourth switched element has a first node, a second node, and a gate node. The gate node of the first switched element is coupled to the first node of the second switched element, and the gate node of the second switched element is coupled to the first node of the first switched element. The gate node of the third switched element is coupled to the first node of the fourth switched element, and the gate node of the fourth switched element is coupled to the first node of the third switched element. The first node of the first switched element and the first node of the third switched element are coupled to the node one, and the first node of the second switched element and the first node of the fourth switched element are coupled to the node two. The second node of the first switched element and the second node of the second switched element are coupled to the node three, and the second node of the third switched element and the second node of the fourth switched element are coupled to the node four. The transconductance-capacitor filter includes a first resistor, a second resistor, a fifth switched element, a sixth switched element, a seventh switched element, and an eighth switched element. Each of the fifth switched element, the sixth switched element, the seventh switched element, and the eighth switched element has a first node, a second node, and a gate node. The first resistor is coupled between the first node and the gate node of the fifth switched element, and second resistor is coupled between the first node and the gate node of the eighth switched element. The gate node of the sixth switched element is coupled to the first node of the seventh switched element, and the gate node of the seventh switched element is coupled to the first node of the sixth switched element. The first node of the fifth switched element and the first node of the sixth switched element are coupled to node three, and the first node of the seventh switched element and the first node of the eighth switched element are coupled to node four.



BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure can be more fully understood by reading the following detailed description, with reference made to the accompanying drawings as follows:
FIG. 1a is a schematic diagram showing a multi-band receiver using multiple LNAs and matching networks for pre-gain and pre-filtering;
FIG. 1b is a schematic diagram showing a multi-band receiver using one wideband LNA to save the die area but demanding more power to lower the NF and nonlinearity due to no pre-gain, no pre-filtering and more harmonic-folding noise;
FIG. 2 is a schematic diagram showing a N-path tunable LNA or bandpass filter;
FIG. 3a illustrates a schematic diagram showing a single-path passive mixer;
FIG. 3b illustrates a schematic diagram showing a single-path passive mixer with gain boosting;
FIG. 3c illustrates a schematic diagram showing an N-path passive mixer;
FIG. 3d illustrates the N-path tunable LNA in FIG. 2 being re-arranged as an N-path tunable receiver by taking the BB outputs at VB1-N on top of Ci, like an N-path passive mixer with gain boosting;
FIG. 4a-1 is a diagram showing a timing diagram of LO1;
FIG. 4a-2 is a diagram showing a 4-path tunable receiver;
FIG. 4b is a diagram showing functional view of a 4-path tunable receiver to model the gain response;
FIG. 5 is a diagram showing simulated BB gain and RF gain of the 4-path tunable receiver (FIG. 4a), and the simulated BB gain from the functional view in FIG. 4b; 
FIG. 6a is a diagram showing the simulated output-noise PSD at the differential BB outputs (VB1,3) due to Rs and 4Gm;
FIG. 6b is a diagram showing simulated output-noise PSD at the differential BB outputs (VB1,3);
FIG. 7 is a diagram showing simulated NF of the N-path tunable receiver with the RF output or BB outputs;
FIG. 8a is a diagram showing AC-coupled 4-path tunable receiver and its operation for RF signal;
FIG. 8b is a diagram showing AC-coupled 4-path tunable receiver and its operation for BB signals;
FIG. 8c is a diagram showing AC-coupled 4-path tunable receiver's functional view to model the gain response;
FIG. 9a is a diagram showing function-reuse receiver embedding a gain-boosted 4-path SC network and its operation for RF signal;
FIG. 9b is a diagram showing function-reuse receiver embedding a gain-boosted 4-path SC network and its operation for BB signals;
FIG. 9c is a diagram showing function-reuse receiver embedding a gain-boosted 4-path SC network's functional view to model the gain response, wherein the front-end gain stage 4Gm and its 4-path SC network follow the structure of FIG. 4b; 
FIG. 10a is a diagram showing simulated BB gain response of the function-reuse receiver and its functional view with a large RF3;
FIG. 10b is a diagram showing simulated BB gain response of the function-reuse receiver and its functional view with a small RF3;
FIG. 11a is a diagram showing simulated BB NF of the function-reuse receiver and its functional view with a large RF3;
FIG. 11b is a diagram showing simulated BB NF of the function-reuse receiver and its functional view with a small RF3;
FIG. 12a is a diagram showing simulated RF gain responses at V0 for the three architectures: N-path tunable receiver, AC-coupled N-path tunable receiver and function-reuse receiver with a gain-boosted N-path SC network. The simulation parameters are RL=800 Ω, Rs=50 Ω, gm1=4gm2=4gm3=20.55 mS, Ci=12.5 pF, fs=400 MHz, RF1=5 kΩ, RF2=20 kΩ and RF3=20 kΩ;
FIG. 12b is a diagram showing simulated RF gain responses at V0 for the two architectures: AC-coupled N-path tunable receiver and function-reuse receiver with a gain-boosted N-path SC network. The simulation parameters are RL=800 Ω), Rs=50 Ω, gm1=4gm2=4gm3=20.55 mS, Ci=12.5 pF, fs=400 MHz, RF1=5 kΩ, RF2=20 kΩ and RF3=150 kΩ;
FIG. 12c is a diagram showing simulated RF NF at V0 for the three architectures: 4-path tunable receiver, AC-coupled 4-path tunable receiver and function-reuse receiver with a gain-boosted 4-path SC network. The simulation parameters are RL=800 Ω, Rs=50 Ω, gm1=4gm2=4gm3=20.55 mS, Ci=12.5 pF, fs=400 MHz, RF1=5 kΩ and RF2=20 kΩ;
FIG. 13 is a schematic diagram showing a low voltage current-reuse VCO filter;
FIG. 14a is a diagram showing the measured key performance metrics: Gain, NF, IRR and OB-IIP3;
FIG. 14b is a diagram showing the measured key performance metrics: VCO phase noise versus BB signal swing;
FIG. 14c is a diagram showing the measured key performance metrics: S11, power and VCO phase @ 3.5-MHz offset;
FIG. 14d is a diagram showing the measured key performance metrics: BB complex gain response centered at −2-MHz IF;
FIG. 15a is a diagram showing the measured P1 dB versus input offset frequency;
FIG. 15b is a diagram showing the measured blocker NF versus input power;
FIG. 16 is a schematic diagram showing an equivalent noise model of the N-path tunable receiver [FIG. 3(d)] for BB output-noise PSD calculation and simulation. N=4 is used. The noise sources gm1 and RF1 from the 4Gm are explicitly shown;
FIG. 17 schematic to model the BB NF of the functional-reuse receiver at VB2,I±; and
FIG. 18a is a diagram showing simulated BB NF from the model and functional-reuse receiver with a small RF3;
FIG. 18b is a diagram showing simulated BB NF from the model and functional-reuse receiver with a larger RF3.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Entered into the nanoscale CMOS regime, the transistors feature sufficiently high fT and low VT favoring the use of a current-reuse architecture. Moreover, by conveying the signal in the current domain, both the RF bandwidth and linearity can be improved. Our previous work was inspired by those facts; it unifies most RF-to-BB functions in one cell for current-mode signal processing at a typical 1.2-V supply, resulting in a high IIP3 (−6 dBm) at small power (2.7 mW) and area (0.3 mm2). Yet, for power savings, another 0.6-V supply was still required for the rest of the circuitries, complicating the power management. In some work, the 2.4-GHz ULV receiver facilitates single 0.3-V operation of the entire receiver at 1.6 mW for energy harvesting, but the limited voltage headroom and transistor fT call for bulky inductors and transformers to assist the biasing and tune out the parasitics, penalizing the area (2.5 mm2). Finally, since both of them target only the 2.4-GHz band, a fixed LC network can be employed for input matching and passive pre-gain (save power). This technique is however costly and inflexible for multi-band designs.
The described multi-band receiver is based on a function-reuse RF front-end implemented with a gain-boosted N-path SC network. The cost is low and die area is compact (0.2 mm2) as on/off-chip inductors and transformers are all avoided except the VCO. The power is squeezed by recycling a set of inverter-based amplifiers for concurrent RF (common mode) and BB (differential mode) amplification, resulting in low-voltage (0.5 V) and low-power (1.15 mW) operation.
Gain-Boosted N-Path SC Networks
The gain-boosted N-path SC network can generate an RF output when it is considered as a LNA or bandpass filter, or BB outputs when it is considered as a receiver (this work). We describe three alternatives to realize and study such a network. With the linear periodically time-variant (LPTV) analysis, the BB signal transfer function (STF) and noise transfer function (NTF) are derived and analyzed. Besides, three intuitive functional views are given to model their gain responses.
A. N-Path Tunable Receiver
By having an N-path SC network as the feedback path of a gain stage (labeled with the symbol 4Gm), an N-path tunable LNA (or bandpass filter) can be realized with the RF output taken at Vo (FIG. 2). This topology has a number of core benefits when compared with the existing N-path filtering. First, double-RF filtering at Vi and Vo is achieved with one N-path SC network. Second, tunable input impedance matching is possible at Vi. Third, the loop gain associated with 4Gm reduces the impact of Rsw (mixer's ON resistance) to the ultimate out-of-band (OB) rejection. Fourth, similar to the continuous-time Miller capacitor, for a given RF bandwidth (BW), the required Ci can be reduced by the loop gain associated with 4Gm. Fifth, the NTF of Rsw to Vo is a notch function around the clock frequency fs. Thus, small switches are allowed without degrading the NF, saving the LO power. Finally, the output noise at Vo is narrowband with a comb-filter shape, reducing the harmonic-folding noise when it is followed by a wideband passive mixer.
Interestingly, if such an operation principle is extended to FIGS. 3(a) to (d), the N-path tunable LNA can be viewed as a passive-mixer receiver, with all capacitors Ci driven by a 4Gm stage. The BB outputs are taken at VB1-N. Unlike the original passive-mixer-first receiver that offers no gain at VB1-N, this receiver has a relatively large BB gain at VB1-N surmounting the NF limitation. The frequency-translational RF filtering at Vi and Vo are realized by LO1-LON to upconvert the BB signals VB1-N to RF, and in-phase summed together.
To establish a basic operation theory, the analysis below follows the LPTV method. For simplicity, N=4 is employed to allow basic I/Q downconversion with LO1-LO4 as 25%-duty-cycle non-overlapping clocks. The timing diagram of LO1 is shown in FIG. 4(a)-1. 4Gm can be based on a self-biased inverter amplifier with gm1 as the transconductance, RL as the output resistance and RF1 as the feedback resistor. LO2-4 are similar to LO1 with a time delay (shown in FIG. 4-(a)-2). The analysis is conducted for VB1 while for VB2-4, when fRF is around qfs, the phase relation between the BB voltages VBi (1≦i≦4) can be described by




  
    
      V
      Bm
    
    =
    
      
        V
        Bn
      
      
        e
        
          
            
              j
              ⁢
              
                
              
              ⁢
              q
              ⁢
              
                
              
              ⁢
              
                π
                ⁡
                
                  (
                  
                    m
                    -
                    n
                  
                  )
                
              
            
            ⁢
            
              
            
          
          2
        
      
    
  
  ,




(1≦(m,n)≦4). Thus, VB1 and VB3 (VB2 and VB4) are either out-of-phase or in-phase with each other, depending on the input frequency. When LO1 is high (K=1), linear analysis reveals the following state-space description,





  
    
      
        
          
            d
            
              
                v
                
                  C
                  ⁢
                  
                    
                  
                  ⁢
                  i
                
              
              ⁡
              
                (
                t
                )
              
            
          
          
            d
            t
          
        
        =
        
          
            
              
                v
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  F
                
              
              ⁡
              
                (
                t
                )
              
            
            
              
                C
                i
              
              ⁢
              
                R
                1
              
            
          
          -
          
            
              
                v
                
                  C
                  ⁢
                  
                    
                  
                  ⁢
                  i
                
              
              ⁡
              
                (
                t
                )
              
            
            
              
                C
                i
              
              ⁢
              
                R
                2
              
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




where




  
    
      
        
          R
          1
        
        =
        
          
            1
            +
            
              
                R
                
                  s
                  ⁢
                  
                    
                  
                  ⁢
                  w
                
              
              
                R
                
                  F
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            +
            
              
                
                  R
                  
                    s
                    ⁢
                    
                      
                    
                    ⁢
                    w
                  
                
                +
                
                  R
                  S
                
              
              
                R
                L
              
            
            +
            
              
                
                  R
                  
                    s
                    ⁢
                    
                      
                    
                    ⁢
                    w
                  
                
                ⁢
                
                  R
                  S
                
              
              
                
                  R
                  
                    F
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  R
                  L
                
              
            
            +
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              ⁢
              
                R
                S
              
            
            +
            
              
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  R
                  
                    s
                    ⁢
                    
                      
                    
                    ⁢
                    w
                  
                
                ⁢
                
                  R
                  S
                
              
              
                R
                
                  F
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
          
          
            
              1
              
                R
                L
              
            
            +
            
              g
              
                m
                ⁢
                
                  
                
                ⁢
                1
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  








  
    
      
        
          R
          1
        
        =
        
          
            1
            +
            
              
                R
                
                  s
                  ⁢
                  
                    
                  
                  ⁢
                  w
                
              
              
                R
                
                  F
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            +
            
              
                
                  R
                  
                    s
                    ⁢
                    
                      
                    
                    ⁢
                    w
                  
                
                +
                
                  R
                  S
                
              
              
                R
                L
              
            
            +
            
              
                
                  R
                  
                    s
                    ⁢
                    
                      
                    
                    ⁢
                    w
                  
                
                ⁢
                
                  R
                  S
                
              
              
                
                  R
                  
                    F
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  R
                  L
                
              
            
            +
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              ⁢
              
                R
                S
              
            
            +
            
              
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  R
                  
                    s
                    ⁢
                    
                      
                    
                    ⁢
                    w
                  
                
                ⁢
                
                  R
                  S
                
              
              
                R
                
                  F
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
          
          
            
              1
              
                R
                
                  F
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            +
            
              1
              
                R
                L
              
            
            +
            
              
                R
                S
              
              
                
                  R
                  
                    F
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  R
                  L
                
              
            
            +
            
              
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  R
                  S
                
              
              
                R
                
                  F
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




When LO1 is low (K=2), we have




  
    
      
        
          
            d
            
              
                υ
                
                  C
                  ⁢
                  
                    
                  
                  ⁢
                  i
                
              
              ⁡
              
                (
                t
                )
              
            
          
          
            d
            t
          
        
        =
        0
      
    
    
      
        (
        4
        )
      
    
  




From (1)-(4), the harmonic transfer functions (HTFs) for the intervals K=1 and K=2 are derived in (5) and (6), respectively,




  
    
      
        
          
            H
            
              n
              ,
              1
              ,
              
                R
                ⁢
                
                  
                
                ⁢
                F
              
            
          
          ⁡
          
            (
            jω
            )
          
        
        =
        
          
            
              
                ω
                
                  
                    r
                    ⁢
                    
                      
                    
                    ⁢
                    c
                  
                  ,
                  B
                
              
              
                
                  ω
                  
                    
                      r
                      ⁢
                      
                        
                      
                      ⁢
                      c
                    
                    ,
                    A
                  
                
                +
                jω
              
            
            ×
            
              
                1
                -
                
                  e
                  
                    
                      -
                      j
                    
                    ⁢
                    
                      
                    
                    ⁢
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    
                      ω
                      s
                    
                    ⁢
                    
                      τ
                      1
                    
                  
                
              
              
                j
                ⁢
                
                  
                
                ⁢
                2
                ⁢
                m
              
            
          
          +
          
            
              
                1
                -
                
                  e
                  
                    jωτ
                    2
                  
                
              
              
                
                  ω
                  
                    
                      r
                      ⁢
                      
                        
                      
                      ⁢
                      c
                    
                    ,
                    A
                  
                
                +
                jω
              
            
            ⁢
            
              G
              ⁡
              
                (
                jω
                )
              
            
            ⁢
            
              f
              a
            
          
        
      
    
    
      
        (
        5
        )
      
    
  








  
    
      
        
          
            H
            
              n
              ,
              2
              ,
              
                R
                ⁢
                
                  
                
                ⁢
                F
              
            
          
          ⁡
          
            (
            jω
            )
          
        
        =
        
          
            -
            
              
                1
                -
                
                  e
                  
                    jωτ
                    2
                  
                
              
              jω
            
          
          ⁢
          
            G
            ⁡
            
              (
              jω
              )
            
          
          ⁢
          
            f
            s
          
        
      
    
    
      
        (
        6
        )
      
    
  




where,




  
    
      
        
          G
          ⁡
          
            (
            jω
            )
          
        
        =
        
          
            
              
                e
                
                  
                    j
                    ⁡
                    
                      (
                      
                        ω
                        -
                        
                          n
                          ⁢
                          
                            
                          
                          ⁢
                          
                            ω
                            s
                          
                        
                      
                      )
                    
                  
                  ⁢
                  
                    τ
                    1
                  
                
              
              -
              
                e
                
                  
                    -
                    
                      ω
                      
                        rc
                        ,
                        A
                      
                    
                  
                  ⁢
                  
                    τ
                    1
                  
                
              
            
            
              
                e
                
                  
                    j2π
                    ⁡
                    
                      (
                      
                        ω
                        -
                        
                          n
                          ⁢
                          
                            
                          
                          ⁢
                          
                            ω
                            s
                          
                        
                      
                      )
                    
                  
                  /
                  
                    ω
                    s
                  
                
              
              -
              
                e
                
                  
                    -
                    
                      ω
                      
                        rc
                        ,
                        A
                      
                    
                  
                  ⁢
                  
                    τ
                    1
                  
                
              
            
          
          ×
          
            1
            
              
                
                  ω
                  
                    rc
                    ,
                    A
                  
                
                
                  ω
                  
                    rc
                    ,
                    B
                  
                
              
              +
              
                
                  j
                  ⁡
                  
                    (
                    
                      ω
                      -
                      
                        
                          n
                          ⁢
                          ω
                        
                        s
                      
                    
                    )
                  
                
                
                  ω
                  
                    rc
                    ,
                    B
                  
                
              
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




ωrc,A=1/R2Ci, ωrc,B=1/R1Ci,




  
    τ
    1
  
  =
  
    
      
        
          T
          s
        
        4
      
      ⁢
      
        
      
      ⁢
      and
      ⁢
      
        
      
      ⁢
      
        τ
        2
      
    
    =
    
      
        
          3
          ⁢
          
            
          
          ⁢
          
            T
            s
          
        
        4
      
      .
    
  




Here, G(jω) represents the switching moment transfer function. By combining (5)-(7), the harmonics transfer function from VRF to Ci is derived,





  
    
      
        
          
            H
            
              D
              ,
              
                R
                ⁢
                
                  
                
                ⁢
                F
              
            
          
          ⁡
          
            (
            jω
            )
          
        
        =
        
          
            
              
                V
                
                  C
                  ⁢
                  
                    
                  
                  ⁢
                  i
                
              
              ⁡
              
                (
                jω
                )
              
            
            
              
                V
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  F
                
              
              ⁡
              
                (
                jω
                )
              
            
          
          =
          
            
              
                H
                
                  n
                  ,
                  1
                  ,
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    F
                  
                
              
              ⁡
              
                (
                jω
                )
              
            
            +
            
              
                H
                
                  n
                  ,
                  2
                  ,
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    F
                  
                
              
              ⁡
              
                (
                jω
                )
              
            
          
        
      
    
    
      
        (
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For the BB signal around fs, the voltages sampling at Ci are differential, and Vo is thus the virtual ground and the state of the circuit VCi(jω) (voltage across Ci) is equal to VBm(jω), where 1≦m≦4. Although the results from the LPTV analysis are exact, they are lacking in conceptual intuition that can be of more practical value for designers. To compare with the usual receiver concept that is based on cascade of blocks, a functional view of a 4-path tunable receiver is given in FIG. 4(b) to model the gain response. An ideal buffer amplifier (infinite input impedance and zero output impedance) is introduced into the model implying that the passive mixer has no loading effect to the front-end 4Gm stage. Note that the model is inapplicable for studying the noise, since the noise sources from the functional view are separated, and thus considered as uncorrelated. Differently with the noise sources of the proposed receiver, they are considered as correlated. From this functional view, the mixers are reused for two roles: double-RF filtering (i.e., as two N-path filters at both input and output of the gain stage) and frequency downconversion (i.e., as an N-path mixer). For the associated capacitors, they are also reused for both double-RF filtering (associated with the 4-path SC network) and BB filtering at VB1-4. These properties lower the LO power and chip area while providing stronger RF filtering. For the RF gain at Vo, it can be derived by the upconversion of VB1-4 and summed together at Vo as given by,




  
    
      
        
          
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After applying Fourier series analysis to (9) around fs, we have,




  
    
      
        
          
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which is an approximation as the influence of Rsw is ignored. Here VB1,3=VB1-VB3. To verify it, the BB and RF STFs of the N-path tunable receiver are plotted together in FIG. 5. The RF gain is  ̃8 dB smaller than that of the BB gain, close to the prediction by (10). Also, the BB gain from the functional view is plotted, which fits well with the original gain-boosted in-band (IB) signal.
The power spectral density (PSD) of the BB output noise is derived in Appendix A, while the PSD of the RF output noise at Vo has been studied in some study. The simulated results are given in FIG. 6 (using the model of FIG. 16 in Appendix A). From simulations, the differential output noise power from Rsw and RF1 are much smaller (around two orders of magnitude) than that from Rs and 4Gm. Thus, the noise contributions from Rsw and RF1 are greatly suppressed, making small mixer's switches and large RF1 possible (constrained by input impedance matching and the required RF filtering). Unlike the passive-mixer-first receiver where the BB NF from Rsw is approximately (Rsw/Rs+γ), here γ is a factor from the harmonic folding. Thus, for the passive-mixer-first design, the BB NF due to Rsw is usually of a similar order of magnitude as Rs. Besides, a small Rsw and additional LO paths are required to minimize such effect.
We also show the simulated BB NF for VB1,3 and RF NF at Vo (FIG. 7), where VB1,3=VB1-VB3 and similar notations such as VX1,3=VX1-VX3 have the same implication in the following text. Interestingly, the BB NF is smaller than the RF NF at the LNA's output Vo, since the BB gain (or noise) and RF gain (or noise) are concurrent but happened under different STF (or NTFs). This characteristic underlines a fundamentally different concept when compared with the traditional receiver that is based on the cascade of blocks, where the RF NF should be smaller than the BB NF. Note that for the BB NF, the even-harmonic-folding noise due to the LO contributes only common-mode noise at the BB outputs, which will be rejected differentially. However, it will contribute to the RF noise at Vo due to its single-ended nature. This is one of the senses that the BB NF can be smaller than the RF NF. The authors are still pursuing deeper exploration of this topic and this paper serves as the foundation. Furthermore, the 1/f noise around DC from the transconductance devices are upconverted to fs with little influence to the total output noise at DC. This was verified by simulations (FIG. 7) where the BB NF at 1 kHz has increased by only 0.15 dB. Thus, short channel-length devices can be employed without degrading the BB low-frequency noise.
B. AC-Coupled N-Path Tunable Receiver
Another alternative to implement such a gain-boosted N-path SC network is shown in FIG. 8(a). The mixers are placed on the feedback path while the input is AC-coupled by capacitors that simplify the cascading of itself for a higher order of filtering. Without considering the memory effect of capacitor Ci, the operation of this architecture can be explained as follows: Initially, at RF frequency, the capacitor Ci can be assumed as a short circuit. The input signal VRF is thus directly coupled to each gain stage Gm (Gm has a transconductance of gm2, output resistance of 4RL, and feedback resistor of RF2) and is amplified along path A [FIG. 8(a)] while the signal along the feedback path is downconverted to BB and summed at Vo, which will be zero since LO1 and LO3 are 180° out-of-phase with each other (the same is true for LO2,4). After that, the amplified RF signal at Vo is immediately down-converted to BB by the 4-path I/Q passive mixers along path B [FIG. 8(b)]. The BB signals at VB1,I+ and VB1,I− are differential (the same is true for VB1,Q+ and VB1,Q−). Thus, node Vi is a virtual ground. The I/Q BB signals will be amplified and summed together again at Vo, which should be zero. This process is explicitly modeled in FIG. 8(c). Similar to FIG. 4(b), an ideal buffer amplifier is inserted between the front-end gain stage (with small signal transconductance gm1 and feedback resistor RF2/4 for the 4Gm stage, as the 4 paths are parallelized) and I/Q passive mixers. When the memory effect of Ci is accounted, the 4-path SC network can be modeled at the feedback path of the 4Gm stage, providing double-RF filtering at both its input and output nodes.
With sufficiently large RF2, the voltages (i.e., the circuit states) sampling at Ci are independent. Around the clock frequency, in the steady state, the BB voltages sampling at Ci are νCi(t), jνCi(t), −νCi(t) and −jνCi(t) respectively for LO1-4. When LO1 is high, linear analysis shows the following state-space description,




  
    
      
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Simplifying (11), the same equation as in (1) is obtained, with RF1=∞ for R1 and R2. When LO1 is low, it is in the hold mode, which can be described by (4). Thus, the same BB voltages VB1,I± (VB1,Q±) as in GB-SC are expected. For the RF voltage at Vo, it can be evaluated by (10), rendering the same RF voltage gain as in FIG. 2. For the BB NTF from Gm, Rsw, Rs and RF2, they are also similar to those of FIG. 2 (not shown here).
If RF2 is small, the voltage sampling at Ci during each LO cycle will be leaked to the ground through RF2, or coupled with other states at the output Vo. The effect of charge leakage or sharing will decrease both the BB and RF gains. In the proposed gain-boosted SC network, however, there is no such a problem since the charge stored at the capacitors is constant. Thus, this architecture has smaller gain than the gain-boosted N-path SC network under a finite feedback resistor with all other parameters unchanged. In a similar way, the AC-coupled N-path tunable receiver blocks the DC response, since at DC the charge stored at the capacitors Ci has infinite time to disappear.
C. Function-Reuse Receiver Embedding a Gain-Boosted N-Path SC Network
Unlike the AC-coupled N-path tunable LNA, the proposed function-reuse receiver with a gain-boosted 4-path SC network [FIG. 9(a)] separates the output of each gain stage Gm (Gm has a transconductance of gm3, output resistance of 4RL, and feedback resistor of RF3) with capacitor Co that is an open circuit at BB. The I/Q BB signals at VB1,I± and VB1,Q± are further amplified along the Path C [FIG. 9(b)] by each Gm stage. With the memory effect of the capacitors, the functional view of the gain response is shown in FIG. 9(c). In order to achieve current-reuse between the RF LNA and BB amplifiers without increasing the supply, the circuit with an active mixer has a similar function. However, the BB NF behavior and the RF filtering behavior are different from the N-path passive mixer applied here that is at the feedback path. For the BB amplifiers, it is one Gm with one RF3, balancing the BB gain and OB-IIP3. After considering that the BB amplifiers have been absorbed in the LNA, the I/Q passive mixers and capacitors absorbed by the 4-path SC network, the blocks after the LNA can be assumed virtual. These virtual blocks reduce the power, area and NF. Similar to the AC-coupled N-path tunable LNA, with a relative small RF3, the voltage sampling at Ci in different phases will either leak to the ground, or couple with each other, lowering the BB and RF gains.
To validate the above analysis, the gain and noise performances under two sets of RF3 are simulated. Here, the virtual blocks in FIG. 9(c) are implemented with physical transistors and capacitors for the BB amplifiers and the mixers while the buffer is ideal. Thus, the power of the modeled receiver is at least 2× larger than the proposed receiver. For the IB BB gain at VB2,I± (VB2,Q±) between the proposed function-reuse receiver and its functional view, the difference is only 1 dB at a large RF3 of 150 kΩ [FIG. 10(a)]. For a small RF3, the gain error goes up to 2 dB [FIG. 10(b)], which is due to the gain difference between the model of the N-path tunable LNA [FIG. 9(c)] and the implementation of the function-reuse receiver that has AC-coupling. For the NF difference (ΔNF), with a large (small) RF3, it is  ̃0.8 dB (3.5 dB) as compared in FIGS. 11(a) and (b). This is due to the lower gain at the LNA's output, forcing the input-referred noise from the downconversion passive mixers and the BB amplifiers to increase with a small RF3. Either with a small or large RF3, it is noteworthy that the variation of BB NF is small (i.e. for RF3=20 kΩ it is 3.6 dB while for RF3=150 kΩ it is 3.4 dB), because the BB NTF has a weak relation with RF3. It also indicates that the BB NTF is weakly related with the gain at the LNA's output, which is dissimilar to the usual receiver where the NF should be small when the LNA's gain is large. Similarly, the NF at the LNA's output (now shown) can be larger than that at BB due to the different NTFs. The BB gain and the output noise at VB2,I± (VB2,Q±) are further discussed in Appendix B.
For the RF gain at Vo, the simulations results are shown in FIG. 12(a) for the three realizations. With relatively small feedback resistors RF1=5 kΩ, RF2=RF3=20 kΩ, the function-reuse receiver has about 10 dB smaller IB gain than the other two. Also, there is a gain response appearing at the 2nd harmonic, which is due to the single-ended realization. The IB gain loss of the function-reuse receiver can be compensated by increasing RF3 from 20 to 150 kΩ, with all other parameters unchanged. The corresponding RF gain responses are plotted in FIG. 12(b). All results are consistent to each other (and this is also true for the BB gain). The NFs at the LNA's output Vo are plotted in FIG. 12(c). With a small RF1-3, the RF NF of the function-reuse receiver is higher due to a lower IB gain [the RF NF is also much higher than the BB NF, as shown in FIG. 11(b)]. However, with a large RF3, the RF NF for the three architectures is almost equal since they have similar RF and BB gains as shown in FIG. 12(a)-(b). From FIGS. 11 and 12, it can be concluded that, although the RF gain of the function-reuse receiver has  ̃10 dB difference, the difference in the BB NF is small (0.2 dB). However, for the functional view model, the BB NF has about 2-dB difference.
Low-Voltage Current-Reuse VCO-Filter
In order to further optimize the power, the VCO is designed to current-reuse with the BB complex low-IF filter (FIG. 13). The negative transconductor of the VCO is divided into multiple Mv cells. The aim is to distribute the bias current of the VCO to all BB gain stages (A1, A2. . . A18) that implement the BB filter. For the VCO, MV operates at the frequency of 2fs or 4fs for a div-by-2 or div-by-4 circuit. Thus, the VCO signal leaked to the source nodes of MV (VF1,I+, VF1,I−) is pushed to very high frequencies (4fs or 8fs) and can be easily filtered by the BB capacitors. For the filter's gain stages such as A1, Mb (gMb) is loaded by an impedance of  ̃1/2gM, when Lp can be considered as a short circuit at BB. Thus, A1 has a ratio-based voltage gain of roughly gMb/gMv, or as given by 4TgMb/GmT, where GmT is the total transconductance for the VCO tank. The latter shows how the distribution factor T can enlarge the BB gain, but is a tradeoff with its input-referred noise and can add more layout parasitics to Vvcop,n (i.e., narrower VCO's tuning range). The −R cell using cross-coupled transistors is added at VF1,I+ and VF1,I− to boost the BB gain without loss of voltage headroom. For the BB complex poles, A2,5 and Cf1 determine the real part while A3,6 and Cf1 yield the imaginary part. There are 3 similar stages cascaded for higher channel selectivity and image rejection ratio (IRR). Rblk and Cblk were added to avoid the large input capacitance of A1,4 from degrading the gain of the front-end.
Results
Two versions of the multi-ISM-band sub-GHz ZigBee receiver were fabricated in 65-nm CMOS and optimized with a single 0.5-V supply. With (without) the LC tank for the VCO, the die area is 0.2 mm2 (0.1 mm2). Since the measurement results of both are similar, only those measured with VCO in FIG. 14(a)-(d) are reported here. From 433 to 960 MHz, the measured BB gain is 50±2 dB. Following the linearity test profile, two tones at [fs+12 MHz, fs+22 MHz] are applied, measuring an OB-IIP3 of −20.5±1.5 dBm at the maximum gain. The IRR is 20.5±0.5 dB due to the low-Q of the VCO-filter. The IIP3 is mainly limited by the VCO-filter. The measured NF is 8.1±0.6 dB. Since the VCO is current-reuse with the filter, it is interesting to study its phase noise with the BB signal amplitude. For negligible phase noise degradation, the BB signal swing should be <60 mVpp, which can be managed by variable gain control. If a 60-mVpp BB signal is insufficient for demodulation, a simple gain stage (e.g., inverter amplifier) can be added after the filter to enlarge the gain and output swing. The total power of the receiver is 1.15 mW (0.3 mW for the LNA+BB amplifiers and 0.65 mW for VCO-filter and 0.2 mW for the divider), while the phase noise is −117.4±1.7 dBc/Hz at 3.5-MHz frequency offset. The S11 is below −8 dB across the whole band. The asymmetric IF response shows 24-dB (41-dB) rejection at the adjacent (alternate) channel.
To study the RF filtering behavior, the P1 dB and blocker NF are measured. For the in-band signal, the P1 dB is −55 dBm while with a frequency offset frequency of 20 MHz, it increases to −35 dBm, which is mainly due to the double-RF filtering [FIG. 15(a)]. For an offset frequency of 60 MHz, the P1 dB is −20 dBm, limited by the current-reuse VCO-filter. For the blacker NF, with a single tone at 50 MHz, the blocker NF is almost unchanged for the blocker <−35 dBm. With a blocker power of −20 dBm, the NF is increased to  ̃14 dB [FIG. 15(b)].
A function-reuse receiver embedding a gain-boosted N-path SC network has been proposed to realize a sub-GHz multi-ISM-band ULP ZigBee radio at a single 0.5-V supply. The featured improvements are fourfold: (1) unlike the usual receiver concept that is based on cascade of blocks, this receiver reuses one set of amplifiers for concurrent RF and BB amplification by arranging an N-path SC network in the feedback loop. Interestingly, this scheme decouples the BB STF (or NTF) from its RF STF (or NTF), allowing a lower BB NTF possible while saving power and area. This new receiver concept is good foundation for a deeper exploration of the topic. (2) The output BB NTF due to Rsw and RF are greatly reduced, lowering the required size of the mixer switches and LO power. (3) Double-RF filtering is performed with one N-path SC network, improving the OB-IIP3 and tolerability of OB blockers. (4) A current-reuse VCO-filter further optimizes the power at just 0.5 V. All of these characteristics affirm the receiver as a potential candidate for emerging ULP radios for IoT applications that should support multi-band operation, being friendly to a single ULV supply for energy harvesting, and compact enough to save cost in nanoscale CMOS.
Appendices
A. Output-Noise PSD at BB for the N-Path Tunable Receiver
The derivation of the output-noise PSD at BB due to RS, 4Gm, Rsw and RF1 is presented here. The model used to obtain the NTFs is shown in FIG. 16. For all output-noise PSDs, there are two parts: one is the direct transfer from input RF to BB (Part A), while another is from harmonics folding noise (Part B). For the latter, increasing the path number N can reduce such contribution. The differential output-noise PSD for Rs, 4Gm, Rsw and RF1 with Vn,RS2=4KTRs, Vn,4Gm2=4KT/gm1, Vn,Rsw2=4KTRsw and Vn,RF12=4KTRF1 are given as (12)-(15),




  
    
      
        
          
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                    2
                  
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                  Part
                  ⁢
                  
                    
                  
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              +
              
                
                  
                    
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                      2
                    
                  
                  }
                
                
                  Part
                  ⁢
                  
                    
                  
                  ⁢
                  B
                
              
            
            }
          
          ×
          4
        
      
    
    
      
        (
        13
        )
      
    
  








  
    
      
        
          
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            }
          
          ×
          4
        
      
    
    
      
        (
        14
        )
      
    
  








  
    
      
        
          
            V
            
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              ,
              
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                  ⁢
                  
                    
                  
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            }
          
          ×
          4
        
      
    
    
      
        (
        15
        )
      
    
  




For the above NTFs, the even order terms (including zero) of n are excluded. The single-ended HTFs for RS, 4Gm, Rsw and RF1 are Hn,RS(jω), Hn,4Gm(jω), Hn,Rsw(jω) and Hn,RF1(jω), respectively. The derivation is similar to Hn,RF(jω) in Section III-A. The only difference is on the linear state-space equation.
B. Derivation and Modeling of BB Gain and Output Noise for the Function-Reuse Receiver
When considering the memory effect of the capacitor Ci and Co with RF3 sufficiently large, the voltages (i.e., the circuit states) at Ci are independent. In the steady-state, around the clock frequency, the voltages sampling at Ci are νCi(t), jνCi(t), −νCi(t), −jνCi(t), while the voltage sampling at Co is νCO(t), jνCO(t), −νCO(t), −jνCO(t), for LO1-4, respectively. When LO1 is high (K=1), linear analysis shows the following state-space description for capacitor Ci,




  
    
      
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        (
        16
        )
      
    
  




Eq. (16) can be simplified similar to (1). Likewise, when LO1 is low, it can be described by (4). Thus, it has the same BB HTFs as in gain-boosted N-path SC network [shown also in (8)].
The BB NF at VB2,I± (VB2,Q±) is approximately modeled in FIG. 17. The BB output noise at VB1,I± (VB1,Q±) are further amplified by two separate BB amplifiers, while in the function-reuse receiver they are amplified by the same BB amplifiers. From simulations, with a large RF3, the model has a good accuracy, while for a small RF3, the error increases for the low-frequency part. This is because the BB gain at VB1,I± (VB1,Q±) gets smaller under a small RF3, and the independent noise sources from the model's Gm contribute additional noise [FIGS. 18(a) and (b)]. Still, this model is more accurate than that of the functional view [FIG. 18(c)]. For both cases, the function-reuse receiver has a smaller NF and requires lower power than the separated Gm situation. For the BB gain, this model has a high accuracy (not shown).
Further Example Embodiments
The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.
Example 1 is a circuit, comprising: two set networks connected in parallel, each of which including: a voltage-controlled oscillator, comprising: a node one, a node two, a node three, and a node four; an inductance coupling between the node one and the node two; a variable capacitor coupling between the node one and the node two; a first switched element, a second switched element, a third switched element, and a fourth switched element, each of which having a first node, a second node, and a gate node; wherein the gate node of the first switched element is coupled to the first node of the second switched element, and the gate node of the second switched element is coupled to the first node of the first switched element, wherein the gate node of the third switched element is coupled to the first node of the fourth switched element, and the gate node of the fourth switched element is coupled to the first node of the third switched element, wherein the first node of the first switched element and the first node of the third switched element are coupled to the node one, and the first node of the second switched element and the first node of the fourth switched element are coupled to the node two, wherein the second node of the first switched element and the second node of the second switched element are coupled to the node three, and the second node of the third switched element and the second node of the fourth switched element are coupled to the node four; a transconductance-capacitor filter, comprising: a first resistor and a second resistor; and a fifth switched element, a sixth switched element, a seventh switched element, and an eighth switched element, each of which having a first node, a second node, and a gate node; wherein the first resistor is coupled between the first node and the gate nod of the fifth switched element, and second resistor is coupled between the first node and the gate nod of the eighth switched element, wherein the gate node of the sixth switched element is coupled to the first node of the seventh switched element, and the gate node of the seventh switched element is coupled to the first node of the sixth switched element, wherein the first node of the fifth switched element and the first node of the sixth switched element are coupled to node three, and the first node of the seventh switched element and the first node of the eighth switched element are coupled to node four.
Example 2 includes the subject matter of example 1, wherein the switched elements are NMOS transistor.
Example 3 includes the subject matter of example 1, wherein the second node of the fifth switched element, sixth switched element, seventh switched element, and eighth switched element are coupled to ground.
Example 4 includes the subject matter of example 1, further comprising a frequency divider, the frequency divider is coupled between the node one and the node two.
Example 5 includes the subject matter of example 4, wherein the outputs of the frequency divider are 4-phase signals (0°, 90°, 180°, 270°), and can be further divided to generate lower frequency 4-phase signals (0°, 90°, 180°, 270°)
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.

## Claims

1. A circuit, comprising:
a voltage-controlled oscillator stacked atop a transconductance-capacitor filter for current-reuse, the voltage-controlled oscillator comprising:
a node one, a node two, a node three, and a node four;
an inductance coupling between the node one and the node two;
a variable capacitor coupling between the node one and the node two;
a first switched element, a second switched element, a third switched element, and a fourth switched element, each of which having a first node, a second node, and a gate node;
wherein the gate node of the first switched element is coupled to the first node of the second switched element, and the gate node of the second switched element is coupled to the first node of the first switched element,
wherein the gate node of the third switched element is coupled to the first node of the fourth switched element, and the gate node of the fourth switched element is coupled to the first node of the third switched element,
wherein the first node of the first switched element and the first node of the third switched element are coupled to the node one, and the first node of the second switched element and the first node of the fourth switched element are coupled to the node two,
wherein the second node of the first switched element and the second node of the second switched element are coupled to the node three, and the second node of the third switched element and the second node of the fourth switched element are coupled to the node four;

the transconductance-capacitor filter, comprising:
a first resistor and a second resistor; and
a fifth switched element, a sixth switched element, a seventh switched element, and an eighth switched element, each of which having a first node, a second node, and a gate node;
wherein the first resistor is coupled between the first node and the gate node of the fifth switched element, and second resistor is coupled between the first node and the gate node of the eighth switched element,
wherein the gate node of the sixth switched element is coupled to the first node of the seventh switched element, and the gate node of the seventh switched element is coupled to the first node of the sixth switched element,
wherein the first node of the fifth switched element and the first node of the sixth switched element are coupled to node three, and the first node of the seventh switched element and the first node of the eighth switched element are coupled to node four.

2. The circuit according to claim 1, wherein the switched elements are NMOS transistor.

3. The circuit according to claim 1, wherein the second node of the fifth switched element, sixth switched element, seventh switched element, and eighth switched element are coupled to ground.

4. The circuit according to claim 1, further comprising a frequency divider, the frequency divider is coupled between the node one and the node two.

5. The circuit according to claim 4, wherein the outputs of the frequency divider are 4-phase signals (0°, 90°, 180°, 270°), and can be further divided to generate lower frequency 4-phase signals (0°, 90°, 180°, 270°).