# Patent

## Title
Dead-time detecting circuit for inductive load and modulation circuit using the same

## Abstract

Dead-time detector includes an N-type power switch and a resistor. The N-type power switch includes a first end coupled to the output end of the output-stage circuit for receiving an output voltage, a second end for outputting a dead-time detecting signal, and a control end for receiving a gate-controlling voltage. The resistor is coupled between the second end of the N-type power switch and a voltage source providing a high voltage for keeping the voltage of the dead-time detecting signal when the N-type power switch does not output the dead-time detecting signal representing “ON”. When the output voltage is so lower than the gate-controlling voltage that the N-type power switch is turned on, the N-type power switch outputs the dead-time detecting signal representing “ON”. When the dead-time detecting signal represents “ON”, the output-stage circuit leaves the dead-time state.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dead-time detecting circuit and the modulation circuit using the same, and more particularly, to a dead-time detecting circuit for inductive load and the modulation circuit using the same, wherein the detecting circuit is utilized for detecting the dead-time of the Pulse Width Modulation/Pulse Frequency Modulation (PWM/PFM) circuit.
2. Description of the Prior Art
In the PWM/PFM circuit, controlling the dead-time is very important. In the prior art, the dead-time generator is composed only of logic gates so that the generated dead-time is easily affected by the fabrication or the temperature. If the generated dead-time is too short, then the power switches of the output-stage circuit of the PWM/PFM circuit may be simultaneously turned on, generating the large current, causing the power switches overheated and even broken-down. If the generated dead-time is too long, the efficiency of the PWM/PFM circuit is reduced. Therefore, in design for the PWM/PFM circuit, the dead-time has to be properly designed and steadily controlled.
SUMMARY OF THE INVENTION
The present invention provides a dead-time detecting circuit. The dead-time detecting circuit is coupled between an output-stage circuit and a previous-stage circuit. The dead-time detecting circuit is utilized for detecting dead-time of the output-stage circuit. An output end of the output-stage circuit is coupled to an inductive load. A first resistor of the dead-time detecting circuit is coupled between a first voltage source and a second end of a first transistor of the dead-time detecting circuit. A first end of the first transistor is coupled to the output end of the output-stage circuit for receiving an output voltage of the output-stage circuit. A control end of the dead-time detecting circuit controls operation of the first transistor according to a controlling voltage. When relation between the output voltage and the controlling voltage conforms to a predetermined relation, the second end of the first transistor outputs a dead-time detecting signal representing turning on to the previous-stage circuit for the previous-stage circuit urging the output-stage circuit to leave a dead-time state.
The present invention further provides a dead-time detecting circuit. The dead-time detecting circuit is coupled between an output-stage circuit and a previous-stage circuit. The dead-time detecting circuit is utilized for detecting a dead-time of the output-stage circuit. The output-stage circuit is coupled to an inductive load. The dead-time detecting circuit comprises a first dead-time detector, and a second dead-time detector. The first dead-time detector is coupled between a first voltage source and an output end of the output-stage circuit. The first dead-time detector is utilized for outputting a first dead-time detecting signal according to a first predetermined relation. The second dead-time detector is coupled between a second voltage source and the output end of the output-stage circuit. The second dead-time detector is utilized for outputting a second dead-time detecting signal according to a second predetermined relation. When the first dead-time detecting signal or the second dead-time detecting signal represents turning on, the output-stage circuit leaves a dead-time state. The first voltage source is a high voltage source, and the second voltage source is a low voltage source.
The present invention further provides a modulation circuit of detecting dead-time. The modulation circuit of detecting dead-time comprises an output-stage circuit, a previous-stage circuit, and a dead-time detecting circuit. The output-stage circuit is utilized for providing an output signal to an inductive load. The previous-stage circuit is coupled to the output-stage circuit. The previous-stage circuit is utilized for providing a switch-driving signal to the output-stage circuit so as to control operation of the output-stage circuit. The dead-time detecting circuit is coupled between the previous-stage circuit and the output-stage circuit. The dead-time detecting circuit is utilized for detecting a dead-time of the output-stage circuit. The dead-time detecting circuit outputs a dead-time detecting signal to the previous-stage circuit according to a predetermined relation. The previous-stage circuit urges the output-stage circuit to leave a dead-time state according to the dead-time detecting signal.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram illustrating a PWM/PFM circuit of the present invention.
FIG. 2 is a diagram illustrating a dead-time detecting circuit of the present invention.
FIG. 3 is a diagram illustrating a dead-time detecting circuit realized with an N-type dead-time detector.



DETAILED DESCRIPTION
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a PWM/PFM circuit 100 of the present invention. The PWM/PFM circuit 100 is utilized for converting an input signal SI into an output signal SOUT, and providing the output signal SOUT to an inductive load L. The PWM/PFM circuit 100 comprises an output-stage circuit 110, a previous-stage circuit 120, and a dead-time detecting circuit 130.
The previous-stage circuit 120 comprises input ends I1, I2, and I3, and output ends O1, and O2. The input ends I1, I2, and I3 of the previous-stage circuit 120 receives the input signal SI, dead-time detecting signals SDP, and SDN, respectively. The output ends O1, and O2 of the previous-stage circuit 120 respectively generates switch-driving signals SSWPD and SSWPN according to the input signal SI, and the dead-time detecting signals SDP, and SDN. More particularly, the previous-stage circuit 120 generates the switch-driving signals SSWPD and SSWND according to the input signal SI, respectively. For avoiding the power switches Q1 and Q2 of the output-stage circuit 110 being turned on at the same time, the previous-stage circuit 120 generates the switch-driving signals SSWPD and SSWND both representing “OFF” for a predetermined period so as to turn off the power switches of the output-stage circuit 110, causing the output-stage circuit 110 to enter the “dead-time” state. However, when the output-stage circuit 110 is in the “dead-time” state, if the previous-stage circuit 120 receives the dead-time detecting signal SDP/SDN representing “ON”, the previous-stage circuit 120 accordingly changes the switch-driving signal SSWPD/SSWNDN from representing “OFF” to representing “ON” so that the output-stage circuit 110 leaves the “dead-time” state.
The output-stage circuit 110 comprises a P type power switch Q1 and an N-type power switch Q2. In a preferred embodiment, the P-type power switch Q1 can be realized with a P-channel Metal Oxide Semiconductor (PMOS) transistor, and the N-type power switch Q2 can be realized with an N channel Metal Oxide Semiconductor (NMOS) transistor.
The first end (source) of the P-type power switch Q1 is coupled to a voltage source VDD; the second end (drain) of the P-type power switch Q1 is coupled to an output end O of the PWM/PFM circuit 100 (one end of the inductive load L); the control end (gate) of the P-type power switch Q1 is coupled to the output end O1 of the previous-stage circuit 120, for receiving the switch-driving signal SSWPD. When the switch-driving signal SSWPD represents “ON”, the P-type power switch Q1 is turned on so that the voltage VDD provided by the voltage source VDD can be transmitted to the output end O of the PWM/PFM circuit 100; when the switch-driving signal SSWPD represents “OFF”, the P-type power switch Q1 is turned off so that the voltage VDD can not be transmitted through the P-type power switch Q1 to the output end O.
The first end (source) of the N-type power switch Q2 is coupled to a voltage source VSS; the second end (drain) of the N-type power switch Q2 is coupled to the output end O of the PWM/PFM circuit 100; the control end (gate) of the N-type power switch Q2 is coupled to the output end O2 of the previous-stage circuit 120, for receiving the switch-driving signal SSWPN. When the switch-driving signal SSWPN represents “ON”, the N-type power switch Q2 is turned on so that the voltage VSS (provided by the voltage source VSS) can be transmitted to the output end O of the PWM/PFM circuit 100; when the switch-driving signal SSWPN represents “OFF”, the N-type power switch Q2 is turned off so that the voltage VSS can not be transmitted through the N-type power switch Q2 to the output end O of the PWM/PFM circuit 100. In a preferred embodiment of the present invention, the voltage source VDD represents a voltage source providing the high voltage VDD; the voltage source VSS represents a voltage source providing the low voltage VSS (for example, the ground).
In addition, the P-type power switch Q1 has a parasitic diode D1, which is coupled between the first end and the second end of the P-type power switch Q1. The N-type power switch Q2 has a parasitic diode D2, which is coupled between the first end and the second end of the N-type power switch Q2. Hence, when the output-stage circuit 110 is in the dead-time state (the power switches Q1 and Q2 are both turned off), if the inductive load L discharges current to the voltage source VDD through the parasitic diode D1, the output voltage on the output end O is equal to (VDD+VD1), wherein VD1 represents the forward voltage of the parasitic diode D1. When the output-stage circuit 110 is in the dead-time state, if the inductive load L discharges current to the voltage source VSS through the parasitic diode D2, the output voltage VO on the output end O is equal to (VSS−VD2), wherein VD2 represents the forward voltage of the parasitic diode D2.
The dead-time detecting circuit 130 comprises an input end I, and output ends OP and ON. The input end I is coupled to the output end O of the PWM/PFM circuit 100, for receiving the output voltage VO. The output end OP of the dead-time detecting circuit 130 is coupled to the input end I2 of the previous-stage circuit 120, for transmitting the dead-time detecting signal SDP; The output end ON of the dead-time detecting circuit 130 is coupled to the input end I3 of the previous-stage circuit 120, for transmitting the dead-time detecting signal SDN. As a result, the dead-time detecting circuit 130 can determine if the output-stage circuit 110 is in the dead-time state and if the inductive load L discharges current to the voltage sources VDD or VSS according to the output voltage VO, and the dead-time detecting circuit 130 accordingly generates the dead-time detecting signals SDP or SDN representing “ON” to the previous-stage circuit 120 so as to turn on the power switches Q1 or Q2.
Please refer to FIG. 2. The dead-time detecting circuit 130 comprises an N-type dead-time detector 131, a P-type dead-time detector 132, and a current-limiting resistor RL. The N-type dead-time detector 131 comprises an N-type transistor Q3, a resistor RXN, and a waveform trimmer 1311. The first end (source) of the N-type transistor Q3 is coupled to the input end I of the dead-time detecting circuit 130 through the current-limiting resistor RL, for receiving the output voltage VO. The current-limiting resistor RL is utilized to avoid the inductive load L discharging too much current to the dead-time detecting circuit 130. The second end (drain) of the N-type transistor Q3 is coupled to the resistor RXN, for generating the previous-stage dead-time detecting signal SDNP; the control end (gate) of the N-type transistor Q3 is utilized for receiving a gate-controlling voltage VG—BIASN. The resistor RXN is coupled between the second end of the N-type transistor Q3 and the voltage source VDD. The waveform trimmer 1311 is coupled between the second end of the N-type transistor Q3 and the output end ON, for trimming the waveform of the previous-stage dead-time detecting signal SDNP, and accordingly outputting the dead-time detecting signal SDN. The waveform trimmer 1311 can be realized with an inverter INVN. In addition, assuming that the voltage drop across the current-limiting resistor RL, and the voltage drops across the power switches Q1 and Q2 can be ignored, the gate-controlling voltage VG—BIASN can be designed as following formulas:

(VSS+VT3)>VG—BIASN>VT3+(VSS−VD2)  (1); and

VGS3≧[VT3+(VSS−VD2)−VO];

wherein VO=VSS−VD2, and VT3 represents the threshold voltage of the N-type transistor Q3; the operational principle of the N-type dead-time detector 131 is illustrated as below.

When the output voltage VO is not lowered to (VSS−VD2), it means that the output voltage VO is higher than (VSS−VD2). The gate-source voltage VGS3 of the N-type transistor Q3 is equal to [VT3+(VSS−VD2)−VO] at the time. Since the output voltage is not lowered to (VSS−VD2), the gate-source voltage VGS3 is not higher than the threshold voltage VT3 of the N-type transistor Q3 at the time so that the N-type transistor Q3 is turned off. In this way, the previous-stage dead-time detecting signal SDNP is pulled up to the high voltage level VDD by the voltage source VDD through the resistor RXN; the inverter INVN outputs dead-time detecting signal SDN representing “OFF” by inverting the previous-stage dead-time detecting signal SDNP, and the dead-time detecting signal SDN is at the low voltage level at the time.
When the output voltage VO is lowered to (VSS−VD2), it means that the output voltage VO is equal to the voltage (VSS−VD2) or the output voltage Vo is lower than the voltage (VSS−VD2), the output-stage circuit 110 is in the dead-time state (both the power switches Q1 and Q2 are turned off) and the inductive load L discharges through the voltage source VSS. The voltage level of the gate-source voltage VGS3 of the N-type transistor Q3 is [VT3+(VSS−VD2)−VO] at the time. Since the output voltage is lowered to (VSS−VD2), the gate-source voltage VGS3 is higher than the threshold voltage VT3 of the N-type transistor Q3 at the time so that the N-type transistor Q3 is turned on. In this way, the previous-stage dead-time detecting signal SDNP is pulled down to the low voltage level through the N-type transistor Q3; the inverter INVN outputs dead-time detecting signal SDN representing “ON” by inverting the previous-stage dead-time detecting signal SDNP, and the dead-time detecting signal SDN is at the high voltage level so that the output-stage circuit 110 leaves the “dead-time” state. That is, the N-type dead-time detector 131 of the present invention can detect the status of the output-stage circuit 110 and the inductive load L so as to turn on the N-type power switch Q2 of the output-stage circuit 110 in time when the output-stage circuit 110 is in the dead-time state and the inductive load L discharges through the voltage source VSS. In this way, the dead-time of the output-stage circuit 110 is efficiently reduced, improving the efficiency of the PWM/PFM circuit 100.
The P-type dead-time detector 132 comprises a P-type transistor Q4, a resistor RXP, and a waveform trimmer 1321. The first end (source) of the P-type transistor Q4 is coupled to the input end I of the dead-time detecting circuit 130 through the current-limiting resistor RL, for receiving the output voltage VO. The second end (drain) of the P-type transistor Q4 is coupled to the resistor RXP, for generating the previous-stage dead-time detecting signal SDPP. The control end (gate) of the P-type transistor Q4 is utilized for receiving a gate-controlling voltage VG—BIASP. The resistor RXP is coupled between the second end of the P-type transistor Q4 and the voltage source VSS. The waveform trimmer 1312 is coupled between the second end of the P-type transistor Q4 and the output end OP, for trimming the waveform of the previous-stage dead-time detecting signal SDPP so as to output the dead-time detecting signal SDP. The waveform trimmer 1312 can be realized with an inverter INVP. In addition, assuming that the voltage drop across the current-limiting resistor RL, and the power switches Q1 and Q2 can be ignored, the gate-controlling voltage VG—BIASP can be designed as following formulas:

VDD−VT4<VG—BIASP<VDD−VT4+VD1  (2); and

VSG4≧[VO−(VDD−VT4+VD1)];

wherein VO=VDD+VD1, and VT4 represents the threshold voltage of the P-type transistor Q4; the operational principle of the P-type dead-time detector 132 is illustrated as below.

When the output voltage VO is not raised up to (VDD+VD1), the gate-source voltage VSG4 of the P-type transistor Q4 is equal to [VO−(VDD−VT4+VD1)]. Since the output voltage is not raised up to (VDD+VD1), the gate-source voltage VSG4 is not higher than the threshold voltage VT4 of the P-type transistor Q4 at the time so that the P-type transistor Q4 is turned off. In this way, the previous-stage dead-time detecting signal SDPP is pulled down to the low voltage level VSS by the voltage source VSS through the resistor RXP; the inverter INVp outputs dead-time detecting signal SDP representing “OFF” by inverting the previous-stage dead-time detecting signal SDPP, and the dead-time detecting signal SDP is at the high voltage level. When the output voltage VO is raised up to (VDD+VD1), that is, when the output voltage VO is equal to the voltage (VDD+VD1) or is higher than the voltage (VDD+VD1), the output-stage circuit 110 is in the dead-time state and the inductive load L discharges through the voltage source VDD. Meanwhile, the voltage level of the gate-source voltage VSG4 of the P-type transistor Q4 is [VO−(VDD−VT4+VD1)]. Since the output voltage is raised up to (VDD+VD1), the gate-source voltage VGS4 is higher than the threshold voltage VT4 of the P-type transistor Q4 at the time so that the P-type transistor Q4 is turned on. In this way, the previous-stage dead-time detecting signal SDPP is pulled up to the high voltage level through the P-type transistor Q4; the inverter INVP outputs dead-time detecting signal SDP representing “ON” by inverting the previous-stage dead-time detecting signal SDPP, and the dead-time detecting signal SDP is at the low voltage level at the time so that the output-stage circuit 110 leaves the “dead-time” state. That is, the P-type dead-time detector 132 of the present invention can detect the status of the output-stage circuit 110 and the inductive load L so as to turn on the P-type power switch Q1 of the output-stage circuit 110 in time when the output-stage circuit 110 is in the dead-time state and the inductive load L discharges through the voltage source VDD. In this way, the dead-time is efficiently reduced, improving the efficiency of the PWM/PFM circuit 100.
In addition, in the embodiment of the present invention, the referred P-type transistor Q4 can be realized with a PMOS transistor, and the referred N-type transistor Q3 can be realized with an NMOS transistor.
Although the P-type and the N-type dead-time detector are both used in the dead-time detecting circuit of the present invention, however, the user can use only one of the dead-time detectors for efficiently detecting the dead-time of the output-stage circuit, according to the requirement in the practical application. Please refer to FIG. 3. The dead-time detecting circuit 330 only includes an N-type dead-time detector 131. The operational principle of the dead-time detecting circuit 330 is similar to the above-mentioned and will not be repeated again for brevity.
In conclusion, the dead-time detecting circuit provided by the present invention can determine if an output-stage circuit is in the dead-time state according to the output voltage of the output-stage circuit, and the dead-time detecting circuit of the present invention can turn on the power switch of the output-stage circuit in time for output-stage circuit leaving the dead-time state. In this way, the dead-time of the output-stage circuit can be dynamically adjusted so that the power switch of the output-stage circuit can be turned on in time for avoiding the turned-on parasitic diode of the power switch causing large power consumption. Thus, the distortion of the output signal is reduced and the efficiency of the PWM/PFM circuit is improved at the same time, providing a great convenience.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

## Claims

1. A dead-time detecting circuit, coupled between an output-stage circuit and a previous-stage circuit, for detecting a dead-time of the output-stage circuit, an output end of the output-stage circuit coupled to an inductive load, a first resistor of the dead-time detecting circuit coupled between a first voltage source and a second end of a first transistor of the dead-time detecting circuit, a first end of the first transistor coupled to the output end of the output-stage circuit for receiving an output voltage of the output-stage circuit, a control end of the dead-time detecting circuit controlling operation of the first transistor according to a controlling voltage, wherein when relation between the output voltage and the controlling voltage conforms to a predetermined relation, the second end of the first transistor outputs a dead-time detecting signal representing turning on to the previous-stage circuit for the previous-stage circuit urging the output-stage circuit to leave a dead-time state.

2. The dead-time detecting circuit of the claim 1, wherein the output-stage circuit comprises:
a first power switch, coupled between the first voltage source and the output end of the output-stage circuit; and
a second power switch, coupled between a second voltage source and the output end of the output-stage circuit;
wherein when both the first power switch and the second power switch are turned off, the output-stage circuit enters the dead-time state;
wherein voltage level of the first voltage source is higher than voltage level of the second voltage source.

3. The dead-time detecting circuit of claim 2, wherein the first transistor is an N-channel Metal-Oxide-Semiconductor (NMOS) transistor; the first power switch is a P-channel Metal-Oxide-Semiconductor (PMOS) transistor; the second power switch is an NMOS transistor;
wherein when the output-stage circuit enters the dead-time state and the inductive load discharges through the second voltage source, the relation between the output voltage and the controlling voltage conforms to the predetermined relation; and
wherein when the relation between the output voltage and the controlling voltage conforms to the predetermined relation, the first transistor outputs the dead-time detecting signal representing turning on for turning on the second power switch so that the output-stage circuit leaves the dead-time state.

4. The dead-time detecting circuit of claim 3, wherein the predetermined relation is:


(VSS+VT3)>VG_BIASN>VT3+(VSS−VD2); and



VGS3≧[VT3+(VSS−VD2)−VO ]; 

wherein VO=VSS−VD2;
wherein VG_BIASN represents the controlling voltage; VO represents the output voltage; VT3 represents a threshold voltage of the first transistor; VSS represents a voltage provided by the second voltage source; VD3 represents a forward voltage of a parasitic diode of the second power switch.

5. The dead-time detecting circuit of claim 1, wherein the dead-time detecting circuit further comprises a waveform trimmer, coupled to the second end of the first transistor, for trimming waveform of the dead-time detecting signal;
wherein the waveform trimmer includes an inverter.

6. The dead-time detecting circuit of claim 1, further comprising a current-limiting resistor, coupled between the first end of the first transistor and the output end of the output-stage circuit, for avoiding discharged current of the inductive load entering the dead-time detecting circuit.

7. A dead-time detecting circuit, coupled between an output-stage circuit and a previous-stage circuit, for detecting a dead-time of the output-stage circuit, the output-stage circuit coupled to an inductive load, the dead-time detecting circuit comprising:
a first dead-time detector, coupled between a first voltage source and an output end of the output-stage circuit, for outputting a first dead-time detecting signal according to a first predetermined relation; and
a second dead-time detector, coupled between a second voltage source and the output end of the output-stage circuit, for outputting a second dead-time detecting signal according to a second predetermined relation;
wherein when the first dead-time detecting signal or the second dead-time detecting signal represents turning on, the output-stage circuit leaves a dead-time state;
wherein the first voltage source is a high voltage source, and the second voltage source is a low voltage source.

8. The dead-time detecting circuit of the claim 7, wherein the output-stage circuit comprises:
a first power switch, coupled between the first voltage source and the output end of the output-stage circuit; and
a second power switch, coupled between the second voltage source and the output end of the output-stage circuit;
wherein when the first power switch and the second power switch are both turned off, the output-stage circuit enters the dead-time state.

9. The dead-time detecting circuit of the claim 8, wherein the first dead-time detector comprises a first transistor and a first resistor; wherein the first resistor is coupled between a second end of the first transistor and the first voltage source; wherein a first end of the first transistor is coupled to the output end of the output-stage circuit, for receiving an output voltage of the output-stage circuit, the second end of the first transistor for outputting a first dead-time detecting signal, a control end of the first transistor for receiving a first controlling voltage; wherein when relation between the output voltage and the first controlling voltage confirms to the first predetermined relation, the first transistor outputs the first dead-time detecting signal representing turning on; and
wherein the second dead-time detector comprises a second transistor and a second resistor; wherein the second resistor is coupled between a second end of the second transistor and the second voltage source; wherein a first end of the second transistor is coupled to the output end of the output-stage circuit, for receiving the output voltage of the output-stage circuit, the second end of the second transistor for outputting a second dead-time detecting signal, a control end of the second transistor for receiving a second controlling voltage; wherein when relation between the output voltage and the second controlling voltage confirms to the second predetermined relation, the second transistor outputs the second dead-time detecting signal representing turning on.

10. The dead-time detecting circuit of claim 9, wherein the first power switch is a PMOS transistor, and the second power switch is an NMOS transistor;
Wherein the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor;
wherein when the output-stage circuit enters the dead-time state and the inductive load discharges through the second voltage source, the relation between the output voltage and the first controlling voltage conforms to the first predetermined relation;
wherein when the relation between the output voltage and the first controlling voltage conforms to the first predetermined relation, the first transistor outputs the first dead-time detecting signal representing turning on for turning on the second power switch so that the output-stage circuit leaves the dead-time state.

11. The dead-time detecting circuit of claim 9, wherein the first predetermined relation is:


(VSS+VT3)>VG_BIASN>VT3+(VSS−VD2); and



VGS3≧[VT3+(VSS−VD2)−VO ]; 

wherein VO=VSS−VD2;
wherein VG_BIASN represents the controlling voltage; VO represents the output voltage; VT3 represents a threshold voltage of the first transistor; VSS represents a voltage provided by the second voltage source; VD2 represents a forward voltage of a parasitic diode of the second power switch.

12. The dead-time detecting circuit of claim 9, wherein when the output-stage circuit enters the dead-time state and the inductive load discharges through the first voltage source, the relation between the output voltage and the second controlling voltage conforms to the second predetermined relation.

13. The dead-time detecting circuit of claim 9, wherein when the relation between the output voltage and the second controlling voltage conforms to the second predetermined relation, the first transistor outputs the second dead-time detecting signal representing turning on for turning on the first power switch so that the output-stage circuit leaves the dead-time state.

14. The dead-time detecting circuit of claim 13, wherein the second predetermined relation is:


VDD−VT4<VG_BIASP<VDD−VT4+VD1; and



VSG4≧[VO−(VDD−VT4+VD1)];

wherein VO=VDD+VD1;
wherein VG_BIASP represents the second controlling voltage; VO represents the output voltage; VT4 represents a threshold voltage of the second transistor; VDD represents a voltage provided by the first voltage source, VD1 represents a forward voltage of a parasitic diode of the first power switch.

15. The dead-time detecting circuit of claim 9, wherein the first dead-time detector further comprises a first waveform trimmer, coupled to the second end of the first transistor, for trimming waveform of the first dead-time detecting signal; the second dead-time detector further comprises a second waveform trimmer, coupled to the second end of the second transistor, for trimming waveform of the second dead-time detecting signal;
wherein the first waveform trimmer comprises an inverter, and the second waveform trimmer comprises an inverter.

16. The dead-time detecting circuit of claim 9, further comprising a current-limiting resistor, coupled between the first end of the first transistor, the first end of the second transistor, and the output end of the output-stage circuit.

17. A modulation circuit for detecting dead-time, comprising:
an output-stage circuit, for providing an output signal to an inductive load;
a previous-stage circuit, coupled to the output-stage circuit, for providing a switch-driving signal to the output-stage circuit so as to control operation of the output-stage circuit; and
a dead-time detecting circuit, coupled between the previous-stage circuit and the output-stage circuit, for detecting a dead-time of the output-stage circuit, the dead-time detecting circuit outputting a dead-time detecting signal to the previous-stage circuit according to a predetermined relation, the previous-stage circuit urging the output-stage circuit to leave a dead-time state according to the dead-time detecting signal;
wherein the dead-time detecting circuit comprises a first transistor and a first resistor, the first resistor coupled between a first voltage source and a second end of the first transistor, a first end of the first transistor coupled to the output end of the output-stage circuit for receiving an output voltage of the output-stage circuit, a control end of the dead-time detecting circuit controlling operation of the first transistor according to a controlling voltage, wherein when relation between output voltage and the controlling voltage conforms to the predetermined relation, the second end of the first transistor outputs a dead-time detecting signal representing turning on to the previous-stage circuit for the previous-stage circuit urging the output-stage circuit to leave the dead-time state.

18. The modulation circuit for detecting dead-time of claim 17, wherein the output-stage circuit comprises:
a first power switch, coupled between a first voltage source and the output end of the output-stage circuit; and
a second power switch, coupled between a second voltage source and the output end of the output-stage circuit;
wherein when both the first power switch and the second power switch are turned off, the output-stage circuit enters the dead-time state;
wherein voltage level of the first voltage source is higher than voltage level of the second voltage source.

19. The modulation circuit for dead-time detecting circuit of claim 17, wherein the predetermined relation is:


(VSS+VT3)>VG_BIASN>VT3+(VSS−VD2); and



VGS3≧[VT3+(VSS−VD2)−VO]; 

wherein VO=VSS−VD2;
wherein VG_BIASN represents the controlling voltage; VO represents the output voltage; VT3 represents a threshold voltage of the first transistor; VSS represents voltage provided by the second voltage source; VD3 represents a forward voltage of a parasitic diode of the second power switch.