# Patent

## Title
Clock generator circuits for generating clock signals

## Abstract

The present invention relates to a circuit for generating a clock signal. The circuit comprises a current source to generate a reference current and provide a first voltage V1, a first current generator to generate a first mirror current during a first half cycle based on the reference current, a first capacitor including a first end, and a first transistor having a first threshold voltage VTH1. The first transistor includes a gate to receive the first voltage V1, a drain coupled to the first current generator and a source coupled to the first end of the first capacitor so as to allow the first mirror current to charge the first capacitor during the first half cycle, wherein the period of the first half cycle is a function of the first bias voltage V1 minus the first threshold voltage VTH1.

## Background
BACKGROUND OF THE INVENTION
The present invention generally relates to clock generator circuits. More particularly, the present invention relates to clock generator circuits for providing stable clock signals and double frequency clock signals in memory devices. The clock generator circuits in accordance with the present invention may serve as an oscillator or a frequency doubler.
Clock circuits play an important role in modern electronic products. Generally, a clock signal generated by a clock circuit within an integrated circuit or on a printed circuit board of an electronic device is used for signal synchronization in the electronic device. Moreover, a clock circuit may generate clock signals at different clock rates for applications requiring different operation frequencies. The clock signals of different clock rates may be generated by multiplying or dividing the frequency of a reference clock signal.
A clock signal may be generated by a resistance-capacitance (RC) delay circuit. FIG. 1 is a circuit diagram of an RC delay clock generator 10 in prior art. Referring to FIG. 1, the RC delay clock generator 10 may include resistors R1 and R2 and capacitors C1 and C2, wherein R1 and C1 form a first RC delay circuit and R2 and C2 form a second RC delay circuit. Under the control of a clock enable signal Clken, an output clock signal Clkout of the clock generator 10 may be generated. The output clock signal Clkout has a period T1 equal to R1C1+R2C2. However, the clock generator 10 may be susceptible to variations in supply voltage VDD and temperature, which may cause deviations in the time constants R1C1 and R2C2, resulting in an unstable and unreliable output clock signal Clkout.
To address the issue, a clock circuit substantially free from the VDD and temperature variations has been proposed. FIG. 2 is a circuit diagram of a clock generator 20 in prior art. Referring to FIG. 2, the clock generator 20 may include a bandgap circuit 21 and a constant current generator 22. The bandgap circuit 21 may generate a reference current IREF and a reference voltage VREF. The current generator 22 may generate a bias voltage Vbias, which may cause the generation of a mirror current ICONST based on the reference current IREF. Under the control of a clock enable signal Clken, an output clock signal Clkout has a period T2 equal to 2C (VREF/ICONST), where “C” represents the capacitance of capacitors C3 and C4 in the clock generator 20. Although the clock generator 20 may provide a more stable and reliable output clock signal than the clock generator 10 illustrated in FIG. 1, the bandgap circuit 21 may be so complicated as to render the clock generator 20 cost ineffective or chip area inefficient in some applications. Moreover, the setup time of the bandgap circuit 21, on the order of several microseconds (us), may not be acceptable in certain applications.
Like the clock generators, frequency multipliers and dividers may also suffer VDD and temperature variations. FIG. 3A is a circuit diagram of a frequency multiplier 30 in prior art. Referring to FIG. 3A, the frequency multiplier 30 includes an RC delay one-shot pulse circuit, which generates an output clock signal Clkout in response to external clock signals Clkext. FIG. 3B is a diagram illustrating the waveforms of the external clock signals Clkext, the output clock signal Clkout and the signals at points “a” and “b” in FIG. 3A. Given a 50% duty cycle, the pulse widths of the signals at points “a” and “b” may be significantly smaller (shown in solid lines) or greater (shown in dashed lines) than a desired one due to variations in VDD and temperature, resulting in deviations in the output clock signal Clkout. To address the issue, a phase lock loop (PLL) may be used to track and stabilize the duty cycle. However, PLL may cause other issues such as stability and design complexity.
It may therefore be desirable to have a clock generator that is able to alleviate the issue of VDD and temperature variations and may be designed in a relatively simple structure.
BRIEF SUMMARY OF THE INVENTION
Examples of the present invention may provide a circuit for generating a clock signal. The circuit comprises a current source to generate a reference current and provide a first voltage V1, a first current generator to generate a first mirror current during a first half cycle based on the reference current, a first capacitor including a first end, and a first transistor having a first threshold voltage VTH1. The first transistor includes a gate to receive the first voltage V1, a drain coupled to the first current generator and a source coupled to the first end of the first capacitor so as to allow the first mirror current to charge the first capacitor during the first half cycle, wherein the period of the first half cycle is a function of the first bias voltage V1 minus the first threshold voltage VTH1.
Some examples of the present invention may also provide a circuit for generating a clock signal. The circuit comprises a first current generator to generate a first mirror current, a first capacitor, a first transistor coupled between the first current generator and the first capacitor, and a first discharging transistor. The first transistor having a first threshold voltage VTH1 includes a gate to receive a first voltage V1 and allows the first mirror current to charge the first capacitor during a first half cycle. Furthermore, the first discharging transistor allows the first capacitor to discharge during a second half cycle.
Examples of the present invention may further provide a circuit for generating a clock signal. The circuit comprises a first current generator to generate a first mirror current, a first capacitor, a first transistor coupled between the first current generator and the first capacitor to allow the first mirror current to charge the first capacitor during a first half cycle, a second current generator to generate a second mirror current, a second capacitor, and a second transistor coupled between the second current generator and the second capacitor to allow the second mirror current to charge the second capacitor during a second half cycle. The period of the clock signal is a function of (V1−VTH1) and (V1−VTH2), where V1 is a voltage to bias the first and the second transistors, and VTH1 and VTH2 are the threshold voltages of the first and the second transistors, respectively.
Examples of the present invention may also provide a clock generator circuit. The clock generator circuit may include a current source and a first clock circuit. The first clock circuit may be coupled to the current source. The first clock circuit may include a first current generator comprising a first transistor and a second transistor, wherein a source of the first transistor may be coupled to a power supply and a drain of the first transistor may be coupled to a source of the second transistor. The first clock circuit may also include a third transistor of which a drain may be coupled to a drain of the second transistor, a fourth transistor of which a drain may be coupled to a source of the third transistor and a source may be grounded, and a first capacitor of which a first end may be coupled to the source of the third transistor and the drain of the fourth transistor and a second end may be grounded.
Additional features and advantages of the present invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.



BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings examples which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.
In the drawings:
FIG. 1 is a circuit diagram of a resistance-capacitance (RC) delay clock generator in prior art;
FIG. 2 is a circuit diagram of another clock generator in prior art;
FIG. 3A is a circuit diagram of a frequency multiplier in prior art;
FIG. 3B is a diagram illustrating the waveforms of an external clock signal and an output clock signal of the frequency multiplier illustrated in FIG. 3A;
FIG. 4A is a circuit diagram of a current source according to an example of the present invention;
FIG. 4B is a circuit diagram of a current source according to another example of the present invention;
FIG. 5A is a circuit diagram of a clock generator to serve as an oscillator according to an example of the present invention;
FIG. 5B is a diagram illustrating the drain voltage levels of a first transistor and a first discharging transistor of the clock generator illustrated in FIG. 5A;
FIG. 6A is a circuit diagram of a clock generator to serve as frequency doubler according to an example of the present invention; and
FIG. 6B is a diagram illustrating the waveforms of an external clock signal and an output clock signal of the clock generator illustrated in FIG. 6A.



DETAILED DESCRIPTION OF THE INVENTION
Reference will now be made in detail to the present examples of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
FIG. 4A is a circuit diagram of a current source 40 according to an example of the present invention. Referring to FIG. 4A, the current source 40 may include a current mirror 42, a first buffer 40-1 and a second buffer 40-2. The current mirror 42 may include n-type metal-oxide-semiconductor (NMOS) field effect transistors 401 and 402 and p-type metal-oxide-semiconductor (PMOS) field effect transistors 403 and 404. In the current mirror 42, a reference current IREF flowing through the transistors 403 and 401 may “mirror” a current IPTAT flowing through the transistors 404 and 402. The current IPTAT may vary in a way “proportional to absolute temperature” (PTAT). That is, the current IPTAT may vary directly or positively proportionally as the absolute temperature varies. The current IPTAT may be expressed in an equation below.

IPTAT =[2/(μnCox(W/L)n)][(1/R)(1−1/√{square root over ( )}k)]2,

wherein “R” is the resistance of a resistor 405, μn is the dielectric constant of the NMOS transistors 402, Cox is the capacitance of oxide in the NMOS transistors 402, (W/L)n is a width-to-length ratio of the NMOS transistors 402 and “k” is a ratio of the area of the transistor 401 to the area of the transistor 402.
The current source 40 may provide a first voltage V1 at an output of the first buffer 40-1, and a second voltage V2 at an output of the second buffer 40-2. The first buffer 40-1 may include a non-inverting terminal coupled to the gates of the NMOS transistors 401 and 402, and an inverting terminal coupled via a feedback path with the output V1. The second buffer 40-2 may include a non-inverting terminal coupled to the gates of the PMOS transistors 403 and 404, and an inverting terminal coupled via a feedback path with the output V2. The first and second buffers 40-1 and 40-2, each being configured to serve as a voltage follower in the present example, may enhance the driving ability of the current source 40. Specifically, the values of the first and second voltages V1 and V2 may be compensated or automatically adjusted via the feedback paths.
In other examples, the first and second buffers 40-1 and 40-2 may be eliminated so that the first voltage V1 may be provided at the gates of the NMOS transistors 401 and 402 and the second voltage V2 may be provided at the gates of the PMOS transistors 403 and 404.
FIG. 4B is a circuit diagram of a current source 41 according to another example of the present invention. Referring to FIG. 4B, the current source 41 may be similar to the current source 40 illustrated in FIG. 4A except that, for example, a first capacitor 41-1 and a second capacitor 41-2 replace the first buffer 40-1 and the second buffer 40-2, respectively. The first capacitor 41-1 may be coupled between a reference or ground potential and the gates of the NMOS transistors 401 and 402. The second capacitor 40-2 may be coupled between the ground potential and the gates of the PMOS transistors 403 and 404. The capacitors 41-1 and 41-2 may be configured to maintain the first and second voltages V1 and V2 substantially constant. Both of the current sources 40 and 41 respectively described and illustrated with reference to FIG. 4A and FIG. 4B can keep relatively stable voltage in V1 and V2 without the coupling effect issue.
FIG. 5A is a circuit diagram of a clock generator 50 to serve as an oscillator according to an example of the present invention. Referring to FIG. 5A, the clock generator 50 may include a first clock circuit 51, a second clock circuit 52, a latch circuit 53 and a current source 54. The current source 54 may be similar to one of the current sources 40 and 41 described and illustrated with reference to FIGS. 4A and 4B, respectively, and thus may generate the current IPTAT and provide the first and second voltages V1 and V2. The first clock circuit 51 may include a first current generator 510, a first transistor (NMOS) MN11, a first capacitor C51 and a first discharging transistor MN12. The first current generator 510, further comprising a first PMOS transistor MP11 and a second PMOS transistor MP12, may generate a first mirror current I1 that is a multiple of the current IPTAT. In the present example, it is assumed that the first mirror current I1 equals the current IPTAT. The first PMOS transistor MP11 may include a source coupled to a voltage supply VDD. The second PMOS transistor MP12 may include a gate biased at the second voltage V2 and a source coupled to the drain of the first PMOS transistor MP11. The first transistor MN11 may include a gate biased at the first voltage V1, a drain coupled to the drain of the second PMOS transistor MP12, and a source coupled to one end (not numbered) of the first capacitor C51. The first discharging transistor MN12 may include a drain coupled to the one end of the first transistor C51. Skilled persons in the art will understand that the source and drain of a transistor may be interchangeable, depending on the voltages applied thereto.
Similarly, the second clock circuit 52 may include a second current generator 520, a second transistor (NMOS) MN21, a second capacitor C52 and a second discharging transistor MN22. The second current generator 520, further comprising a first PMOS transistor MP21 and a second PMOS transistor MP22, may generate a second mirror current I2 substantially equal to IPTAT. The first PMOS transistor MP21 may include a source coupled to the voltage supply VDD. The second PMOS transistor MP22 may include a gate biased at the second voltage V2 and a source coupled to the drain of the first PMOS transistor MP21. The second transistor MN21 may include a gate biased at the first voltage V1, a drain coupled to the drain of the second PMOS transistor MP22, and a source coupled to one end (not numbered) of the second capacitor C52. The second discharging transistor MN22 may include a drain coupled to the one end of the second transistor C52.
The latch circuit 53 may include a first NAND gate 531 and a second NAND gate 532 cross-coupled to each other. The first NAND gate 531 may include a first input coupled with the drain of the second transistor MN21 of the second clock circuit 52 via a first inverter 541, and a second input coupled to an output of the second NAND gate 532. The second NAND gate 532 may include a first input coupled with the drain of the first transistor MN11 of the first clock circuit 51 via a second inverter 542, a second input coupled with an output of the first NAND gate 531, and a third input to receive an enable signal Clken. Furthermore, the output of the first NAND gate 531 may be coupled with the gates of the first PMOS transistor MP11 and the first discharging transistor MN12 of the first clock circuit 51 via a third inverter 543. The output of the second NAND gate 532 may be coupled with the gates of the first PMOS transistor MP21 and the second discharging transistor MN22 of the second clock circuit 52 via a fourth inverter 544.
It may be assumed that initially the drain voltage Vp of the first transistor MN11 and the drain voltage Vn of the second transistor MN21 are below the trigger points of the second and first inverters 542 and 541, respectively, and thus are not able to turn on the first and second inverters 541 and 542. The outputs of the first and second inverters 541 and 542 are therefore at a logic “high” level. Furthermore, it may be assumed that initially the output of the first NAND gate 531 is logic high and the output of the second NAND gate 532 is logic low. In operation, when the enable signal Clken is asserted, that is, changed to a logic high level, the output of the second NAND gate 532 is logic low and the output of the fourth NAND gate 544, “Ck”, is logic high. Meanwhile, the output of the third NAND gate 543, “Ckb”, is logic low because Ckb is the complement of Ck. The logic low Ckb may turn on the first PMOS transistor MP11 and turn off the first discharging transistor MN12, which allows the first mirror current I1 to charge the first capacitor C51. The drain voltage of the first discharging transistor MN12, “Vp1”, may increase during the charging process until it reaches V1−VTH1, where VTH1 is the threshold voltage of the first transistor MN11. The first transistor MN11 may be turned off as Vp1 reaches V1−VTH1, and at that time the drain voltage Vp of the first transistor MN11 may quickly rise above the trigger point of the second inverter 542, which turns on the second inverter 542 and switches the output of the second inverter 542 from logic high to logic low. Consequently, the output Ck switches to logic low while the output Ckb switches to logic high.
The logic high Ckb may turn off the first PMOS transistor MP11 and turn on the first discharging transistor MN12, which cuts off the first mirror current I1 and allows the first capacitor C51 to discharge through the first discharging transistor MN12. Meanwhile, the logic low Ck may turn on the first PMOS transistor MP21 and turn off the second discharging transistor MN22, which allows the second mirror current I2 to charge the second capacitor C52. The drain voltage of the second discharging transistor MN22, “Vn1”, may increase during the charging process until it reaches V1−VTH2, where VTH2 is the threshold voltage of the second transistor MN21. The second transistor MN21 may be turned off as Vn1 reaches V1−VTH2, and at that time the drain voltage Vn of the second transistor MN21 may quickly rise above the trigger point of the first inverter 541, which turns on the first inverter 541 and switches the output of the first inverter 541 from logic high to logic low. Consequently, the output Ckb switches to logic low while the output Ck switches to logic high.
Accordingly, the clock generator 50 may generate at an output of an inverter 55 a clock signal Clkout that has a first state, logic low in the present example, during a first half cycle and a second state, logic high, during a second half cycle. The first half cycle may refer to a period when the first capacitor C51 is charged from approximately the ground level to V1−VTH1, and the second half cycle may refer to a period when the second capacitor C52 is charged from approximately the ground level to V1−VTH2. The period t1 of the first half cycle may be calculated below.

t1=C51(V1−VTH1)/I1 

Likewise, the period t2 of the second half cycle may be calculated below.

t2=C52(V1−VTH2)/I2 

Accordingly, we may obtain the period “T” of the clock signal Clkout:

T=C51(V1−VTH1)/I1+C52(V1−VTH2)/I2; or

T=2C (V1−VTHI)/I1, if the first clock circuit 51 is symmetrical to the second clock circuit 52 so that C51 equals C52, VTH1 equals VTH2 and I1 equals I2, which may facilitate a 50% duty cycle.
The clock generator 50 may alleviate the issue of VDD variation because the first and second capacitors C51 and C52, unlike the RC delay circuits illustrated in FIGS. 1 and 3, wherein the capacitors are charged to approximately 1⁄2 VDD, are only charged to V1−VTH1 and V1−VTH2, respectively. In one example according to the present invention, V1 may range from approximately 0.8 to 1 volt (V) and VTH1 and VTH2 may range from approximately 0.3 to 0.4V, given a VDD of 1.8 to 3V. Furthermore, the clock generator 50 may compensate for the temperature variation by means of a temperature compensation mechanism as described below. Generally, the threshold voltage of a transistor may vary inversely as the temperature varies. Furthermore, as previously discussed, the mirror currents I1 and 12 may vary directly as the absolute temperature varies. As a result, when the temperature increases, the first and second mirror currents I1 and 12 may also increase, and the threshold voltages VTH1 and VTH2 may decrease. The lower VTH1 and VTH2 may prolong the charging time or the periods of the first and second half cycles but the larger charging currents I1 and I2 may reduce the charging time, resulting in substantially the same charging time. Consequently, the periods of the first and second half cycles may not be significantly changed due to the temperature variation.
FIG. 5B is a diagram illustrating the drain voltage levels of the first transistor MN11 and the first discharging transistor MN12 of the clock generator 50 illustrated in FIG. 5A. Referring to FIG. 5B, the drain voltage Vp1 of the first transistor MN11 may increase due to the charging process during the first half cycle t1, and the drain voltage Vp of the first discharging transistor MN12 may exceed the trigger point of the second inverter 542 as Vp1 reaches V1−VTH1. Furthermore, Vp1 and Vp may be maintained at the reference or ground level due to the discharging process during the second half cycle t2.
FIG. 6A is a circuit diagram of a clock generator 60 to serve as a frequency doubler according to another example of the present invention. Referring to FIG. 6A, the clock generator 60 may be similar to the clock generator 50 described and illustrated with reference to FIG. 5A except that, for example, the latch circuit 53 of the clock generator 50 may be replaced by a multiplier circuit 63. With the multiplier circuit 63, the clock generator 60 may serve as a frequency doubler. The multiplier circuit 63 may include a first NAND gate 631, a third inverter 633 in series with the first NAND gate 631, a second NAND gate 632, a fourth inverter 634 in series with the second NAND gate 632, and a NOR gate 635. The first NAND gate 631 may include a first input to receive a first external clock signal Clkext, and a second input coupled to the output of the second inverter 542. The second NAND gate 632 may include a first input to receive a second external clock signal Clkextb, which is the complement of the first external clock signal Clkext as a function of an inverter 64, and a second input coupled to the output of the first inverter 541. The NOR gate 635 may include a first input “c” coupled to the output of the third inverter 633, a second input “d” coupled to the output of the fourth inverter 634, and an output coupled to an inverter 65 at which an output clock signal Clkout is outputted. Furthermore, the first external signal Clkext may be coupled to the gates of the first PMOS transistor MP21 and the second discharging transistor MN22, and the second external signal Clkextb may be coupled to the gates of the first PMOS transistor MP11 and the first discharging transistor MN12.
In operation, it may be assumed that initially the first external signal Clkext is logic low while the second external signal Clkextb is logic high. The logic low Clkext may turn on the first PMOS transistor MP21 and turn off the second discharging transistor MN22, which allows the second mirror current I2 to charge the second capacitor C52. The drain voltage of the second discharging transistor MN22, “Vn1”, may increase during the charging process until it reaches V1−VTH2. The second transistor MN21 may be turned off as Vn1 reaches V1−VTH2, and at that time the drain voltage Vn of the second transistor MN21 may quickly rise above the trigger point of the first inverter 541, which turns on the first inverter 541 and switches the output of the first inverter 541 from logic high to logic low.
On the other hand, the logic high Clkextb may turn off the first PMOS transistor MP11 and turn on the first discharging transistor MN12, which cuts off the first mirror current I1 and allows the first capacitor C51 to discharge, resulting in a low voltage level Vp not able to turn on the second inverter 542 so that the output of the second inverter 542 may be maintained at logic high.
As a result, the logic low Clkext and the logic high output of the second inverter 542, by the function of the first NAND gate 631 and the third inverter 633, result in a logic low first input “c” to the NOR gate 635. Moreover, the logic high Clkextb and the logic low output of the first inverter 541, by the function of the second NAND gate 632 and the fourth inverter 634, result in a logic low second input “d” to the NOR gate 635.
Next, when the first external signal Clkext is asserted, that is, changed to logic high, the second external signal Clkextb is logic low. The logic high Clkext and the logic high output of the second inverter 542 result in a logic high first input “c” to the NOR gate 635. That is, the first input “c” is changed from logic low to logic high in response to the rising edge of the first external signal Clkext. Moreover, the logic low Clkextb and the logic low output of the first inverter 541 maintain the second input “d” at logic low. Meanwhile, the logic low Clkextb may turn on the first PMOS transistor MP11 and turn off the first discharging transistor MN12, which allows the first mirror current I1 to charge the first capacitor C51. The drain voltage of the first discharging transistor MN12, “Vp1”, may increase during the charging process until it reaches V1−VTH1. The first transistor MN11 may be turned off as Vp1 reaches V1−VTH1, and at that time the drain voltage Vp of the first transistor MN11 may quickly rise above the trigger point of the second inverter 542, which turns on the second inverter 542 and switches the output of the second inverter 542 from logic high to logic low.
On the other hand, the logic high Clkext may turn off the first PMOS transistor MP21 and turn on and the second discharging transistor MN22, resulting in a low voltage level Vn not able to turn on the first inverter 541 so that the output of the first inverter 541 is changed to logic high. As a result, the logic high Clkext and the logic low output of the second inverter 542 switch the logic high first input “c” to logic low. Moreover, the logic low Clkextb and the logic high output of the first inverter 541 still maintain the second input “d” at logic low. That is, the first input “c” may transit from low to high and then from high to low during the assertion of the first external signal Clkext, and the second input “d” is kept at logic low during the assertion of the first external signal Clkext. Similarly, the second input “d” may transit from low to high and then from high to low during the assertion of the second external signal Clkextb, and the first input “c” is kept at logic low during the assertion of the second external signal Clkextb.
FIG. 6B is a diagram illustrating the waveforms of the first external clock signal Clkext, the signals at the first and second inputs “c” and “d”, and the output clock signal Clkout of the clock generator 60 described and illustrated with reference to FIG. 6A. Referring to FIG. 6B, the first input “c” may transit from low to high at the rising edge of the first external signal Clkext, and the second input “d” may transit from low to high at the falling edge first external signal Clkext (which is the rising edge of the second external signal Clkextb). In one example according to the present invention, the pulse width of the first external signal Clkext may be predetermined, and the capacitances of the first and second capacitors C51 and C52 may then be determined so as to ensure a 50% duty cycle. For example, the pulse width of the first external signal Clkext may be approximately 10 nanoseconds (ns), and the pulse widths of the signals at the first and second inputs “c” and “d” are approximately 5 ns. The deviations of the pulse widths of the signals at the inputs c and d may be insignificant. Consequently, the output clock signal Clkout may have a 50% duty cycle. The frequency of the output clock signal Clkout may be twice that of the first external clock signal Clkext. Accordingly, the clock generator 60 may serve as a frequency doubler.
It will be appreciated by those skilled in the art that changes could be made to the examples described above without departing from the broad inventive concept thereof It is understood, therefore, that this invention is not limited to the particular examples disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.
Further, in describing representative examples of the present invention, the specification may have presented the method and/or process of the present invention as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. As one of ordinary skill in the art would appreciate, other sequences of steps may be possible. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. In addition, the claims directed to the method and/or process of the present invention should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the present invention.

## Claims

1. A circuit for generating a clock signal, the circuit comprising:
a current source to generate a reference current and provide a first voltage V1;
a first current generator to generate a first mirror current during a first half cycle based on the reference current;
a first capacitor including a first end; and
a first transistor having a first threshold voltage VTH1, the first transistor including a gate to receive the first voltage V1, a drain coupled to the first current generator and a source coupled to the first end of the first capacitor so as to allow the first mirror current to charge the first capacitor during the first half cycle,
wherein the period of the first half cycle is a function of the first bias voltage V1 minus the first threshold voltage VTH1.

2. The circuit of claim 1, wherein the period of the first half cycle equals C1 (V1−VTH1)/I1, wherein C1 represents the capacitance of the first capacitor, and I1 represents the magnitude of the first mirror current.

3. The circuit of claim 1, wherein the first current generator includes a p-type metal-oxide-semiconductor (PMOS) transistor, the PMOS transistor including a gate to receive a first control signal having a first state during the first half cycle and a second state during a second half cycle.

4. The circuit of claim 3 further comprising a first discharging transistor including a gate to receive the first control signal and a drain coupled to the first end of the first capacitor.

5. The circuit of claim 3 further comprising:
a second current generator to generate a second mirror current during a second half cycle based on the reference current;
a second capacitor including a first end; and
a second transistor having a second threshold voltage VTH2, the second transistor including a gate to receive the first voltage V1, a drain coupled to the second current generator and a source coupled to the first end of the second capacitor so as to allow the second mirror current to charge the second capacitor during the second half cycle.

6. The circuit of claim 5 further comprising:
a first inverter including an input coupled to the drain of the second transistor and a second inverter including an input coupled to the drain of the first transistor, wherein the first inverter is turned on when the second capacitor is charged to (V1−VTH2), and the second inverter is turned on when the first capacitor is charged to (V1−VTH1).

7. The circuit of claim 6 further comprising a latch circuit including a first NAND gate and a second NAND gate cross-coupled to each other, wherein the first NAND gate includes an input coupled to an output of the first inverter, and the second NAND gate includes an input coupled to an output of the second inverter.

8. The circuit of claim 6 further comprising a frequency multiplier circuit including:
a first NAND gate including an input coupled to an output of the second inverter;
a third inverter including and input coupled to an output of the first NAND gate;
a second NAND gate including an input coupled to an output of the first inverter;
a fourth inverter including and input coupled to an output of the second NAND gate; and
a NOR gate including a first input coupled to an output of the third inverter and a second input coupled to an output of the fourth inverter.

9. A circuit for generating a clock signal, the circuit comprising:
a first current generator to generate a first mirror current;
a first capacitor;
a first transistor coupled between the first current generator and the first capacitor, the first transistor having a first threshold voltage VTH1 and including a gate to receive a first voltage V1 so as to allow the first mirror current to charge the first capacitor during a first half cycle; and
a first discharging transistor to allow the first capacitor to discharge during a second half cycle,
wherein the period of the first half cycle is proportional to the first bias voltage V1 minus the first threshold voltage VTH1.

10. A clock generator circuit comprising:
a current source; and
a first clock circuit coupled to the current source, the first clock circuit comprising:
a first current generator comprising a first transistor and a second transistor,
wherein a source of the first transistor is coupled to a power supply and a drain of the first transistor is coupled to a source of the second transistor;
a third transistor of which a drain is coupled to a drain of the second transistor;
a fourth transistor of which a drain is coupled to a source of the third transistor and a source is grounded; and
a first capacitor of which a first end is coupled to the source of the third transistor and a second end is grounded.

11. The circuit of claim 10, wherein the current source generates a reference current and provides a first voltage V1, and the first current generator generates a first mirror current based on the reference current.

12. The circuit of claim 11, wherein the third transistor has a first threshold voltage VTH1, the third transistor further including a gate to receive a first voltage V1.

13. The circuit of claim 12 further comprising a first half cycle and a second half cycle, wherein the period of the first half cycle is a function of the first bias voltage V1 minus the first threshold voltage VTH1.

14. The circuit of claim 13, wherein the drain of the third transistor being coupled to the first current generator and the source of the third transistor being coupled to the first end of the first capacitor so as to allow the first mirror current to charge the first capacitor during the first half cycle.

15. The circuit of claim 14 further comprising:
a second clock circuit coupled to the current source, the second clock circuit comprising:
a second current generator comprising a fifth transistor and a sixth transistor,
wherein a source of the fifth transistor is coupled to the power supply and a drain of the fifth transistor is coupled to a source of the sixth transistor;
a seventh transistor of which a drain is coupled to a drain of the sixth transistor;
an eighth transistor of which a drain is coupled to a source of the seventh transistor and a source is grounded; and
a second capacitor of which a first end is coupled to the source of the seventh transistor and a second end is grounded.

16. The circuit of claim 15, wherein the drain of the seventh transistor being coupled to the second current generator and the source of the seventh transistor being coupled to the first end of the second capacitor so as to allow the second mirror current to charge the second capacitor during the first half cycle.

17. The circuit of claim 16 further comprising a first inverter including an input coupled to the drain of the seventh transistor and a second inverter including an input coupled to the drain of the third transistor, wherein the first inverter is turned on when the second capacitor is charged to (V1−VTH2), and the second inverter is turned on when the first capacitor is charged to (V1−VTH1).

18. The circuit of claim 17 further comprising a latch circuit including a first NAND gate and a second NAND gate cross-coupled to each other, wherein the first NAND gate includes an input coupled to an output of the first inverter, and the second NAND gate includes an input coupled to an output of the second inverter.

19. The circuit of claim 17 further comprising a frequency multiplier circuit including:
a first NAND gate including an input coupled to an output of the second inverter;
a third inverter including and input coupled to an output of the first NAND gate;
a second NAND gate including an input coupled to an output of the first inverter;
a fourth inverter including and input coupled to an output of the second NAND gate; and
a NOR gate including a first input coupled to an output of the third inverter and a second input coupled to an output of the fourth inverter.

20. The circuit of claim 10, wherein the current source comprises:
a first buffer;
a second buffer; and
a current mirror coupled to the first buffer and the second buffer, respectively.