# Patent

## Title
Liquid crystal display device capable of reducing image flicker and method for driving the same

## Abstract

A method for driving a liquid crystal display adjusts the falling edges of the gate driving signals for reducing image flicker. A first gate driving signal falls from a high level to a first level at the signal falling edge. A second gate driving signal falls from the high level to a second level at the signal falling edge. When the parasitic capacitance of a first pixel is larger than that of a second pixel, the first level is lower than the second level; when the parasitic capacitance of the first pixel is substantially the same as that of the second pixel, the first level is the same as the second level; when the parasitic capacitance of the first pixel is smaller than that of the second pixel, the first level is higher than the second level.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a liquid crystal display device and method for driving the same, and more particularly, to a liquid crystal display device capable of reducing image flicker and method for driving the same.
2. Description of the Prior Art
Liquid crystals display (LCD) devices, characterized in low radiation, small size and low power consumption, have gradually replaced traditional cathode ray tube (CRT) devices and been widely used in electronic products, such as notebook computers, personal digital assistants (PDAs), flat panel TVs, or mobile phones. In traditional LCD devices, a source driver and a gate driver are used for driving the pixels of the panel in order to display images. Since the source driver is more expensive than the gate driver, LCD devices adopting half source driver (HSD) structure have been developed in order to reduce the number of source drivers. In other words, for the same amount of pixels, the manufacturing cost can be reduced by halving the number of data lines receiving signals from the source driver and doubling the number of gate lines receiving signals from the gate driver.
FIG. 1 is a prior art LCD device 100 which adopts HSD structure. The LCD device 100 includes a timing controller 130, a source driver 110, a gate driver 120, a plurality of data lines DL1-DLm, a plurality of gate lines GL1-GLn, and a pixel matrix. The pixel matrix includes a plurality of pixel units PXL and PXR each having a thin film transistor (TFT) switch, a liquid crystal capacitor CLC and a storage capacitor CST, and respectively coupled to a corresponding data line, a corresponding gate line and a common node. The timing controller 130 can generate control signals YOE and YV1C, input clock signals CK and CKB or an output enable signal OE for operating the source driver 110 and the gate driver 20. The source driver 110 can generate data driving signals SD1-SDm corresponding to display images. If the gate driver 120 is an external driving circuit, the gate driving signals SG1-SGn for turning on the TFT switches are generated according to the control signals YOE and YV1C; if the gate driver 120 is fabricated using gate on array (GOA) technique, the gate driving signals SG1-SGn are generated according to the input clock signals CK,CKB and the output enable signal OE.
When the TFT switch is turned off, the pixel electrode is not connected to any voltage source and thus has a floating level. Any voltage variation around the pixel electrode is coupled to the pixel electrode via its parasite capacitance, which in turn influences the voltages applied to the liquid crystal capacitor CLC and the storage capacitor CST. The feed-through voltage VFD due to voltage variations caused by parasite capacitance can be represented by the following equation:

VFD=[CGD/(CLC+CST+CGD)]*ΔVG=K*ΔVG 

CGD represents the parasite capacitance between the gate and the drain of the TFT switch. K represents the percentage of CGD which contributes to the overall parasite capacitance. ΔVG represents the gate voltage difference caused by a gate driving signal when turning off a corresponding TFT switch. The parasite capacitance is an inherent characteristic of the TFT switch. In order to effectively reduce image flicker, the gate voltage difference ΔVG needs to be lowered first before adjusting the common voltage Vcom for compensating the feed-through voltage VFD.
FIGS. 2 and 3 are diagrams illustrating methods for driving the prior art LCD device 100. FIG. 2 shows the waveforms of the control signal YOE and the gate driving signals SG1-SG4 when the gate driver 120 is an external circuit. FIG. 3 shows the waveforms of the clock signals CK, CKB, O_CK, O_CKB, the output enable signal OE and the gate driving signals SG1-SG4 when the gate driver 120 is fabricated using GOA technique.
In the driving method depicted in FIG. 2, the length of the enable period in the gate driving signals SG1-SG4 is determined by the pulse width of the control signal YOE, and the length of the signal falling time in the gate driving signals SG1-SG4 is determined by the signal falling start point of the control signals YOE and YV1C. In each period, the control signal YOE remains at high level for a constant length, and the waveform of the control signal YV1C starts to fall at the same point. Therefore, the gate driving signals SG1-SG4 result in an identical gate voltage difference ΔVG′ when turning off corresponding TFT switches. As previously stated, the feed-through voltage is proportional to the gate voltage difference. Since the gate voltage difference ΔVG′ after voltage trimming is smaller than the gate voltage difference ΔVG without voltage trimming, the effect of the feed-through voltage can be compensated.
In the driving method depicted in FIG. 3, the clock signals CK and CKB having opposite phases switch between high/low voltage levels based on a predetermined period which determines the length of the enable period in the gate driving signals SG1-SG4. When the output enable signal OE is at high level, the gate driver 120 outputs the clock signals CK and CKB for providing the corresponding clock signals O_CK and O_CKB. When the output enable signal OE is at low level, the gate driver 120 stops outputting the clock signals CK and CKB. Charge-sharing is then performed between the clock signals O_CK and O_CKB, thereby achieving voltage trimming at the signal falling edge. The gate driving signals SG1-SG4 can thus be provided according to the clock signals O_CK and O_CKB after charge-sharing. In each period, the output enable signal OE remains at low level for a constant length T, the degree of voltage trimming in the gate driving signals SG1-SG4 is identical. Therefore, the gate driving signals SG1-SG4 result in an identical gate voltage difference ΔVG′ when turning off corresponding TFT switches. As previously stated, the feed-through voltage is proportional to the gate voltage difference. Since the gate voltage difference ΔVG′ after voltage trimming is smaller than the gate voltage difference ΔVG without voltage trimming, the effect of the feed-through voltage can be compensated.
In the prior art LCD device 100, the pixel units are disposed on both sides of each data line, wherein the pixel units PXL disposed on the left side of the data lines are controlled by the gate driving signals SG1, SG3, . . . , SGn-1 transmitted from the odd-numbered gate lines, while the pixel units PXR disposed on the right side of the data lines are controlled by the gate driving signals SG2, SG4, . . . , SGn transmitted from the even-numbered gate lines. Normally adopting different designs, these two types of pixel units PXL and PXR have different CLC, CST, CGS or CGD, and the value of the feed-through voltage VFD also varies. Even if the two types of pixel units PXL and PXR adopt the same design, the value of the feed-through voltage VFD may also vary due to characteristic shift caused by manufacturing process deviations, For example, the process shift between the first metal layer M1 and the second metal layer M2 may result in different CGD values of the pixel units PXL and PXR.
In the driving methods depicted in FIGS. 2 and 3, the gate voltage difference of each pixel is lowered by the same degree. Since each pixel has different feed-through voltage, image flicker can not be effectively reduced by adjusting the common voltage Vcom.
SUMMARY OF THE INVENTION
The present invention provides an LCD device which improves image flicker, comprising a first gate line for transmitting a first gate driving signal; a second gate line adjacent and parallel to the first gate line for transmitting a second gate driving signal; a data line perpendicular to the first and second gate lines for transmitting data driving signals; a first pixel disposed at an intersection of the data line and the first gate line and on a first side of the data line, and for displaying images according to the first gate driving signal and a received data driving signal; a second pixel disposed at an intersection of the data line and the second gate line and on a second side of the data line, and for displaying images according to the second gate driving signal and a received data driving signal; a trimming circuit for generating a trimming signal according to the parasite capacitances of the first and second pixels; and a gate driver for generating the first and second gate driving signals by adjusting a signal falling edge of a gate pulse signal according to the trimming signal, wherein a signal falling edge of the first gate driving signal falls from a high level to a first level, and a signal falling edge of the second gate driving signal falls from the high level to a second level.
The present invention also provides a method for driving an LCD device which comprises a data line, two adjacent first and second gate lines, a first pixel disposed at an intersection of the data line and the first gate line and on a first side of the data line, and a second pixel disposed at an intersection of the data line and the second gate line and on a second side of the data line. The method comprises providing a gate pulse signal; generating a first gate driving signal by adjusting the gate pulse signal according to a parasite capacitance of the first pixel, wherein a signal falling edge of the first gate driving signal falls from a high level to a first level; generating a second gate driving signal by adjusting the gate pulse signal according to a parasite capacitance of the second pixel, wherein a signal falling edge of the second gate driving signal falls from the high level to a second level; and outputting the first and second gate driving signals to the first and second gate lines for driving the first and second pixels, respectively.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram of a prior art LCD device which adopts HSD structure.
FIGS. 2 and 3 are diagrams illustrating methods for driving the prior art LCD device.
FIGS. 4 and 5 are diagrams of LCD devices which adopt HSD structure according to the present invention.
FIG. 6 is a timing diagram illustrating a method for driving the LCD device according to a first embodiment of the present invention.
FIG. 7 is a diagram illustrating the trimming circuit capable of performing the driving method according to the first embodiment of the present invention.
FIG. 8 is a timing diagram illustrating a method for driving the LCD device according to a second embodiment of the present invention.
FIG. 9 is a diagram illustrating the trimming circuit capable of performing the driving method according to the second embodiment of the present invention.
FIG. 10 is a timing diagram illustrating a method for driving the LCD device according to a third embodiment of the present invention.



DETAILED DESCRIPTION
FIGS. 4 and 5 are diagrams of LCD devices 200 and 300 which adopt HSD structure according to the present invention. The LCD devices 200 and 300 each include a source driver 210, a gate driver 220, a timing controller 230, a trimming circuit 240, a plurality of data lines DL1-DLm, a plurality of gate lines GL1-GLn, and a pixel matrix. The pixel matrix of the LCD device 200 includes a plurality of pixel units PXL and PXR, and the pixel matrix of the LCD device 300 includes a plurality of pixel units PXLU, PXLB, PXRU and PXRB. Each of the pixel units includes a TFT switch, a liquid crystal capacitor CLC and a storage capacitor CST respectively coupled to a corresponding data line, a corresponding gate line and a common node. The timing controller 230 can generate control signals YOE and YV1C, clock signals CK and CKB or an output enable signal OE for operating the source driver 210 and the gate driver 220. The source driver 210 can generate data driving signals SD1-SDm corresponding to display images. If the gate driver 220 is an external driving circuit, the trimming circuit 240 generates a trimming signal VTRIM according to the control signal YV1C and the parasite capacitance of the pixel units, and the gate driver 220 then generates the gate driving signals SG1-SGn for turning on the TFT switches according to the control signal YOE and the trimming signal VTRIM; if the gate driver 220 is fabricated using GOA technique, the trimming circuit 240 generates a trimming signal VTRIM according to the output enable signal OE and the parasite capacitance of the pixel units, and the gate driver 220 then generates the gate driving signals SG1-SGn for turning on the TFT switches according to the clock signals CK, CKB and the trimming signal VTRIM.
In the LCD device 200 according to the present invention, the pixel units are disposed on both sides of each data line, wherein the first type of pixel units PXL disposed on the left side of the data lines are controlled by the gate driving signals SG1, SG3, . . . , SGn-1 transmitted from the odd-numbered gate lines, while the second type of pixel units PXR disposed on the right side of the data lines are controlled by the gate driving signals SG2, SG4, . . . , SGn transmitted from the even-numbered gate lines. Normally adopting different designs, these two types of pixel units PXL and PXR have different CLC, CST, CGS or CGD/and the value of the feed-through voltage VFD also varies. Even if the two types of pixel units PXL and PXR adopt the same design, the value of the feed-through voltage VFD may also vary due to characteristic shift caused by manufacturing process deviations.
In the LCD device 300 according to the present invention, the pixel units are disposed on both sides of each data line, wherein the first type of pixel units PXLU disposed on the left side of the data lines are controlled by the gate driving signals SG1, SG5, . . . , SGn-3 transmitted from the gate lines GL1, GL5, . . . , GLn-3, the second type of pixel units PXRB disposed on the right side of the data lines are controlled by the gate driving signals SG2, SG6, . . . , SGn-2 transmitted from the gate lines GL2, GL6, . . . , GLn-2, the third type of pixel units PXRU disposed on the right side of the data lines are controlled by the gate driving signals SG3, SG7, . . . , SGn-1 transmitted from the gate lines GL3, GL7, . . . , GLn-1, the fourth type of pixel units PXLB disposed on left side of the data lines are controlled by the gate driving signals SG4, SG8, . . . , SGn transmitted from the gate lines GL4, GL8, . . . , GLn (assuming n is a multiple of 4). Normally adopting different designs, these four types of pixel units PXLU, PXLB, PXRU and PXRB have different CLC, CST, CGS or CGD/and the value of the feed-through voltage VFD also varies. Even if the four types of pixel units PXLU, PXLB, PXRU and PXRB adopt the same design, the value of the feed-through voltage VFD may also vary due to characteristic shift caused by manufacturing process deviations.
In the present invention, the gate driving signals SG1-SGn with trimmed signal falling edges are used for reducing the gate voltage differences. Meanwhile, the degree of voltage trimming is adjusted according to the parasite capacitance of the pixel units, so that the gate driving signals SG1-SGn result in various gate voltage differences ΔVG1-ΔVGn when turning off corresponding TFT switches. In the LCD device 300 for instance, the gate driving signals SG1-SG4 with different trimmed signal falling edges are used for driving the four types of pixel units, thereby resulting in various gate voltage differences ΔVG1-ΔVG4 when turning off corresponding TFT switches. The capacitance percentages K1-K4 of the four types of the pixel units which influence the feed-through voltage differently can thus be compensated. Since the feed-through voltages VFD1-ΔVFD4 of the four types of the pixel units are substantially the same after voltage trimming, image flicker can be effectively reduced.
FIG. 6 is a timing diagram illustrating a method for driving the LCD device 200 or 300 when the gate driver 310 is an external driving circuit according to a first embodiment of the present invention. FIG. 6 shows the waveforms of the control signal YOE and YV1C, the trimming signal VTRIM and the gate driving signals SG1-SG4. In the driving method depicted in FIG. 6, the control signal YOE remains at high level for a constant length in each period, and the length of the enable period in the gate driving signals SG1-SG4 is determined by the pulse width of the control signal YOE. The signal falling edge start points in each period of the control signal YV1C vary according to the parasite capacitances of the pixel units. The total lengths of the signal falling time T1-T4 of the gate driving signals SG1-SG4 are determined by the signal falling start points of the control signals YOE and YV1C in corresponding periods. The trimming circuit 340 first generates the trimming signal VTRIM having distinct signal falling edge start points in corresponding periods according to the control signal YV1C and the capacitance percentages K1-K4. The gate driver 320 then generates the gate driving signals SG1-SG4 having distinct trimmed signal falling edges in corresponding periods according to the control signal YOE and the trimming signal VTRIM. The gate driving signals SG1-SG4 result in different gate voltage differences ΔVG1-ΔVG4 when the control signal YOE switches from high level to low level. Assuming the relationship of the capacitance percentages is K1<K2<K3<K4, then the relationship of the total lengths of the signal falling time is T1<T2<T3<T4, and the relationship of the gate voltage differences is thus ΔVG1>ΔVG2>ΔVG3>ΔVG4. As previously stated, the feed-through voltage is proportional to the multiple of the capacitance percentage and the gate voltage difference. When K1<K2<K3<K4, the first embodiment of the present invention provides the gate driving signals SG1-SG4 which result in gate voltage differences having the relationship of ΔVG1>ΔVG2>ΔVG3>ΔVG4. Since the feed-through voltages of each type of pixel units are substantially the same after voltage trimming, image flicker can be effectively reduced by adjusting the common voltage Vcom.
FIG. 7 is a diagram illustrating the trimming circuit 340 capable of performing the driving method according to the first embodiment of the present invention. The trimming circuit 340 in FIG. 7, including an inverter 70, a level shifter 72, a slope-adjusting circuit 74, and transistor switches QP and QN, can generate the trimming signal VTRIM according to the control signal YV1C. When the control signal YV1C is at high level, the transistor switch QP is turned on and the transistor switch QN is turned off, and the trimming signal VTRIM is at a high level VGH. When the control signal YV1C is at low level, the transistor switch QP is turned off and the transistor switch QN is turned on, and the level of the trimming signal VTRIM is pulled down to low level via the resistor R1 of the slope-adjusting circuit 74. Therefore in the embodiments of FIGS. 6 and 7, the trimming circuit 340 receives the control signal YV1C having distinct signal falling edge start points, and then provides the trimming signal VTRIM having a slope at the signal falling edge. The slope-adjusting circuit 74 can be an impedance device, such as a resistor or a variable resistor.
FIG. 8 is a timing diagram illustrating a method for driving the LCD device 200 or 300 when the gate driver 310 is an external driving circuit according to a second embodiment of the present invention. FIG. 8 shows the waveforms of the control signal YOE and YV1C, the trimming signal VTRIM and the gate driving signals SG1-SG4. In the driving method depicted in FIG. 8, the control signal YOE remains at high level for a constant length in each period, and the length of the enable period in the gate driving signals SG1-SG4 is determined by the pulse width of the control signal YOE. The signal falling edge start points in each period of the control signal YV1C vary according to the parasite capacitances of the pixel units. The waveform of the control signal YV1C starts to fall at the same point in each period, thereby resulting in an identical total length of the signal falling time T in the gate driving signals SG1-SG4. The slopes m1-m4 of the signal falling edges in the gate driving signals SG1-SG4 are determined by the trimming circuit 340. The trimming circuit 340 first generates the trimming signal VTRIM having distinct signal falling edge slopes in corresponding periods according to the control signal YV1C and the capacitance percentages K1-K4. The gate driver 320 then generates the gate driving signals SG1-SG4 having distinct trimmed signal falling edges in corresponding periods according to the control signal YOE and the trimming signal VTRIM. The gate driving signals SG1-SG4 result in different gate voltage differences ΔVG1-ΔVG4 when the control signal YOE switches from high level to low level. Assuming the relationship of the capacitance percentages is K1<K2<K3<K4, then the relationship of the signal falling edge slopes is m1<m2<m3<m4, and the relationship of the gate voltage differences is thus ΔVG1>ΔVG2>ΔVG3>ΔVG4. As previously stated, the feed-through voltage is proportional to the multiple of the capacitance percentage and the gate voltage difference. When K1<K2<K3<K4, the second embodiment of the present invention provides the gate driving signals SG1-SG4 which result in gate voltage differences having the relationship of ΔVG1>ΔVG2>ΔVG3>ΔVG4. Since the feed-through voltages of each type of pixel units are substantially the same after voltage trimming, image flicker can be effectively reduced by adjusting the common voltage Vcom.
FIG. 9 is a diagram illustrating the trimming circuit 340 capable of performing the driving method according to the second embodiment of the present invention. The trimming circuit 340 in FIG. 9, including an inverter 70, a level shifter 72, a slope-adjusting circuit 94, and transistor switches QP and QN, can generate the trimming signal VTRIM according to the control signal YV1C. When the control signal YV1C is at high level, the transistor switch QP is turned on and the transistor switch QN is turned off, and the trimming signal VTRIM is at a high level VGH. When the control signal YV1C is at low level, the transistor switch QP is turned off and the transistor switch QN is turned on, and the level of the trimming signal VTRIM is pulled down to low level via the resistor R1 of the slope-adjusting circuit 94. The slope-adjusting circuit 94, including a resistor R1, a variable resistor R2, and switches S1 and S2, can provide different equivalent resistances according to the capacitance percentages K1*K4 and can pull down the level of the trimming signal VTRIM using an adequate slope. Therefore in the embodiments of FIGS. 8 and 9, the trimming circuit 340 receives the control signal YV1C having identical signal falling edge start points, and then provides the trimming signal VTRIM having distinct slopes at the signal falling edge using the slope-adjusting circuit 94.
FIG. 10 is a timing diagram illustrating a method for driving the LCD device 200 or 300 when the gate driver 310 is fabricated using GOA technique according to a third embodiment of the present invention. FIG. 10 shows the waveforms of the clock signals CK, CKB, O_CK and O_CKB, the output enable signal OE and the gate driving signals SG1-SG4. In the driving method depicted in FIG. 8, the clock signals CK and CKB having opposite phases switch between high/low voltage levels based on a predetermined period which determines the length of the enable period in the gate driving signals SG1-SG4. The trimming circuit 340 first generates a trimming signal OETRIM having distinct disable lengths (low level) T1-T4 in corresponding periods according to the enable signal OE and the capacitance percentages K1-K4. The gate driver 320 then outputs the clock signals CK and CKB for providing the clock signals O_CK and O_CKB. When the trimming signal OETRIM is at high level, the gate driver 220 outputs the clock signals CK and CKB for providing the corresponding clock signals O_CK and O_CKB. When the trimming signal OETRIM is at low level, the gate driver 220 stops outputting the clock signals CK and CKB. Charge-sharing is then performed between the clock signals O_CK and O_CKB, thereby achieving voltage trimming at the signal falling edge. The gate driver 320 then generates the gate driving signals SG1-SG4 having distinct trimmed signal falling edges in corresponding periods according to the clock signals OCK and O_CKB.
The gate driving signals SG1-SG4 result in different gate voltage differences ΔVG1-ΔVG4 when the corresponding clock signals O_CK and O_CKB switch from high level to low level. Assuming the relationship of the capacitance percentages is K1<K2<K3<K4, then the relationship of the disable lengths is T1<T2<T3<T4, and the relationship of the gate voltage differences is thus ΔVG1>ΔVG2>ΔVG3>ΔVG4. As previously stated, the feed-through voltage is proportional to the multiple of the capacitance percentage and the gate voltage difference. When K1<K2<K3<K4, the third embodiment of the present invention provides the gate driving signals SG1-SG4 which result in gate voltage differences having the relationship of ΔVG1>ΔVG2>ΔVG3>ΔVG4. Since the feed-through voltages of each type of pixel units are substantially the same after voltage trimming, image flicker can be effectively reduced by adjusting the common voltage Vcom.
The present invention can adjust the total length or the slope of the signal falling edge in the gate driving signals SG1-SG4 according to the capacitance percentages K1-Kn of the pixel units. Different parasite capacitances can be compensated by various voltage differences ΔVG1-ΔVGn so that the feed-through voltages of each type of pixel units are substantially the same. The present invention can effectively reduce image flicker the by adjusting the common voltage Vcom, and thus provide better display quality.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

## Claims

1. A liquid crystal display (LCD) device which improves image flicker, comprising:
a first gate line for transmitting a first gate driving signal;
a second gate line adjacent and parallel to the first gate line for transmitting a second gate driving signal;
a data line perpendicular to the first and second gate lines for transmitting data driving signals;
a first pixel disposed at an intersection of the data line and the first gate line and on a first side of the data line for displaying images according to the first gate driving signal and a received data driving signal;
a second pixel disposed at an intersection of the data line and the second gate line and on a second side of the data line for displaying images according to the second gate driving signal and a received data driving signal;
a trimming circuit for generating a trimming signal according to parasitic capacitances of the first and second pixels; and
a gate driver for generating the first and second gate driving signals by adjusting a signal falling edge of a gate pulse signal according to the trimming signal, wherein:
a signal falling edge of the first gate driving signal falls from a high level to a first level;
a signal falling edge of the second gate driving signal falls from the high level to a second level;
the first level is lower than the second level when the parasitic capacitance of the first pixel is larger than the parasitic capacitance of the second pixel;
the first and second levels are substantially the same when the parasitic capacitances of the first and second pixels are substantially the same; and
the first level is higher than the second level when the parasitic capacitance of the first pixel is smaller than the parasitic capacitance of the second pixel.

2. The LCD device of claim 1, wherein:
the first pixel comprises:
a first switch including:
a first end coupled to the data line;
a second end; and
a control end coupled to the first gate line;

a first liquid crystal capacitor coupled between the second end of the first switch and a common node; and
a first storage capacitor coupled in parallel with the first liquid crystal capacitor; and

the second pixel comprises:
a second switch including:
a first end coupled to the data line;
a second end; and
a control end coupled to the second gate line;

a second liquid crystal capacitor coupled between the second end of the second switch and the common node; and
a second storage capacitor coupled in parallel with the second liquid crystal capacitor.

3. The LCD device of claim 2, wherein the first and second switches include thin film transistors, and the parasitic capacitances of the first and second pixels are gate-to-drain capacitances of the thin film transistors.

4. The LCD device of claim 1 further comprising:
a third gate line adjacent and parallel to the second gate line for transmitting a third gate driving signal;
a fourth gate line adjacent and parallel to the third gate line for transmitting a fourth gate driving signal;
a third pixel disposed at an intersection of the data line and the third gate line and on the first side of the data line for displaying images according to the third gate driving signal and a received data driving signal; and
a fourth pixel disposed at an intersection of the data line and the fourth gate line and on the second side of the data line for displaying images according to the fourth gate driving signal and a received data driving signal;
wherein the trimming circuit further generates the trimming signal according to parasitic capacitances of the third and fourth pixels, and the gate driver further generates the third and fourth gate driving signals by adjusting the signal falling edge of the gate pulse signal according to the trimming signal, wherein:
a signal falling edge of the third gate driving signal falls from the high level to a third level;
a signal falling edge of the fourth gate driving signal falls from the high level to a fourth level;
the third level is lower than the fourth level when the parasitic capacitance of the third pixel is larger than the parasitic capacitance of the fourth pixel;
the third and fourth levels are substantially the same when the parasitic capacitances of the third and fourth pixels are substantially the same; and
the third level is higher than the fourth level when the parasitic capacitance of the third pixel is smaller than the parasitic capacitance of the fourth pixel.

5. The LCD device of claim 4, wherein:
the third pixel comprises:
a third switch including:
a first end coupled to the data line;
a second end; and
a control end coupled to the third gate line;

a third liquid crystal capacitor coupled between the second end of the third switch and a common node; and
a third storage capacitor coupled in parallel with the third liquid crystal capacitor; and

the fourth pixel comprises:
a fourth switch including:
a first end coupled to the data line;
a second end; and
a control end coupled to the fourth gate line;

a fourth liquid crystal capacitor coupled between the second end of the fourth switch and the common node; and
a fourth storage capacitor coupled in parallel with the fourth liquid crystal capacitor.

6. The LCD device of claim 5, wherein the third and fourth switches include thin film transistors, and the parasitic capacitances of the third and fourth pixels are gate-to-drain capacitances of the thin film transistors.

7. The LCD device of claim 1, further comprising:
a third gate line adjacent and parallel to the second gate line for transmitting a third gate driving signal;
a fourth gate line adjacent and parallel to the third gate line for transmitting a fourth gate driving signal;
a third pixel disposed at an intersection of the data line and the third gate line and on the second side of the data line for displaying images according to the third gate driving signal and a received data driving signal; and
a fourth pixel disposed at an intersection of the data line and the fourth gate line and on the first side of the data line for displaying images according to the fourth gate driving signal and a received data driving signal;
wherein the trimming circuit further generates the trimming signal according to parasitic capacitances of the third and fourth pixels, and the gate driver further generates the third and fourth gate driving signals by adjusting the signal falling edge of the gate pulse signal according to the trimming signal, wherein:
a signal falling edge of the third gate driving signal falls from the high level to a third level, and
a signal falling edge of the fourth gate driving signal falls from the high level to a fourth level;
the third level is lower than the fourth level when the parasitic capacitance of the third pixel is larger than the parasitic capacitance of the fourth pixel;
the third and fourth levels are substantially the same when the parasitic capacitances of the third and fourth pixels are substantially the same; and
the third level is higher than the fourth level when the parasitic capacitance of the third pixel is smaller than the parasitic capacitance of the fourth pixel.

8. The LCD device of claim 7, wherein:
the third pixel comprises:
a third switch including:
a first end coupled to the data line;
a second end; and
a control end coupled to the third gate line;

a third liquid crystal capacitor coupled between the second end of the third switch and a common node; and
a third storage capacitor coupled in parallel with the third liquid crystal capacitor; and

the fourth pixel comprises:
a fourth switch including:
a first end coupled to the data line;
a second end; and
a control end coupled to the fourth gate line;

a fourth liquid crystal capacitor coupled between the second end of the fourth switch and the common node; and
a fourth storage capacitor coupled in parallel with the fourth liquid crystal capacitor.

9. The LCD device of claim 8, wherein the third and fourth switches include thin film transistors, and the parasitic capacitances of the third and fourth pixels are gate-to-drain capacitances of the thin film transistors.

10. The LCD device of claim 1, wherein the trimming circuit comprises:
a switch for controlling a signal falling edge start point of the trimming signal in each period.

11. The LCD device of claim 1, wherein the trimming circuit comprises:
a resistor for controlling a signal falling slope of the trimming signal in each period.

12. A method for driving an LCD device which comprises a data line, two adjacent first and second gate lines, a first pixel disposed at an intersection of the data line and the first gate line and on a first side of the data line, and a second pixel disposed at an intersection of the data line and the second gate line and on a second side of the data line, the method comprising:
providing a gate pulse signal;
generating a first gate driving signal by adjusting the gate pulse signal according to a parasitic capacitance of the first pixel, wherein a signal falling edge of the first gate driving signal falls from a high level to a first level;
generating a second gate driving signal by adjusting the gate pulse signal according to a parasitic capacitance of the second pixel, wherein a signal falling edge of the second gate driving signal falls from the high level to a second level; and
outputting the first and second gate driving signals to the first and second gate lines for driving the first and second pixels, respectively, wherein:
the first level is lower than the second level when the parasitic capacitance of the first pixel is larger than the parasitic capacitance of the second pixel;
the first and second levels are substantially the same when the parasitic capacitances of the first and second pixels are substantially the same; and
the first level is higher than the second level when the parasitic capacitance of the first pixel is smaller than the parasitic capacitance of the second pixel.

13. The method of claim 12 wherein:
generating the first gate driving signal includes lowering the first gate driving signal from the high level for a first time length so as to reach the first level; and
generating the second gate driving signal includes lowering the second gate driving signal from the high level for a second time length so as to reach the second level.

14. The method of claim 13 wherein:
the first time length is longer than the second time length when the parasitic capacitance of the first pixel is larger than the parasitic capacitance of the second pixel;
the first and second time lengths are substantially the same when the parasitic capacitances of the first and second pixels are substantially the same; and
the first time length is shorter than the second time length when the parasitic capacitance of the first pixel is smaller than the parasitic capacitance of the second pixel.

15. The method of claim 12 wherein:
generating the first gate driving signal includes lowering the first gate driving signal from the high level with a first slope so as to reach the first level; and
generating the second gate driving signal includes lowering the second gate driving signal from the high level with a second slope so as to reach the second level.

16. The method of claim 15 wherein the first slope is larger than the second slope when the parasitic capacitance of the first pixel is larger than the parasitic capacitance of the second pixel.

17. The method of claim 15 wherein the first and second slopes are substantially the same when the parasitic capacitances of the first and second pixels are substantially the same.

18. The method of claim 12 further comprising:
providing a first clock signal and a second clock signal, wherein the first and second clock signals switch phases based on a predetermined period, and the first and second clock signals have opposite phases at the same time;
determining a first time length according to the parasitic capacitance of the first pixel;
determining a second time length according to the parasitic capacitance of the second pixel;
performing charge-sharing on the first and second clock signals for the first time length during periods corresponding to the first pixels;
performing charge-sharing on the second and second clock signals for the second time length during periods corresponding to the second pixels; and
generating the first or the second gate driving signal by adjusting the gate pulse signal according to the first and second clock signals after performing charge-sharing.

19. The method of claim 18 wherein the first time length is longer than the second time length when the parasitic capacitance of the first pixel is larger than the parasitic capacitance of the second pixel.

20. The method of claim 18 wherein the first and second time lengths are substantially the same when the parasitic capacitances of the first and second pixels are substantially the same.