# Patent

## Title
Feedback compensation detector for a direct conversion transmitter

## Abstract

A feedback compensation detector for a direct conversion transmitter includes a baseband processor, a direct up-converter, an antenna, and an impairment detection and compensation feedback circuit. The baseband processor generates an in-phase (I) baseband signal and a quadrature-phase (Q) baseband signal. The direct up-converter is coupled to the baseband processor, and combines the I and Q baseband signals with an RF carrier signal to generate an RF output signal. The antenna is coupled to the direct up-converter, and transmits the RF output signal. The impairment detection and compensation feedback circuit is coupled to the RF output signal and the I and Q baseband signals. The impairment detection and compensation feedback circuit down-converts the RF output signal to generate an intermediate frequency (IF) signal, measures as least one signal impairment in the IF signal, and pre-distorts the I and Q baseband signals to compensate for the measured signal impairment.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
This is a continuation of U.S. application Ser. No. 12/785,607, filed May 24, 2010, which is a continuation of U.S. application Ser. No. 12/494,835, filed Jun. 30, 2009 (now U.S. Pat. No. 7,725,087), which is a continuation of U.S. application Ser. No. 11/274,581, filed Nov. 15, 2005, which is a continuation of U.S. application Ser. No. 10/145,930, filed May 15, 2002 (now U.S. Pat. No. 6,987,954), which claims priority from U.S. Provisional Application No. 60/291,239, filed May 15, 2001, all the above applications hereby incorporated by reference.


FIELD OF THE INVENTION
This application relates generally to the field of radio frequency (RF) signal transmission. More specifically, a feedback compensation detector for a direct conversion transmitter is provided that is particularly well-suited for use in a Quadrature Amplitude Modulated (QAM) transmitter, but may also provide utility in any transmitter that uses sufficiently independent modulation on the two quadrature axes (I and Q), such as a Code Division Multiple Access (CDMA) transmitter, a Wideband Direct Sequence CDMA (WCDMA) transmitter, or a Global System for Mobile Communications (GSM) transmitter.
BACKGROUND OF THE INVENTION
Direct conversion transmitters are known. In a typical direct conversion transmitter chain, baseband in-phase (I) and quadrature-phase (Q) digital signals are converted to analog signals, filtered, amplified and modulated to form an analog baseband signal. The analog baseband signal is then converted to a radio frequency (RF) signal at a carrier frequency, amplified, filtered, and transmitted via an antenna. Such transmitter chains, however, typically propagate signal impairments which are often resultant from channel delays, imbalances, and other signal distortions occurring within the transmitter chain.
SUMMARY
A feedback compensation detector for a direct conversion transmitter includes a baseband processor, a direct up-converter, an antenna, and an impairment detection and compensation feedback circuit. The baseband processor generates an in-phase (I) baseband signal and a quadrature-phase (Q) baseband signal. The direct up-converter is coupled to the baseband processor, and combines the I and Q baseband signals with an RF carrier signal to generate an RF output signal. The antenna is coupled to the direct up-converter, and transmits the RF output signal. The impairment detection and compensation feedback circuit is coupled to the RF output signal and the I and Q baseband signals. The impairment detection and compensation feedback circuit down-converts the RF output signal to generate an intermediate frequency (IF) signal, measures as least one signal impairment in the IF signal, and pre-distorts the I and Q baseband signals to compensate for the measured signal impairment.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a direct up-conversion transmitter chain with an impairment compensation feedback path;
FIG. 2 is a more detailed block diagram of the direct up-converter shown in FIG. 1;
FIG. 3 is a block diagram of the direct up-conversion transmitter chain shown in FIG. 1 with a more detailed illustration of the impairment detector;
FIG. 4 is a more detailed block diagram of the impairment compensator shown in FIG. 1;
FIG. 5 is a block diagram of a timing estimator circuit for estimating the in-phase (I) component delay, Tie, shown in FIG. 4;
FIG. 6 is a block diagram of a direct up-conversion transmitter chain having an automatic gain control (AGC) correction loop in the impairment compensation feedback path;
FIG. 7 is a block diagram of a direct up-conversion transmitter chain having a local oscillator (LO) leakage nulling loop in the impairment compensation feedback path;
FIG. 8 is a block diagram of a direct up-conversion transmitter chain having a quadrature imbalance compensation loop in the impairment compensation feedback path;
FIG. 9 is a block diagram of a direct up-conversion transmitter chain having a differential timing error compensation loop in the impairment compensation feedback path;
FIG. 10 is a block diagram of an exemplary temperature and supply voltage compensation circuit for the impairment detector shown in FIGS. 1, 3, and 6-9;
FIG. 11 is a flow diagram of a method for iteratively estimating the values of the ambient temperature T and battery supply voltage Vd shown in FIG. 10; and
FIG. 12 is a flow diagram illustrating an exemplary method for operating the feedback compensation detector described above with reference to FIGS. 1-9.



DETAILED DESCRIPTION
Impairment Compensation Feedback Path
Referring now to the drawing figures, FIG. 1 is a block diagram of a direct up-conversion transmitter chain 100 with an impairment compensation feedback path. The transmitter chain 100 includes a baseband processor 110, an impairment compensator 112, a direct up-converter 114, and an impairment detector 116. The baseband processor 110 may, for example, be a digital signal processor (DSP), a central processing unit (CPU), or some other type of processing device or logic circuitry. The transmitter chain also includes a pair of digital-to-analog converters DACs 118, a frequency synthesizer 120, a band pass filter 122, and an antenna 124. Operationally, the impairment detector 116 measures signal impairments in the direct up-converter output 121, and generates a feedback signal 126 that is coupled to the impairment compensator 112. Exemplary signal impairments which may be detected by the impairment detector 116 are described below with reference to FIG. 3.
The baseband processor 110 generates in-phase (I) and quadrature-phase (Q) digital baseband signals for RF transmission. The I and Q baseband signals are modified prior to analog conversion by the impairment compensator 112, as described below. The modified baseband signals are then converted into the analog domain by the DACs 118 and are coupled to the direct up-converter 114 which combines the analog baseband signals with an RF carrier signal 119 from the frequency synthesizer 120. An exemplary direct up-converter 114 is described below with reference to FIG. 2. The RF output signal 121 from the direct up-converter 114 is filtered by the band pass filter 122, and is transmitted by the antenna 124. In addition, the RF output signal 121 is coupled to the impairment detector 116 which measures signal impairments, as described below, and generates the feedback signal 126 that is coupled to the impairment compensator 112. The feedback signal 126 is used by the impairment compensator 112 to pre-distort the I and Q baseband signals such that the pre-distortion cancels any actual distortion caused by impairments in the direct up-converter 114.
FIG. 2 is a more detailed block diagram 200 of the direct up-converter 114 shown in FIG. 1. The direct up-converter 114 includes a pair of low pass filters 202, a pair of amplifiers 204, a quadrature up-converter 206, an automatic gain control (AGC) amplifier 208, a band pass filter 210, and a power amplifier (PA) 212.
The analog I and Q baseband signals from the DACs 118 are received as inputs to the direct up-converter 114. The I and Q inputs are then filtered by the pair of low pass filters 202, amplified by the pair of amplifiers 204, and coupled as inputs to the quadrature up-converter 206. The quadrature up-converter 206 also receives a carrier signal (F1) from the frequency synthesizer 120, and combines the analog baseband signals with the carrier signal (F1) to generate a radio frequency (RF) signal having a carrier frequency of F1. The RF signal is amplified by the AGC amplifier 208 in order to provide the necessary gain to drive the power amplifier (PA) 212. The PA 212 further amplifies the RF signal to generate the RF output signal 121.
FIG. 3 is a block diagram 300 of the direct up-conversion transmitter chain 100 shown in FIG. 1 with a more detailed illustration of the impairment detector 116. The impairment detector 116 includes a variable attenuator 302, a down-conversion mixer 304, a band pass filter 306, an analog-to-digital (A/D) converter 308, and a impairment detector processor 310. The impairment detector processor 310 may, for example, be a digital signal processor (DSP), a central processing unit (CPU), or some other type of processing device or logic circuitry. In one embodiment, the processing functions of the impairment detector processor 310 and the baseband processor 110 described above may be performed by the same processing device.
The RF output signal 121 from the direct up-converter 114 is sampled by the variable attenuator 302 which reduces the gain of the signal 121 to an appropriate power range for the down-conversion mixer 304. The output from the variable attenuator 302 is coupled to the down-conversion mixer 304 along with a local oscillator (LO) signal 303 generated by the frequency synthesizer 120, which has a different frequency (F2) than the frequency (F1) of the RF carrier signal 119. The intermediate frequency (IF) output of the down-conversion mixer 304 thus has a center frequency that is substantially equal to the difference between the frequencies of the LO signal 303 and the RF carrier signal 119 (F1-F2).
The band pass filter 306 is centered at the intermediate frequency (F1-F2), and filters the IF output to a pre-determined passband to generate an analog impairment signal z(t), where z is a time domain function and t is time. The analog impairment signal z(t) is sampled by the A/D converter 308, and the resulting digital signal is coupled to the impairment detector processor 310 and may also be stored in a memory device, such as a buffer memory, via the processor 310.
The impairment detector processor 310 is configured to estimate one or more impairments present in the RF signal 121. For instance, the impairment detector processor 310 may be configured to estimate the overall gain of the up-converter chain 100, a leakage component from the LO signal 303, a phase or amplitude imbalance in the quadrature up-converter 206, a differential delay between the I and Q baseband channels, or some other signal impairment. The feedback signal 126 from the impairment detector 116 is generated by the impairment detector processor 310 based on the impairments detected in the RF signal 121 and is applied to the I and Q baseband signals in the impairment compensator 112. In addition, the impairment detector processor 310 generates an attenuation control signal 312 that is fed back to control the negative gain applied by the variable attenuator 302. The relationship between the operations of the impairment detector 116 and the impairment compensator 112, including the estimation of signal impairments by the impairment detector processor 310, is described below with reference to FIGS. 5-9.
FIG. 4 is a more detailed block diagram 400 of the impairment compensator 112 shown in FIG. 1. The impairment compensator 112 includes in-phase and quadrature-phase delay compensation blocks 402, 404, in-phase and quadrature-phase bias compensation adders 406, 408, a linear compensation block 410, and in-phase and quadrature-phase gain multipliers 412, 414. Also illustrated are the in-phase (I) and quadrature-phase (Q) digital baseband signals from the baseband processor 110, denoted in the time domain as gi(t) and gq(t) respectively.
The in-phase and quadrature-phase baseband signals gi(t) and gq(t) are advanced by estimated I and Q component delay values, Tie and Tqe, in the delay compensation blocks 402, 404. The estimated I and Q component delay values Tie and Tqe compensate for 1 and Q component delays from the transmitter chain 100, and are received as inputs from the impairment detector 116. An exemplary method for estimating the I and Q component delay values, Tie and Tqe, is described below with reference to FIG. 5.
The in-phase and quadrature-phase outputs from the delay compensation blocks 402, 404 are coupled as positive inputs to the in-phase and quadrature-phase bias compensation adders 406, 408. In addition, estimated in-phase and quadrature-phase bias offset values, bie and bqe, derived by the impairment detector 116, are coupled as negative inputs to the in-phase and quadrature-phase bias compensation adders 406, 408. The bias offset values, bie and bqe, compensate for direct-current (DC) bias caused, for example, by leakage of the LO signal 303 in the RF output signal 121 (see FIG. 3). An exemplary method for estimating the bias offset values, bie and bqe, is described below.
The in-phase and quadrature-phase outputs from the bias compensation adders 406, 408 are coupled as inputs to the linear compensation block 410 along with estimated phase and amplitude imbalance parameters, ee and fe, calculated by the impairment detector 116. Using the estimated phase and amplitude imbalance parameters, ee and fe, the linear compensation block 410 applies an inverse model of the phase and amplitude imbalance in the quadrature up-converter 206, and outputs balanced in-phase and quadrature-phase signal components. An exemplary method for estimating the phase and amplitude imbalance parameters, ee and fe, is described below.
The balanced outputs from the linear compensation block 410 are coupled as inputs to the in-phase and quadrature-phase gain multipliers 412, 414. Also coupled as inputs to the gain multipliers 412, 414 is a scaling factor, Gdes/Goe, which adjusts the in-phase and quadrature-phase signals to compensate for gain imbalances. The numerator of the scaling factor, Gdes, represents the desired gain for the transmitter chain 100, and the denominator, Goe, is the estimated actual gain. The desired gain Gdes is pre-selected according to the desired characteristics of the transmitter chain 100. The estimated actual gain Goe may be calculated by the impairment detector 116, as described below. The in-phase and quadrature-phase outputs from the gain multipliers 412, 414 are coupled to the DACs 118, as described above with reference to FIG. 1.
In one alternative embodiment, the impairment detector 112 may be implemented as a software application executing on the baseband processor 110 or on some other processing device.
Estimating I and Q Component Delays (Tie and Tqe)
FIG. 5 is a block diagram 500 of a timing estimator circuit for estimating the I component delay, Tie, shown in FIG. 4. The timing estimator circuit 500 may, for example, be implemented by the impairment detector processor 310, and includes a first mixer 502, a second mixer 504, and an integrator 506.
The analog impairment signal z(t), described above with reference to FIG. 3, is coupled as an input to the first mixer 502 along with a delayed in-phase baseband signal gi(t−Tie) 508. The delayed in-phase baseband signal gi(t−Tie) 508 is delayed by an estimated value for the I component delay Tie. The output from the first mixer 504 is then coupled as an input to the second mixer 504 along with a sampling phase adjustment parameter 510. The sampling phase adjustment parameter 510 may be calculated as: cos(2π(F1−F2)t+p); where (F1−F2) is the frequency of the IF output from the down-conversion mixer 304 shown in FIG. 3, and p is a phase parameter. The output from the second mixer 504 is fed into the integrator 506, which integrates the signal over a sampling epoch (M/(F1−F2)) to produce an output signal (Y) 512, where M is an integer parameter corresponding to the number of integration cycles.
Operationally, the estimated I component delay, Tie, is calculated by varying the values of Tie and p until a maximum value is obtained for the timing estimator output (Y) 512. The maximum value for Y may be approximated, for example, by calculating Y 512 over a pre-determined range of the variables Tie and p. The value of Tie that results in the maximum timing estimator output (Y) 512 is an estimate of the total in-phase component delay.
The estimated Q component delay, Tiq, may be calculated using a timing estimator circuit similar to the circuit 500 shown in FIG. 5 in which the delayed in-phase baseband signal (gi(t−Tie)) is replaced with a delayed quadrature-phase baseband signal (gq(t−Tiq)).
Estimating Phase, Amplitude, and Gain Imbalance (ee, fe and Goe)
Referring again to FIG. 4, the linear compensation block 410 uses the phase and amplitude parameters ee and fe to compensate for phase and amplitude imbalance in the quadrature up-converter 206, and the in-phase and quadrature-phase gain multipliers 412, 414 use the scaling factor Gdes/Goe to balance the gain. The phase and amplitude parameters ee and fe and the overall gain Goe may be estimated from the analog impairment signal z(t) described above with reference to FIG. 3. The subscript “e” or “est” as used within this application denotes that the value for the given parameter is an estimated value.
The analog impairment signal z(t) may be expressed by the following equation:

z(t)=(C(t)a+S(t)c)*gieq(t−T)+(C(t)b+S(t)d)*gqeq(t−Tq);

where:

    
    
        gieq(t)=gi(t−Ti)+bi;
        gqeq(t)=gq(t−Tq)+bq;
        C(t)=cos(2π(F1−F2)t);
        S(t)=sin(2π(F1−F2)t); and
    
    






  
    [
    
      
        
          a
        
        
          b
        
      
      
        
          c
        
        
          d
        
      
    
    ]
  
  =
  
    
      
        
          G
          o
        
        ⁡
        
          [
          
            
              
                
                  cos
                  ⁡
                  
                    (
                    
                      φ
                      o
                    
                    )
                  
                
              
              
                
                  sin
                  ⁡
                  
                    (
                    
                      φ
                      o
                    
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                  -
                  
                    sin
                    ⁡
                    
                      (
                      
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                        o
                      
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                  ⁡
                  
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          ]
        
      
      ⁡
      
        [
        
          
            
              1
            
            
              0
            
          
          
            
              e
            
            
              f
            
          
        
        ]
      
    
    .
  




The matrix coefficients {a, b, c, d} represent the model of the impaired quadrature up-converter with a random start phase φo, and may be estimated by sampling z(t). In addition, since the I and Q time delays, Ti and Tq, are independent of other impairments, they may be assumed to be equal to zero (0) for the purposes of estimating the phase, amplitude, and gain imbalance parameters, ee, fe, and Goe.
Assume that z(t) is sampled such that z(n) is the sample of z(t) at t=nTs, where the value of n ranges from 0 to (N−1) and N=M(Ts(F1−F2))−1, and where M is an integer parameter corresponding to the number of integration cycles. Also assume that gi(t) and gq(t) are independent random processes with zero mean. Then, the matrix coefficients {a, b, c, d} may be estimated as follows:



  
    
      
        a
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          ⁢
          
            
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    ;
  




  
    
      
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    ;
    
      
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                =
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                2
              
            
          
        
        .
      
    
  



The estimated matrix coefficients {ae, be, ce, de} may then be used to estimate the phase, amplitude, and gain imbalance parameters, ee, fe, and Goe, as follows:



  
    
      
        e
        e
      
      =
      
        
          
            
              d
              e
            
            ⁢
            
              c
              e
            
          
          +
          
            
              b
              e
            
            ⁢
            
              a
              e
            
          
        
        
          
            
              a
              e
            
            ⁢
            
              d
              e
            
          
          -
          
            
              c
              e
            
            ⁢
            
              b
              e
            
          
        
      
    
    ;
  




  
    
      
        f
        e
      
      =
      
        
          
            d
            e
            2
          
          +
          
            b
            e
            2
          
        
        
          
            
              a
              e
            
            ⁢
            
              d
              e
            
          
          -
          
            
              c
              e
            
            ⁢
            
              b
              e
            
          
        
      
    
    ;
    and
  




  
    
      G
      oe
    
    =
    
      
        
          
            
              a
              e
            
            ⁢
            
              d
              e
            
          
          -
          
            
              c
              e
            
            ⁢
            
              b
              e
            
          
        
        
          
            
              b
              e
              2
            
            +
            
              d
              e
              2
            
          
        
      
      .
    
  



Estimating Bias Offset (bie and bqe)

With reference to FIG. 4, the in-phase and quadrature-phase delay compensation blocks 402, 404 offset the I and Q baseband signals by in-phase and quadrature-phase bias parameters bie and bqe. The bias parameters, bie and bqe, may be estimated from the analog impairment signal z(t) independently of the other impairment parameters ee, fe, and Goe. The analog impairment signal z(t) 126 may thus be expressed as:




  
    
      z
      ⁡
      
        (
        t
        )
      
    
    =
    
      
        
          [
          
            
              
                
                  cos
                  (
                  
                    φ
                    ⁡
                    
                      (
                      t
                      )
                    
                  
                
              
              
                
                  sin
                  ⁡
                  
                    (
                    
                      φ
                      ⁡
                      
                        (
                        t
                        )
                      
                    
                    )
                  
                
              
            
          
          ]
        
        ⁢
        
          
            
              G
              o
            
            ⁡
            
              [
              
                
                  
                    1
                  
                  
                    0
                  
                
                
                  
                    e
                  
                  
                    f
                  
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    b
                    i
                  
                
              
              
                
                  
                    b
                    q
                  
                
              
            
            ]
          
        
      
      =
      
        
          
            [
            
              
                
                  C
                
                
                  S
                
              
            
            ]
          
          ⁡
          
            [
            
              
                
                  a
                
                
                  b
                
              
              
                
                  c
                
                
                  d
                
              
            
            ]
          
        
        ⁡
        
          [
          
            
              
                
                  b
                  i
                
              
            
            
              
                
                  b
                  q
                
              
            
          
          ]
        
      
    
  
  ;




such that:

z(t)=(Ca+Sc)bi+(Cb+Sd)bq.

The term (Ca+Sc) may be regarded as a vector in the two-dimensional Hilbert space of C(t) and S(t), and an orthogonal vector to (Ca+Sc) is (Cc−Sa). Consequently <(Ca+Sc)(Cc−Sa)>=0, which allows the parameters bi and bq to be extracted from the equation. Thus estimates of bi and bq, denoted as bie and bqe, may be derived as:




  
    
      
        
          
            b
            ie
          
          =
          
          ⁢
          
            
              
                ∑
                
                  n
                  =
                  0
                
                
                  N
                  -
                  1
                
              
              ⁢
              
                
                  z
                  ⁡
                  
                    (
                    n
                    )
                  
                
                ⁢
                
                  (
                  
                    
                      
                        C
                        ⁡
                        
                          (
                          n
                          )
                        
                      
                      ⁢
                      
                        c
                        e
                      
                    
                    -
                    
                      
                        S
                        ⁡
                        
                          (
                          n
                          )
                        
                      
                      ⁢
                      
                        a
                        e
                      
                    
                  
                  )
                
              
            
            
              
                ∑
                
                  n
                  =
                  0
                
                
                  N
                  -
                  1
                
              
              ⁢
              
                
                  (
                  
                    
                      
                        C
                        ⁡
                        
                          (
                          n
                          )
                        
                      
                      ⁢
                      
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                        e
                      
                    
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                          )
                        
                      
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                        a
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                      ⁢
                      
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                        e
                      
                    
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                        S
                        ⁡
                        
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                          )
                        
                      
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                        d
                        e
                      
                    
                  
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            =
            
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                2
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                  ⁢
                  
                    
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                        n
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                            ⁡
                            
                              (
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                          ⁢
                          
                            a
                            e
                          
                        
                      
                      )
                    
                  
                
              
              
                
                  
                    a
                    e
                  
                  ⁢
                  
                    d
                    e
                  
                
                -
                
                  
                    b
                    e
                  
                  ⁢
                  
                    c
                    e
                  
                
              
            
          
          ;
        
      
    
  




  and




  
    
      b
      qe
    
    =
    
      
        
          
            ∑
            
              n
              =
              0
            
            
              N
              -
              1
            
          
          ⁢
          
            
              z
              ⁡
              
                (
                n
                )
              
            
            ⁢
            
              (
              
                
                  
                    C
                    ⁡
                    
                      (
                      n
                      )
                    
                  
                  ⁢
                  
                    d
                    e
                  
                
                -
                
                  
                    S
                    ⁡
                    
                      (
                      n
                      )
                    
                  
                  ⁢
                  
                    b
                    e
                  
                
              
              )
            
          
        
        
          
            
              a
              e
            
            ⁢
            
              d
              e
            
          
          -
          
            
              b
              e
            
            ⁢
            
              c
              e
            
          
        
      
      .
    
  



Automatic Gain Control Correction Loop

FIG. 6 is a block diagram of a direct up-conversion transmitter chain 600 having an automatic gain control (AGC) correction loop in the impairment compensation feedback path. This transmitter chain 600 is similar to the transmitter chain 100 described above with reference to FIGS. 1-5, except the feedback path includes a comparator 602, a mixer 604, and a gain correction loop 606. In operation, the AGC loop compensates for errors in the AGC amplifier 208 described above with reference to FIG. 2.
The comparator 602 has a positive input coupled to the estimated gain Goe from the impairment detector 116 and a negative input coupled to the pre-selected desired gain Gdes. The comparator 602 subtracts the desired gain Gdes from the estimated gain Goe to generate a comparator output that is coupled as an input to the mixer 604. The mixer 604 applies a pre-selected gain coefficient KG to the comparator output, and generates a mixer output that is coupled as an input to the gain correction loop 606. The gain correction loop 606 may, for example, be a first order correction loop that generates a gain-compensated output Gcomp that may be expressed by the equation: Gcomp=Gcomp−KG(Goe−Gdes). Accordingly, the speed at which the AGC correction loop 606 will track AGC errors may be increased by increasing the value of the gain coefficient KG.
The gain-compensated output, Gcomp, from the AGC correction loop 606 is coupled as the inputs to the gain multipliers 412, 414 in the impairment compensator 112, as described above with reference to FIG. 4. It should be understood, that although the impairment compensator 112 illustrated in FIG. 6 has been simplified to show only the gain multipliers 412, 414, the impairment compensator 112 may include the additional elements described above with reference to FIG. 4.
Local Oscillator Leakage Nulling Loop
FIG. 7 is a block diagram of a direct up-conversion transmitter chain 700 having a local oscillator (LO) leakage nulling loop 702 in the impairment compensation feedback path. This transmitter chain 700 is similar to the transmitter chain 100 described above with reference to FIGS. 1-5, except for the inclusion of the LO leakage nulling loop 702 in the feedback path. In operation, the LO leakage nulling loop 702 corrects for corruption of the RF signal 121 caused by the LO signal 303.
The LO signal 303 may be suppressed in the RF signal 121 by nulling the DC bias parameters bie and bqe. The LO leakage nulling loop 702 accomplishes this by implementing a first order correction loop that applies a pre-selected bias coefficient Kb, and generates compensated in-phase and quadrature-phase bias offset parameters, bicomp and bqcomp, according to the equations:

bicomp=bicomp−Kbbie; and

bqcomp=bqcomp−Kbbqe.

The compensated in-phase and quadrature-phase bias offset parameters, bicomp and bqcomp, are coupled as inputs to the in-phase and quadrature-phase bias compensation adders 406, 408, as described above with reference to FIG. 4. It should be understood, that although the impairment compensator 112 illustrated in FIG. 7 has been simplified to show only the bias compensation adders 406, 408, the impairment compensator 112 may include the additional elements described above with reference to FIG. 4.
Quadrature Imbalance Compensation Tracking Loop
FIG. 8 is a block diagram of a direct up-conversion transmitter chain 800 having a quadrature imbalance compensation loop 802 in the impairment compensation feedback path. This transmitter chain 800 is similar to the transmitter chain 100 described above with reference to FIGS. 1-5, except for the inclusion of the quadrature imbalance compensation loop 802 in the feedback path. In operation, the quadrature imbalance compensation loop 802 further compensates for phase and amplitude imbalance in the quadrature up-converter 206.
The phase and gain imbalance of the quadrature up-converter 206 is represented by the phase and amplitude parameters “e” and “f” as described above. In order to compensate for phase and amplitude imbalance, the I and Q components of the baseband signal are multiplied by:




  
    
      
        [
        
          
            
              1
            
            
              0
            
          
          
            
              e
            
            
              f
            
          
        
        ]
      
      
        -
        1
      
    
    =
    
      
        [
        
          
            
              1
            
            
              0
            
          
          
            
              
                -
                
                  e
                  f
                
              
            
            
              
                1
                f
              
            
          
        
        ]
      
      =
      
        [
        
          
            
              1
            
            
              0
            
          
          
            
              
                e
                comp
              
            
            
              
                f
                comp
              
            
          
        
        ]
      
    
  
  ,




where ecomp and fcomp are the desired compensation variables tracked by the quadrature imbalance compensation loop 802. If values of the phase and amplitude parameters, e and f, where known, then the desired compensation variables could be calculated according to the equations:




  
    
      
        e
        comp
      
      =
      
        -
        
          e
          f
        
      
    
    ;
    and
  




  
    
      f
      comp
    
    =
    
      
        1
        f
      
      .
    
  



Since the impairment detector 116 only calculates estimated phase and amplitude parameters, ee and fe, however, the quadrature imbalance compensation loop 802 applies a pre-selected quadrature balancing coefficient KQ to calculate the desired compensation variables, ecomp and fcomp. The quadrature imbalance compensation loop 802 may, for example, be a first order loop correction loop that generates the desired compensation variables, ecomp and fcomp, according to the following equations:



  
    
      
        e
        comp
      
      =
      
        
          e
          comp
        
        -
        
          
            K
            Q
          
          ⁢
          
            
              e
              e
            
            
              f
              e
            
          
        
      
    
    ;
    and
  




  
    
      f
      comp
    
    =
    
      
        f
        comp
      
      +
      
        
          
            K
            Q
          
          ⁡
          
            (
            
              
                1
                
                  f
                  e
                
              
              -
              1
            
            )
          
        
        .
      
    
  



The desired compensation variables, ecomp and fcomp, are coupled as inputs to the linear compensation block 410 of the impairment compensator 112, as described above with reference to FIG. 4. It should be understood, that although the impairment compensator 112 illustrated in FIG. 8 has been simplified to show only the linear compensation block 410, the impairment compensator 112 may include the additional elements described above with reference to FIG. 4.
Differential Timing Error Compensation Loop
FIG. 9 is a block diagram of a direct up-conversion transmitter chain 900 having a differential timing error compensation loop 902 in the impairment compensation feedback path. This transmitter chain 900 is similar to the transmitter chain 100 described above with reference to FIGS. 1-5, except for the inclusion of the differential timing error compensation loop 902 in the feedback path. In operation, the differential timing error compensation loop 902 adjusts the I and Q component delays, Tie and Tqe, to compensate for dynamic changes in the up-converter channel delays.
The differential timing error compensation loop 902 receives the in-phase and quadrature-phase component delays, Tie and Tqe, estimated by the impairment detector 116 as described above, and applies a pre-selected timing adjustment coefficient KT to generate compensated in-phase and quadrature-phase component delays, Tqc and Tic. The differential timing error compensation loop 902 may, for example, be implemented as a first order correction loop that generates the compensated component delays, Tqc and Tic, according to the following equations:

Tic−Tic+KT(Tie−To); and

Tqc=Tqc+KT(Tie−To),

where To is a target common delay of the in-phase and quadrature-phase channels that is pre-selected such that the delay implemented by the impairment compensator 112 is always positive.

The compensated component delays, Tqc and Tic, are coupled as inputs to the in-phase and quadrature-phase delay compensation blocks 402, 404 in the impairment compensator 112, as described above with reference to FIG. 4. It should be understood, that although the impairment compensator 112 illustrated in FIG. 9 has been simplified to show only the delay compensation blocks 402, 404, the impairment compensator 112 may include the additional elements described above with reference to FIG. 4.
Detector Temperature and Supply Voltage Compensation
FIG. 10 is a block diagram of an exemplary temperature and supply voltage compensation circuit 1000 for the impairment detector 116 shown in FIGS. 1, 3, and 6-9. Portions of the impairment detector 116 described above may be sensitive to fluctuations in temperature and supply voltage. These temperature and supply voltage sensitive components may, for example, include the variable attenuator 302, the down-conversion mixer 304 and the A/D converter 308 described above with reference to FIG. 3. These and any other temperature and/or voltage sensitive components are represented in FIG. 10 by the RF and IF component block 1010. In addition, the temperature and supply voltage compensation circuit 1000 also includes a band gap voltage reference 1020, a temperature sensor 1030, a multiplexer 1040, a first analog-to-digital (A/D) converter 1050, a processor 310, and a second analog-to-digital (A/D) converter 1070. The temperature sensor 1030 may, for example, be a device that is sensitive to temperature and has a repeatable response and negligible hysteresis, such as a diode detector. The processor 310 may, for example, be the impairment detector processor 310 described above with reference to FIG. 3.
The band gap voltage reference 1020 generates a reference voltage Vref. Since the band gap voltage reference 1020 is not ideal, however, the reference voltage is a function of the ambient temperature T and the battery supply voltage Vd.
The temperature sensor 1030 generates a temperature sensor voltage, Vtemp, which is proportional to the ambient temperature T. Since the temperature sensor 1030 is not ideal, however, its output, Vtemp, is also a function of the battery supply voltage Vd.
The multiplexer 1040 is coupled to the reference voltage Vref, the temperature sensor voltage Vtemp, and the battery supply voltage Vd. In addition, the multiplexer 1040 also receives a control input 1045 from the processor 310 which selects either Vtemp or Vd as a selected input to the multiplexer 1040. The multiplexer 1040 then divides the selected input, Vtemp or Vd, by the reference voltage Vref to generate an analog ratio output Rtemp or Rvd, as follows:

Rtemp=Vtemp/Vref; and

Rvd=Vd/Vref.

The selected analog ratio output, Rtemp or Rvd, is sampled by the first A/D converter 1050 and coupled as an input to the processor 310. The processor 310 may, for example, alternate between selecting Vtemp and Vd as the selected input to the multiplexer 1040 in order to generate alternating sampled Rtemp and Rvd inputs to the processor 310. In addition, the analog intermediate frequency (IF) signal generated by the temperature and supply voltage sensitive components 1010 in the impairment detector is sampled by the second A/D converter 1070 and coupled as an additional input to the processor 310. In operation, the processor 310 uses the sampled ratios, Rtemp and Rvd, to estimate the actual ambient temperature T and supply voltage Vd (the estimated values of T and Vd are designated herein as Test and Vdest respectively). A method for estimating the values of T and Vd is described below with reference to FIG. 11.
The estimated temperature and supply voltage values, Test and Vdest, are used to estimate the overall gain G(Test, Vdest) of the analog portion of the impairment detector 116, which is a function of both the ambient temperature T and the supply voltage Vd. By comparing the estimated overall gain G(Test, Vdest) to the pre-selected desired gain of the impairment detector 116, the processor 310 compensates for temperature- and supply voltage-related impairments in the analog IF signal by correcting one or more of the parameters in the feedback signal 126 described above. For instance, temperature- and supply voltage-related corrections in the analog IF signal may be implemented by adjusting the estimated gain Goe, described above with reference to FIGS. 4 and 6, by a factor of G(Test, Vdest).
FIG. 11 is a flow diagram that illustrates a method 1100 for iteratively estimating the values of the ambient temperature T and battery supply voltage Vd shown in FIG. 10. The method 1100 may, for example, be performed by the processor 310 described above with reference to FIG. 10.
The method 1100 begins in step 1110. In step 1120, the voltage value of the reference voltage output Vref from the band gap voltage reference 1020 is estimated. The reference voltage Vref may be calculated, for example, using the estimated values for the ambient temperature Test and the supply voltage Vdest, according to the following equation:

Vref=C1+C2Test+C3Vdest;

where C1, C2 and C3 are constants that may be derived as part of a calibration process. The initial values of Test and Vdest may be pre-selected or otherwise initialized, and therefore should be in error. In successive iterations of the method 1100, however, the values of Test and Vdest should converge on their respective actual values, and thus the estimated value of Vref should also converge on its actual value.

In step 1130, the estimated value of the battery supply voltage, Vdest, is calculated. The value of Vdest may, for example, be calculated according to the equation:

Vdest=RvdVref;

where Rvd is a sampled ratio output from the first multiplexer 1040 described above, and Vref is the voltage reference output from the band gap voltage reference 1020. Similarly, in step 1140, the value of the temperature sensor voltage, Vtemp, as described above, is estimated according to the equation:

Vtest=RtempVref;

where Rtemp is a sampled ratio output from the first multiplexer 1040. Then, in step 1150, the ambient temperature T is estimated according to the equation:

Test=(Vtest−C4−C6Vdest)/C5;

where C4, C5 and C6 are constants that may be derived as part of a calibration process.

In step 1160, the estimated values, Vdest and Test, for the ambient temperature T and supply voltage Vd are examined to determine if the values have sufficiently converged with their respective actual values. This step 1160 may be performed, for example, by saving the values of Vdest and Test to a memory device at each iteration of the method 1100, and comparing the current values with stored values. The estimated values, Vdest and Test, may be deemed to have sufficiently converged when the difference between values calculated at successive iterations reaches a pre-selected value. If it is determined in step 1160 that either of the estimated values, Vdest or Test, has not sufficiently converged with its actual value, then the method repeats at step 1120. Otherwise, the method 1100 ends at step 1170.
Method of Operating a Feedback Compensation Detector
FIG. 12 is a flow diagram illustrating an exemplary method 1200 for operating the feedback compensation detector described above with reference to FIGS. 1-9. The method begins in step 1210. In step 1220, the in-phase and quadrature-phase component delays Ti and Tq are estimated, as described above with reference to FIG. 5. In steps 1230-1250, the matrix coefficients {a, b, c, d}, the phase, amplitude and gain imbalances (ee fe, and Goe), and the bias offset values (bie and bqe) are estimated, as described above with reference to FIG. 4. Then, in step 1260, the I and Q baseband signals are compensated using one or more of the estimated impairment parameters, as described above with reference to FIGS. 4-9. If control loops, such as those described above with reference to FIGS. 6-9, are utilized in the I and Q baseband signal compensation step 1260, then the method 1280 may repeat at step 1270. Otherwise, the method 1200 ends at step 1280.
This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to make and use the invention. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art.

## Claims

1. A method of calculating an estimated temperature, comprising iteratively performing the steps of:
calculating an estimated reference voltage as a function of an estimated temperature and an estimated supply voltage;
calculating an estimated temperature sensor voltage as a function of the estimated reference voltage;
calculating the estimated supply voltage value as a function of the estimated reference voltage; and
calculating the estimated temperature as a function of the estimated temperature sensor voltage and the estimated supply voltage.

2. The method of claim 1 further comprising:
iteratively performing the calculating steps until each of an estimated supply voltage value and an estimated temperature value sufficiently converges such that a difference between the respective values calculated at successive iterations reaches a pre-selected value.

3. The method of claim 1 further comprising:
calculating an estimated gain of an electronic circuit as a function of the estimated supply voltage and the estimated temperature.

4. The method of claim 3 further comprising:
multiplying a signal by a scaling factor calculated as a preselected desired gain divided by the estimated gain.

5. The method of claim 4 wherein the signal is a baseband signal in an impairment compensator of a direct conversion transmitter chain.

6. The method of claim 1 wherein the estimated reference voltage is a linear function of both the estimated temperature and of the estimated supply voltage.

7. The method of claim 1 wherein the estimated temperature sensor voltage is a linear function of the estimated reference voltage.

8. The method of claim 7 further comprising:
dividing an analog output voltage of a temperature sensor by an analog output voltage of a voltage reference device to yield a ratio analog voltage;
performing an analog-to-digital conversion of the ratio analog voltage to yield a digital ratio value; and
in the calculating of the estimated temperature sensor voltage, calculating the estimated temperature sensor voltage as the ratio value times the estimated reference voltage.

9. The method of claim 1 wherein the estimated supply voltage is a linear function of the estimated reference voltage.

10. The method of claim 9 further comprising:
dividing an analog supply voltage by an analog output voltage of a voltage reference device to yield a ratio analog voltage;
performing an analog-to-digital conversion of the ratio analog voltage to yield a digital ratio value; and
in the calculating of the estimated supply voltage, calculating the estimated supply voltage as the ratio value times the estimated reference voltage.

11. The method of claim 1 wherein the estimated temperature is a linear function of the estimated temperature voltage and of the estimated supply voltage.

12. The method of claim 1 wherein the calculating steps are performed by an impairment compensator of a direct conversion transmitter chain in compensating for a signal impairment.

13. A circuit for calculating an estimated temperature, comprising:
a processor configured to, in an iterative manner:
calculate an estimated reference voltage as a function of both an estimated temperature and an estimated supply voltage,
calculate an estimated temperature sensor voltage as a function of the estimated reference voltage,
calculate the estimated supply voltage as a function of the estimated reference voltage, and
calculate the estimated temperature as a function of the estimated temperature sensor voltage and the estimated supply voltage.

14. The circuit of claim 13 further comprising:
a temperature sensor configured to output a temperature sensor analog voltage;
a battery configured to output an analog supply voltage;
a voltage reference device configured to output an analog reference voltage; and
a divider configured to
divide the temperature sensor analog voltage by the analog reference voltage to yield a temperature-related ratio, and
divide the analog supply voltage by the analog reference voltage to yield a supply voltage-related ratio;

the processor being further configured to
multiply the temperature-related ratio by the estimated reference voltage to calculate the estimated temperature sensor output voltage, and
multiply the supply voltage-related ratio by the estimated reference voltage to calculate the estimated supply voltage.

15. The circuit of claim 14 wherein the processor is further configured to calculate an estimated gain as a function of the estimated supply voltage and the estimated temperature, and the circuit further comprising:
a gain multiplier configured to multiply a baseband signal in a direct conversion transmitter chain by a scaling factor that is inversely proportional to the estimated gain.

16. The circuit of claim 15 wherein the signal is a quadrature signal.