# Patent

## Title
Method and apparatus to increase efficiency in a power factor correction circuit

## Abstract

A power factor correction (PFC) controller includes a first integrator coupled to integrate an input current of a PFC converter. A first signal is generated in response to the first integrator to end an on time of a power switch of the PFC converter. A second integrator is coupled to integrate a difference between a constant voltage and an input voltage of the PFC converter. A second signal is generated in response to the second integrator to end an off time of the power switch of the PFC converter. A driver circuit is coupled to vary the switching frequency of the power switch of the PFC converter in response to the first and the second signals and to output a third signal to switch the power switch of the PFC converter to control the input current to be substantially proportional to the input voltage.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of U.S. application Ser. No. 12/267,397, filed on Nov. 7, 2008, now pending. U.S. application Ser. No. 12/267,397 is hereby incorporated by reference.


BACKGROUND
1. Field of the Disclosure
The present invention relates generally to power factor correction circuits in a power supply, and more specifically, the invention relates to increasing efficiency of a power factor correction circuit.
2. Background
Power supplies are typically used to convert alternating current (“ac”) power provided by an electrical outlet into usable direct current (“dc”) power for an electrical device. One important consideration for power supply design is how efficiently power is delivered to the power supply. To improve power delivery efficiency a power factor correction (PFC) circuit may be used in the power supply. More specifically, a power factor correction circuit attempts to shape the current waveform as closely to the shape of the voltage waveform.
Typically, PFC circuits are designed to include a power switch that is controlled to switch between an off state and on state in order to transform a distorted input current waveform transmitted from the distribution line into a more ideal current waveform that resembles the shape of the input voltage waveform. More specifically, the power switch is coupled to an energy transfer element to transfer energy to the output of the power supply. However, during operation the PFC circuit experiences switching losses that are created in the power switch due to parasitic capacitances. Typically, parasitic capacitance can be defined as an unwanted capacitance that exists between parts of an electrical component due to their proximity to each other. Additional losses are also realized in the energy transfer element.



BRIEF DESCRIPTION OF THE DRAWINGS
Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
FIG. 1 is a functional block diagram of an example boost converter including an example controller in accordance with the teachings of the present invention;
FIG. 2 is a functional block diagram further illustrating the example controller of FIG. 1 in accordance with the teachings of the present invention;
FIG. 3A illustrates example input waveforms associated with FIGS. 1 and 2 and corresponding with a switching signal and a load signal in accordance with the teachings of the present invention;
FIG. 3B illustrates a magnified view of one of the input waveforms in FIG. 3A and a corresponding switching waveform;
FIG. 4A illustrates an example relationship between load and average switching frequency in accordance with the teachings of the present invention;
FIG. 4B illustrates an alternate example relationship between load and average switching frequency in accordance with the teachings of the present invention;
FIG. 4C illustrates an alternate example relationship between load and average switching frequency in accordance with the teachings of the present invention;
FIG. 4D illustrates an alternate example relationship between load and average switching frequency in accordance with the teachings of the present invention;
FIG. 5A illustrates an example integrated circuit that implements a control technique for power factor correction (PFC) in accordance with the teachings of the present invention;
FIG. 5B illustrates an example switching frequency adjuster in accordance with the teachings of the present invention;
FIG. 6A illustrates an example relationship between an error voltage, an adjusted error voltage, and a load in accordance with the teachings of the present invention;
FIG. 6B illustrates an example graph of adjusted error voltages in accordance with the teachings of the present invention; and
FIG. 7 is a flow diagram illustrating an example method for adjusting the average switching frequency in response to a varying load in a PFC circuit in accordance with the teachings of the present invention.



DETAILED DESCRIPTION
In one aspect of the present invention, methods and apparatuses disclosed here for explanation purposes use a control technique to increase efficiency in a power factor correction (PFC) circuit. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. Well-known methods related to the implementation have not been described in detail in order to avoid obscuring the present invention.
Reference throughout this specification to “one embodiment,” “an embodiment,” “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment or example of the present invention. Thus, the appearances of the phrases “in one embodiment,” “in an embodiment,” “in one example” or “in an example” in various places throughout this specification are not necessarily all referring to the same embodiment. The particular features, structures or characteristics may be combined for example into any suitable combinations and/or sub-combinations in one or more embodiments or examples.
As will be discussed below, various examples in accordance with the teachings of the present invention implement a control technique for a power factor correction circuit to further increase power efficiency delivery. More specifically, the control technique adjusts the average switching frequency of a power switch in the PFC circuit in response to a varying load coupled at the output of the PFC circuit. In one embodiment of the present invention, the load is representative of a dc-dc converter to be coupled to the output of the PFC correction circuit. This concept will be explained in accordance with the Figures described below.
To illustrate, FIG. 1 is a functional block diagram of an example boost PFC converter 100 (also referred to as PFC converter) including a controller 102 in accordance with the teachings of the present invention. In the example shown, PFC converter 100 is a boost power converter that receives an ac line current IG 104 which corresponds with an ac line voltage VG 106. Typically, ac line current IG 104 and corresponding ac line voltage VG 106 are provided by an electrical distribution system (e.g., power plant) through an electrical socket). As shown, a bridge rectifier 108 converts ac line voltage VG 106 to a dc input voltage VIN 110.
Referring now to FIG. 3A, example waveforms 302, 304, and 306 are representative of ac line voltage VG 106, dc input voltage VIN 110, and dc input current IIN 111, respectively. As shown, an ‘ac’ waveform is denoted by a waveform that reverses its polarity at certain intervals. For example, ac line voltage VG 106 is represented by waveform 302 that alternates between a positive value and a negative value. In comparison, a ‘dc’ waveform is denoted by a waveform that is always the same polarity. For example, as illustrated by waveforms 304 and 306, dc input voltage VIN 110 and a dc input current IIN 111 are substantially always positive. Note that dc input voltage VIN 110 (i.e., waveform 304) and dc input current IIN 111 (i.e., waveform 306) vary in magnitude with time.
Referring back to FIG. 1, in the example shown, a filter 112 is coupled across bridge rectifier 108 to filter high frequency noise currents from dc input current IIN 111. In one aspect of the invention, dc input current IIN 111 is substantially controlled to follow the waveform shape of dc input voltage VIN 110. As shown in FIG. 3A waveform 306, representative of dc input current IIN 111, generally follows a shape of waveform 304, representative of dc input voltage VIN 110.
As shown in the example of FIG. 1, one end of an energy storage element, shown as an inductor L1 114, is coupled to controller 102 while an opposite end of inductor L1 114 is coupled to a power switch SW1 118. In operation, power switch SW1 118 is in an ‘on’ or ‘closed’ state when switch 118 is able to conduct current and in an ‘off’ or ‘open’ state when switch 118 in unable to conduct current. A switching cycle is defined as a time period when the switch is on and a subsequent time period when the switch is off. For example, a switching cycle may include an on time period when switch SW1 118 is able to conduct, followed by an off time period when switch SW1 118 is unable to conduct. In another example, a switching cycle may include an off time period when switch SW1 118 is unable to conduct, followed by an on time period when switch SW1 118 is able to conduct. An on-time may be defined as the time period switch SW1 118 is conducting during a switching cycle and an off-time may be defined as the time period switch SW1 118 is not conducting during a switching cycle.
In the example of FIG. 1, an input return 120 is coupled to power switch SW1 118. In operation, the energy storage inductor L1 114 transfers energy to an output of the power converter 100 in response to the switching of switch SW1 118 in accordance with the teachings of the present invention. As shown in the example, a bulk capacitor 122 is coupled to supply a substantially constant output voltage VOUT 124 to a load 126. In one example, load 126 may be an input to a dc-dc power supply. A diode D1 128 is coupled such that current from bulk capacitor 122 is prevented from flowing back through inductor L1 114. In the example of FIG. 1, an input voltage signal UVIN 130, representative of dc input voltage VIN 110, is received by controller 102. An input current sense signal UIIN 132, representative of dc input current IIN 111, is also received by controller 102. More specifically, a current sense 134 such as for example, a current transformer, or a voltage across a discrete resistor, a voltage across a transistor when the transistor is conducting, or a sense FET element couple to a power switch may be used to measure dc input current IIN 111. In the example of FIG. 1, an output voltage signal UVOUT 136, representative of output voltage VOUT 124, is also received by controller 102. In one example, output voltage signal UVOUT 136 may be representative of a constant reference value. In one embodiment of the present invention, sense signals UVIN 130, UIIN 132, and UVOUT 136 may be in the form of a voltage or a current.
In operation, controller 102 outputs a switching signal USW 119 that controls a switching of switch SW1 118 in response to the input voltage signal UVIN 130, the input current signal UIIN 132, and/or the output voltage signal UVOUT 136 in order to regulate the output voltage VOUT 124 and control the dc input current IIN 111 to follow the waveform of dc input voltage VIN 110, also referred to as ‘input voltage VIN 110.’ In one example, controller 102 regulates output voltage VOUT 124 and controls dc input current IIN 111 by varying each switching cycle of switch SW1 118 also referred to as a variable switching frequency control technique. In another example, controller 102 regulates output voltage VOUT 124 and controls dc input current IIN 111 by maintaining a constant switching cycle of switch SW1 118 also referred to as a fixed switching frequency control. In one aspect of the present invention, controller 102 also adjusts an average switching frequency of the switch in response to load 124 to further increase efficiency of PFC converter 100. In particular, the average switching frequency is defined as the switching frequency over multiple switching cycles. More specifically, controller 102 employs a control technique that reduces power loss by adjusting an average switching frequency of switch SW1 118 in response to load 126.
Referring now to FIG. 2, a functional block diagram of power converter 100 further illustrates an example of controller 102 of FIG. 1 in accordance with the teachings of the present invention. As shown, the controller 102 includes power factor correction (PFC) circuitry 202 and an switching frequency adjuster 204. According to the example of FIG. 2, PFC circuitry 202 outputs switching signal USW 119 and a load signal ULOAD 206 representative of the load 126 coupled to the output of PFC converter 100. PFC circuitry 202 receives input voltage signal UVIN 130, output voltage signal UVOUT 136, and/or input current signal UIIN 134. Switching frequency adjuster 204 receives load signal ULOAD 206 and outputs a frequency adjust fADJ signal 208.
In operation, as an example, the PFC circuitry 202 regulates an output of the power supply and controls the input current such that the input current IIN 111 follows the waveform of the input voltage VIN 110 in response to input voltage signal UVIN 130, input current signal UIIN 134, and/or output voltage signal UVOUT 136. Switching frequency adjuster 204 outputs frequency adjust signal fADJ 208 in response to load signal ULOAD 206 and PFC circuitry 202 adjusts the average switching frequency of power switch SW1 118 in response to frequency adjust signal fADJ 208.
As shown, controller 102, current sense 134, and switch SW1 118 may be included in an integrated circuit 210. In one example, switch SW1 118 may be included on a same single monolithic device as controller 102. In an alternate example, controller 102 may be included on a single monolithic device without switch SW1 118. In one example, switch SW1 118 may be a metal oxide semiconductor field effect transistor (MOSFET). In operation, switch SW1 118 allows conduction of current from a drain terminal 212 to a source terminal 214 when the switch SW1 118 is on and substantially prevents conduction of current when the switch SW1 118 is off. In another example, current sense 134 may be coupled to the switch SW1 118 to measure a switch current ISW 216 as shown. Since switch current ISW 216 is substantially equal to dc input current IIN 111 during the on time of a switching cycle (as shown in FIG. 3B), switch current ISW 216 may be sensed instead of dc input current IIN 111 during the on time of a switching cycle. As shown, current sense 134 may sense input current IIN 111 at the drain terminal 212 of power switch SW1 118. In an alternative embodiment, current sense 134 may sense input current IIN 111 at the source terminal 214 of power switch SW1 118. In an alternate embodiment, switch current ISW 216 may be sensed by current sense 134 before drain terminal 212 or after source terminal 214.
As shown, switch SW1 118 includes parasitic capacitance CP 222. More specifically, parasitic capacitance can be defined as an unwanted capacitance that exists within parts of an electrical component due to their proximity to each other. In operation, when switch SW1 118 switches to an off state, parasitic capacitance CP 222 in PFC converter 100 stores electrical energy. Although, it is shown that stray capacitance CP 22 is across power switch SW1 118, stray capacitance may be contributing from all components within the PFC controller 100. When switch SW1 118 switches to an on state, the stored electrical energy within components of PFC converter 100 is discharged and the energy is dissipated in power switch SW1 118. During operation of controller 100, as the switching frequency of switch SW1 118 increases and switch SW1 118 switches more frequently between an on state and an off state, more energy is dissipated in switch SW1 118. Therefore, it may be beneficial to minimize the switching frequency of switch SW1 118 whenever possible. In one example, the switching frequency of switch SW1 118 may be reduced as the load 126 across the output of PFC converter 100 is reduced in order to limit the power dissipation in SW1 118. However, when limiting the frequency of SW1 118, losses in energy transfer element L1 114 are increased. More specifically, as switching frequency of power switch SW1 118 becomes lower, increases in peak current may generate more power dissipation in the inductor. Additionally, losses in the energy transformer core become larger due to excursion of magnetic flux in the core. Typically, losses in energy transfer element L1 114 are much greater than the prevented losses in switch SW1 118 when switching frequency is reduced in a PFC converter. However, in certain PFC converter designs, it may be beneficial to lower the switching frequency since the losses in the power switch are greater than the additional power losses incurred from the energy transfer element L1 114.
As shown in the depicted example, filter 112 includes, but is not limited to, a capacitor 220 that filters high frequency noise from dc input current IIN 111. More specifically, in one example, a capacitance value of capacitor 220 is a value picked such that capacitor 220 may filter out high frequency noise, but is not large enough to reduce the time varying component of dc input voltage VIN 110. In an alternative embodiment, integrated circuit 210 may be used in PFC converter 100 that includes a flyback converter.
As referenced previously, FIG. 3A illustrates ac line voltage waveform 302, dc input voltage waveform 304, dc input current waveform 306, switch signal USW 119, and load signal ULOAD 206 according to the teachings of the present invention. The ac line voltage waveform 302 is representative of ac line voltage VG 106 and is substantially a sinusoidal waveform. A line cycle is defined as the time intervals between three consecutive zero crossings of the ac line voltage waveform 302 and corresponds to a line cycle period TL 310 which is representative of the time it takes to complete one line cycle. More specifically, in the example shown, the line cycle period TL 310 is dependent on a frequency of the ac line voltage VG 106. For example, if the frequency of the ac line voltage VG 106 increases, the line cycle period TL 310 will become shorter. Conversely, if the frequency of the ac line voltage VG 106 decreases, the line cycle period TL 310 will become longer. According to the embodiments of the present invention, the line cycle period TL 310 is substantially longer than a switching cycle period TSW 312. To further illustrate, in one example the line frequency is 60 Hz which corresponds to a line cycle period TL 310 of 16,666 microseconds, and the average switching frequency in segment 1 is 100 kHZ which corresponds to a switching cycle period TSW 312 of 10 microseconds.
As shown, dc input voltage waveform 304 is representative of dc input voltage VIN 110 and is the rectified waveform of the ac line voltage waveform 302. In operation, bridge rectifier 108 rectifies ac line voltage VG 106, represented by ac line voltage waveform 302, to generate dc input voltage VIN 110, represented by dc input voltage waveform 304. The dc input current waveform 306 is representative of dc input current IIN 111. As shown, the dc input current waveform 306 is superimposed on input voltage waveform 304 to illustrate how dc input current IIN 111 is controlled during the switching cycles to follow dc input voltage VIN 110. A magnified view 314 of the dc input current waveform 306 is shown in FIG. 3B.
As shown in FIG. 3A, an average switching frequency of switching signal USW 119 varies with the magnitude of signal ULOAD 206. According to the teachings of the present invention, the average switching frequency is adjusted in response to load 126. More specifically, the average switching frequency is defined as the average switching frequency of over at least a half line cycle or more. Therefore, the average switching frequency can be adjusted even when the control scheme of PFC circuitry implements a variable switching frequency. As shown in segment 1, load signal ULOAD 206 is at the highest magnitude and corresponds with switching signal USW 119 being at the highest average switching frequency. As shown in segment 2, load signal ULOAD 206 is reduced in magnitude and corresponds with switching signal USW 119 having a lower average switching frequency. As shown in segment 3, the load signal ULOAD 206 is further reduced in magnitude which corresponds with switching signal USW 119 having an even lower average switching frequency. As shown in FIG. 3A switching input current waveform 306 depicts input current IIN 111 in continuous conduction mode. More specifically, continuous conduction mode is a switching control technique implemented such that the input current IIN 111 is prevented from reaching zero within a switching cycle because switch SW1 118 turns on before energy in energy transfer element L1 114 goes to zero. It will be appreciated that since input to PFC converter 100 is an ac signal, that when the input voltage is zero the ac input current will be zero even in continuous conduction mode. A discontinuous conduction mode control technique may be implemented such that the PFC controller 102 prevents input current IIN 111 from going to zero during each off time of each switching cycle. In one embodiment according to the present invention, as the average switching frequency is reduced, PFC controller 102 may switch to a discontinuous mode of operation from a continuous conduction mode of operation. Conversely, when the average switching frequency is increased, input current IIN 111 may go from a discontinuous mode of operation to a continuous mode of operation.
As shown in FIG. 3B, magnified view 314 depicts a portion of input current waveform 306 of FIG. 3A in continuous conduction mode. As shown, dc input current IIN 111 corresponds with switching current ISW 216 during the on time of the switch. In operation input current IIN 111 is controlled for a first switching cycle period TSW1 316 in response to a first on time TON1 318 and a first off time TOFF1 320 that is determined by controller 102. As illustrated in magnified view 314, switching cycles TSW1, TSW2, and TSW3 are varied due to a variable frequency control technique implemented by controller 102 for PFC correction. Therefore, according to one embodiment of the present invention, controller 102 may adjust the average switching frequency of switch SW1 118 over multiple line cycles in response to varying loads and may also adjust the cycle by cycle switching frequency to regulate the output voltage and control the input current IIN 111 to follow input voltage VIN 110 for PFC.
Referring now to FIGS. 4A, 4B, 4C, and 4D, the average switching frequency may be adjusted in various ways in response to the load of the PFC converter 100. In FIG. 4A, the average switching frequency of switch SW1 118 varies linearly and continuously with load 126. In FIG. 4B, the average switching frequency of switch SW1 118 varies exponentially and continuously with load 126. In FIG. 4C, the average switching frequency of switch SW1 118 varies linearly and discretely with load 126. According to an embodiment of the present invention and as illustrated in FIGS. 4A, 4B, and 4C, the average switching frequency is adjusted over the entire load range of the boost converter. That is, the average switching frequency may be at a minimum frequency in response to a minimum load condition and the average switching frequency may be at a maximum frequency in response to a maximum load condition of the boost converter. In another embodiment, as shown in FIG. 4D the average switching frequency is adjusted linearly and continuously over a portion of the entire load range. In another embodiment of the present invention, FIGS. 4A, 4B, 4C, and 4D may be combined in any type of combination to determine the relationship between average switching frequency of switch SW1 118 and load 126.
Referring now to FIG. 5A, an example integrated circuit controller 500 that uses a particular control technique to implement PFC and further includes a switching frequency adjuster 501 to improve efficiency in accordance with the teachings of the present invention is shown. In the example, a power MOSFET 502 switches between an on state and an off state to permit and prevent a flow of input current IIN 503 between a drain terminal D 504 and a source terminal S 506. A voltage terminal VIN 507 is coupled to receive input voltage signal VIN 110. As shown, an input voltage detector 508 outputs a current MN 512 representative of an instantaneous dc input voltage of PFC converter 100. In operation, a generated current signal IVIN2 513 is derived from input voltage detector 508. According to the teachings of the embodiment in the present invention, generated current signal IVIN2 513 may be representative of a peak input voltage of a half-line cycle, either/or an rms value of the input voltage, either/or an average input voltage over a half cycle. A feedback terminal FB 514 receives a voltage VVOUT representative of an output voltage at the output of PFC converter 100. In one example, voltage VVOUT may be any constant value.
As shown, a reference current IREF flows from a current source 520 in the opposite direction of a scaled current ISVIN which flows from a current source 522. More specifically, scaled current ISVIN is equal to current MN multiplied by a scaling factor for signal processing. A capacitor COFF 524 is coupled across a transistor TOFF 526. In operation, capacitor COFF 524 charges when transistor TOFF 526 is off. More specifically, the current that charges capacitor COFF 524 is the difference between reference current IREF and scaled current ISVIN. When transistor TOFF 526 turns on, capacitor COFF 524 discharges via a common return 529. A voltage comparator 528 is coupled to capacitor COFF 524 such that a negative terminal of the comparator 528 is at a same potential voltage as the capacitor COFF 524. When the voltage on capacitor COFF 524 equals an adjusted error voltage V′ERR 530, a voltage signal VOFF 532 transitions from low to high which results in power MOSFET 502 transitioning to an on state. In this manner, the off time of a switching cycle for power MOSFET 502 is adjusted. In one embodiment of the present invention, capacitor COFF 524 functions as an integrator that integrates a difference between a constant voltage and an input voltage of a power converter to determine the off time of a switching cycle.
In operation, in the example shown, an error voltage VERR 531 is an output of error amplifier 533. In operation, error amplifier 533 compares voltage VVOUT with a reference voltage VREF 535 to determine error voltage VERR 531 which is representative of the output voltage at the output of a power converter. According to an embodiment of the present invention voltage error signal VERR 531 gives an indication of the output voltage of the power converter 100 and also the load at the output of the controller. According to the teachings of the present invention, the error signal VERR 531 is designed to have a substantially slower response time in comparison to the switching signal USW 119 (e.g., drive signal 554). For example, in one embodiment, error signal VERR 531 is an averaged value representative of an averaged magnitude of output voltage VOUT 124 over several line cycles such that output voltage VOUT 124 is considered a substantially constant value when controlling the input current over a line cycle.
More specifically, in this example, error signal VERR 531 is substantially non-responsive to ac time variances in the output voltage VOUT 124 over a line cycle. It can also be assumed that error signal VERR 531 is substantially constant over multiple switching cycles. In one example, error voltage VERR 531 may be output via a COMP terminal 537 to a gain setting filter that adjusts a response time of error voltage VERR 531.
As shown in the example, a switching frequency adjuster 501 is coupled between the output of error amplifier 533 and a non inverting terminal of comparator 528. Switching frequency adjuster 501 is one possible implementation of switching frequency adjustor 204 of FIG. 2, while some or all of the remaining circuitry of integrated circuit controller 500 is a possible implementation of PFC circuitry 202. In operation, switching frequency adjuster 501 outputs an adjusted error signal VERR 530 in response to receiving an error voltage signal VERR 531. In one example according to the embodiment of the present invention the error voltage signal VERR 531 is modified based on the following equation:

V′ERR=VC−VERR  EQ. 1

where VC is a constant value determined based on design parameters of the feedback loop of PFC converter 100. In accordance with the teachings of the present invention, error voltage signal VERR 531 can be considered equivalent to load signal ULOAD 206 shown in FIG. 2. More specifically, the magnitude of the error voltage signal VERR 531 is directly proportional to the load at the output of the power converter. Typically, the magnitude of error voltage signal VERR 531 may be influenced by a varying input voltage as well as a changing load condition, therefore a directly proportional relationship between the magnitude of the feedback signal VERR 531 and the load condition at the output of the power converter may be difficult to establish. According to the embodiment of the present invention, input voltage detector generates signal current IVIN2 which is representative of an average input voltage value and is multiplied with current source 534 to offset the effects of input voltage on the magnitude of error voltage signal VERR 531. In other words, current IVIN2 is multiplied to current source 534 in a feed forward system such that the magnitude of error voltage signal VERR 531 is independent of input voltage VIN 111 and may be representative of the load 126 coupled to the output of PFC converter 100. In one embodiment according to the present invention adjusted error signal V′ERR 530 can be considered the equivalent of frequency adjust signal fADJ 208 in FIG. 2.

In another example embodiment according to the present invention, switching frequency adjuster 501 is coupled between error amplifier 533 and the positive input terminal of voltage comparator 544. In operation of this example the adjusted error signal V′ERR 530 is received by voltage comparator 544.
As shown in the example of FIG. 5A, a current source 534 outputs a scaled current ISIIN that is representative of a sensed input current IS 538 multiplied by a scaling factor for signal processing. A capacitor CON 540 is coupled across a transistor TON 542. In operation, scaled current ISIIN charges capacitor CON 540 when transistor TON 542 is off. When transistor TON 542 is on, capacitor CON 540 discharges via common return 529. Voltage comparator 544 is coupled to capacitor CON 540 such that a negative input of the comparator 544 is at the same potential voltage as the capacitor CON 540. When the voltage on capacitor CON 540 equals error voltage VERR 531, a voltage signal VON 546 at an output of comparator 544 transitions from a low signal to a high signal, which results in setting power MOSFET 502 to an off state. In this manner, the on time of a switching cycle for power MOSFET 502 is controlled. In one aspect of the present invention, the capacitor CON 540 functions as an integrator that integrates an input current of a power converter to determine the on time of a switching cycle.
As shown in the example of FIG. 5A, a first input of an OR gate 548 is coupled to the output of comparator 544 and a second input of OR gate 548 is coupled to an output of an AND gate 550. In operation, OR gate 548 outputs a high signal to reset (R) of latch 552 when the voltage signal VON 546 transitions high or an over current protection (OCP) signal 553 transitions high. In operation, when reset input R of latch 552 receives a high signal, output Q is set high and complementary output Q is set low. Conversely, when voltage signal VOFF 532 transitions high, input S of latch 552 sets output Q low and complementary output Q is set high. In this manner, complementary output Q outputs a drive signal DRIVE 554 that controls a switching of power MOSFET 502. An amplifier 556, amplifies drive signal DRIVE 554 in order to supply adequate current to charge and discharge the gate of power MOSFET 502 to control the switching of power MOSFET 502.
As shown in the example, a current limit comparator 558 compares sensed input current IS 538 with a current limit reference ILIM 559. In one example, the output of current limit comparator 558 goes high when the sensed input current IS 538 reaches the current limit reference ILIM 559. More specifically, in this example, sensed input current IS 538 is a portion of input current IIN 503. In one example, sensed input current IS 538 is representative of input current IIN 503 in accordance with the teachings of present invention. In one example, drive signal 554 is delayed by leading edge blanking (LEB) circuit 562 before being applied to the input of AND gate 550 to prevent the over current protection signal 553 from indicating a false current limit condition when power MOSFET 502 momentarily discharges stray capacitance as it turns on. More specifically, over current protection signal 553 indicates when the current in power MOSFET 502 has reached the current limit reference ILIM 559, to prevent damage to the power MOSFET 502 and/or any other internal components of integrated circuit 500.
As is discussed above the teachings of the present invention allow a power converter to employ a control technique to shape an input current waveform of the power converter. In addition average frequency adjust circuit 501 is included to adjust the average switching frequency of MOSFET 502 along all load ranges to limit losses in the controller. In the examples discussed, the PFC controller controls the input current waveform to follow the shape of an input voltage waveform by varying an on time and an off time of a power switch in the power converter. More specifically, the input current is controlled to be directly proportional to the input voltage over each half line cycle. However, when the input current is averaged out over multiple half line cycles input current IIN 111 is no longer proportional to the input voltage VIN 110. More specifically, the control technique forces the on time of the power switch to be inversely proportional to a rectified time-varying input voltage VIN(t) by setting a constant volt-seconds for the off time. The off-time is controlled to be a constant product of:

(VOUT−VIN)×TOFF  EQ. 2

In particular, integrating the quantity:

VOUT−VIN  EQ. 3

during the off time allows for a constant volt-seconds to be set during the off time. By setting the off time to have a constant volt-seconds, the on-time volt-seconds is forced to be substantially constant over a few switching cycles in order to maintain a volt-second balance that satisfies the properties of a boost inductor. A balance of volt-seconds on the boost inductor allows the on-time to be substantially inversely proportional to the input voltage. This relationship of on-time to input voltage sets up a convenient and simple means for controlling the input current as a function of the rectified time varying input voltage VIN(t) which is representative of the input line voltage. If the input current is sensed by integrating the input current during the on time, the on time can be terminated by reaching a constant integral value of:





  
    
      
        
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where the duration from T1 to T2 is the on time as determined by the substantially constant feedback signal over a few switching cycles. This will cause average input current over a switching cycle to be substantially proportional to the input voltage.

Referring now to FIG. 5B, an example switching frequency adjuster 501 includes a current mirror 560 in accordance with the teachings of the present invention. As shown, current mirror 560 further includes a gate of a first transistor T1 562 coupled to a gate of a second transistor T2 564. In operation, current mirror 560 receives first current I1 to control a second current I2 through second transistor T2 564. More specifically, error voltage signal VERR 531 is converted to first current I1 by a first resistor R1 566 and second current I2 is proportional to first current I1 due to the current mirror configuration. In other words, as first current I1 increases the second current I2 will increase proportionately. A second resistor R2 568 converts the constant voltage VC, discussed in FIG. 5A, to second current I2. Adjusted error voltage V′ERR 530 is determined. In an example operation, as first current I1 increases due to an increase in error voltage signal V′ERR 530, the second current I2 increases in proportion. As second current I2 increases, a voltage drop across second resistor R2 568 increases thus reducing the magnitude of the adjust error voltage signal V′ERR 530. According to the embodiment in FIG. 5A, since adjusted error signal V′ERR 530 functions as a threshold to determine the off time, as shown in the example control circuit of FIG. 5A, the adjusted error voltage signal V′ERR 530 adjusts the average switching frequency of the switch by varying the off time of power switch SW1 118 during a switching cycle
Referring now to FIG. 6A, an example graph 600 further illustrates the functional relationship of adjusted error voltage signal V′ERR 530 as a function of error voltage signal VERR 531 implemented by average frequency adjuster 501 according to an embodiment of the present invention. In one example, error voltage signal VERR 531 is representative of load signal ULOAD 206 and adjusted error voltage signal V′ERR 530 is representative of frequency adjust signal fADJ 208. As shown, the magnitude of voltage error signal VERR 531 increases as load increases. Conversely, adjusted error voltage signal V′ERR 530 decreases as load increases. As stated above, in one example, a relationship between error voltage VERR 531, adjusted error voltage V′ERR 530, and a constant voltage VC is described below:

V′ERR=VCVERR  EQ. 5

where VC is a constant voltage that is picked in accordance with the design parameters of the feedback loop in the PFC converter 100. In alternate embodiments according to the teachings of the present invention, graph 600 may resemble other functional relationships or a combination of the other functional relationships between average switching frequency and load as illustrated in FIGS. 4A, 4B, 4C, and 4D.

Referring now to FIG. 6B, a graph 650 illustrates a first adjusted error voltage V′ERR1 and a second adjusted voltage V′ERR2. As shown, adjusted error voltage V′ERR 530 has an inverse relationship with the load, therefore when the adjusted error voltage V′ERR 530 is increased from V′ERR1 to V′ERR2 it is representative of a decreasing load at the output of PFC converter 100.
Referring back to FIG. 5, when adjusted error voltage threshold V′ERR 530 increases it will take a longer time for the voltage across capacitor COFF 524 to meet the increased adjusted threshold and therefore delay the time the MOSFET 502 is turned on again, thus lengthening the off time of the switching cycle. In this manner the average switching frequency is reduced when load 126 at the output of PFC converter 100 is reduced. Due to the control technique implemented in integrated controller 500 the on time of each switching cycle is also stretched so as to maintain to the same duty ratio. Conversely, the average switching frequency can be increased when load 126 increases the adjusted voltage reference coupled to positive terminal of voltage comparator 528 thus reducing the time it takes to charge CON 540 and leading to a shorter off time.
FIG. 7 is a flow diagram illustrating an example method for adjusting the switching frequency in response to a varying load condition according to the teachings of the present invention. In a process block 710, switch SW1 118 is switched to regulate an output voltage and to implement power factor correction such that the input current IIN 111 is directly proportional to the input current VIN 110. In a next process block 715, PFC circuitry 212 outputs a load signal ULOAD 206 representative of load 126 to an average frequency adjuster 204. In a next process block 720, switching frequency adjuster outputs frequency adjust signal fADJ 208 to PFC circuitry to adjust the average switching frequency in response to the load signal ULOAD 206. In a next process block 725, PFC circuitry adjusts switching signal USW 119 such that the average switching frequency of power switch SW1 1118 is adjusted in response to load 126 coupled to output of PFC converter 100. After execution of decision block 725, the process returns back to process block 710.
The above description of illustrated examples of the present invention, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention.
These modifications can be made to examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The present specification and figures are accordingly to be regarded as illustrative rather than restrictive.

## Claims

1. A power factor correction (PFC) controller, comprising:
a first integrator coupled to integrate an input current of a PFC converter, wherein a first signal is generated in response to the first integrator to end an on time of a power switch of the PFC converter;
a second integrator coupled to integrate a difference between a constant voltage and an input voltage of the PFC converter, wherein a second signal is generated in response to the second integrator to end an off time of the power switch of the PFC converter; and
a driver circuit coupled to vary the switching frequency of the power switch of the PFC converter in response to the first and the second signals and to output a third signal to switch the power switch of the PFC converter to control the input current to be substantially proportional to the input voltage.

2. The PFC controller of claim 1 further comprising a frequency adjust circuit coupled to receive an error voltage signal representative of an output of the PFC converter, wherein the frequency adjust circuit is further coupled to output an adjusted error signal to adjust the end of the off time of the power switch of the PFC converter in response to the error voltage signal.

3. The PFC controller of claim 2 wherein the driver circuit is coupled to regulate an output voltage of the PFC converter.

4. The PFC controller of claim 1 wherein the power switch of the PFC converter comprises a metal oxide field effect transistor (MOSFET).

5. The PFC controller of claim 2 further comprising an error amplifier coupled to generate the error voltage signal in response to a feedback signal representative of the output of the PFC converter and a reference voltage.

6. The PFC controller of claim 1 wherein the first integrator includes a first capacitor coupled to be charged with a scaled current when the power switch is on, wherein the scaled current is representative of the input current.

7. The PFC controller of claim 6 wherein a scaling factor of the scaled current is representative of a peak input voltage of a half-line cycle.

8. The PFC controller of claim 6 wherein a scaling factor of the scaled current is representative of an rms value of the input voltage.

9. The PFC controller of claim 6 wherein a scaling factor of the scaled current is representative of an average input voltage over a half cycle.

10. The PFC controller of claim 6 further comprising a first comparator coupled to compare a voltage on the first capacitor with an error voltage signal representative of an output of the PFC converter and to generate the first signal.

11. The PFC controller of claim 1 wherein the second integrator includes a second capacitor coupled to be charged with a difference between a scaled current and a reference current when the power switch is off, wherein the scaled current is representative of the input voltage.

12. The PFC controller of claim 11 wherein a scaling factor of the scaled current is representative of an instantaneous dc input voltage.

13. The PFC controller of claim 11 further comprising a second comparator coupled to compare a voltage on the second capacitor with an adjusted error signal and to generate the second signal.