# Patent

## Title
Digitally controlled oscillator

## Abstract

A digitally controlled oscillator is provided. The digitally controlled oscillator includes a pair of transistors cross-coupled to each other, a switched capacitor array coupled to the pair of transistors and a plurality of frequency tracking units coupled to the pair of transistors. The pair of transistors provides an output signal. The switched capacitor array tunes a frequency of the output signal. The frequency tracking units tune the frequency of the output signal to a target frequency. At least one of the frequency tracking units is capable of selectively providing a first capacitance and a second capacitance. A tuning resolution of the frequency tracking unit is determined by a difference between the first and second capacitances.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an oscillator, and more particularly to a digitally controlled oscillator.
2. Description of the Related Art
Generally, a digitally controlled oscillator (DCO) has a relatively wide tuning range in order to execute phase locked loop (PLL), voltage controlled oscillator (VCO) or other circuit digital automatic frequency calibration. In a DCO, the oscillating frequency is adjusted by controlling a plurality of digitally controlled frequency tracking units. In order to provide finer tuning resolutions and wider tuning ranges, a large number of frequency tracking units are needed for the oscillating frequency adjustment.
In a PLL, the DCO will contribute extra quantization noise as the frequency tracking units have finite tuning resolutions. In some improved circuits, the extra quantization noise can be noise shaped by a delta-sigma (4E) modulator, to meet phase noise (PN) requirements. However, the frequency tracking units may increase design complexity and reversely affect the operation frequency of the delta-sigma modulator.
Nevertheless, when the amount of frequency tracking units increases, the performance of the DCO is affected by the mismatches among the capacitors of the frequency tracking units. For example, the mismatch will degrade the phase error, the error vector magnitude (EVM) and the output RF spectrum (ORFS) performances of a direct frequency modulation transmitter using such a DCO implementing a large number of the frequency tracking units. Furthermore, a larger parasitic capacitor will narrow the total tuning range of the oscillating frequency the DCO can provide.
Accordingly, it is difficult to implement a DCO with a fine resolution.
BRIEF SUMMARY OF THE INVENTION
Digitally controlled oscillators are provided. An embodiment of a digitally controlled oscillator is provided. The digitally controlled oscillator comprises: a pair of transistors cross-coupled to each other for generating an output signal; a switched capacitor array coupled to the pair of transistors, for tuning a frequency of the output signal; and a plurality of frequency tracking units coupled to the pair of transistors, for tuning the frequency of the output signal to a target frequency. At least one of the frequency tracking units is capable of selectively providing a first capacitance and a second capacitance, and a tuning resolution of the frequency tracking unit is determined by a difference between the first and second capacitances.
Furthermore, another embodiment of a digitally controlled oscillator is provided. The digitally controlled oscillator comprises an amplifier with a negative resistance, having a first input terminal, a second input terminal and an output terminal for providing an output signal; and an LC circuit coupled to the first and second input terminals of the amplifier. The LC circuit comprises an inductor coupled between the first and second input terminals of the amplifier; and a plurality of frequency tracking units coupled to the inductor in parallel, each for providing a first capacitance or a second capacitance according to a control signal, so as to finely tune a frequency of the output signal. A tuning resolution of the frequency tracking unit is determined according to a difference between the first and second capacitances.
A detailed description is given in the following embodiments with reference to the accompanying drawings.



BRIEF DESCRIPTION OF DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 shows a digitally controlled oscillator according to an embodiment of the invention;
FIG. 2 shows a schematic illustrating the frequency tracking unit of FIG. 1 according to an embodiment of the invention;
FIG. 3 shows a digitally controlled oscillator according to another embodiment of the invention;
FIG. 4 shows a schematic illustrating the sub-unit of a frequency tracking unit of FIG. 3 according to an embodiment of the invention;
FIG. 5 shows a schematic illustrating the sub-unit of a frequency tracking unit of FIG. 3 according to another embodiment of the invention;
FIG. 6 shows a schematic illustrating the sub-unit frequency tracking unit of FIG. 3 according to another embodiment of the invention;
FIG. 7 shows a digitally controlled oscillator according to another embodiment of the invention; and
FIG. 8 shows a digitally controlled oscillator according to another embodiment of the invention.



DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 1 shows a digitally controlled oscillator (DCO) 100 according to an embodiment of the invention. The digitally controlled oscillator 100 comprises the transistors M1 and M2, a switched capacitor array 10, a frequency tracking array 20, two inductors L1 and L2 and a resistor R. The transistors M1 and M2 are cross-coupled to each other. The switched capacitor array 10 is coupled to the drains of the transistors M1 and M2, and the frequency tracking array 20 is coupled to the switched capacitor array 10 in parallel. The inductor L1 is coupled between a common node Ncom and the drain of the transistor M1, and the inductor L2 is coupled between the common node Ncom and the drain of the transistor M2. The resistor R is coupled between the common node Ncom and a ground GND.
In FIG. 1, the switched capacitor array 10 comprises a plurality of switched capacitor units 30 coupled in parallel. Each switched capacitor unit 30 comprises a capacitor C1 coupled to the drain of the transistor M1, a capacitor C2 coupled to the drain of the transistor M2 and a switch SW coupled between the capacitors C1 and C2, wherein the switch SW is controlled by an individual control signal. By switching the switches SW of the switched capacitor array 10, an output frequency of a signal Sout can be tuned coarsely. The switched capacitor unit 30 is used as an example for description, and does not limit the invention. Furthermore, the frequency tracking array 20 comprises a plurality of frequency tracking units 40 coupled in parallel, which is used to finely tune the output frequency of the signal Sout to a target frequency. In the frequency tracking array 20, each frequency tracking unit 40 is controlled by an individual control signal that controls the frequency tracking unit 40 to provide a first capacitance or a second capacitance. In the embodiment, the first capacitances of the frequency tracking units 40 are the same, and the second capacitances of the frequency tracking units 40 are the same.
FIG. 2 shows a schematic illustrating the frequency tracking unit 40 of FIG. 1 according to an embodiment of the invention. The frequency tracking unit 40 comprises three capacitors CA1, CA2 and CB, two resistors R1 and R2 and a switch MSW. Referring to FIG. 1 and FIG. 2 together, the capacitor CA1 is coupled between the drain of the transistor M1 and a node N1, and the capacitor CA2 is coupled between the drain of the transistor M2 and a node N2, wherein the capacitors CA1 and CA2 have the same capacitances. The capacitor CB is coupled between the nodes N1 and N2. The resistor R1 is coupled between the node N1 and the ground GND, and the resistor R2 is coupled between the node N2 and the ground GND. The switch MSW is coupled to the capacitor CB in parallel, which is controlled by an individual control signal Sctrl. When the switch MSW is turned on by the control signal Sctrl, the frequency tracking unit 40 provides an equivalent capacitance CON according to the capacitors CA1 and CA2. When the switch MSW is turned off by the control signal ctrl, the frequency tracking unit 40 provides an equivalent capacitance COFF according to the capacitors CA1, CA2 and CB. The equivalent capacitances CON and COFF are obtained by the following equations:



  
    
      C
      ON
    
    =
    
      
        
          C
          A
        
        2
      
      =
      
        C
        AD
      
    
  




  
    
      C
      OFF
    
    =
    
      
        
          
            
              C
              A
            
            2
          
          ·
          
            C
            B
          
        
        
          
            
              C
              A
            
            2
          
          +
          
            C
            B
          
        
      
      =
      
        
          
            
              C
              AD
            
            ·
            
              C
              B
            
          
          
            
              C
              AD
            
            +
            
              C
              B
            
          
        
        .
      
    
  



Therefore, a unit capacitance Cstep is obtained according to a difference between the capacitances CON and COFF, wherein Cstep is obtained by the following equation:





  
    
      
        
          C
          step
        
        =
        
          
            
              C
              ON
            
            -
            
              C
              OFF
            
          
          =
          
          ⁢
          
            
              C
              AD
              2
            
            
              
                C
                AD
              
              +
              
                C
                B
              
            
          
        
      
    
    
      
        
      
    
  
  
    
      
        
          =
          
          ⁢
          
            
              C
              AD
              2
            
            
              C
              B
            
          
        
        ,
      
    
    
      
        if
        ⁢
        
          
        
        ⁢
        
          C
          AD
        
        ⁢
        
          
            <<
            
              C
              B
            
          
          .
        
      
    
  




In the embodiment, the unit capacitance Cstep is used as a tuning resolution of the frequency tracking unit 40 for turning the output frequency of the signal Sout to a target frequency. Note that the three capacitors CA1, CA2 and CB, are passive metal capacitors which are insensitive to noise and voltage swings. Furthermore, low fixed parasitical capacitances are obtained and layout structure of the frequency tracking unit 40 is easily matched for the capacitors CA1, CA2 and CB. For example, the mismatching of the frequency tracking unit 40 is obtained by the following equation:




  
    
      Δ
      ⁢
      
        
      
      ⁢
      
        C
        step
      
    
    
      C
      step
    
  
  =
  
    
      2
      ⁢
      
        
          Δ
          ⁢
          
            
          
          ⁢
          
            C
            AD
          
        
        
          C
          AD
        
      
    
    -
    
      
        
          Δ
          ⁢
          
            
          
          ⁢
          
            C
            B
          
        
        
          C
          B
        
      
      .
    
  




Therefore, the gain factor KDCO of the digitally controlled oscillator 100 of FIG. 1 is obtained by the following equation:





  
    
      K
      DCO
    
    =
    
      
        
          C
          step
        
        
          2
          ·
          
            C
            
              tan
              ⁢
              
                
              
              ⁢
              k
            
          
        
      
      ·
      
        f
        DCO
      
    
  
  ,




where fDCO represents the output frequency of the signal Sout, i.e.





  
    
      f
      DCO
    
    =
    
      1
      
        2
        ⁢
        
          π
          ·
          
            
              LC
              
                tan
                ⁢
                
                  
                
                ⁢
                k
              
            
          
        
      
    
  
  ,




wherein Ctank and L represent the tank capacitance and inductance, respectively. In one embodiment, each of the capacitors CA1, CA2 and CB may be formed by a plurality of capacitors connected in series, parallel or combinations thereof.

FIG. 3 shows a digitally controlled oscillator 200 according to another embodiment of the invention. Compared with the digitally controlled oscillator 100 of FIG. 1, a frequency tracking array 50 of the digitally controlled oscillator 200 comprises a plurality of frequency tracking units 60 coupled in parallel, wherein each frequency tracking unit 60 comprises a sub-unit 70A coupled between the drain of the transistor M1 and the ground GND and a sub-unit 70B coupled between the drain of the transistor M2 and the ground GND, wherein the sub-units 70A and 70B have the same circuit structures. Similarly, each frequency tracking unit 60 is controlled by an individual control signal, i.e. the sub-units 70A and 70B of the frequency tracking unit 60 are controlled by the same control signal, wherein the individual control signal controls the sub-units 70A and 70B to provide a first capacitance or a second capacitance simultaneously. In the embodiment, the first capacitances of the sub-units 70A and 70B of each frequency tracking unit 60 are the same, and the second capacitances of the sub-units 70A and 70B of each frequency tracking units 60 are the same.
FIG. 4 shows a schematic illustrating the sub-unit 70A/70B of FIG. 3 according to an embodiment of the invention. Referring to FIG. 3 and FIG. 4 together, a capacitor CA is coupled to the drain of a corresponding transistor. For example, the capacitor CA of the sub-unit 70A is coupled to the drain of the transistor Ml, and the capacitor CA of the sub-unit 70B is coupled to the drain of the transistor M2. Furthermore, a capacitor CB is coupled between the capacitor CA and the ground GND, and a switch MSW is coupled to the capacitor CB in parallel, wherein the switch MSW is controlled by an individual control signal Sctrl. When the switch MSW is turned on by the control signal Sctrl, the sub-unit 70A/70B provides an equivalent capacitance CON1 according to the capacitor CA. When the switch MSW is turned off by the control signal Sctrl, the sub-unit 70A/70B provides an equivalent capacitance COFF1 according to the capacitors CA and CB. The equivalent capacitances CON1 and COFF1 are obtained by the following equations:



  
    
      C
      
        ON
        ⁢
        
          
        
        ⁢
        1
      
    
    =
    
      C
      A
    
  




  
    
      C
      
        OFF
        ⁢
        
          
        
        ⁢
        1
      
    
    =
    
      
        
          
            C
            A
          
          ·
          
            C
            B
          
        
        
          
            C
            A
          
          +
          
            C
            B
          
        
      
      .
    
  



Therefore, a unit capacitance Cstep1 is obtained according to a difference between the capacitances CON1 and COFF1, wherein Cstep1 is obtained by the following equation:





  
    C
    
      step
      ⁢
      
        
      
      ⁢
      1
    
  
  =
  
    
      
        C
        
          ON
          ⁢
          
            
          
          ⁢
          1
        
      
      -
      
        C
        
          OFF
          ⁢
          
            
          
          ⁢
          1
        
      
    
    =
    
      
        
          C
          A
          2
        
        
          
            C
            A
          
          +
          
            C
            B
          
        
      
      .
    
  




In the embodiment, the unit capacitance Cstep1 is used as a tuning resolution of the frequency tracking unit 60 for turning the output frequency of the signal Sout to a target frequency. Furthermore, the capacitors CA and CB are passive metal capacitors.

FIG. 5 shows a schematic illustrating the sub-unit 70A/70B of FIG. 3 according to another embodiment of the invention. Referring to FIG. 3 and FIG. 5 together, the capacitors CA1 and CA2 are coupled to the drain of a corresponding transistor. For example, the capacitors CA1 and CA2 of the sub-unit 70A are coupled to the drain of the transistor M1, and the capacitors CA1 and CA2 of the sub-unit 70B are coupled to the drain of the transistor M2. A capacitor CB1 is coupled between the capacitor CA1 and the ground GND, and a switch MSW1 is coupled to the capacitor CB1 in parallel, wherein the switch MSW1 is controlled by an individual control signal Sctrl. A capacitor CB2 is coupled between the capacitor CA2 and the ground GND, and a switch MSW2 is coupled to the capacitor CB2 in parallel, wherein the switch MSW2 is controlled by a control signal SBctrl that is complementary to the control signal Sctrl. When the switch MSW1 is turned on by the control signal Sctrl and the switch MSW2 is turned off by the control signal SBctrl, the sub-unit 70A/70B provides an equivalent capacitance CON2 according to the capacitors CA1, CA2 and CB2. When the switch MSW1 is turned off by the control signal Scttl and the switch MSW2 is turned on by the control signal SBctrl, the sub-unit 70A/70B provides an equivalent capacitance COFF2 according to the capacitors CA1, CB1 and CA2. In the embodiment, the capacitors CA1 and CA2 have the same capacitance CA, thus the equivalent capacitances CON2 and COFF2 are obtained by the following equations:



  
    
      C
      
        ON
        ⁢
        
          
        
        ⁢
        2
      
    
    =
    
      
        
          
            C
            A
          
          ·
          
            C
            
              B
              ⁢
              
                
              
              ⁢
              2
            
          
        
        
          
            C
            A
          
          +
          
            C
            
              B
              ⁢
              
                
              
              ⁢
              2
            
          
        
      
      +
      
        C
        A
      
    
  




  
    
      C
      
        OFF
        ⁢
        
          
        
        ⁢
        2
      
    
    =
    
      
        
          
            C
            A
          
          ·
          
            C
            
              B
              ⁢
              
                
              
              ⁢
              1
            
          
        
        
          
            C
            A
          
          +
          
            C
            
              B
              ⁢
              
                
              
              ⁢
              1
            
          
        
      
      +
      
        
          C
          A
        
        .
      
    
  



Therefore, a unit capacitance Cstep2 is obtained according to a difference between the capacitances CON2 and COFF2, wherein Cstep2 is obtained by the following equation:





  
    C
    
      step
      ⁢
      
        
      
      ⁢
      2
    
  
  =
  
    
      
        C
        
          ON
          ⁢
          
            
          
          ⁢
          2
        
      
      -
      
        C
        
          OFF
          ⁢
          
            
          
          ⁢
          2
        
      
    
    =
    
      
        
          
            C
            A
            2
          
          ⁡
          
            (
            
              
                C
                
                  B
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              -
              
                C
                
                  B
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            )
          
        
        
          
            (
            
              
                C
                A
              
              +
              
                C
                
                  B
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            )
          
          ⁢
          
            (
            
              
                C
                A
              
              +
              
                C
                
                  B
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
            )
          
        
      
      .
    
  




In the embodiment, the unit capacitance Cstep2 is used as a tuning resolution of the frequency tracking unit 60 for turning the output frequency of the signal Sout to a target frequency. Furthermore, the capacitors CA1, CA2, CB1 and CB2 are passive metal capacitors.

FIG. 6 shows a schematic illustrating the sub-unit 70A/70B of FIG. 3 according to another embodiment of the invention. Referring to FIG. 3 and FIG. 6 together, the capacitor CA is coupled to the drain of a corresponding transistor. For example, the capacitors CA of the sub-unit 70A is coupled to the drain of the transistor M1, and the capacitors CA of the sub-unit 70B is coupled to the drain of the transistor M2. Two capacitors CB1 and CB2 are coupled to the capacitor C. A switch MSW1 is coupled between the capacitor CB1 and the ground GND, wherein the switch MSW1 is controlled by an individual control signal Sctrl. A switch MSW2 is coupled between the capacitor CB2 and the ground GND, wherein the switch MSW2 is controlled by a control signal SBctrl complementary to the control signal Sctrl. When the switch MSW1 is turned on by the control signal Sctrl and the switch MSW2 is turned off by the control signal SBctrl, the sub-unit 70A/70B provides an equivalent capacitance CON3 according to the capacitors CA and CB1. When the switch MSW1 is turned off by the control signal Sctrl and the switch MSW2 is turned on by the control signal SBctrl, the sub-unit 70A/70B provides an equivalent capacitance COFF3 according to the capacitors CA and CB2. The equivalent capacitances CON3 and COFF3 are obtained by the following equations:



  
    
      C
      
        ON
        ⁢
        
          
        
        ⁢
        3
      
    
    =
    
      
        
          C
          A
        
        ·
        
          C
          
            B
            ⁢
            
              
            
            ⁢
            1
          
        
      
      
        
          C
          A
        
        +
        
          C
          
            B
            ⁢
            
              
            
            ⁢
            1
          
        
      
    
  




  
    
      C
      
        OFF
        ⁢
        
          
        
        ⁢
        3
      
    
    =
    
      
        
          
            C
            A
          
          ·
          
            C
            
              B
              ⁢
              
                
              
              ⁢
              2
            
          
        
        
          
            C
            A
          
          +
          
            C
            
              B
              ⁢
              
                
              
              ⁢
              2
            
          
        
      
      .
    
  



Therefore, a unit capacitance Cstep3 is obtained according to a difference between the capacitances CON3 and COFF3, wherein Cstep3 is obtained by the following equation:





  
    C
    
      step
      ⁢
      
        
      
      ⁢
      3
    
  
  =
  
    
      
        C
        
          ON
          ⁢
          
            
          
          ⁢
          3
        
      
      -
      
        C
        
          OFF
          ⁢
          
            
          
          ⁢
          3
        
      
    
    =
    
      
        
          
            C
            A
            2
          
          ⁡
          
            (
            
              
                C
                
                  B
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              -
              
                C
                
                  B
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
            )
          
        
        
          
            (
            
              
                C
                A
              
              +
              
                C
                
                  B
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            )
          
          ⁢
          
            (
            
              
                C
                A
              
              +
              
                C
                
                  B
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
            )
          
        
      
      .
    
  




In the embodiment, the unit capacitance Cstep3 is used as a tuning resolution of the frequency tracking unit 60 for turning the output frequency of the signal Sout to a target frequency. Furthermore, the capacitors CA, CB1 and CB2 are passive metal capacitors.

FIG. 7 shows a digitally controlled oscillator 300 according to another embodiment of the invention. The digitally controlled oscillator 300 comprises an amplifier 80 with a negative resistance and an LC circuit 90. The LC circuit 90 comprises an inductor L coupled between the input terminals In1 and In2 of the amplifier 80, a switched capacitor array 10 and a frequency tracking array 20, wherein the switched capacitor array 10 and frequency tracking array 20 are coupled to the inductor L in parallel. In one embodiment, the amplifier 80 comprises a pair of transistors cross-coupled to each other, e.g. the transistors M1 and M2 of FIG. 1 and FIG. 3. As described above, the switched capacitor array 10 comprises a plurality of switched capacitor units 30 coupled in parallel. Each switched capacitor unit 30 comprises a capacitor C1 coupled to the input terminal In1 of the amplifier 80, a capacitor C2 coupled to the input terminal In2 of the amplifier 80 and a switch SW coupled between the capacitors C1 and C2, wherein the switch SW is controlled by an individual control signal. By switching the switches SW of the switched capacitor array 10, an output frequency of a signal Sout provided by the amplifier 80 can be tuned coarsely. Furthermore, the frequency tracking array 20 comprises a plurality of frequency tracking units 40 coupled between the input terminals In1 and In2 of the amplifier 80, which is used to finely tune the output frequency of the signal Sout to a target frequency. In the frequency tracking array 20, each frequency tracking unit 40 is controlled by an individual control signal that controls the frequency tracking unit 40 to provide a first capacitance (e.g. CON) or a second capacitance (e.g. COFF), so as to obtain a unit capacitance (e.g. Cstep) that is used as a tuning resolution for turning the output frequency of the signal Sout.
FIG. 8 shows a digitally controlled oscillator 400 according to another embodiment of the invention. In the digitally controlled oscillator 400, a frequency tracking array 50 comprises a plurality of frequency tracking units 60 coupled between the input terminals In1 and In2 of the amplifier 80. As described above, each frequency tracking unit 60 comprises a sub-unit 70A coupled between the input terminal In1 of the amplifier 80 and the ground GND and a sub-unit 70B coupled between the input terminal In2 of the amplifier 80 and the ground GND, wherein the sub-units 70A and 70B have the same circuit structures. Similarly, each frequency tracking unit 60 is controlled by an individual control signal, i.e. the sub-units 70A and 70B of the frequency tracking unit 60 are controlled by the same control signal, wherein the individual control signal controls the sub-units 70A and 70B to provide a first capacitance (e.g. CON1, CON2 and CON3) or a second capacitance (e.g. COFF1, COFF2 and COFF3) simultaneously, so as to obtain a unit capacitance (e.g. Cstep1, Cstep2 and Cstep3) that is used as a tuning resolution for turning the output frequency of the signal Sout.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

## Claims

1. A digitally controlled oscillator, comprising:
a pair of transistors cross-coupled to each other for providing an output signal;
a switched capacitor array coupled to the pair of transistors, for tuning a frequency of the output signal; and
a plurality of frequency tracking units coupled to the pair of transistors, for tuning the frequency of the output signal to a target frequency, wherein at least one of the frequency tracking units is capable of selectively providing only one of a first capacitance and a second capacitance, and a tuning resolution of the frequency tracking units is determined by a difference between the first and second capacitances, wherein at least one of the frequency tracking units comprises:
a first capacitor coupled to one drain of the pair of transistors;
a second capacitor coupled between the first capacitor and a ground; and
a first switch coupled to the second capacitor in parallel, wherein the first switch is arranged to have only ON and OFF states;
wherein the at least one of the frequency tracking units provides only the first capacitance when the first switch is in the ON state and provides the second capacitance when the first switch is in the OFF state.

2. The digitally controlled oscillator as claimed in claim 1, further comprising:
a first inductor coupled between a common node and the one drain of the pair of transistors; and
a second inductor coupled between the common node and the other drain of the pair of transistors.

3. The digitally controlled oscillator as claimed in claim 1, wherein the switched capacitor array comprises a plurality of switched capacitor units coupled in parallel, each comprising:
a third capacitor coupled to the one drain of the pair of transistors;
a fourth capacitor coupled to the other drain of the pair of transistors; and
a second switch coupled between the third and fourth capacitors.

4. The digitally controlled oscillator as claimed in claim 1, wherein each of the frequency tracking units comprises a first sub-unit coupled between the one drain of the pair of transistors and the ground, and a second sub-unit coupled between the other drain of the pair of transistors and the ground, wherein at least one of the first and second sub-units comprises the first capacitor and the second capacitor, and the first and second capacitors are metal capacitors.

5. The digitally controlled oscillator as claimed in claim 1, wherein each of the frequency tracking units comprises a first sub-unit coupled between the one drain of the pair of transistors and the ground, and a second sub-unit coupled between the other drain of the pair of transistors and the ground, wherein at least one of the first and second sub-units comprises:
the first capacitor;
the second capacitor;
the first switch;
a third capacitor coupled to the one drain of the pair of transistors, having a capacitance which is identical to the first capacitor;
a fourth capacitor coupled between the third capacitor and the ground, having a capacitance which is identical to the second capacitor; and
a second switch coupled to the fourth capacitor in parallel;
wherein the first, second, third and fourth capacitors are metal capacitors.

6. The digitally controlled oscillator as claimed in claim 1, wherein the tuning resolutions of the frequency tracking units are identical.

7. A digitally controlled oscillator, comprising:
an amplifier with a negative resistance, having a first input terminal, a second input terminal and an output terminal for providing an output signal; and
a LC circuit coupled to the first and second input terminals of the amplifier, comprising:
a inductor coupled between the first and second input terminals of the amplifier; and
a plurality of frequency tracking units coupled to the inductor in parallel, wherein at least one of the frequency tracking units is arranged for providing only one of a first capacitance or a second capacitance according to a control signal, so as to finely tune a frequency of the output signal, wherein at least one of the frequency tracking units comprises:
a first capacitor coupled to a corresponding input terminal of the amplifier;
a second capacitor coupled between the first capacitor and a ground; and
a first switch coupled to the second capacitor in parallel, wherein the first switch is arranged to have only ON and OFF states,
wherein the at least one of the frequency tracking units provides only the first capacitance when the first switch is in the ON state and provides the second capacitance when the first switch is in the OFF state, and
wherein a tuning resolution of the frequency tracking unit is determined according to a difference between the first and second capacitances.

8. The digitally controlled oscillator as claimed in claim 7, wherein each of the frequency tracking units comprises a first sub-unit coupled between the first input terminal of the amplifier and the ground and a second sub-unit coupled between the second input terminal of the amplifier and the ground, wherein at least one of the first and second sub-units comprises the first capacitor and the second capacitor, wherein the first switch is controlled by the control signal, and
the first and second capacitors are metal capacitors.

9. The digitally controlled oscillator as claimed in claim 7, wherein each of the frequency tracking units comprises a first sub-unit coupled between the first input terminal of the amplifier and the ground and a second sub-unit coupled between the second input terminal of the amplifier and the ground, wherein at least one of the first and second sub-units comprises:
the first capacitor;
the second capacitor;
the first switch, wherein the first switch is controlled by the control signal;
a third capacitor coupled to the corresponding input terminal of the amplifier, having a capacitance which is identical to the first capacitor;
a fourth capacitor coupled between the third capacitor and the ground, having a capacitance which is identical to the second capacitor; and
a second switch coupled to the fourth capacitor in parallel, wherein the second switch is controlled by a signal complementary to the control signal;
wherein the first, second, third and fourth capacitors are metal capacitors.

10. The digitally controlled oscillator as claimed in claim 7, wherein the amplifier comprises:
a first transistor having a source coupled to a power, a gate coupled to the second input terminal and a drain coupled to the first input terminal; and
a second transistor having a source coupled to the power, a gate coupled to the first input terminal and a drain coupled to the second input terminal and the output terminal.

11. The digitally controlled oscillator as claimed in claim 7, wherein the LC circuit further comprises:
a switched capacitor array coupled to the inductor in parallel, for coarsely tuning the frequency of the output signal and comprising a plurality of switched capacitor units, wherein each of the switched capacitor units comprises:
a third capacitor coupled to the first input terminal of the amplifier;
a fourth capacitor coupled to the second input terminal of the amplifier; and
a second switch coupled between the third and fourth capacitors.

12. The digitally controlled oscillator as claimed in claim 7, wherein the tuning resolutions of the frequency tracking units are identical.