80210 Federal Register / Vol. 89, No. 191 / Wednesday, October 2, 2024 / Notices 

1Semiconductor Research Corporation, ‘‘MAPT 

Microelectronics and Advanced Packaging 

Technologies Roadmap’’, 2023. Available online at: 

https://srcmapt.org/wp-content/uploads/2024/03/ 

SRC–MAPT-Roadmap-2023-v4.pdf. 

2AI Aspirations: AI for Sustainable Materials, 

White House Office of Science and Technology 

Policy, 2024. Available online at: https://ai.gov/ 

aspirations/. 

exporter certifications have been completed 

and maintained and all other applicable 

certification requirements have been met 

such that the entry is entered into the United 

States as not subject to the antidumping and 

countervailing duty orders on corrosionresistant steel from the People’s Republic of 

China, the antidumping and countervailing 

duty orders on corrosion-resistant steel from 

the Republic of Korea, or the antidumping 

duty order on corrosion-resistant steel from 

Taiwan. 

The products subject to the investigations 

are currently classified in the Harmonized 

Tariff Schedule of the United States (HTSUS) 

under item numbers: 7210.30.0030, 

7210.30.0060, 7210.41.0000, 7210.49.0030, 

7210.49.0040, 7210.49.0045, 7210.49.0091, 

7210.49.0095, 7210.61.0000, 7210.69.0000, 

7210.70.6030, 7210.70.6060, 7210.70.6090, 

7210.90.6000, 7210.90.9000, 7212.20.0000, 

7212.30.1030, 7212.30.1090, 7212.30.3000, 

7212.30.5000, 7212.40.1000, 7212.40.5000, 

7212.50.0000, 7212.60.0000, 7225.91.0000, 

7225.92.0000, 7226.99.0110, and 

7226.99.0130. 

The products subject to the investigations 

may also enter under the following HTSUS 

item numbers: 7210.90.1000, 7215.90.1000, 

7215.90.3000, 7215.90.5000, 7217.20.1500, 

7217.30.1530, 7217.30.1560, 7217.90.1000, 

7217.90.5030, 7217.90.5060, 7217.90.5090, 

7225.99.0090, 7226.99.0180, 7228.60.6000, 

7228.60.8000, and 7229.90.1000. 

The HTSUS subheadings above are 

provided for convenience and customs 

purposes only. The written description of the 

scope of the investigations is dispositive. 

[FR Doc. 2024–22591 Filed 10–1–24; 8:45 am] 

BILLING CODE 3510–DS–P 

DEPARTMENT OF COMMERCE 

National Institute for Standards and 

Technology 

Artificial Intelligence-Powered 

Autonomous Experimentation (AI/AE) 

for Sustainable Semiconductor 

Materials 

AGENCY: National Institute of Standards 

and Technology, Department of 

Commerce. 

ACTION: Notice of intent (NOI). 

SUMMARY: The CHIPS Research and 

Development Office (CHIPS R&D) 

intends to announce an open 

competition for industry-informed, 

university-based collaborations 

demonstrating artificial intelligencepowered autonomous experimentation 

(AI/AE) into sustainable materials and 

processes relevant to semiconductor 

manufacturing. CHIPS R&D expects a 

total Federal commitment of up to 

approximately $100 million over a 

period not to exceed five years as 

needed to support at least two large, 

team-oriented awards. 

FOR FURTHER INFORMATION CONTACT: 

Questions may be submitted via email 

to askchips@chips.gov with ‘‘2024– 

NIST–CHIPS–AI/AE–NOI’’ in the 

subject line or via phone to Jim Warren 

at (301) 975–5708. Responses to 

questions received, provided at the sole 

discretion of CHIPS R&D, will be posted 

on the CHIPS R&D website at https://

www.nist.gov/chips/chips-RD-fundingopportunities, with further information 

provided on this site once the open 

competition has been announced. 

SUPPLEMENTARY INFORMATION: 

Purpose. CHIPS R&D intends to 

announce, via a Notice of Funding 

Opportunity (NOFO), an open 

competition for industry-informed, 

university-based AI/AE collaborations 

relevant to sustainable semiconductor 

manufacturing. The NOFO would seek 

to support the long-term viability of 

domestic semiconductor manufacturing 

by accelerating the discovery, design, 

synthesis, and deployment of new 

materials and processes and the 

development of new researchers needed 

to meet the industry’s technological, 

economic, and sustainability goals. 

These goals may include but are not 

limited to improving leading-edge 

product performance; improving 

manufacturing yield, energy and water 

efficiency, and supply chain resiliency; 

and reducing manufacturing emissions 

and waste (including PFAS) through the 

development of materials and process 

alternatives, for the benefit of human 

health and safety. If successful, the 

competition should demonstrate that 

new sustainable semiconductor 

materials and processes, meeting 

industry needs, can be designed and 

adopted for industry testing within five 

years. The competition should further 

accelerate a step-change in the number 

of universities, researchers, and 

graduates participating in the U.S. 

semiconductor R&D ecosystem, 

including in CHIPS Act funded 

activities at the National Semiconductor 

Technology Center (NSTC) and CHIPS 

Manufacturing USA Institute. 

For general planning purposes, CHIPS 

R&D expects a total Federal 

commitment of up to approximately 

$100 million over a period not to exceed 

five years, as needed to support at least 

two large, team-oriented awards. CHIPS 

R&D expects eligible uses of Federal 

funds to include the procurement, 

upgrade, or maintenance of necessary 

research equipment at universities; 

accessing such equipment outside of 

academia or outside of the project team; 

basic and applied research and 

development (R&D); workforce 

development; and technology transition. 

CHIPS R&D further envisions that 

university research teams may leverage 

industry-provided expertise, intellectual 

property, facility access, or other forms 

of partner co-investment during the 

award period of performance. The 

anticipated program outcomes, if 

successful, should prove relevant and 

translatable to the NSTC, CHIPS 

Manufacturing USA Institute, and other 

CHIPS programs.. The purpose of this 

NOI is to facilitate the development of 

meaningful collaborations and 

responsive proposals by offering 

preliminary information to potential 

applicants. Consistent with the 

direction under Executive Order 14080 

(Implementation of the CHIPS Act of 

2022) for agencies to prioritize 

benefitting a broad range of stakeholders 

and to establish collaborative networks, 

CHIPS R&D expects to encourage 

proposals that significantly expand the 

capabilities of emerging research 

institutions (ERIs) in partnership with 

industry, other research universities, 

and national laboratories. 

This NOI is provided to allow 

potential applicants sufficient time to 

develop meaningful collaborations and 

responsive proposals. CHIPS R&D 

intends to announce the competition by 

posting the NOFO on Grants.gov 

(https://www.grants.gov) in the fourth 

quarter of calendar year 2024. CHIPS 

R&D will refine program structure, cost, 

and other program details in the 

upcoming NOFO. In the event of 

inconsistencies between the NOI and 

the NOFO, the NOFO shall govern and 

control. More information about the 

expected NOFO will be made available 

on the CHIPS for America website at 

https://www.nist.gov/chips/chips-rdfunding-opportunities. 

Background. Accelerated discovery, 

design and validation of new materials 

promises critical benefits to the future of 

the global semiconductor industry.1 2 In 

its 2023 Microelectronics and Advanced 

Packaging Technologies Roadmap 

(‘‘Roadmap’’), the Semiconductor 

Research Corporation indicated a 

demand for innovative semiconductor 

materials and chemistries. The 

Roadmap stated that ‘‘tools 

encompassing co-optimization of 

performance metrics and 

environmental, health, and safety 

metrics will help accelerate the 


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Federal Register / Vol. 89, No. 191 / Wednesday, October 2, 2024 / Notices 80211 

3Semiconductor Research Corporation, ‘‘MAPT 

Microelectronics and Advanced Packaging 

Technologies Roadmap’’, 2023. Available online at: 

https://srcmapt.org/wp-content/uploads/2024/03/ 

SRC-MAPT-Roadmap-2023-v4.pdf. 

4Perfluoroalkyl and polyfluoroalkyl substances. 

5Semiconductor PFAS Consortium, ‘‘Background 

on Semiconductor Manufacturing and PFAS’’, May 

17, 2023. Available online at: https://

www.semiconductors.org/wp-content/uploads/ 

2023/05/FINAL-PFAS-Consortium-BackgroundPaper.pdf. 

6 Id. 

discovery of more sustainable materials 

and chemicals without compromising 

the performance of the product.’’ 3 Other 

industry reports, including one from the 

Semiconductor PFAS 4 Consortium, 

recognize the need to identify and test 

substitute semiconductor manufacturing 

materials or to develop abatement 

technologies that prevent the release of 

certain chemicals into the 

environment.5

However, the deployment of new 

materials and processes can require 

years of research, development, testing, 

and validation.6 AI/AE has emerged as 

a potentially game-changing approach to 

accelerate materials R&D. AI/AE 

combines automated synthesis and 

characterization tools with an AI 

‘‘planner’’ to determine the next round 

of an experimental campaign, vastly 

accelerating the design of new materials 

and the acquisition of materials data. 

The AI planner can have multiple 

objectives, reflecting the materials 

designer’s goals. For materials 

development, AI/AE systems may 

include, for instance, (1) a combination 

of specialized and generalized 

automated laboratory devices for 

materials handling, (2) software for data 

analysis, and (3) machine learning tools 

(which may be informed by physicsbased models and shared databases) to 

predict material properties and help 

plan further experiments. Accessing this 

combination of capabilities will likely 

require multiple organizations, 

including universities, industry, and 

national laboratories, operating in 

partnership. If successful, these 

techniques can enable the cooptimization during materials discovery 

of multiple metrics important to nextgeneration microelectronics including 

microelectronics performance, 

manufacturing readiness, manufacturing 

economics, human health and safety, 

and environmental impact, including 

but not limited to PFAS mitigation and 

elimination, waste reduction and 

manufacturing water/energy efficiency. 

CHIPS R&D intends for the technical 

focus and R&D goals of the planned 

NOFO to emphasize the sustainability of 

the U.S. semiconductor industry and the 

demand for improved microelectronics 

power, performance, area, and cost 

metrics. By leveraging AI/AE and 

working in close partnerships with 

industry, CHIPS R&D intends to allow 

for the more rapid and cost-efficient 

discovery, design, validation, and 

deployment of sustainable materials and 

processes compared to traditional R&D 

approaches. 

CHIPS R&D Mission. The CHIPS and 

Science Act appropriated approximately 

$50 billion to the Department of 

Commerce, which includes $39 billion 

in incentives to onshore semiconductor 

manufacturing and $11 billion to 

advance U.S. leadership in 

semiconductor R&D. Within CHIPS for 

America, the mission of CHIPS R&D is 

to accelerate the development and 

commercial deployment of foundational 

semiconductor technologies by 

establishing, connecting, and providing 

access to domestic research efforts, 

tools, resources, workers, and facilities. 

NOFO Objectives. CHIPS R&D expects 

that the planned NOFO will solicit 

proposals seeking to achieve the 

following objectives: 

1. Through the application of AI/AE, 

accelerate research into and delivery of 

targeted, industry-relevant, sustainable 

semiconductor materials and processes; 

2. Propagate models for incorporating 

sustainability metrics into the 

semiconductor industry materials 

discovery, in addition to traditional 

power, performance, area, and cost 

metrics; 

3. Expand the capabilities of emerging 

research institutions through aggressive, 

innovative teams of universities, 

industry, government labs, and other 

stakeholders; and 

4. Build an exceptional workforce of 

university graduates and research 

faculty with AI/AE R&D expertise. 

Application Process and Award 

Information. The envisioned application 

process consists of a mandatory concept 

paper and a required full application. 

CHIPS R&D anticipates a due date for 

concept papers of approximately 60 

days after the date of NOFO publication. 

Full applications would only be 

accepted from applicants that are 

invited to apply after completion of the 

concept paper stage. Submissions 

received from entities other than those 

invited to submit a full application 

would not be reviewed or considered in 

any way. CHIPS R&D expects to fund at 

least two awards, subject to the 

availability of funds and the merit of 

applications received. 

CHIPS R&D expects to host one or 

more webinars to provide additional 

opportunities to learn about this NOI. 

Details regarding the time and date of 

webinar events will be posted on the 

CHIPS R&D website at https://

www.nist.gov/chips/chips-RD-fundingopportunities. Participation in webinars 

is not a prerequisite for submitting a 

concept paper or a full application. 

Competition Information. Once the 

open competition has been announced, 

further information may be found at 

https://www.nist.gov/chips/chips-RDfunding-opportunities. 

System for Award Management and 

Grants.gov. In anticipation of the NOFO, 

CHIPS R&D encourages potential 

applicants to complete the following 

steps, which are required to submit 

concept papers and full applications for 

Federal assistance: 

• Register with the System for Award 

Management (SAM) at https://

www.sam.gov. CHIPS R&D strongly 

encourages applicants to register for 

SAM.gov as early as possible. While this 

process ordinarily takes between three 

days and two weeks to complete, in 

some circumstances it can take six or 

more weeks to complete due to 

information verification requirements. 

Recipients will be required to maintain 

an active registration in SAM and revalidate registration annually. 

• Register for a Grants.gov (http://

www.grants.gov/) account. It is 

advisable also to go to ‘‘manage 

subscriptions’’ on Grants.gov and sign 

up to receive email notifications and 

updates on specific opportunities, 

including amendments to published 

opportunities. Information about how to 

manage subscriptions is available at 

https://grants.gov/connect/managesubscriptions/. 

Disclaimer. This NOI does not 

constitute a solicitation. An application 

may not be submitted in response to this 

NOI. Any inconsistency between 

information in this NOI and the planned 

NOFO announcing a CHIPS R&D award 

competition shall be resolved in favor of 

the NOFO. 

Authority. CHIPS R&D activities are 

authorized by Title XCIX—Creating 

Helpful Incentives to Produce 

Semiconductors for America of the 

William M. (Mac) Thornberry National 

Defense Authorization Act for Fiscal 

Year 2021 (Pub. L. 116–283), often 

referred to as the CHIPS Act. 

Alicia Chambers, 

NIST Executive Secretariat. 

[FR Doc. 2024–22664 Filed 10–1–24; 8:45 am] 

BILLING CODE 3510–13–P 


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