# Patent

## Title
Nanowires, nanowire networks and methods for their formation and use

## Abstract

Various embodiments provide non-planar nanowires, nanowire arrays, and nanowire networks as well as methods of their formation and applications. The non-planar nanowires and their arrays can be formed in a controlled manner on surfaces having a non-planar orientation. In embodiments, two or more adjacent nanowires from different surfaces can grow to merge together forming one or more nanowire branches and thus forming a nanowire network. In embodiments, the non-planar nanowires and nanowire networks can be used for cantilever oscillation, switching and transistor actions.

## Background
RELATED APPLICATIONS
This application is a continuation-in-part of U.S. patent application Ser. No. 13/677,203, filed Nov. 14, 2012, which is a divisional of U.S. patent application Ser. No. 12/635,151, filed Dec. 10, 2009, which claims priority from U.S. Provisional Patent Application Ser. No. 61/203,137, filed Dec. 19, 2008, all three of which applications are hereby incorporated by reference in their entirety.


GOVERNMENT RIGHTS
This invention was made with Government support under Contract No. F49620-03-1-0013 awarded by the Air Force Office of Scientific Research (AFOSR). The U.S. Government has certain rights in this invention.


DESCRIPTION OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductors and, more particularly, to semiconductor nanowires, nanowire arrays, and nanowire networks.
2. Background of the Invention
Nanowires formed of Group III-N alloys (e.g., GaN) provide the potential for new semiconductor device configurations such as nanoscale optoelectronic devices. For example, GaN nanowires can provide large bandgap, high melting point, and chemical stability that is useful for devices operating in corrosive or high-temperature environments.
Conventional nanowire fabrication is based on a vapor-liquid-solid (VLS) growth mechanism and involves the use of catalysts such as Au, Ni, Fe, or In. Problems arise, however, because these conventional catalytic processes can not control the position and uniformity of the resulting nanowires. A further problem with conventional catalytic processes is that the catalyst is inevitably incorporated into the nanowires. This degrades the crystalline quality of the nanowires, which limits their applications.
Thus, there is a need to overcome these and other problems of the prior art and to provide high-quality nanowires, nanowire arrays, and nanowire networks. It is further desirable to provide non-planar nanowires with precise and uniform control of the geometry, position and crystallinity of each nanowire.
SUMMARY OF THE INVENTION
According to various embodiments, the present teachings include a nanowire device. The nanowire device can include a semiconductor layer disposed on a dielectric layer. The semiconductor layer can include one or more openings with each opening having a plurality of semiconductor sidewalls and exposing a portion of the underlying dielectric layer. A selective growth mask can be disposed on at least two of the semiconductor sidewalls having a plurality of Group III-N nanowires selectively disposed on each of at least two semiconductor sidewalls through the selective growth mask. The Group III-N nanowires can be oriented along a single direction on the same semiconductor sidewall and each nanowire maintains a constant cross-sectional feature.
According to various embodiments, the present teachings also include a method of making nanowires. In this method, a semiconductor layer can be provided on a dielectric layer. The semiconductor layer can include one or more openings with each opening having a plurality of semiconductor sidewalls and exposing a portion of the underlying dielectric layer. A selective growth mask can then be formed on at least two of the semiconductor sidewalls. The selective growth mask can include one or more patterned apertures with each patterned aperture exposing a portion of the underlying semiconductor sidewall. On the portion of the semiconductor sidewall that is exposed in each patterned aperture, a semiconductor material can be grown to form a nanowire having a constant cross-sectional feature.
According to various embodiments, the present teachings further include a nanowire device. The nanowire device can include a silicon-on-insulator substrate having an etched silicon layer on an oxide insulator. The etched silicon layer can include one or more openings with each opening having a plurality of silicon sidewalls and exposing a portion of the oxide insulator. A selective growth mask can be disposed on at least two of the silicon sidewalls. Within the selective growth mask provided can be a plurality of selected surface regions on the underlying silicon sidewall. A Group III-N nanowire can be extended from each of the plurality of selected surface regions and can be oriented along a single direction on the same silicon sidewall while maintaining a cross-sectional feature of the corresponding selected surface region. Adjacent nanowires on different silicon sidewalls of the at least two semiconductor sidewalls can merge into one or more nanowire branches.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.



BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIGS. 1A-1D depict an exemplary nanowire device at various stages of its formation in accordance with various embodiments of the present teachings.
FIGS. 2A-2D depict exemplary nanowires in accordance with various embodiments.
FIGS. 3A-3B depict exemplary nanowire networks in accordance with various embodiments of the present teachings.
FIGS. 4A-4D illustrate details of a wafer structure with having apertures formed in a dielectric coating, according to an embodiment of the present disclosure.
FIGS. 5A-5B illustrate a wafer structure of FIG. 4A with nanowires grown using the apertures as a selective growth mask, according to an embodiment of the present disclosure.
FIGS. 6A to 6C illustrate a device formed using nanowires, according to an embodiment of the present disclosure.



DESCRIPTION OF THE EMBODIMENTS
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the invention. The following description is, therefore, merely exemplary.
Various embodiments provide non-planar nanowires, nanowire arrays, and nanowire networks as well as methods for their formation and applications. The non-planar nanowires and their arrays can be formed in a controlled manner on surfaces having a non-planar orientation. In embodiments, two or more adjacent nanowires from different surfaces can grow to merge together forming one or more nanowire branches and thus forming a nanowire network. For example, non-parallel nanowires can be made to connect forming a 3 or 4 terminal device. In embodiments, each nanowire can be formed with high-quality (i.e., essentially defect free) semiconductor material and with a precise control of the position, crystalline orientation, cross-sectional features, length and geometry.
FIGS. 1A-1D depict an exemplary method for forming non-planar nanowires in accordance with various embodiments of the present teachings.
In FIG. 1A, a substrate 110 can be provided. The substrate 110 can include a semiconductor layer 116 disposed on a dielectric layer 114, that is disposed on a substrate layer 112. In embodiments, the semiconductor layer 116 can include a material of, for example, Si, SiC, and III-V semiconductor compounds such as GaN or GaAs. The dielectric layer 114 can include any dielectric material, for example, SiO2 or SiNx as known to one of ordinary skill in the art.
As shown, the semiconductor layer 116 can include one or more openings 64. Each opening 64 within the semiconductor layer 116 can be defined by a plurality of semiconductor sidewalls 116s and a portion of the underlying dielectric layer 114. In embodiments, the openings 64 can include various cross-sectional shapes defined by the semiconductor sidewalls 116s. For example, the opening 64 can include a trench having a trapezoid cross-sectional shape. In embodiments, the semiconductor sidewalls 116s can provide a suitable crystal plane for Group III-N nanowires to grow thereon. For example, the semiconductor sidewalls 116s can include a low-index crystal plane that is produced by, for example, a wet chemical etching.
In an exemplary embodiment, the substrate 110 can include a SOI substrate. For example, the SOI substrate can include an etched silicon layer on an oxide insulator that is in turn on a silicon substrate.
The etched silicon layer can be etched from a thick silicon layer of an SOI wafer to form various silicon blocks separated by openings within the thick silicon layer. The thick silicon layer or the etched silicon layer can have a thickness of, for example, about 20.0 nm to about 50.0 nm. The silicon blocks of the etched silicon layer can have silicon sidewalls, for example, formed or etched along one or more of the crystal planes of silicon. For example, the silicon sidewalls can be formed by a wet chemical etching having a Si(111) facet, where the Si(111) is at angle of about 54.7° with respect to the (001) Si plane of the etched silicon layer.
In FIG. 1B, a selective growth mask 120 can be formed on at least two of the semiconductor sidewalls 116s of the nanowire device 100A of FIG. 1A. In some cases as shown, the selective growth mask 120 can also be formed on the entire surface of the semiconductor layer 116. In embodiments, the exposed underlying dielectric layer 114 may or may not be covered by the selective growth mask. In various embodiments, the selective growth mask 120 can be made of any dielectric material and formed using techniques known to one of ordinary skill in the art. In various embodiments, the selective growth mask 120 can include a conducting material made of, for example, metal tungsten.
In embodiments, the selective growth mask 120 can have a thickness of, for example, about 100 nm or less, including about 30 nm or less, although other thicknesses in the range of about 10 nm to about 1000 nm can also be used.
The selective growth mask 120s on the semiconductor sidewalls 116s can further include one or more patterned apertures 125. Each patterned apertures 125 can expose a portion of the underlying semiconductor sidewall 116s. In embodiments, the selective growth mask 120s can be formed by, for example, patterning and etching a dielectric layer overlaying the silicon sidewalls 116s to form the apertures 125.
In FIG. 1C, nanowires 130 can then be selectively formed on semiconductor sidewalls 116s through the patterned apertures 125 of the selective growth mask 120s. 
As used herein, the term “nanowire” refers to any elongated conductive or semiconductive material that includes at least one minor dimension, for example, one of the cross-sectional dimensions such as width or diameter, of less than or equal to about 1000 nm. In various embodiments, the minor dimension can be less than about 100 nm or less than about 10 nm, for example, about 1 nm to about 5 nm. In embodiments, the length of each nanowire can be, for example, about 10 nm to about 100 microns.
In embodiments, the nanowires can have an aspect ratio (e.g., length: width and/or major dimension: minor dimension) of about 5 or greater. In embodiments, the aspect ratio can be about 10 or greater, or about 100 or greater. In an exemplary embodiment, the cross-section of the nanowire can be highly asymmetric such that in one direction of the cross-sectional dimension can be much less than 1000 nm and in an orthogonal direction the dimension can be substantially greater than 1000 nm.
It is also intended that the term “nanowires” also encompass other elongated structures of like dimensions including, but not limited to, nanoshafts, nanopillars, nanoneedles, nanorods, and nanotubes (e.g., single wall nanotubes, or multiwall nanotubes), and their various functionalized and derivatized fibril forms, such as nanofibers in the form of thread, yarn, fabrics, etc.
In embodiments, the nanowires 130 can be made of, for example, Group III-V materials such as Group III-N semiconductor alloy compositions including, but not limited to, GaN, AlN, InN, InGaN, AlGaN, or AlInGaN.
In various embodiments, the nanowires can be formed by various crystal growth techniques including, but not limited to, metal-organic chemical vapor deposition (MOCVD) (also known as organometallic vapor phase epitaxy (OMVPE)), molecular-beam epitaxy (MBE), gas source MBE (GSMBE), metal-organic MBE (MOMBE), atomic layer epitaxy (ALE), or hydride vapor phase epitaxy (HVPE).
In embodiments, the nanowires 130 and their formation can include materials and methods as described in the related U.S. patent application Ser. No. 11/684,264, entitled “Pulsed Growth of GaN Nanowires and Applications in Group III Nitride Semiconductor Substrate Materials and Devices,” which is hereby incorporated by reference in its entirety.
In embodiments, the nanowires 130 can include high-quality Group III-N nanowires forming Group III-N nanowire arrays and networks, wherein the position, orientation, cross-sectional features, length and/or the crystallinity of each nanowire can be precisely controlled. In embodiments, the nanowires 130 can have various cross-sectional shapes, such as, for example, rectangular, polygonal, square, oval, or circular shape.
In embodiments, each nanowire 130 can be formed by growing a semiconductor material, for example, a Group III-V material, on a portion of the semiconductor sidewall 116s that is exposed in each patterned aperture 125 of the selective growth mask 120s. 
Specifically, a selective growth mode that is non-pulsed can be used to grow the semiconductor material on the exposed portion of the semiconductor sidewall 116s, followed by a growth-mode-transition from the selective growth mode to a pulsed growth mode. Semiconductor nanowire 130 can further be formed by continuing the pulsed growth mode of the semiconductor material to provide a length and a constant cross-sectional feature. That is, the cross-sectional features, for example, the cross-sectional dimensions (e.g., diameter or width) and the cross-sectional shapes, of each nanowire can be maintained by continuing the growth using the pulsed growth mode.
FIGS. 2A-2D depict various nanowires and arrays formed on the same sidewalls in accordance with various embodiments of the present teachings.
In embodiments as shown in FIG. 2A, nanowires 130 can be epitaxially grown, e.g., by MOCVD, through each patterned aperture 125 of the selective growth mask 120s and on the exposed surface of the underlying semiconductor sidewalls 116s. In this case, the nanowire diameter can be controlled substantially similar to the diameter of the corresponding aperture. During the formation, a growth-mode transition from the non-pulsed growth mode to the pulsed growth mode can occur before growth of the semiconductor material protrudes over a top of the selective growth mask 120s, where semiconductor material deposited within the patterned aperture can be used as a nanowire nucleus providing a selected surface region for further formation.
In embodiments as shown in FIG. 2B, a Group III-V, for example, a Group III-N buffer layer 222 such as a GaN layer can be formed between the semiconductor sidewalls 116s and the selective growth mask 120s. The nanowires 130 can be epitaxially grown on the Group III-N buffer layer 222 through the selective growth mask 120s. 
In embodiments of FIGS. 2C-2D, an increased duration can be used as compared to the methods and structures shown in FIGS. 2A-2B. As shown, nanostructure nuclei 240 can be formed within the patterned apertures 125 (see FIG. 1B) and protrude over the selective growth mask 120s and then spread laterally and vertically to form a truncated pyramid structure 242. The pyramid structure 242 can have sidewall facets of the {1 1 00} family and a top (0001) facet, which truncates the pyramid. As the pyramid structures 242 continue to grow, the diameter of this top (0001) facet can decrease and eventually this facet can disappear completely, for example, leaving a pyramid that is un-truncated.
In this case, the growth-mode transition from the non-pulsed growth mode to the pulsed growth mode can occur after growth of the semiconductor material protrudes over the top of the selective growth mask 120s to form the pyramid-shaped nanostructures 242, which can be truncated or un-truncated and can provide a selected surface region for further formation. Semiconductor nanowires can then be formed, e.g., on the top (0001) facet, by continuing the pulsed growth of the semiconductor material such that a cross-sectional feature of the semiconductor nanowire and a top facet of the pyramid-shaped nanostructures 242 are similar or substantially the same. Therefore, the dimensions and shapes of the exemplary III-N nanowires can be controlled.
In FIG. 2D, the nanowires 130 can be epitaxially grown on a Group III-N buffer layer 222 through the selective growth mask 120s. As similarly described in FIG. 2B, the Group III-N buffer layer 222 can be disposed between the semiconductor sidewall 116s and the selective growth mask 120s. 
Referring back to FIG. 1C, the nanowires 130 formed on the same sidewalls 116s can be highly oriented in a single direction. For example, a GaN nanowire can be oriented along (0001) crystallographic direction. In embodiments, the nanowires 130 formed on the same sidewalls 116s can be lack of tapering and tangling, because the nanowires can remain attached to the parent substrate 110. In various embodiments, nanowires 130 formed on the same semiconductor sidewalls 116s can be, for example, substantially parallel. In embodiments, the nanowires 130 formed on the same sidewalls 116s can include, for example, one or more linear, square or hexagonal arrays with each array having a pitch (i.e., center-to-center spacing between any two adjacent nanowires) ranging from about 50 nm to about 10 μm. Because the plurality of sidewalls 116s of the semiconductor layer 116 covered by the selective growth mask 120s are non-planar, nanowires 130 formed on different sidewalls can be non-planar and the growth of adjacent nanowires from different sidewalls can be grown merging together and further forming a nanowire branch as shown in FIGS. 3A-3B.
In FIG. 3A, the growth of a nanowire 130a formed on a first semiconductor sidewall 116s-a (see FIG. 1C) and the growth of a nanowire 130b on a second semiconductor sidewall 116s-b (see FIG. 1C) can be merged to create a third nanowire branch 130branch.
In embodiments, a number of non-planar nanowires can be grown merging together forming a nanowire branch. For example, in FIG. 3B, the growth of a nanowire 130a on a first semiconductor sidewall (not shown), the growth of a nanowire 130b on a second semiconductor sidewall (not shown), and the growth of a nanowire 130c on a third semiconductor sidewall (not shown) can be merged to create a fourth nanowire branch 130branch.
Additionally, nanowire branches 130branch can also continue to grow, to merge together and to form a secondary generation of nanowire branches. Nanowire networks that include one or more nanowire branches can be formed.
Referring back to FIG. 1D, the exemplary substrate 110 can allow, for example, row(s) of nanowires 130 on the same sidewall to be biased via a contact pad 140. The contact pads 140 can include a metal or metal alloy as known to one of ordinary skill in the art. As shown, when adjacent nanowire tips from different sidewalls reach close proximity, field emission and/or Fowler-Nordheim conduction can occur between the two separate groups of nanowire rows. When a voltage pulse is applied to the contact pads 140, nanowires can attract and bend. However, when the voltage pulse is removed, the nanowires can oscillate at a mechanical frequency. For example, the nanowires can be used in MEMS devices as cantilever beams having oscillation frequencies of more than about 1 GHz.
In embodiments, because each nanowire can provide nonpolar sidewalls, a core-shell growth can be performed to form, for example, non-planar core-shell nanowire structures. The core-shell growth on nanowires can include that similarly described in a related U.S. patent application Ser. No. 12/246,044, entitled “Nanowire and Larger GaN Based HEMTs,” which is hereby incorporated by reference in its entirety.
In embodiments, each nanowire of the devices in FIGS. 1-3 can have a thin-walled structure as disclosed in a related U.S. patent application Ser. No. 12/237,469, entitled “Thin-Walled Structures,” which is hereby incorporated by reference in its entirety.
In embodiments, the merged nanowire networks can be used for, for example, switching and transistor actions. In embodiments, the disclosed non-planar nanowires and nanowire networks can be used for various devices including, but not limited to light emitting devices (LEDs), lasers, high electron mobility transistors (HEMTs), MEMs devices or other suitable devices.
FIG. 4A shows the wafer structure before the GaN nanowires have been grown. The precision of fabrication and patterning of the wafer structure control the position, orientation, dimensions and cross-sectional shape of the subsequently grown GaN nanowires. The wafer structure is based on a commercially available {100} silicon-on-insulator (SOI) wafer. Semiconductor processing, including etching, dielectric deposition, ion-implantion and nanoscale patterning, which are well known to one practiced in the art, are used to fabricate the structure shown in FIG. 4A. For clarity, only a small portion of the full wafer structure is shown in FIG. 4A. This portion includes silicon ridges (450) distributed regularly on a pitch “r”. Each ridge has a mesa shaped cross section with sloping sidewalls. The dielectric coating (120s) on each of these sloping sidewalls is patterned with apertures (125) along the sidewall. It will be understood that a real sample can contain billions of such ridges and that the sloping sidewalls of each ridge can contain billions of apertures.
FIG. 4B details the structure of one ridge. Any suitable etch, such as a previously known potassium hydroxide etch procedure, is used to define the two inclined {111} crystallographic facets (116s, 116s). The angle between the two silicon {111} planes (116s, 116s), which form the ridge sidewalls, can be about 70°, such as 70.52°. Again using well-known semiconductor practices, an isolation ion-implantion (452) is performed to render the central portion of each silicon ridge semi-insulating. This isolation ion-implantation electrically isolates the two side portions of the silicon ridge (116A, 116B). Two metal contacts (140A, 140B) are fabricated so as to make contact with two side portions (116A, 116B). These metal contacts are patterned to run along the top surface the ridge and to extend out to probe pads (not shown) that are located at the side of the wafer structure.
The ridge and spaces between ridges are covered with a dielectric film (114, 120, 120s). This dielectric material can be, for example, silicon nitride, silicon dioxide or other dielectric material that is compatible with the subsequent nanowire growth. On the inclined sidewalls of the ridge (116s, 116s) the dielectric film (120s) is patterned with open apertures (125) that expose regions of the underlying silicon {111} sidewall facets. This patterning can be accomplished by any suitable methods, such as the established methods of interferometric lithography or nano-imprinting. The shape of the individual apertures on the sidewalls can be any desired shape, such as elliptical or striped.
FIG. 4C is a plan view of part of this wafer containing four ridges that have apertures on each sidewall. The aperture arrays on either side of the ridge are offset from each other by a distance “s”. This offset (145) defines the separation “s” of the nanowires at their crossing point. Other aperture schemes are possible depending on the crossbar functionality that is desired. FIG. 4D shows a plan view of part of this wafer containing four ridges that have striped apertures on each sidewall. Again an offset “s” (145) is employed to fix the separation of the nanowires at their crossing point.
FIG. 5A shows the wafer structure of FIG. 4A after a short length of GaN nanowire (130) has been grown. The nanowire length is sufficient to create two crossing points per nanowire. The nanowires can be grown to any desired length in order to create additional crossing points, such as three, four or more.
FIG. 5B shows the angular relationship between the crossing GaN nanowires (130). This angular relationship is precisely determined by the silicon {111} planes that form the sloping sidewalls (116s and 116s) of the ridges in the initial wafer structure. It has been previously demonstrated that GaN nanowires will grow epitaxially on silicon {111} planes (116s, 116s) such that the axial, or “c”, direction of the GaN nanowire aligns at 90° to the {111} silicon plane. See, for example, the paper entitled, “Nanoheteroepitaxial growth of GaN on Si by organometallic vapor phase epitaxy”, D. Zubia et al., Appl. Phys. Lett., 76, 858 (2000), the disclosure of which is hereby incorporated by reference in its entirety. This means that the crossing of the GaN nanowires can define two angles, φ1=about 109°, such as 109.48° and φ2=about 70°, such as 70.52°, as shown in FIG. 5B. As all of the GaN nanowires within the network originate from epitaxial growth on a {111} sidewall facet, and have one of the two {111} orientations that are available, the crossing angle of the nanowires will be precise and will remain constant whether the array contains two, or trillions of, nanowires. Thus this method provides the precise control of orientation that is necessary for scaling-up to massive nanowire networks.
The position of the GaN nanowires is also precisely defined as the nanowires only grow on the sidewall facet where there is an available aperture. The positioning of these apertures is defined by proven nano-patterning techniques such as interferometric lithography or nanoimprint patterning. Furthermore, the cross-sectional size and shape of the nanowire are defined by the size and shape of the aperture, both of which can be precisely controlled using modern nanopatterning methods. Finally, the length of the nanowire is determined by the duration of the growth process.
This invention thus provides a method with the extreme precision that is required to build a massive network of nanowire crossbars. The potential integration density of such a network can be readily estimated with reference to FIG. 5B:
In an example based on previous experiments, we assume a GaN nanowire length “L”=10−2 cm. We assume achievable dimensions for a ridge pitch, “r”=5×10−5 cm, an aperture pitch, “p”=3×10−5 cm, and a nanowire length of 10−2 cm. The crossing point period, “cp”, is given by:




  cp
  =
  
    
      r
      
        2
        ⁢
        
          
        
        ⁢
        
          cos
          ⁡
          
            (
            35.26
            )
          
        
      
    
    =
    
      
        3.062
        ⨯
        
          10
          
            -
            5
          
        
      
      ⁢
      
        
      
      ⁢
      cm
    
  




In this example, every nanowire will experience L/cp crossing points, =327. A 1 cm2 area, using the above values of “r” and “p”, will have 1.2×109 nanowires. The total number of crossing points per cm2 area will be 327×1.2×109=4×1011. This nanowire network will achieve a crossbar density of 4×1011 cm−2. At 4×1011 cm−2 this crossbar density exceeds the current ITRS integration density targets by 50× for SRAM memory and by 250× for logic circuits. Further reduction of the pitches “r” and/or “p”, and/or increasing of the nanowire length “L” can further increase this crossbar density to above 4×1011 cm−2.
As discussed in greater detail below, some or all of the crossbars within the nanowire network can be addressable and can exhibit some type of transistor functionality. For example, all crossing points within this network can be individually addressed using the four contact approach shown in FIG. 6A. After partially or completely filling the nanowire region with a dielectric (350), the contacts (660, 662) are deposited on top of the structure such that they make an electrical connection with the upper tips of the nanowires. For clarity only, a small array section is shown and the nanowire length L has been limited to  ̃5 cp in this figure. FIG. 6B is a plan view of the wafer structure and shows the relative orientations of the upper contacts (660, 662) with respect to the lower contacts (140A, 140B). The upper contacts (660, 662) are aligned to be perpendicular to the lower contacts (140A, 140B), and to the underlying ridges of semiconductor layer (116). This contact arrangement allows every crossing point to be individually addressed.
To promote robustness of these top contacts the space surrounding the nanowire network can be partially or completely filled by a dielectric. This can be accomplished using by any suitable method, such as by using a spin-on dielectric that is first applied as a liquid and is then cured to form a solid. Such approaches for dielectric deposition are well known to those practiced in the art of semiconductor materials.
Providing transistor functionality at each crossing point within the crossbar can be accomplished by various methods. One such method is to employ the transistor action demonstrated by Reukes. See, for example, the article entitled “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing”, T. Reukes et al., Science 289, 94 (2000), the disclosure of which is hereby incorporated by reference in its entirety. In this method, the biasing of one CNT (carbon nanotube) within a crossbar changed the resistance in the second CNT of the crossbar. This change of resistance was caused by an electrostatically-induced mechanical deformation of the CNT at the crossing point, which induced a piezoresistive change of resistance. The elastic modulus of GaN at nanowire scale is around 250 GPa compared to 1 TPa for carbon nanotubes. This means that a 4× larger deformation will be obtained in GaN than in a CNT for an applied stress. The gauge factor, which is a measure of the piezoresistivity, is less well known but based on available literature appears to be approximately 10× higher for CNTs than for GaN. This indicates that the resistance change exhibited by GaN nanowires will be less than that for CNTs under a similar mechanical deformation. For similar stresses and similar nanowire separations, it is estimated that the resistance change exhibited by GaN nanowires in this crossbar arrangement will be approximately half the resistance change exhibited by CNTs. This remains a useful level of functionality.
Furthermore, the ability of this invention to control the cross-sectional shape of the GaN nanowire should facilitate an improved interaction between nanowires at the crossing point. For example, as discussed in U.S. Pat. No. 7,521,274, a circular aperture can result in a hexagonal GaN nanowire cross-section. More recent experiments show that an elliptical aperture or letterbox aperture can promote a stretched hexagon cross-section. If a thin stripe aperture is used, as illustrated in FIG. 4D, then the cross-section can be made highly elongated to produce a nano-thickness GaN wall. A method for fabricating thin-walled nanoscale objects was taught in our previous U.S. Pat. No. 7,968,359. The disclosures of both U.S. Pat. No. 7,521,274, and U.S. Pat. No. 7,968,359 are incorporated herein by reference in their entirety.
It is likely that the electrostatic interaction described above in Reukes, and the resulting mechanical deformation at the nanowire crossing point, will be enhanced if the overlap area between the nanowires is increased. The Reukes type of transistor functionality as described above is only one possible functionality that can occur at the network crossing points.
While the invention has been illustrated with respect to one or more implementations, alterations and/or modifications can be made to the illustrated examples without departing from the spirit and scope of the appended claims. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular function. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.” As used herein, the term “one or more of” with respect to a listing of items such as, for example, A and B, means A alone, B alone, or A and B. The term “at least one of” is used to mean one or more of the listed items can be selected.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein are to be understood to encompass any and all sub-ranges subsumed therein. For example, a range of “less than 10” can include any and all sub-ranges between (and including) the minimum value of zero and the maximum value of 10, that is, any and all sub-ranges having a minimum value of equal to or greater than zero and a maximum value of equal to or less than 10, e.g., 1 to 5. In certain cases, the numerical values as stated for the parameter can take on negative values. In this case, the example value of range stated as “less than 10” can assume values as defined earlier plus negative values, e.g. −1, −1.2, −1.89, −2, −2.5, −3, −10, −20, −30, etc.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

## Claims

1. A nanowire device comprising:
a semiconductor layer disposed on a dielectric layer, wherein the semiconductor layer comprises a plurality of semiconductor ridges separated by one or more openings, with each opening having a first semiconductor sidewall and a second semiconductor sidewall, an isolation region dividing each of the plurality of semiconductor ridges into two side portions;
a selective growth mask disposed on both the first semiconductor sidewall and the second semiconductor sidewall of each opening, the selective growth mask including one or more patterned apertures; and
a plurality of Group III-N nanowires selectively disposed on each of the first and second semiconductor sidewalls through the one or more patterned apertures in the selective growth mask; wherein the Group III-N nanowires on the first sidewall are oriented along a first direction, and wherein the Group III-N nanowires on the second sidewall are oriented along a second direction so as to cross the nanowires on the first sidewall.

2. The device of claim 1, wherein adjacent crossing nanowires are separated at a closest crossing point by an offset distance.

3. The device of claim 2, wherein the first sidewall has a first surface plane and the second sidewall has a second surface plane, an axial direction of the nanowires on the first sidewall being at a first angle with respect to the first surface plane, and an axial direction of the nanowires on the second sidewall being at a second angle with respect to the second surface plane, the first angle being substantially equal to the second angle.

4. The device of claim 2, wherein the one or more openings include at least a first opening and a second opening, wherein nanowires on the first sidewall of the first opening are sufficiently long to cross both a nanowire on the second sidewall of the first opening and a nanowire on the second sidewall of the second opening.

5. The device of claim 4, wherein nanowires on the second sidewall of the second opening are sufficiently long to cross both a nanowire on the first sidewall of the first opening and a nanowire on the first sidewall of the second opening.

6. The device of claim 5, wherein the crossing of the nanowires defines an upper angle and a side angle, the upper angle being approximately 109° and the side angle being approximately 70°.

7. The device of claim 5, wherein the nanowires each comprise an end that is distal from a sidewall on which the nanowires are formed, a contact layer being positioned on the distal end of each nanowire.

8. The device of claim 5, further comprising a second dielectric that at least partially fills a space between the nanowires, the contact layer being formed on the second dielectric layer.

9. A method of making a nanowire device, the method comprising:
providing a semiconductor layer disposed on a dielectric layer, wherein the semiconductor layer comprises a plurality of semiconductor ridges separated by one or more openings, with each opening having a first semiconductor sidewall and a second semiconductor sidewall;
forming an isolation region dividing each of the plurality of semiconductor ridges into two side portions;
forming a selective growth mask on both the first semiconductor sidewall and the second semiconductor sidewall of each opening, the selective growth mask including one or more patterned apertures; and
selectively growing a plurality of Group III-N nanowires on each of the first and second semiconductor sidewalls through the one or more patterned apertures in the selective growth mask; wherein the Group III-N nanowires on the first sidewall are oriented along a first direction, and wherein the Group III-N nanowires on the second sidewall are oriented along a second direction so as to cross the nanowires on the first sidewall.

10. The method of claim 9, wherein the selective growth mask is configured so that adjacent crossing nanowires are separated at a closest crossing point by an offset distance.

11. The method of claim 10, wherein the one or more openings include at least a first opening and a second opening, the method further comprising growing the nanowires for a sufficient length of time so that the nanowires on the first sidewall of the first opening are sufficiently long to cross both a nanowire on the second sidewall of the first opening and a nanowire on the second sidewall of the second opening.

12. The method of claim 11, wherein nanowires on the second sidewall of the second opening are sufficiently long to cross both a nanowire on the first sidewall of the first opening and a nanowire on the first sidewall of the second opening.

13. The method of claim 12, wherein the nanowires each comprise an end that is distal from a sidewall on which the nanowires are formed, the method further comprising forming a contact layer on the distal end of each nanowire.

14. The method of claim 13, further comprising forming a second dielectric to at least partially fill a space between the nanowires, the contact layer being formed on the second dielectric layer.