# Patent

## Title
System and method for responding to failure of a hardware locus at a communication installation

## Abstract

A method for responding to a failure of hardware locus of at a communication installation having a plurality of control apparatuses for controlling a plurality of processes distributed among a plurality of hardware loci, the hardware loci including at least one spare hardware locus, includes the steps of: (a) Shifting control of a failed process from an initial control apparatus to an alternate control apparatus located at an alternate hardware locus than the failed hardware locus. The failed process is a respective process controlled by the initial control apparatus located at the failed hardware locus. (b) Relocating the respective control apparatuses located at the failed hardware locus to a spare hardware locus. (c) Shifting control of the failed process from the alternate control apparatus to the initial control apparatus relocated at the spare hardware locus.

## Background
RELATED APPLICATIONS
This application is a continuation of co-pending U.S. patent application Ser. No. 11/523,195, entitled “SYSTEM AND METHOD FOR RESPONDING TO FAILURE OF A HARDWARE LOCUS AT A COMMUNICATION INSTALLATION,” which was filed on Sep. 18, 2006, and is hereby incorporated herein by reference in its entirety.


FIELD OF THE INVENTION
The present invention relates to controlling operation of a communication installation in a communication system, and in particular to controlling operation of a communication installation in response to a failure of a hardware unit at the communication installation.
BACKGROUND OF THE INVENTION
Today's communication systems are operated at a high level of reliability. One way such reliability is achieved is by operating equipment at a communication installation using a one-to-one redundancy arrangement by which a hot standby equipment unit-mate is kept ready to assume the role of a primary equipment unit in the event of failure of the primary equipment unit. Failure of a first hardware locus at which is located a primary equipment unit may therefore be substantially instantaneously remedied by employing the assigned standby equipment unit-mate—preferably located at a different hardware locus than the first hardware locus.
Equipping for such a one-to-one back-up capability requires equipping with redundant hardware. Equipping with redundant hardware can be an expensive endeavor, especially since the processing power of the standby equipment unit-mate can be required to nothing more than data-synchronize with the primary equipment unit, which in many situations assures that the standby equipment unit-mate is under-utilized.
There is a need for a system and method for responding to a failure of a hardware locus at a communication installation that avoids providing redundant hardware for one-to-one equipment redundancy.
SUMMARY OF THE INVENTION
A method for responding to a failure of hardware locus at a communication installation having a plurality of control apparatuses for controlling a plurality of processes distributed among a plurality of hardware loci, the hardware loci including at least one spare hardware locus, includes the steps of: (a) Shifting control of a failed process from an initial control apparatus to an alternate control apparatus located at an alternate hardware locus than the failed hardware locus. The failed process is a respective process controlled by the initial control apparatus located at the failed hardware locus. (b) Relocating the respective control apparatuses located at the failed hardware locus to a spare hardware locus. (c) Shifting control of the failed process from the alternate control apparatus to the initial control apparatus relocated at the spare hardware locus.
A system for effecting continuity of operation in response to failure of a failed hardware locus of a plurality of hardware loci is used at a communication installation that includes a plurality of control apparatuses for controlling a plurality of processes distributed among the plurality of hardware loci. Each respective process of the plurality of processes is controlled by one of a respective first control apparatus of the plurality of control apparatuses or a respective second control apparatus of the plurality of control apparatuses. The respective first control apparatus and the respective second control apparatus associated with a particular the respective process are located at different hardware loci of the plurality of hardware loci. The plurality of hardware loci includes at least one spare hardware locus. No respective first control apparatus and no respective second control apparatus are initially located at any respective spare hardware locus. The system includes: a control unit coupled with the plurality of control apparatuses for effecting a shifting of control of a failed process to an alternate control apparatus located at an alternate hardware locus than the failed hardware locus. The failed process is a respective process controlled by one control apparatus of the first control apparatus and the second control apparatus located at the failed hardware locus. The alternate control apparatus is the other control apparatus of the first control apparatus and the second control apparatus. The alternate hardware locus is the respective hardware locus at which is located the other control apparatus. The control unit effects relocation of the respective control apparatuses located at the failed hardware locus to a respective spare hardware locus. The control unit effects a shifting of control of the failed process from the other control apparatus to the one control apparatus relocated at the respective spare hardware locus.
It is therefore a feature of the present invention to provide a system and method for responding to a failure of a hardware locus at a communication installation that avoids providing redundant hardware for one-to-one equipment redundancy.
Those skilled in the art will appreciate the scope of the present invention and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.



BRIEF DESCRIPTION OF THE DRAWING FIGURES
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the invention, and together with the description serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of a prior art arrangement of control apparatuses among a plurality of hardware loci at a communication installation.
FIG. 2 is a schematic diagram of a preferred arrangement of control apparatuses among a plurality of hardware loci at a communication installation established according to the teachings of the present invention.
FIG. 3 is a schematic diagram indicating a failed hardware locus among hardware loci in the arrangement of control apparatuses illustrated in FIG. 2.
FIG. 4 is a schematic diagram indicating a shifting control of a process to a second control apparatus in response to the failed hardware locus illustrated in FIG. 3.
FIG. 5 is a schematic diagram indicating shifting location of control apparatuses away from the failed hardware locus illustrated in FIG. 3.
FIG. 6 is a schematic diagram indicating a shifting control of a process back to the control apparatus originally controlling the process before the failure of a hardware locus illustrated in FIG. 3.
FIG. 7 is a flow chart illustrating the method of the present invention.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
FIG. 1 is a schematic diagram of a prior art arrangement of control apparatuses among a plurality of hardware loci at a communication installation. In FIG. 1, a communication installation 10 includes an arbitrator unit 12 coupled with a plurality of hardware loci 141, 142, 14m, 14s. Hardware locus 14s is a spare hardware locus. The indicator “m” is employed to signify that there can be any number of hardware loci in communication installation 10. The inclusion of three hardware loci 141, 142, 14m and spare hardware locus 14s in FIG. 1 is illustrative only and does not constitute any limitation regarding the number of hardware loci or the number of spare hardware loci that may be included in the communication installation of the present invention.
Each respective hardware locus 14m includes control apparatuses for controlling processes at communication installation 10. The various control apparatuses are controlled by arbitrator unit 12. One may observe that a first control apparatus and a second control apparatus controlling a particular process are co-located at each respective hardware locus 14m. More than two control apparatuses may be located at a respective hardware locus 14m. However, prior art configurations provided for first and second control apparatuses for a particular process to be co-located at a respective hardware locus 14m.
Thus, hardware locus 141 includes control apparatuses GWC-1/Unit-0, GWC-1/Unit-1 (referred to here by way of example and not by way of limitation, as Gate Way Controller (GWC)). Control apparatus GWC-1/Unit-0 is active—controlling Process-1. Control apparatus GWC-1/Unit-1 is inactive standing by for backing up control apparatus GWC-1/Unit-0 should control apparatus GWC-1/Unit-0 fail.
Hardware locus 142 includes control apparatuses GWC-2/Unit-0, GWC-2/Unit-1. Control apparatus GWC-2/Unit-0 is active—controlling Process-2. Control apparatus GWC-2/Unit-1 is inactive standing by for backing up control apparatus GWC-2/Unit-0 should control apparatus GWC-2/Unit-0 fail.
Hardware locus 14m includes control apparatuses GWC-n/Unit-0, GWC-n/Unit-1. The indicator “n” is employed to signify that there can be any number of Gate Way Controllers (GWCs) in communication installation 10. The inclusion of three Gate Way Controllers GWC-1, GWC-2, GWC-n in FIG. 1 is illustrative only and does not constitute any limitation regarding the number of GWCs that may be included in the communication installation of the present invention. Control apparatus GWC-n/Unit-0 is active—controlling Process-n. Control apparatus GWC-n/Unit-1 is inactive standing by for backing up control apparatus GWC-n/Unit-0 should control apparatus GWC-n/Unit-0 fail.
Hardware locus 14s is a spare hardware locus having capacity for receiving or hosting two (or more) control apparatuses of the sort located at hardware loci 141, 142, 14m.
Because of the prior art arrangement co-locating the primary and secondary control apparatuses controlling a particular process, as indicated in FIG. 1, when a hardware locus 14m failed, both of the control apparatuses for the particular affected process had to be moved to a spare hardware locus 14s. When a hardware locus 14m failed, the control units located at the failed hardware locus were moved to a spare hardware locus 14s and remained at the spare hardware locus 14s until the failed hardware locus was repaired. Accordingly, for reliability of operation it was necessary in such prior art configurations to provide one-to-one redundancy of spare hardware loci 14s for each occupied hardware locus 141, 142, 14m (only one representative spare hardware locus 14s is illustrated in FIG. 1).
FIG. 2 is a schematic diagram of a preferred arrangement of control apparatuses among a plurality of hardware loci at a communication installation established according to the teachings of the present invention. In FIG. 2, a communication installation 20 includes an arbitrator unit 22 coupled with a plurality of hardware loci 241, 242, 24m, 24s. Hardware locus 24s is a spare hardware locus. The indicator “m” is employed to signify that there can be any number of hardware loci in communication installation 20. The inclusion of three hardware loci 241, 242, 24m and spare hardware locus 24s in FIG. 2 is illustrative only and does not constitute any limitation regarding the number of hardware loci or the number of spare hardware loci that may be included in the communication installation of the present invention.
Each respective hardware locus 24m includes control apparatuses for controlling processes at communication installation 20. The various control apparatuses are controlled by arbitrator unit 22. One may observe that the present invention provides that a first control apparatus and a second control apparatus controlling a particular process are not co-located at each respective hardware locus 24m. More than two control apparatuses may be located at a respective hardware locus 24m. However, the present invention provides that first and second control apparatuses for a particular process are not to be co-located at a respective hardware locus 24m.
Further, the present invention also preferably locates control apparatuses so that both of the control apparatuses located at a respective hardware locus 24m are not active in controlling operation of a process.
Thus, hardware locus 241 includes control apparatuses GWC-1/Unit-0, GWC-2/Unit-0. Control apparatus GWC-1/Unit-0 is active—controlling Process-1. Control apparatus GWC-2/Unit-0 is inactive standing by for backing up control apparatus GWC-2/Unit-1 located at hardware locus 242 should control apparatus GWC-2/Unit-1 fail.
Hardware locus 242 includes control apparatuses GWC-2/Unit-1, GWC-n/Unit-0. The indicator “n” is employed to signify that there can be any number of Gate Way Controllers (GWCs) in communication installation 20. The inclusion of three Gate Way Controllers GWC-1, GWC-2, GWC-n in FIG. 2 is illustrative only and does not constitute any limitation regarding the number of GWCs that may be included in the communication installation of the present invention. Control apparatus GWC-2/Unit-1 is active—controlling Process-2. Control apparatus GWC-n/Unit-0 is inactive standing by for backing up control apparatus GWC-n/Unit-1 located at hardware locus 24m should control apparatus GWC-n/Unit-1 fail.
Hardware locus 24m includes control apparatuses GWC-n/Unit-1, GWC-1/Unit-1. Control apparatus GWC-n/Unit-1 is active—controlling Process-n. Control apparatus GWC-1/Unit-1 is inactive standing by for backing up control apparatus GWC-1/Unit-0 located at hardware locus 241 should control apparatus GWC-1/Unit-0 fail.
Hardware locus 24s is a spare hardware locus having capacity for receiving or hosting two (or more) control apparatuses of the sort located at hardware loci 241, 242, 24m.
FIG. 3 is a schematic diagram indicating a failed hardware locus among hardware loci in the arrangement of control apparatuses illustrated in FIG. 2. FIG. 4 is a schematic diagram indicating a shifting control of a process to a second control apparatus in response to the failed hardware locus illustrated in FIG. 3. Regarding FIGS. 3 and 4 together, communication installation 20 is configured substantially similar to the configuration of communication installation 20 described in connection with FIG. 2. In order to avoid prolixity, only pertinent portions of communication installation 20 will be described sufficient to illustrate the operation of the present invention.
In FIG. 3, hardware locus 24m has failed, as indicated by the “X” notation superimposed upon hardware locus 24m. Failure of hardware locus 24m is noted by arbitrator unit 22. Failure of hardware locus 24m does not have an immediate effect relating to Process-1 because control apparatus GWC-1/Unit-1 located at hardware locus 24m is inactive. However, failure of hardware locus 24m has an effect on Process-n because control apparatus GWC-n/Unit-1 located at hardware locus 24m is active and is effecting control of Process-n. Arbitrator unit 22 is programmed or otherwise instructed to respond to failure of hardware unit 24m by first shifting control of active control unit GWC-n/Unit-1 to a backup control apparatus for Process-n: GWC-n/Unit-0, located at hardware locus 242, as indicated in FIG. 4.
As indicated in FIG. 4, arbitrator unit 22 has responded to failure of hardware unit 24m to assure continuity of operation of Process-n. Process-n is now (FIG. 4) controlled by control apparatus GWC-n/Unit-0, located at hardware locus 242. However, Process-1 and Process-n (in the situation indicated in FIG. 4) have no backup control apparatuses because control apparatuses GWC-n/Unit-1 and GWC-1/Unit-1 are located at a failed hardware locus 24m.
FIG. 5 is a schematic diagram indicating shifting location of control apparatuses away from the failed hardware locus illustrated in FIG. 3. Regarding FIG. 5, communication installation 20 is configured substantially similar to the configuration of communication installation 20 described in connection with FIGS. 2-4. In order to avoid prolixity, only pertinent portions of communication installation 20 will be described sufficient to illustrate the operation of the present invention. In FIG. 5, after arbitrator unit 22 has shifted control of Process-n to control apparatus GWC-n/Unit-0 located at hardware locus 242 (FIG. 4), control apparatuses GWC-n/Unit-1 and GWC-1/Unit-1 are relocated to spare hardware locus 24s. This action permits continuity of operational availability of control apparatuses GWC-n/Unit-1 and GWC-1/Unit-1 so that Process-1 and Process-n have backup control apparatuses available, now located at spare hardware locus 24g. Relocating control apparatuses GWC-n/Unit-1 and GWC-1/Unit-1 to spare hardware locus 24s also makes failed hardware locus 24m (labeled “OOS”; Out Of Service) available for repair.
However, because control of Process-n has been shifted to control apparatus GWC-n/Unit-0 at hardware locus 242, there are now two active control apparatuses located at hardware locus 242: GWC-2/Unit-1 and GWC-n/Unit-0. This condition—having two active control apparatuses located at a respective hardware locus—is not desired.
FIG. 6 is a schematic diagram indicating a shifting control of a process back to the control apparatus originally controlling the process before the failure of a hardware locus illustrated in FIG. 3. Regarding FIG. 6, communication installation 20 is configured substantially similar to the configuration of communication installation 20 described in connection with FIGS. 2-5. In order to avoid prolixity, only pertinent portions of communication installation 20 will be described sufficient to illustrate the operation of the present invention. In FIG. 6, arbitrator unit 22 takes action to remedy having two active control apparatuses located at hardware locus 242 by shifting control of Process-n back to control apparatus GWC-n/Unit-1, now located at spare hardware locus 24s.
Because the present invention does not co-locate the primary and secondary control apparatuses controlling a particular process and because only one of two control apparatuses at a respective hardware locus is active, as indicated in FIGS. 2-6, when a hardware locus 24m fails, control for a process affected by failure of the respective hardware locus 24m need only be moved to another hardware location (by arbitrator unit 22). This is so because the present invention assures that an inactive control apparatus for a respective process is not co-located with an active control apparatus for the respective process, as was the situation in prior art communication installation 10 (FIG. 1). By this new arrangement, failure of a respective hardware locus 24m will not result in loss of both active and inactive control apparatuses for the respective process. One result of this arrangement is that there is no longer a necessity for one-to-one redundancy between spare hardware loci 24s and active hardware loci 24m. To be sure, redundancy is necessary to assure reasonable reliability of operation by communication installation 20. However, one skilled in the design of communication installations will recognize that a less than one-to-one redundancy will provide sufficient reliability of operation, especially in a communication installation 20 having a large number of hardware loci 24m. This is so because a failure of a hardware locus 24m does not assure loss of all control capability for a respective process, as is the case in prior art communication installation 10 (FIG. 1) in which both active and inactive control apparatuses for a respective process are co-located at a respective hardware locus 14m. In contrast, the present invention assures that failure of a hardware locus 24m merely necessitates migration or reassignment of control of a process to another hardware locus at which a second control apparatus for the respective process is located.
Further, by assuring that both control apparatuses located at a respective hardware locus are not active, only one process is affected by failure of a hardware locus. One skilled in the art of communication installation design may recognize that the example here assigning only two control apparatuses to a respective hardware locus is representative only and that the teachings of the present invention may readily be applied to a communication installation having greater than two control apparatuses located at a respective hardware locus 24m.
FIG. 7 is a flow chart illustrating the method of the present invention. In FIG. 7, a method 100 for responding to a failure of a failed hardware locus of a plurality of hardware loci at a communication installation begins at a START locus 102. The installation includes a plurality of control apparatuses distributed among the plurality of hardware loci for controlling a plurality of processes. Each respective process of the plurality of processes is controlled by one of a respective first control apparatus of the plurality of control apparatuses or a respective second control apparatus of the plurality of control apparatuses. The respective first control apparatus and the respective second control apparatus associated with a particular respective process are located at different hardware loci of the plurality of hardware loci. The plurality of hardware loci includes at least one spare hardware locus. No respective first control apparatus and no respective second control apparatus are initially located at any respective spare hardware locus.
Method 100 continues with the step of shifting control of a failed process from an initial control apparatus to an alternate control apparatus located at an alternate hardware locus than the failed hardware locus, as indicated by a block 104. The failed process is a respective process controlled by one control apparatus of the first control apparatus and the second control apparatus located at the failed hardware locus. The alternate control apparatus is the other control apparatus of the first control apparatus and the second control apparatus. The alternate hardware locus is the respective hardware locus at which is located the other control apparatus.
Method 100 continues with the step of relocating the respective control apparatuses located at the failed hardware locus to a respective spare hardware locus of the plurality of hardware loci, as indicated by a block 106.
Method 100 continues with the step of shifting control of the failed process from the other control apparatus to the one control apparatus now located at the respective spare hardware locus, as indicated by a block 108. Method 100 terminates at an END block 110.
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present invention. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

## Claims

1. A hardware arrangement for running a plurality of processes, the hardware arrangement comprising:
a plurality of primary processors, each primary processor being operable to run a respective one of the plurality of processes and being located at a respective hardware location of a plurality of hardware locations; and
a plurality of secondary processors, each secondary processor being associated with at least one primary processor of the plurality of primary processors and being operable to run at least the respective one of the plurality of processes which the at least one associated primary processor is operable to run should the at least one associated primary processor fail, each secondary processor being located at a respective hardware location of the plurality of hardware locations such that no primary processor is located at a same hardware location as its associated secondary processor, wherein each secondary processor is located at a respective hardware location of the plurality of hardware locations of at least one primary processor, the at least one primary processor not being associated with the secondary processor at the same hardware location.

2. The hardware arrangement of claim 1, wherein a respective primary processor and a respective secondary processor are located at each hardware location of the plurality of hardware locations, the primary processor at each hardware location being associated with a secondary processor at a different hardware location.

3. The hardware arrangement of claim 2, wherein a failure at any respective hardware location that results in a failure of either a respective primary processor at the respective hardware location or a respective secondary processor at the respective hardware location results in a failure of both the respective primary processor and the respective secondary processor at the respective hardware location.

4. The hardware arrangement of claim 1, further comprising at least one arbitrator operable to move control of a process running on a primary processor to its associated secondary processor upon failure of the primary processor.

5. The hardware arrangement of claim 4, wherein the at least one arbitrator is operable to move control of a process running on a secondary processor back to an associated primary processor on restoration of the associated primary processor.

6. The hardware arrangement of claim 1, further comprising a plurality of spare processors located at a hardware location different from the plurality of hardware locations of the primary and secondary processors.

7. The hardware arrangement of claim 6, wherein a pair of spare processors is provided for N primary processors, N being an integer greater than 1.

8. The hardware arrangement of claim 1, further comprising:
a plurality of spare processors located at a spare hardware location of the plurality of hardware locations different from the respective hardware locations of the primary and secondary processors; and
at least one arbitrator operable to move control of a process running on a primary processor to its associated secondary processor on failure of the primary processor, the at least one arbitrator being further operable to move control of a process running on a secondary processor to one of the plurality of spare processors.

9. The hardware arrangement of claim 8, wherein the at least one arbitrator is further operable to move control of a process running on a spare processor back to an associated primary processor upon restoration of the associated primary processor.

10. The hardware arrangement of claim 8, wherein a pair of spare processors is provided for N primary processors, N being the integer greater than 1.

11. A method for running a plurality of processes, the method comprising:
configuring a plurality of primary processors at respective hardware locations;
configuring a plurality of secondary processors, each secondary processor being associated with at least one primary processor of the plurality of primary processors and being located at a respective hardware location of a plurality of hardware locations such that no primary processor is located at a same hardware location as its associated secondary processor, wherein each secondary processor is located at a respective hardware location of the plurality of hardware locations of at least one primary processor, the at least one primary processor not being associated with the secondary processor at the same hardware location;
running a respective one of the plurality of processes on each primary processor; and
upon failure of one of the plurality of processes, transferring control of the failed process from the primary processor running the process to the secondary processor associated with the primary processor.

12. The method of claim 11, wherein a respective primary processor and a respective secondary processor are located at each hardware location of the plurality of hardware locations, the primary processor at each hardware location of the plurality of hardware locations being associated with a secondary processor at a different hardware location.

13. The method of claim 11, further comprising operating at least one arbitrator to move control of a process running on a primary processor to its associated secondary processor upon failure of the primary processor.

14. The method of claim 11, further comprising moving control of a process running on a secondary processor back to an associated primary processor on restoration of the associated primary processor.

15. The method of claim 11, further comprising configuring a plurality of spare processors located at a hardware location of the plurality of hardware locations different from the hardware locations of the primary and secondary processors.

16. The method of claim 15, comprising configuring a pair of spare processors is provided for N primary processors, N being an integer greater than 1.

17. The method of claim 11, further comprising:
configuring a plurality of spare processors at a spare hardware location of the plurality of hardware locations different from the respective hardware locations of the primary and secondary processors; and
moving control of a process running on a primary processor to its associated secondary processor upon failure of the primary processor; and
moving control of a process running on a secondary processor to one of the plurality of spare processors.

18. The method of claim 17, further comprising moving control of a process running on a spare processor back to an associated primary processor upon restoration of the associated primary processor.

19. The method of claim 17, wherein a pair of spare processors is provided for N primary processors, N being an integer greater than 1.