# Patent

## Title
Automatically routing nets with variable spacing

## Abstract

A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. patent application Ser. No. 11/555,202, filed Oct. 31, 2006, issued as U.S. Pat. No. 8,095,903 on Jan. 10, 2012, which is a continuation in part of U.S. patent application Ser. No. 10/709,843, filed Jun. 1, 2004, issued as U.S. Pat. No. 7,131,096 on Oct. 31, 2006; Ser. No. 10/709,844, filed Jun. 1, 2004, issued as U.S. Pat. No. 7,784,010 on Aug. 24, 2010; Ser. No. 11/383,658, filed May 16, 2006, issued as U.S. Pat. No. 7,530,040 on May 5, 2009, and Ser. No. 11/383,673, filed May 16, 2006, issued as U.S. Pat. No. 7,373,628 on May 13, 2008. These applications are incorporated by reference along with all other cited references in this application.


BACKGROUND OF THE INVENTION
The present invention relates to the field of electronic design automation for integrated circuits, and in particular, to the area of automatic routing of nets or interconnect with variable spacing.
Integrated circuits are important building blocks of the information age and are critical to the information age, affecting every industry including financial, banking, legal, military, high technology, transportation, telephony, oil, medical, drug, food, agriculture, education, and many others. Integrated circuits such as DSPs, amplifiers, DRAMs, SRAMs, EPROMs, EEPROMs, Flash memories, microprocessors, ASICs, and programmable logic are used in many applications such as computers, networking, telecommunications, and consumer electronics.
Consumers continue to demand greater performance in their electronic products. For example, higher speed computers will provide higher speed graphics for multimedia applications or development. Higher speed internet web servers will lead to greater on-line commerce including on-line stock trading, book sales, auctions, and grocery shopping, just to name a few examples. Higher performance integrated circuits will improve the performance of the products in which they are incorporated.
Large modern day integrated circuits have millions of devices including gates and transistors and are very complex. As process technology improves, more and more devices may be fabricated on a single integrated circuit, so integrated circuits will continue to become even more complex with time. To meet the challenges of building more complex and higher performance integrated circuits, software tools are used. These tools are in an area commonly referred to as computer aided design (CAD), computer aided engineering (CAE), or electronic design automation (EDA). There is a constant need to improve these electronic automatic tools in order to address the desire to for higher integration and better performance in integrated circuits.
Within an integrated circuit, there are devices, such as transistors, and interconnect. Interconnect is used to connect signals between the circuitry and also to supply power to the circuitry. Interconnect may include metal lines, polysilicon lines, polysilicide lines, or other conductive materials. Interconnect is also sometimes referred to as nets. There may be more than one layer of interconnect, such as metal-1 and metal-2 layers. There is a need for a technique of automatically routing the interconnect of an integrated circuit. Automatic routing will automatically connect the inputs of particular devices or circuits to the appropriate inputs, typically from other circuits or devices, or from the pins of those devices.
When automatically routing the interconnect, it is desirable to consider the current or power handling of the particular interconnect line. Certain lines will carry larger currents than other lines. It is desirable that the interconnect lines can carry the current or power they will potentially see during operation, otherwise problems such as electromigration, IR voltage drop, or self-heating will reduce the reliability, longevity, or performance of the integrated circuit.
Furthermore, when automatically routing the interconnect, it is desirable to consider the spacing between interconnect lines in order to improve performance. There will be inductance and capacitance effects that will affect performance. It is desirable to vary the spacing of the automatically routed nets so performance of the signals through the nets improves. Also, longevity of the device may be improved by adjusting spacing because electromigration can be reduced.
Therefore, there is a need for an electronic design automation technique of varying spacing when automatically routing interconnect in order to improve performance.
BRIEF SUMMARY OF THE INVENTION
A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.
In an embodiment, the invention is a method including: providing first pins of a layout to be routed together using a first net; providing second pins of the layout to be routed together using a second net; performing an automatic routing of the first net using a first track; performing an automatic routing of the second net using a second track; and selecting a spacing between the first and second tracks based on at least a first variable. The layout may be gridded or gridless. A spacing between the first and second tracks may be selected by referring to a lookup table or based upon a function.
In an embodiment, the invention is a method including: providing first pins of a layout to be routed together using a first net; providing second pins of the layout to be routed together using a second net; performing an automatic routing of the first net using a first track; performing an automatic routing of the second net using a second track, where a space between the first and second track is a first value; and based on at least a first variable, adjusting the first and second track so the space is second value, different from the first value. The first value may be a minimum space permitted by design rules. The second value may be a greater value than the first value.
The spacing between the first track and second track is greater than a minimum space allowed by design rules. The first variable may include a current associated with at least one of the first or second tracks. The first variable may include a width of at least one of the first or second tracks. The first variable may include an inductance associated with at least one of the first or second tracks. The first variable may include a capacitance associated with at least one of the first or second tracks. The first variable may include an angled turn in at least one of the first or second tracks. This angled turn may be a ninety-degree corner.
In an specific embodiment, the spacing between the first and second tracks is adjusted based on the first variable and a second variable, where the first variable is a capacitance associated with at least one of the first or second tracks and the second variable is an inductance associated with at least one of the first or second tracks. In a further embodiment, when performing the automatic routing of the first net, a width of the first track is determined based on a second variable. The second variable may include a current associated with the first second track. A specific embodiment may further include performing an automatic routing of a first shielding track, positioned adjacent to the first track.
In an embodiment, the invention is a method including: providing first pins on a first layer of a layout to be routed together using a first net; providing second pins on a second layer of the layout to be routed together using a second net, where the second layer is different from the first layer; performing an automatic routing of the first net using a first track; performing an automatic routing of the second net using a second track, where based on a first variable, the second is positioned so the second net is not directly on above or below the first track. The method may include performing an automatic routing of a first shielding track, where the first shielding track is positioned on the first layer, above or below, to the second track.
In an embodiment, the invention is a method including: providing a layout of a circuit design; providing a plurality of pins of the layout to be routed together using a net, each pin having a current value associated with it; using at least one current value, determining a first current requirement for a first track segment of the net; determining a first track width for a first end of the first track segment of the net based on the first current requirement; and performing an automatic routing of the net using the first track segment in the layout, where the automatically routed first track segment has the first track width at the first end and a second track width, different than the first track width, at a second end.
In an embodiment, the invention is a method including: providing a layout of a circuit design; providing pins of the layout to be routed together using a net, a first pin having a first value associated with it and a second pin having a second value associated with it, where the first value is greater than the second value; and automatically generating a first track between the first and second pins, where the first track has a tapered width so a first end of the first track has a width greater than a second end of the first track, and the first end is coupled the first pin and the second end is coupled to the second pin. The first track may have a continuously varying width from the first end to the second end. Alternatively, the first track may have a number of portions, each portion having a different width. The portions may successively have decreasing widths.
In an embodiment, the invention is a method including: providing pins of a layout to be routed together using a net, each pin having a pin value associated with it; using at least one pin value, determining a first requirement for a first track segment of the net; determining a first track width for at least a portion of the first track segment of the net based on the first requirement; and performing an automatic routing of the net using the first track segment, where at least a portion of the automatically routed first track segment has the first track width, and a portion of the first track segment has another track width, different from the first track width.
The method may further include: using at least one pin value and the first track width, determining a second requirement for a second track segment of the net; determining a second track width for at least a portion of the second track segment of the net based on the second requirement, where the second track width is different from the first track width; and performing the automatic routing of the net using the second track segment, where at least a portion of the automatically routed second track segment has the second track width.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a system of the present invention for performing electronic circuit design, including automatic interconnect routing according to current density rules.
FIG. 2 shows a simplified system block diagram of computer system 1 used to execute the software of the present invention.
FIG. 3 shows a simplified functional block diagram of an exemplary EDA system incorporating aspects of the present invention.
FIG. 4 shows an example of current requirement calculation for nets.
FIG. 5 shows an unrouted net with points.
FIG. 6 shows prerouting of the net of FIG. 5.
FIG. 7 shows proposed paths for the net obtained by Steiner tree creation.
FIG. 8 shows some examples of automatically routed tracks having tapered widths.
FIG. 9 shows three automatically routed tracks having a specific spacing between them.
FIG. 10 shows three tracks automatically routed with variable spacing.
FIG. 11 shows four tracks, two on each layer, where two upper layer tracks are on top of two lower layer tracks.
FIG. 12 shows an automatic routing of four tracks, two on each layer, where the spacing between the track of the different layers has been altered.
FIG. 13 shows two tracks turning a corner.
FIG. 14 shows an automatic routing of two tracks turning a corner where the spacing has been altered.



DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an electronic design automation (EDA) system of the present invention for designing an electronic circuit or integrated circuit, including routing of nets of the circuit according to current density rules. In an embodiment, the invention is software that executes on a computer workstation system, such as shown in FIG. 1. FIG. 1 shows a computer system 1 that includes a monitor 3, screen 5, cabinet 7, keyboard 9, and mouse 11. Mouse 11 may have one or more buttons such as mouse buttons 13. Cabinet 7 houses familiar computer components, some of which are not shown, such as a processor, memory, mass storage devices 17, and the like.
Mass storage devices 17 may include mass disk drives, floppy disks, magnetic disks, optical disks, magneto-optical disks, fixed disks, hard disks, CD-ROMs, recordable CDs, DVDs, recordable DVDs (e.g., DVD-R, DVD+R, DVD-RW, DVD+RW, HD-DVD, or Blu-ray Disc), flash and other nonvolatile solid-state storage (e.g., USB flash drive), battery-backed-up volatile memory, tape storage, reader, and other similar media, and combinations of these.
A computer-implemented or computer-executable version of the invention may be embodied using, stored on, or associated with computer-readable medium. A computer-readable medium may include any medium that participates in providing instructions to one or more processors for execution. Such a medium may take many forms including, but not limited to, nonvolatile, volatile, and transmission media. Nonvolatile media includes, for example, flash memory, or optical or magnetic disks. Volatile media includes static or dynamic memory, such as cache memory or RAM. Transmission media includes coaxial cables, copper wire, fiber optic lines, and wires arranged in a bus. Transmission media can also take the form of electromagnetic, radio frequency, acoustic, or light waves, such as those generated during radio wave and infrared data communications.
For example, a binary, machine-executable version, of the software of the present invention may be stored or reside in RAM or cache memory, or on mass storage device 17. The source code of the software of the present invention may also be stored or reside on mass storage device 17 (e.g., hard disk, magnetic disk, tape, or CD-ROM). As a further example, code of the invention may be transmitted via wires, radio waves, or through a network such as the Internet.
FIG. 2 shows a system block diagram of computer system 1 used to execute software of the present invention. As in FIG. 1, computer system 1 includes monitor 3, keyboard 9, and mass storage devices 17. Computer system 1 further includes subsystems such as central processor 202, system memory 204, input/output (I/O) controller 206, display adapter 208, serial or universal serial bus (USB) port 212, network interface 218, and speaker 220. The invention may also be used with computer systems with additional or fewer subsystems. For example, a computer system could include more than one processor 202 (i.e., a multiprocessor system) or the system may include a cache memory.
The processor may be a dual core or multicore processor, where there are multiple processor cores on a single integrated circuit. The system may also be part of a distributed computing environment. In a distributed computing environment, individual computing systems are connected to a network and are available to lend computing resources to another system in the network as needed. The network may be an internal Ethernet network, Internet, or other network.
Arrows such as 222 represent the system bus architecture of computer system 1. However, these arrows are illustrative of any interconnection scheme serving to link the subsystems. For example, speaker 220 could be connected to the other subsystems through a port or have an internal direct connection to central processor 202. Computer system 1 shown in FIG. 1 is but an example of a computer system suitable for use with the present invention. Other configurations of subsystems suitable for use with the present invention will be readily apparent to one of ordinary skill in the art.
Computer software products may be written in any of various suitable programming languages, such as C, C++, C#, Pascal, Fortran, Perl, Matlab (from MathWorks, Inc.), SAS, SPSS, Java, JavaScript, and AJAX. The computer software product may be an independent application with data input and data display modules. Alternatively, the computer software products may be classes that may be instantiated as distributed objects. The computer software products may also be component software such as Java Beans (from Sun Microsystems) or Enterprise Java Beans (EJB from Sun Microsystems).
An operating system for the system may be one of the Microsoft Windows® family of operating systems (e.g., Windows 95, 98, Me, Windows NT, Windows 2000, Windows XP, Windows XP x64 Edition, Windows Vista, Windows CE, Windows Mobile), Linux, HP-UX, UNIX, Sun OS, Solaris, Mac OS X, Alpha OS, AIX, IRIX32, or IRIX64, or combinations of these. Other operating systems may be used. A computer in a distributed computing environment may use a different operating system from other computers.
Furthermore, the computer may be connected to a network and may interface to other computers using this network. For example, each computer in the network may perform part of the task of the many series of steps of the invention in parallel. Furthermore, the network may be an intranet, internet, or the Internet, among others. The network may be a wired network (e.g., using copper), telephone network, packet network, an optical network (e.g., using optical fiber), or a wireless network, or any combination of these. For example, data and other information may be passed between the computer and components (or steps) of a system of the invention using a wireless network using a protocol such as Wi-Fi (IEEE standards 802.11, 802.11a, 802.11b, 802.11e, 802.11g, 802.11i, and 802.11n, just to name a few examples). For example, signals from a computer may be transferred, at least in part, wirelessly to components or other computers.
FIG. 3 shows a simplified functional block diagram of an exemplary EDA system 300 incorporating aspects of the present invention. The EDA system includes a number of software tools, any of which may access a shaped-based database model 301 containing an integrated circuit design, or one or more portions of an integrated circuit design. The EDA system provides such tools as a graphical user interface 302, global router 304, manual editor 306, detail router 308, engineering change option (ECO) engine 310, timing-driven routing engine 312, extraction engine 314, data export interface 318, DSM process engine 320, and silicon interface format 322. An EDA system may include any number of the system tools shown in FIG. 3, and in any combination. Further, the EDA system may include additional tools not shown in FIG. 3.
An EDA system may be a grid-based system or shape-based system. Techniques of the present invention may be applied to a gridded or shape-based EDA system. A grid-based system relies heavily on the concept of a grid and routing grids. Gridded modeling, however, becomes difficult to implement successfully as the routing and feature sizes become smaller. The amount of data increases according to a square law, which means that tasks become increasingly more computationally complex and time-consuming as the amount of data increase. As feature sizes in integrated circuits continue to shrink, more features or geometries may be fitted into the same unit area of an integrated circuit. Therefore, it is important for an EDA system to handle increasingly complex integrated circuits and provide output or results quickly.
The techniques of the invention are especially suited for a shaped-based system, which may also be referred to as a gridless system. A shape-based system has no defined cell size. Each cell, or expansion area, is as large as possible. In brief, a shape-based system can expand edges, which means that an edge of an enclosing rectangle (or other polygon) may be expanded in the direction of the edge as far as desired until the edge finds an obstacle. This may be referred to as a “flood” operation. The rectangle may be representative of any polygon of the integrated circuit, such as a net, contact, via, transistor gate, or transistor active area. Blocked edges are edges that cannot be extended because they are blocked by a perimeter of another rectangle, such as another segment, net, or obstacle. Once an obstacle is encountered, then a shape-based approach floods around the obstacle—making a ninety degree or other angle (any angle may be used) turns as needed to route around the obstacle.
Chip design, be it analog, custom or digital, will increasingly suffer from timing and signal integrity issues, and in particular crosstalk, as geometries continue to decrease and ever more fine wires are introduced. Gridded solutions are not flexible enough to resolve these issues, let alone achieve a high rate of routing completion. A high performance timing and crosstalk-driven routing solution will become a mandatory requirement in physical design. The grid-based approach offers fast routing but requires customization to handle off-grid connections and is inefficient for postroute timing and signal integrity optimizations. When net widths and spacings must be changed to reduce resistance or cross-talk, grid-based approaches waste space by moving nets to the next available grid and waste time by resorting to rip-up and re-route techniques. Gridded systems are not good at irregular intervals, irregular spacings, or routing things that do not fit onto a regular grid. The gridless approach easily handles off-grid connections and is efficient for postroute optimizations. In a shape-based or gridless system, the layout may be a gridless layout, which means there is no grid which structures or polygon of the layout are associated with.
In an embodiment, the structure of database 301 facilitates shape-based operations. For example, a structure of this database may include an obstacle tree having nodes and leaves containing the obstacles of an integrated circuit. This tree structure permits rapid determination of where obstacles are when doing operations on the database, such as routing nets.
In an embodiment, the invention may be implemented in a high performance auto-interactive IC physical design solution for analog, custom, digital, mixed-signal, embedded DRAM or SRAM, and system-on-chip (SoC) design. The system incorporates solutions for automatic placement, routing, full ECO capabilities, timing closure, signal integrity, and power routing. In another embodiment, the invention is implemented in an ultra high capacity, high performance IC physical design solution for very large digital/ASIC designs, running into millions of nets and cells. This software package incorporates solutions for ECO placement and routing, powered by a scalable architecture, using a true distributed computing environment.
In FIG. 3, the EDA system 300 includes one or more of the components discussed below, in any combination. One skilled in the art will recognize that one or more of components shown in FIG. 3 may not be required to practice specific aspects of present invention. For example, when DSM process engine 320 is omitted from system, the system could still perform automatic routing of interconnect, but without providing DRC checking capabilities.
A graphical user interface 302 provides users a graphical interface in which to perform operations on the integrated circuit design. For example, the user can view the integrated circuit using the graphical interface. The user may use the mouse and cursor to select a particular polygon or feature, such as a net. The user may expand or zoom into areas of the integrated circuit design.
A global router 304 is an automatic routing engine that coarsely routes interconnects of the integrated circuit, thus enabling large designs to be routed more rapidly and completely. The global router may also provide visual and quantitative analysis of the congestion in the design by highlighting problem areas that can be fixed by incremental adjustments to the floor plan. The global router is sometimes referred to as a coarse router because it provides generally the routes for the interconnect, and may work in conjunction with a detail router 308 (discussed below) to place the geometries of the interconnect.
A manual editor 306 is a shape-editing suite for creating or editing metal, keep-outs, routing areas, and the ability to partition a design into smaller areas. These areas can then be worked upon individually and can be recombined at a later stage to complete the design. Full on-line design rule checking (DRC) ensures that manual operations are completed error-free first time. Powerful tools automatically push-aside existing wiring to make way for new wires and semiautomatic routing tools quickly close down troublesome nets by allowing the user to guide the routing engine around complex areas of the design.
The detail router 308 is an automatic router that completes the wiring in a design by determining the specific routes for each interconnect. The detail router may complete a portion of the wiring for design, such as for sections or specified cells of the design, or may complete all the wiring of the design. The detail router may route starting from scratch or from partially completed routing. In an implementation, the global router determines the general route paths for the interconnect, and the detail router takes this routing information from the global router and puts in the physical detailed geometries of the tracks and vias.
An ECO engine 310 provides a capability to handle late stage ECO changes. Every element of the design can be modeled incrementally, thus eliminating the need to ever restart the physical design, no matter what changes may need to be made from upstream or downstream processes in the design. ECO engine capabilities can include the ability to shove or push cells aside to make space for new or relocated instances, and the ability to drop groups of components and automatically find legal placement sites for them minimizing the disruption to the design. When pushing or pulling cells, the wires remain connected to the cells and the wires lengthen, shorten, and move as needed, if possible, to keep the connections. The detail router can then repair any violating interconnects and stitch-up any newly introduced interconnects, with minimum impact, ensuring circuit stability is never compromised.
A timing-driven routing engine 312 provides RC timing analysis of interconnects. Used in concert with the detail router, the timing engine can determine the path of least delay for critical nets. Furthermore, the timing engine, in concert with an extraction engine, can actively select a longer path with a lower associated delay (e.g., due to lower capacitance) in preference to a shorter but slower route.
An extraction engine 314 is provided. Utilizing a unified, high-speed RC extraction engine, the crosstalk functionality accurately calculates the coupling between victim and aggressor signals. This same technology is then used to identify potential problems, and automatically implements a DRC correct solution without changing the path of the signal unnecessarily. In addition, signal-to-signal (or within and between classes of signals) spacing rules can be applied, and fully controllable automatic shielding can be used to protect particularly sensitive signals. The user is provided with unprecedented control over the resistance and capacitance in the signal path. Again, using the advanced built-in RC extraction technology, the user can separately control path resistance and capacitance, which is particularly useful for analog and mixed signal design.
In an implementation, the global router and detail router are linked to the extraction engine. So, for example, when running, the global router or detail router, or both, can call the extraction engine to obtain RC extraction information. The global router, detail router, or both, may use the RC extraction information when creating the interconnect routes. For example, the detail router may obtain RC extraction info from the RC engine in order determine whether an interconnect route meets current density rules, and widen the interconnect width as needed.
In a specific embodiment, the internal RC extraction driven constraints manager has been enhanced to ensure matching on a per-layer basis as well as the whole net or subnet. There is an increasing requirement in today's designs to match length, time, resistance and capacitance across nets on a per-layer basis. This ensures total net constraints are met as before but also guarantees designated nets can match on a per-layer basis.
The tightly coupled, high-speed RC extraction engine is used both during routing (global router or detail router, or both) and for postrouting extraction to reach timing closure in record time. Integrated timing analysis and curative features enable the management of delay within the design; the matching of delays within and between multiple nets; the sharing of delay between many nets in a signal path; and reducing the delay in critical nets by minimizing resistance and capacitance. Intelligent lengthening increases the delay of the faster nets, preventing shoot-through.
The detail router can address current density issues in analog design, to help achieve an optimum routing result for the entire design, and save valuable design time. The current information which is used to drive this current density functionality may come from, for example, a front-end schematic engine or simulation engine. The router can automatically route a net at varying widths to guarantee sufficient track widths at every point in the topology of the net to carry all current requirements. DRC and process checking tools locate any insufficient width areas that may exist in any routing, including automatically generated routing, manual routing, and imported prerouting.
A data export interface 316 is provided so data of the EDA system 300 may be exported for other processes. For example, output from the EDA system may be passed through the export interface to other EDA systems or software tools provided by other manufacturers. The export interface would provide output in a form, format, or structure, acceptable by process or software tool which is being exported to.
A data import interface 318 provides the means to import data, such as a circuit layout, netlist, or design constraints. The data to be import may be in various formats including data saved from other EDA systems or software tools. In addition, the source of the data may be a database, floppy drive, tape, hard disk drive, CD-ROM, CD-R, CD-RW, DVD, or a device over a communication network. Some example of import formats include text, ASCII, GDSII, and LEF/DEF.
A DSM process engine 320 is provided. The DSM process engine does design rule checking (DRC). Design rule checking locates and highlights where a design is breaking process design rules. For example, a design rule is the minimum spacing between metal lines (i.e., geometries on a specific layer). A design rule may be the minimum width of a metal line. A design rule may be a minimum polysilicon-to-diffusion spacing. There are many other design rules for a typical process. Some design rules are for checking geometries within a single layer, and some design rules are for checking geometries of two or more layers.
A silicon interface format 322 is provided, which in a specific implementation is an ASCII database format. However, in other implementations, other silicon interface formats may be used.
A user may design an integrated circuit using a system such as shown in FIG. 3. A representative flow for designing an integrated circuit is outlined in steps 1 to 8 below in flow A. Step 5 is further subdivided into three substeps.
Flow A
Integrated Circuit Design Flow
1. Provide Circuit Specification
2. Create Circuit Design
3. Generate Netlist
4. Simulate Performance and Verify Functionality of Circuit Design
5. Generate Layout
5a. Layout Devices
5b. Connect Devices
5c. Connect Blocks of Circuitry
6. Physical Verification and Design Checking
7. Create Masks
8. Fabricate Integrated Circuit
Although the steps above are listed in a specific order, the steps may take place in any order, as desired and depending on the specific application. These are general steps that may be applied to designing an integrated circuit including custom, a gate array, standard cell, field programmable logic, microprocessor, digital signal processor, microcontroller, system-on-a-chip (SOC), memory, ASIC, mixed signal, analog, radio frequency (RF) or wireless, and others. There may be additional or other steps, which may replace one or more above steps. Certain steps may be repeated. For example, after generating a layout for a circuit design, the step of simulating performance and verifying functionality may be performed again. This time, the parasitics and RC considerations from the layout can be back-annotated into the netlist or circuit design, and the design simulated again. The results of this simulation will presumably be more accurate because more precise information is provided.
In step 1 of the flow, a circuit specification is provided. This is a specification or description of what the integrated circuit or circuit will do, and what the performance will be. For example, the integrated circuit may be a memory integrated circuit with particular address input pins and input-output (I/O) pins. Integrated circuit performance may be quantified terms in AC and DC performance. For example, AC performance refers to propagation delays, maximum clock frequency, clock-to-output delay, hold time, and other similar parameters. DC performance refers to maximum supply current, maximum and minimum supply voltage, output current drive, and other similar parameters.
In step 2, an engineer creates a circuit design that presumably will meet the circuit specification. This circuit design may include transistors, resistors, capacitors, and other electronic components. The engineer uses these electronic components as building blocks of the design, interconnecting them to achieve the desired functionality and performance. The engineer may make a custom design using electronic component building blocks or use a gate array, where the building blocks are sets of cells set by the gate array manufacturer. The design may be input using a graphical design tool such as schematic capture program, and any other design tool may be used. The circuit may be described using a high-level design language (HDL). These design tools will create a netlist (step 3) of the circuitry, which is a listing of the components of the devices and their interconnections.
During the design phase, the engineer simulates the performance and verifies the functionality of the circuitry (step 4). There are transistor and process models to model the components. Some simulation tools include Spice, which performs circuit simulation, and Verilog, which performs functional and timing verification. This is where the electrical information for current density routing is generated.
After deciding upon an initial circuit design, the engineer begins layout (step 5) of the circuitry. Layout refers to making the three-dimensional dispositions of the element and interconnections to make an integrated circuit. Making an integrated circuit is a layer by layer process. Some layers of an integrated circuit are diffusion, polysilicon, metal-1, metal-2, contact, via, and others. There may be multiple layers of the same material, but on different layers. For example, diffusion and polysilicon layers are used to make MOS transistors (step 5a). For example, metal-1 and metal-2 are two different layers, where metal-1 is below the metal-2 layers. These metal layers may be connected together using a via. Metal is typically used for interconnections (step 5b) and supplying power and ground to the devices.
Software tools may be used to help with the layout of the circuit, such as the automatic routing of interconnect (steps 5b and 5c). The interconnect may be between devices. Devices and circuitry may be grouped into blocks or cells having inputs and outputs. The interconnect may be between these blocks or cells (step 5b).
In step 6, after or while the layout is generated, the physical design is verified and checked. For example, some of these operations may include layout-versus-schematic (LVS) checking, electrical rule checking (ERC), design rule checking (DRC), layout simulation (especially for analog circuitry), power analysis, and timing analysis. Physical verification and design checking is often iterative. Based on the design check, a design engineer or user may make changes to the design or layout, or both and the design may be rechecked in order to make sure any areas of concern or design errors have been cleared.
The result of layout is data (e.g., provided in GDSII or other format) that is used to make the masks (step 7). The masks are used to fabricate the integrated circuit (step 8) using a photolithography process. Typically, there are many “copies” of the same integrated circuited fabricated on the same wafer. Each integrated circuit is a “die” on the wafer. Good dies are separated from the bad dies. The good dies are sawed and packaged. Packaging generally includes encapsulating the die in plastic or other material, and connecting pads of the integrated circuit to pins of the package, where the integrated circuit can be interfaced.
The invention provides techniques to automatically route nets according to current density rules. The invention would help with steps 5b and 5c (routing interconnect) of the design process.
There are several effects that can cause reliability or performance problems due to currents flowing in wires within an integrated circuit. One potential problem is electromigration. At high current densities, such as when the value of current divided by cross sectional area of a wire is large, electrons become accelerated to a level where they can displace atoms from the crystal lattice of the metal wire. Over time this can lead to voids in the wire and ultimately an open circuit can form. Furthermore, the displaced atoms may leave the body of the wire altogether and form spurs at corners in the wire, leading to short-circuits with other neighboring electrical signals. Both opens and shorts lead to functional errors. This effect gets worse with time and hence can cause failures in the field a considerable time after manufacture. The wider a wire, the lower the current density will become.
Another potential problem is IR voltage drop. Due to Ohm's law, a current flowing throw a resistance (a resistance in this case is a narrow wire) will create a potential difference, and in the case of an electronic circuit this invariably means that the voltage of a signal will become degraded. This may mean that logic transitions fail to cross thresholds, or take longer to do so, or that noise will cause false transitions, or in an analog circuit the signal-to-noise ratio will be reduced. This will reduce functional yield and may cause failures in the field. The wider a wire is, then the lower the resistance and hence the lower the voltage drop.
Another potential problem is self-heating. Current flowing through a resistance (a resistance in this case is a narrow wire) generates heat (I^2R). This heat will generally slow down circuit operation (as transistor characteristics get worse at raised temperature), and if localized can cause mismatches in analog circuitry or clocking structures and thus generate functional errors. This will reduce functional yield and may cause failures in the field. The wider a wire is, then the lower the resistance and hence the lower the temperature. Another potential problem from self-heating is that with sufficient current and heat, an interconnect may be like a unintended fuse and can burn out. This would create an open circuit, which may also cause functional problems.
For most signals, the minimum width wire allowed by design rules is sufficient to avoid these problems because the current involved is low and transitory. But for analog nets, power supplies, clocks and other high-drive digital signals—one or more of the effects may cause concern. The design rules are a set of guidelines that are followed when laying out the integrated circuit. The design rules are generally provided by the process engineers or foundry.
It is inefficient to set all segments of the routing of such nets to a large width, or even the worst case width as this will take up an unnecessarily large part of the design area, hence increasing production costs.
One way to efficiently handle the current requirements of such nets while not using excessive real estate on the design space is to connect the devices on the net by hand, ensuring that each “section” of the net in the routed topology is sufficiently wide enough to handle the relevant pin current of the devices. The problem with this approach is that it is very time consuming and unreliable as the user will have to calculate the necessary widths for each section of the routed topology and ensure the sections are at such width. Also, invariably the hand-routed nets will have to be redone frequently to make way for other requirements, placement adjustments, congestion, ECO requirements, and so forth.
It is therefore desirable to automatically route the nets and automatically determine the minimum required width for each section of the routing of such nets, taking into account the relevant rules (electromigration, IR drop, and self-heating), as well as the characteristics of the individual net such as switching frequency, noise margin, pin currents, capacitance, and other characteristics.
Traditionally, automatic routers have no knowledge of and do not take into consideration current density rules. Traditionally, automatic routers take into consideration spacing rules when routing interconnect. Using a traditional automatic router, a user may make adjustments manually to account for current density rules. When using a traditional automatic router, some strategies may include: (a) route using the minimum track width, and manually apply a fattening postprocess, or (b) route using a larger track width for the whole net. A problem with (a) is that it may not be possible to fatten the routes by the necessary amount to meet the current density rules. A problem with (b) is that it is unlikely to be possible to route the design one hundred percent when using an artificially large track width for the whole net
There is need for a technique of allowing the current density rules to be considered during the routing process itself that would result in a net being fully automatically routed at various differing widths to sufficiently handle the current densities at each section of the resultant topology. This strategy could be extended to determine track widths according to the resistance of the various paths on a net.
Input Data
Input data includes a current density function, where current density is given as a function of at least one of layer, net frequency, or track width, or all or any combination of these. There may be other factors that affect current density and these factors may also be part of the function. The current density function may be provided in the form of a formula, equation, table, table, look-up table, or any other technique for quantifying a current density relationship.
In a specific embodiment, the data to be used includes one or more current density tables and a frequency of each net. A current density table is a table providing the current density as a function of layer, net frequency, and track width. Such a table will enable a minimum track width to be determined, given a frequency, a layer, and a current requirement. In another specific implementation, the technique uses entries from the table. If current is higher than a particular value, then the next higher entry in the table is used. This approach provides a conservative value for the width of the interconnect, because the interconnect will be wide enough to handle the expected or calculated current. In another implementation, where a specific current requirements value is not found in the table, a current requirement value may be obtained by interpolating using entries available in the table.
For example, a linear interpolation technique may be used to determine a current requirement, where the frequency is between two different frequencies provided in the table. As a sample calculation, two entries in the table are (50, 10) and (40, 5), where for (M, N), M represents frequency and N represents current requirements. Then, then using linear interpolation, for a frequency of 45, the current requirement will be 7.5. For a frequency of 48, the current requirement will be 9 (i.e., (48−30)/2). Although this is an example of linear interpolation, other types of interpolation may be used including polynomial, exponential, logarithmic, and others.
A frequency of each net (where 0 is a DC net) is also provided as input. In an embodiment, when frequency information is not provided for a particular net, DC operation of the nets will be assumed. In another embodiment, when frequency information is not provided for a particular net, a warning message will be provided to the user. The user then can supply the frequency information.
The current requirements for a net changes as the frequency changes. The function of current density as a function of frequency is given in the current density table. For example, typically, as the frequency on a net increases, there is an increase in current or power requirements. The current associated with each device pin of relevant nets, where a +ve value indicates driver/source, and a −ve value indicates receiver or sink. Normally the sum of the currents of all the device pins on a net will be zero, but this is not essential.
Width Formula
The invention may use following width formula. The following describes how to determine the needed track width for a particular track segment on a routed net.
A net is the wire connecting all the points together. There may be many branches and segments in a single net. Each of the branches or segments may have different current requirements because there are inputs and outputs along the path, and current path gets divided up. A subportion of the net may be referred to as a track. Interconnect will be used to form the net in the integrated circuit design. And based on the current requirements for a track, a particular track width is selected and this width is used for the interconnect in the design.
Assume we have a net N, and a track segment T on layer L. Firstly, we will determine the current requirement C, for the track T.
Determine which pin on the net is the “main driver,” i.e., the pin with the largest (positive) current. Having done this, we can determine which pins are downstream of track T. The current requirement C is the (absolute) sum of the current requirements of the downstream pins.
FIG. 4 shows an example of an application of a width formula of the invention. FIG. 4 shows nets and pins. Boxes 403 represent device pins with their associated pin current values. The +6 pin 406 will be treated as the main driver. The derived current 409 for the various paths are shown.
For example, a branch or segment 411 provides a current of 6 while a segment 413 provides a current of 2. Therefore segment 418 handles current of 8, which is the sum of the currents on segments 411 and 413. These calculations provide the current requirements for those nets.
Having determined the current requirement for a particular track segment, we can now derive the corresponding track width. This calculation depends on the net frequency, the track layer, and current density tables. The actual currents may be less, but the width of the net will be wide enough to handle the provided current requirements.
Routing Technique
Given a routed net, it has been shown how it is possible to determine the current requirement of each route path. From this, we can determine the width requirement for each track. Any track that is deemed to be of insufficient width to support its current requirement can then be widened provided there is sufficient space, or that adjacent wiring can be pushed aside to create sufficient space.
An aspect of the invention is to allow the current density rules to be considered during the routing process. A key problem with this is that the precise routing topology of a net is not known in advance. Thus we do not know which pins are downstream of each potential track, and therefore we cannot derive the appropriate track widths to use.
A basic strategy or flow for solving this problem is to route nets with current density rules using Steiner trees. Flow B provides an example of pseudocode for such a technique of routing while considering current density rules.












Flow B


ROUTENET( N )


{









// form a set of points S to be connected for net N



// generate Steiner tree for S



// this will gives a new set of points S′ and a set of links L between



// these points



// for each point in S' that was not in S



{









// create virtual pin









}



// rearrange the unrouted connections on N according to the Steiner



// links L



// for each unrouted connection C on N



{









// determine the current requirement A of this connection C



// this is done by finding the sum of the currents of all



// the downstream pins



// determine the track width per layer for C using









// the current requirement A, the net frequency, and the



// current density tables



// autoroute this connection with these track widths



}







}









Steiner Tree Creation
At the core of this strategy is the ability to create a Steiner tree for the net. A Steiner tree is a tree in a distance graph which spans a given subset of vertices (Steiner points) with the minimal total distance on its edges. In the seventeenth century, French mathematician Pierre Fermat asked how we could find a point P in a triangle with the distances from P to the vertices being as small as possible. This problem was later solved by Toricelli. The Steiner problem is a generalization of this question allowing for an arbitrary number of initial vertices and an arbitrary number of vertices to be added. Even more simply stated, the Steiner problem is to join a set of points with the smallest collection of connections. Steiner tree creation should be very efficient and will necessarily be a heuristic algorithm as Steiner tree creation is NP complete. Heuristic algorithms have been designed to approximate the result within polynomial time.
Various Steiner tree algorithms exist today. Mostly these are from academic research. One approach is referred to as the “batched greedy algorithm” (BGA), worked on by Kahng, Mandiou, and Zelikosky. However, in other implementations of the invention, other Steiner tree algorithms may be used including Prim's algorithm and Kruskal's algorithm.
Prim's algorithm is an algorithm to find a minimum spanning tree. The steps for Prim's algorithm are:
1. Set i=0, S0={u0=s}, L(u0)=0, and L(v)=infinity for v< >u0. If |V|=1 then stop, otherwise go to step 2.
2. For each v in V\Si, replace L(v) by min{L(v), dv ui}. If L(v) is replaced, put a label (L(v), ui) on v.
3. Find a vertex v which minimizes {L(v): v in V\Si}, say u(i+1).
4. Let S(i+1)=Si cup {u(i+1)}.
5. Replace i by i+1. If i=|V|−1 then stop, otherwise go to step 2.
The time used by Prim's algorithm is O(|V|^2). It will be reduced to O(|E|log|V|) if heap is used to keep {v in V\Si:L(v)<infinity}.
Kruskal's algorithm is another algorithm to find a minimum spanning tree. The steps for Kruskal's algorithm are:
1. Set i=1 and let E0={ }
2. Select an edge ei of minimum value not in E(i−1) such that Ti=<E(i−1) cup {ei}> is acyclic and define Ei=E(i−1) cup {ei}. If no such edge exists, let T=<Ei> and stop.
3. Replace i by i+1. Return to Step 2.
The time used by Kruskal's algorithm is O(|E|log|V|).
For an implementation of the invention, a Steiner tree algorithm is used where improvements are made to the batched greedy algorithm. This improved batched greedy algorithm is highly scalable and in tests is able to find a near optimal solution for 35,000 terminals in 24 seconds compared to several hours or days for other heuristic algorithms.
The standard batched greedy algorithm has some limitations that are addressed by the improved approach of the invention. Some limitations of the standard batched greedy algorithm that are addressed by the invention include:
1. The standard batched greedy algorithm works on idealized points not arbitrary shapes—e.g., prerouting, and so forth.
2. The standard batched greedy algorithm does not consider electrically equivalent points.
3. The standard batched greedy algorithm does not consider routing obstacles.
New Batched Greedy Algorithm for Prerouting and Large Shapes
Because the standard batched greedy algorithm does not consider rectangles or anything more complicated than points, we improve the algorithm to handle with these real world items.
In an approach of the invention for the purposes of batched greedy algorithm, preroutes are deconstructed to a number of points and that the batched greedy algorithm is modified to consider forced connections. Therefore a segment (or number of segments) could be represented as a number of terminals which are already connected to each other and whose connections cannot be broken.
In the case of a track these points will be placed at the ends of the segment and at the intersection of the track with the lines of a Hanan grid. A Hanan grid is an induced grid which is formed by drawing vertical and horizontal lines through the points. By imposing a Hanan grid, this restricts the feasible solution search space to a finite collection of trees. Hanan's classic result states that a shortest Steiner tree exists on the grid induced by the points.
For vias, it is only necessary to add a single point at the connections point. For shaped items, i.e., large pins and metal, points are added at the centre and around the perimeter where the perimeter intersects the Hanan grid.
All points that belong to the same subnet should be connected together so that the BGA algorithm will not attempt to disconnect them.
FIG. 5 shows an example layout of an unrouted net showing points 506 on pins. Pins are indicated by shaded rectangles 509. In FIG. 5, there are five pins. Within the pins are deconstruction points 506 for the pins. Each of the pins of FIG. 5 has three deconstruction points each. There are dashed lines 512 connecting the pins; these dashed lines show the logical connections. Surrounding each pin is a rectangle 517, which is the cell outline. There are dark three rectangles 521 that are obstacles, which the interconnect cannot route through.
FIG. 6 shows the net of FIG. 5 with prerouting 608. There is a Hanan grid with grid lines going vertically 608 and horizontally 611. There are projected points 616 on the prerouting 605. Where the Hanan grid and track intersect or cross each other, a deconstruction point is placed. Therefore, on prerouting track 605, there are six projected points 616, each occurring at an intersection with the Hanan grid. Prerouting is a term used for routing that already exists in a design—i.e., not created by any part of the tool, rather it has been imported along with the design into the tool.
The result of the Steiner tree includes the proposed paths and one or more virtual pins. The proposed path is shown in FIG. 7. Paths connecting at a virtual pin will guarantee the topology of the net, which means the current density will be guaranteed because there the width of the branch will be sufficient.
The position of the virtual pin is such that when defined in the topology of the netlist, it will define a branch point that is to be connected to by the paths from the pins, and all those paths connecting to the virtual pin can be widened sufficiently to meet the current requirements of the pins on those paths.
FIG. 7 shows proposed paths for routing a net. The proposed paths determined by Steiner tree creation are indicated by reference numbers 708, 711, and 715. A virtual pin is indicated by the reference number 719.
Technique for Electrically Equivalent Points
A single logical pin may have multiple subpins. These shapes may be internally connected, in which case only one of the subpins will be routed to, or they may not be internally connected in which case they all should be routed to. All members of a subpin group are assumed internally connected sufficiently so that only one will be routed.
Separate subpin groups are assumed to have no internal connection, so each subpin group must have at least one routed pin. The connection between two subpins may be sufficiently strong so as to allow for through routing. In this case a subpin arc is defined between the two subpins.
Where a pin contains subpins that are electrically equivalent, then one of the two following approaches is used depending of the exact nature of the equivalence.
For subpins in the same group that are not connected by an arc then the points for each pin should be replaced by a single point at the centre of the subpins. After the Steiner tree has been constructed each such group will be visited in turn and the lowest cost subpin in each group will marked as the preferred subpin and other subpins will be marked unexitable. In this way once a preference for the top or the bottom of a cell row is established by the first group, other cells in the row are likely to follow resulting in a better routing pattern.
For subpins that are connected by an arc then both pins will be represented to batched greedy algorithm as connected by a forced connection in a similar way to prerouting, the batched greedy algorithm will then be able use the potential feed through.
Technique for Routing Obstacles
Many routing obstacles do not need to be considered in great detail. The two main types of routing obstacles that should be considered are:
1. Those obstacles, or combination of obstacles, that block all routing in a particular bias through an area or completely block all routing in a particular area.
2. Those obstacles that would prevent the placement of Steiner points (virtual pins).
The inner part of the batched greedy algorithm is changed to consider these obstacles when proposing potential routing structures. In an implementation, this is achieved by passing into the batched greedy algorithm a set of rectangles that represent routing obstacles along with the direction of routing blocked by each.
However this is likely to have an impact of the single point method for routing electrically equivalent points as many such subpins are either side of routing obstacles. So when routing between such pins by the batched greedy algorithm, the technique should ignore the routing obstacles if both points lie within the same contiguous region of the obstacle.
To ensure that there is not an explosion of these regions, only items that are bigger in the anti-bias dimension than a number of routing pitches will be considered (the number of pitches is to be found by experiment).
Other Considerations
Buried Pins
A buried pin is a pin that is fully enclosed by an obstacle. Buried pins should be treated slightly differently than other pins. Buried pins will be represented by a point just outside the blockage where the first legal routing pitch would be. In order to automatically route buried pins and consider current density rules, strict rules are used which allow obstacles to be ignored so buried pin may be routed in a strict way. More specifically, if the buried pin is near the edge of the obstacle, it may be routed directly through that edge. Therefore, as far as the Steiner tree is concerned it is better modeled as a point outside the obstacle.
CMOS Transistors
CMOS transistors, where the gate of a transistor has been modeled as a single pin and the middle is covered with an obstacle, should be represented as a single point in the middle on the pin. Then in a similar way to that of electrically equivalent pins each possible exit direction should be considered and the lowest cost edge preferred and other exit directions barred. This should encourage a routing pattern that connects multiple transistors along the same side.
Considering Width of a Previously Routed Segment
As previously discussed, a technique of the invention includes evaluating a current density function having as input at least one of a layer of the first track, a frequency of the net, a current requirement for a branch or segment of a net, or power requirement for a branch or segment of a net. The technique may further include determining whether the current in a particular branch or segment of a net may change due to the width of a previously routed segment. In other words, there may be an alteration of the current in a segment to be routed (where the width is to be determined) due to other segments already routed or projected to be routed within the same net. The width of a segment to be routed may be adjusted based on widths of previously routed segments of the same net.
Tapering of Track or Segment Widths
A technique of the invention of automatic routing includes tapering (or otherwise varying) the widths of the tracks, segments, or a net based on proximity to current sinks and sources. In some cases, the current coming from the pins does not sum to zero because some proportion of the current from a first pin goes to charging the parasitics of the wiring (such as charging up the parasitic capacitance). The total current flowing in the net sums to zero, but the pins are not the only sources or sinks of that current. This means that the wiring will taper between nodes in the net. For example, even if there are only two pins the wire will taper down from the source to the sink pin. In other words, a track will be wider closer to a source of current and will be narrower closer to the sink of the current. This is especially relevant to RF or high speed CMOS style designs.
FIG. 8 shows some examples of automatically routed tracks with tapered widths. Tracks 805, 809, 816, and 820 have tapered widths, where a width is wider on a first end and gets narrower as the track progresses from the first end to a second end. Typically, the wider end may be referred to as a source end since it will be closer to a current or voltage source. For example, the source end will be closer to VCC or VDD or closer to a signal source. The narrower end may be referred to as a sink end since it will be closer to a current or voltage sink. For example, the source end will be closer to VSS or the most (or more) negative voltage rail of a circuit, or closer to a signal receiver.
For track or segment 805, one side of the track is continuously tapered from the wide end to the narrow end. The wide end and narrow end are both shorter distances than either of the sides of the track. For a typical tapered track, the sides are substantially longer than either of the sides. The tapering of this track is according to a function such as w=mx, where w is a width of a track at a relative position x from the wider end. When x is 0, the width will be at its widest. As the tracks progresses to the narrower end, the width gradually gets narrower according a factor m. The factor m may be any number, such as 1/2, 1/3, 1/4, 1/10, 1/15, 1/64, 1/256, 1/1000, 1/10,000, 1/55,498, 23/122,500, 1/4,087,010,035, or others. The m factor may be user selectable.
For this track, the function is a linear arithmetic function, where the width varies linearly with position from one of the ends. However in other implementations, the tapering may be according to any function, not just arithmetic, but a geometric, logarithmic, exponential, or other function may be used. The track is drawn to show the desired result after fabrication. However, one of skill recognizes, there may be additional steps where the drawn shape is altered in order to address variations between a drawn layout and the result structure after processing (e.g., OPC effect). Further, the processing may produce a final result which is not exactly what was drawn.
Track 809 is similar to track 805 except that both sides are tapered, instead of only one side. Tracks 805 and 809 are examples where the tapering is continuous. The width continuously gets smaller (or larger, depending on perspective) from an initial value to a final value. For example, the width may be, for example, 10 microns near the sink and continuously gets narrower in width until the net reaches a sink, where the width is, for example, 6 microns.
Track 816 has portions or sections of the track which become narrower when progressing from a wide end to a narrow end. This track has three portions 832, 834, and 836. Compared to portion 832, one side of portion 834 becomes narrower. Compared to portion 834, one side of portion 836 becomes narrower. Here, the tapering takes the form of discrete or distinct step downs (or step ups) of the width, such as reducing the width after a certain length. For example, the width may drop 0.2 microns every 0.5 microns of length. For a particular track or segment, there can be any number of portions. Track 816 has 3 portions, but in other embodiments, the track may have 2, 4, 8, 9, 20, 25, 48, 64, 100, 168, 556, 1066, 1492, 8088, 10,423, 68,000, 100,265, or more or other number of portions.
Track 820 is similar to track 816 but both sides of the portions are tapered, instead of only one side.
A gridless router can handle a continuous tapering approach more easily than a gridded router. This is because for a gridless router, there is not a concern of a segment becoming “off grid.” For a continuously varying width in a gridded system, the width of a track at some point will become off grid. An off-grid polygon or other feature is not permitted in a gridded system and typically causes an error. Therefore, for each segment, the gridded router can round up or round down the position of edges to the next grid size. However, this will be inefficient, when compared to the gridless router. To avoid causing errors, for a discrete tapering approach would generally be preferable in the gridded router case.
A further embodiment of the invention may adjust the width of a segment in order to minimize timing delay. For example, tapered wiring from a source to a sink will give the lowest delay if the resistance of the net is comparable with the resistance of the driver. Considering timing delay may be in addition to considering current carrying or other concerns.
In a further embodiment of the invention, the width of a segment will be varied based on its proximity to other nets and segments. More specifically, the width of a first segment may be set according to its spacing from a segment of a second net. This is to take into account factors such as (i) parasitics (e.g., capacitance and inductance) between those segments, (ii) current flows through those segments, the timing of voltage events on those segments, and (iii) the criticality of those two nets to the overall circuit performance.
In a specific algorithm, when a spacing of a segment A of a net B is a distance V (e.g., microns) away from a segment C of another net D, the width of A will be X. However, when the spacing is Y, which is different from X, the width of A will be Z, which is different from X.
Variable Spacing
To reduce space utilization, automatic routers typically use minimum spacing when routing nets and tracks. However, in an embodiment of the invention, a technique varies the spacing between nets or segments when they are being automatically routed. The spacing between nets or tracks may be increased or decreased. For example, the spacing between two tracks may be increased to a spacing greater than a minimum spacing permitted by the design rules. Alternatively, the spacing between two tracks may already be greater than the minimum. Then the technique will reduce the spacing between the two tracks in order to reduce the amount of space used. Further, a technique may include a combination of increasing and decreasing spacing in order to meet performance constraints, while at the same time minimizing the impact on integrated circuit area.
The technique of the invention may be used for automatic routing of analog circuits or digital circuits. Analog circuits have signal lines carrying analog signals (e.g., AC signal, sine wave). Digital circuits have signal lines carrying varying signals. These varying signals may be pulses, steps, or other dynamically changing signals. For a digital circuit, example of a varying signal which would be important to consider (e.g., relatively large dynamic current) include charging a relatively large capacitive load and power line bounce.
It is generally desirable to reduce coupling or other interactions between nets carrying varying signals and other nets of analog and digital circuits. Some varying signals can affect each other through crosstalk. Crosstalk may affect the timing of the signals so performance is degraded. Crosstalk may be so severe that it may affect the logical validity at a point in time that the signal is observed. Similarly, nonvarying signals may be affected by crosstalk from varying ones and this may affect circuits observing those signals. For example, a signal line that is suppose to be at a logical 1 level may be pulled to a logical 0 level because of crosstalk from a neighboring track. Crosstalk between wires may be reduced by increasing the spacing between the wires.
The technique of the invention may control the spacing of the segments due to effects caused by the current flowing through those segments. The spacing may be varied or altered in order to improve timing, electrical performance, or to meet design rules, such as current density and electromigration, or any combination of these. By increasing the spacing between two tracks, this reduces the noise interaction between the two tracks, thus increasing noise immunity. For example, where a track is anticipated to have a large amount of dynamic current (such as an input buffer), the spacing of nearby tracks may be increased in order to reduce noise affecting the nearby tracks.
For example, the technique may include (i) spacing some tracks away from a segment in order to avoid inductive coupling, (ii) shielding a segment to minimize inductive coupling, or (iii) increasing spacing for turns (such as 90 or other angle turns) and vias in the routing to improve yield due to electromigration effects in high current nets increasing the risk of shorts where the current is forced to turn sharp corners. Automatic routing of shielding conductors is discussed in U.S. patent application Ser. No. 10/908,895, filed May 31, 2005, which is incorporated by reference.
The spacing of interconnect, segments, tracks, or nets may be varied or set separately or in combination with other techniques described in this invention. For example, a technique of the invention may include both varying the width of a net (or segment) and varying the spacing between nets (or segments). A technique of the invention may include both tapering the width of a net (or segment) and varying the spacing between nets (or segments).
The technique of the invention may alter spacing based factors including any one of (a) inductance and its effect on performance, (b) capacitance and its effect on performance, or (c) electromigration, or any combination of these.
Inductance. There is self-inductance and mutual inductance. Self-inductance reflects the energy taking by a current flowing through a wire to build a magnetic field around that wire. Voltage lags as the current varies according to V=L(di/dt), where V is voltage, L is inductance, and di/dt is the varying current. There is a back electromotive force (EMF) due to the change current flow, and this means that the voltage takes time to build after the current changes.
When an “inductor” component is added to circuit then this is adding self-inductance to the signal in which it is placed, and it is the energy flowing between the magnetic field of the inductor, the electric field of any capacitance, and the energy losses due to any resistance that give the circuit its linear analog characteristics (e.g., low pass filtering, or resonance). Mutual inductance reflects coupling between the magnetic fields of two signals, and often is an unwanted effect. It leads to cross coupling of the signals.
Hence the spacing of the wires or shielding of them, or both, could be driven either by the amount of current flowing in the wire or the sensitivity of the receiver to variations in that current or both. This causes inductively coupled noise. The current flowing through the wire creates a magnetic field which can induce currents in other wires (and vice versa).
In an embodiment, this effect is modeled using tables or a function (e.g., formula) that states the relationship between the dynamic or AC current flow in the wire, the induced current in a neighboring wire, and the separation between them. The known current (dynamic or AC) in the track segment is used as a term into a formula or in a table lookup to model the inductance between two tracks, and hence the induced current in the second track. The “victim receiver” will be modeled with a tolerance to induced or noise currents. The net is the victim while the receiver is the circuit element observing the net. The modeling may be by way of a hard limit (e.g., N microamps) or a limit computed from other operational parameters of the net or receiver (e.g., voltage on the net, current through the net or output load).
The frequency of the signal, change in current per unit time (di/dt), and voltage change, will also affect the amount of noise, and these may among the factors or variables to consider when determining spacing of interconnect. Generally greater voltage or current changes, or both, will cause more noise.
Thus, one can calculate for each potential victim what a maximum tolerable noise current would be (e.g., by looking up in a noise sensitivity table for the receivers of the net using the known parameters of net voltage, current, and output load) and from this and the current flowing in the aggressor what the desired separation or shielding, or both, between the victim and aggressor would be.
For an integrated circuit, for a given track, there will be a certain amount of picohenries of self-inductance or mutual inductance, or both. The amount of inductance will vary layer by layer. A relatively simple inductance model would give self-inductance in inductance per unit length (e.g., henries per meter). Inductance is largely independent of the size of the conductor but not of its shape. For example, a ring of conductor has more inductance than a straight line. A more sophisticated model would vary this by the surroundings of the wire, such as how far away from the wire is the nearest conductor that acts as a ground plane.
Mutual inductance is similar but has terms in the separation of the wires and also their distance from the ground plane. If the wires are close and the ground plane is far away then the coupling will be higher. As for the self-inductance case, this would be modeled as henries per meter of coupling length.
Capacitance. The voltage of one net can cause an additional voltage on another net through capacitive coupling. Generally, the smaller the distance is between two conductors, the greater the capacitive coupling. In order to improve performance, it is generally desirable to reduce capacitive coupling between nets.
One can model the capacitance between the aggressor and victim nets using formula or table lookup, where the terms include, for example, width of the conductors, spacing between the conductors, layers of the conductors, and so forth. Through modeling the sensitivity of the receiver-to-noise events (this time as noise voltage) or through modeling variation in the timing of pulses on the victim net due to noise events from the aggressor net (and hence the sensitivity of paths containing that net to variations in delay), a maximum allowable coupling voltage or energy can be calculated. This may then be translated into a maximum allowable capacitance between the aggressor and victim nets using the same or similar tables that are used to calculate capacitance, or inversions of these tables, or formula derived from them by fitting, or by trial-and-error iterations until the desired result is reached, or any combination of these.
The modeling of noise sensitivity can be characterized using analog simulation techniques or other analyses and can take account of input voltages, currents and waveforms, internal cell state, output loads, and other derating factors. This may involve using multidimensional table lookup with interpolation or a formula derived from, for example, a curve fitting the results of simulation.
Thus, one can calculate the required spacing between each potential victim and aggressor to meet noise or performance requirements, or both, through either reducing capacitance as separation increases or adding shielding, or both. Automatic routing of shielding conductors is discussed in U.S. patent application Ser. No. 10/908,895, filed May 31, 2005.
For both inductance and capacitance, the analyses can be performed in a “summed for all of the aggressor and all of the victim” method. Or alternatively, the analyses can be performed at a finer level of granularity, calculating the noise and spacing at each track segment or area of parallelism between the two nets.
In addition, the cumulative effects of multiple aggressors may be taken into account with additional information about the relative timing and waveforms of pulses on the aggressors. This allows the system to detect failure conditions which would be invisible if only pairs of nets are examined at any one time.
In a further embodiment, the technique of the invention changes spacing in place between wires, rather than either calculating a desired spacing a priori or ripping up and rerouting nets that are too close.
Electromigration. High currents turning corners can lead to gradual creep of metal atoms from the conductor due to the electrons colliding with the atoms and displacing them from the crystal lattice through transfer of momentum. This means that the space required around corners in a high current conductor to achieve long term performance without risk of shorts developing to nearby nets is higher than the spacing along the sides of the conductor (parallel to the direction of current flow). This can be modeled using either a formula or table where the terms include, for example, the current flow, the layer, the operational temperature, the operational voltage, and the design life. The yielded result would be the spacing required.
Similar effects can happen around vias due to the current turning a corner to enter or exit the via. Therefore, the spacing to vias could again be dependent on current flow. This spacing would be three dimensional in order to avoid interlayer shorts.
FIG. 9 shows three automatically routed tracks having a specific spacing between them. There are tracks 901, 905, and 910. These tracks may have the same width, or each may have a different width. The widths of the tracks may be altered according to one of the techniques described in this patent. Between tracks 901 and 905 is a space S1, and between tracks 905 and 910 is a space S2. Spaces S1 and S2 may be the same or different. These spacings may be based on the minimum design rules or other similar considerations.
FIG. 10 shows three tracks automatically routed with variable spacing. There are tracks 1002, 1006, and 1011. These tracks may have the same width, or each may have a different width. The widths of the tracks may be altered according to one of the techniques described in this patent. Between tracks 1002 and 1006 is a space S3, and between tracks 1006 and 1011 is a space S4.
In comparison to FIG. 9, based on factors including at least one of inductance, capacitance, or electromigration (see above), the automatic router of the invention will alter or vary the spaces S3 and S4 so that they are different than S1 and S2, respectively. The spaces S3 and S4 may be the same or different for each other. In this figure, S3 is greater than S1, and S4 is greater than S2. Alternatively, the automatic router may also reduce the spacing in certain situations.
The principles of the invention may also be applied to alter or vary spacing between tracks on different layers. For example, FIG. 11 shows four tracks, two on each layer, where two upper layer tracks are on top of two lower layer tracks. Two upper layer tracks are 1103 and 1106. Two lower layer tracks are 1109 and 1114. These tracks are shown for illustration purposes as not being exactly the same width and length. However, in a particular implementation, the upper tracks may be the same or different width than the lower tracks.
FIG. 12 shows an automatic routing of four tracks, two on each layer, where the spacing between the tracks of the different layers has been altered. The widths of these tracks may be altered according to one of the techniques described in this patent. In comparison to FIG. 11, based on factors including at least one of inductance, capacitance, or electromigration (see above), the automatic router of the invention will alter or vary the spacings, so tracks 1209 and 1214 on a lower level are no longer directly below tracks 1203 and 1206 on the upper layer. This increases the spacing between these tracks on different layers. Alternatively, the automatic router may also reduce the spacing of tracks on different layers in certain situations (such as when capacitive coupling is desirable for certain tracks).
FIG. 13 shows two tracks turning a corner. Tracks 1319 and 1323 turn a 90-degree corner. In other implementations, the corner may be any angle other than 90 degrees so the track no longer continues in a straight line, such as 25 degrees, 30 degrees, 45 degrees, 60 degrees, 76 degrees, 135 degrees, curved, arced, or other type of bend or turn in the track. There is a spacing S5 and S6 between the tracks.
FIG. 14 shows an automatic routing of two tracks turning a corner where the spacing has been altered. Tracks 1419 and 1423 turn a 90-degree corner. However, as discussed above, the angle may be any angle or shape. Depending on the angle or curve, electromigration may be more or less of a problem, and the spacing will be adjusted accordingly. In comparison to FIG. 13, based on factors including at least one of inductance, capacitance, or electromigration (see above), the automatic router of the invention will alter or vary the spacings when tracks turn a corner. Here a spacing S7 is greater than S5, and a spacing S8 is greater S6. For example, by increasing the spacing, this may reduce electromigration problems.
In an embodiment of the invention, the spacing of the tracks in a vicinity of a corner or turn will be greater than in other sections of track (such as when tracks are straight and running in parallel). The vicinity of a corner may be within some distance X from the corner, where X may be, for example, 2, 3, 4, 5, 6, 7, 8, 9, 10, or other number of microns. By having greater spacing between tracks in the corners, and not in other sections when the greater than minimum spacing is not needed, this reduces the amount of integrated circuit area used.
This description of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the teaching above. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications. This description will enable others skilled in the art to best utilize and practice the invention in various embodiments and with various modifications as are suited to a particular use. The scope of the invention is defined by the following claims.

## Claims

1. A method comprising:
providing a layout of a circuit design;
providing a plurality of pins of the layout to be routed together using a net, each pin having a current value associated with it;
using at least one current value, determining a first current requirement for a first track segment of the net;
determining a first track width for a first end of the first track segment of the net based on the first current requirement; and
using at least one processor, performing an automatic routing of the net using the first track segment in the layout, wherein the automatically routed first track segment has the first track width at the first end and a second track width, different than the first track width, at a second end.

2. A method comprising:
providing a layout of a circuit design;
providing a plurality of pins of the layout to be routed together using a net, a first pin having a first value associated with it and a second pin having a second value associated with it, wherein the first value is greater than the second value; and
using at least one processor, automatically generating a first track between the first and second pins, wherein the first track has a tapered width so a first end of the first track has a width greater than a second end of the first track, and the first end is coupled to the first pin and the second end is coupled to the second pin.

3. The method of claim 2 wherein the first track has a continuously varying width from the first end to the second end.

4. The method of claim 2 wherein the first track has a plurality of portions, each portion having a different width.

5. A method comprising:
providing a plurality of pins of a layout to be routed together using a net, each pin having a pin value associated with it;
using at least one pin value, determining a first requirement for a first track segment of the net;
determining a first track width for at least a portion of the first track segment of the net based on the first requirement; and
using at least one processor, performing an automatic routing of the net using the first track segment, wherein at least a portion of the automatically routed first track segment has the first track width, and a portion of the first track segment has another track width, different from the first track width.

6. The method of claim 5 further comprising:
using at least one pin value and the first track width, determining a second requirement for a second track segment of the net;
determining a second track width for at least a portion of the second track segment of the net based on the second requirement, wherein the second track width is different from the first track width; and
performing the automatic routing of the net using the second track segment, wherein at least a portion of the automatically routed second track segment has the second track width.

7. The method of claim 1 wherein the layout is gridless.

8. The method of claim 1 wherein the layout is gridded.

9. The method of claim 1 wherein the plurality of pins comprises signal pins and the net conducts a first logical signal between the first signal pins, the first signal varies between at least a first voltage level and a second voltage level, the first voltage level represents a logic 0, and the second voltage level represents a logic 1.

10. The method of claim 2 wherein the first and second values comprise current.

11. The method of claim 2 wherein the first and second values comprise inductance.

12. The method of claim 2 the first and second values comprise capacitance.

13. The method of claim 2 the first and second values comprise an angled turn.

14. The method of claim 5 wherein the first requirement comprises a current.

15. The method of claim 5 wherein the first requirement comprises an inductance.

16. The method of claim 5 the first requirement comprises a capacitance.

17. The method of claim 5 the first requirement comprises an angled turn.

18. The method of claim 1 wherein the net comprises the first track width at the first end and the second track width at the second end.

19. The method of claim 2 wherein the net comprises the first track width at the first end and the second track width at the second end.

20. The method of claim 5 wherein the first track segment comprises the first track width and the another track width.