# Patent

## Title
Systems and methods of signal synchronization for driving light emitting diodes

## Abstract

System and method for signal synchronization. The system includes a first selection component, a first signal generator, a second signal generator and a first gate drive component. The first selection component is configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal. The first signal generator is configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal. Furthermore, the first gate drive component is configured to, if the first selection signal satisfies the one or more first conditions, receive at least the first clock signal and output a first drive signal to a first switch.

## Background
1. CROSS-REFERENCES TO RELATED APPLICATIONS
This application is a continuation of U.S. patent application Ser. No. 13/367,088, filed Feb. 6, 2012, which claims priority to Chinese Patent Application No. 201110461570.7, filed Dec. 31, 2011, both applications being commonly assigned and incorporated by reference herein for all purposes.


2. BACKGROUND OF THE INVENTION
The present invention is directed to integrated circuits. More particularly, the invention provides systems and methods for signal synchronization. Merely by way of example, the invention has been applied to light-emitting-diode (LED) drivers. But it would be recognized that the invention has a much broader range of applicability.
In LED back-lighting applications, such as TV with liquid crystal display (LCD), multiple LED drivers often are used to drive multiple LED strings. However, the LED drivers usually have different switching frequencies from each other, which may result in audio noises and/or screen flickers. Hence, synchronization of the LED drivers often is needed to reduce audio noises and/or screen flickers.
LED drivers with lower switching frequencies usually are synchronized with LED drivers with higher switching frequencies. But this scheme often suffers from issues related to un-defined ramping ranges. For example, slope compensation is often needed to make a control loop stable in a continuous current mode. If multiple LED drivers operate at the same switching frequency, the magnitudes of slope compensation in different LED drivers should be the same in order to provide the same switching duty cycle and achieve system stability and LED current precision. But the accuracy of slope compensation usually depends on semiconductor-process variations and component mismatches. Hence, the slope compensation can vary significantly from integrated-circuit (IC) chip to chip. Even though components trimming can be used to reduce the effect of the semiconductor-process variations and component mismatches, such trimming usually is applicable to only fixed frequency operations with increased costs.
Hence it is highly desirable to improve the techniques of synchronizing LED drivers.
3. BRIEF SUMMARY OF THE INVENTION
The present invention is directed to integrated circuits. More particularly, the invention provides systems and methods for signal synchronization. Merely by way of example, the invention has been applied to light-emitting-diode (LED) drivers. But it would be recognized that the invention has a much broader range of applicability.
According to one embodiment, a system for signal synchronization includes a first selection component, a first signal generator, a second signal generator, and a first gate drive component. The first selection component is configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal, the first selection signal indicating a first operation mode. The first signal generator configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal, the first input signal including a first input rising edge and being associated with a first input frequency, the first clock signal including a first clock rising edge and being associated with a first clock frequency. The second signal generator configured to, if the first selection signal satisfies one or more second conditions, generate at least a second clock signal, the second clock signal including a second clock rising edge and being associated with a second clock frequency. Additionally, the first gate drive component configured to, if the first selection signal satisfies the one or more first conditions, receive at least the first clock signal and output a first drive signal to a first switch based on at least information associated with the first clock signal. Further, the first gate drive component configured to, if the first selection signal satisfies the one or more second conditions, receive at least the second clock signal and output a second drive signal to the first switch based on at least information associated with the second clock signal. In addition, the first input frequency and the first clock frequency are the same. The first input rising edge and the first clock rising edge both correspond to a first time. Moreover, the one or more second conditions are different from the one or more first conditions.
According to another embodiment, a method for signal synchronization includes receiving a mode signal, processing information associated with the mode signal, and generating a selection signal based on at least information associated with the mode signal, the selection signal indicating an operation mode. Additionally, the method includes if the selection signal satisfies one or more first conditions, receiving an input signal, processing information associated with the input signal, and generating at least a first clock signal based on at least information associated with the input signal, the input signal including a first input rising edge and being associated with a first input frequency, the first clock signal including a first clock rising edge and being associated with a first clock frequency. The method further includes receiving at least the first clock signal, processing information associated with the first clock signal, and outputting a first drive signal to a first switch based on at least information associated with the first clock signal. Moreover, the method includes, if the selection signal satisfies one or more second conditions, generating at least a second clock signal, the second clock signal including a second clock rising edge and being associated with a second clock frequency, receiving at least the second clock signal, processing information associated with the second clock signal, and outputting a second drive signal to the first switch based on at least information associated with the second clock signal. Furthermore, the first input frequency and the first clock frequency are the same, and the first input rising edge and the first clock rising edge both correspond to a first time. The one or more second conditions are different from the one or more first conditions.
Many benefits are achieved by way of the present invention over conventional techniques. For example, some embodiments of the present invention synchronize a number of LED drivers to a clock signal generated by a master LED driver or other external sources. In another example, each LED driver to generate a fixed-duty-cycle slope-compensation signal adaptively. Certain embodiments of the present invention enable the LED drivers to work at any switching frequency. As an example, no component trimming is needed for synchronizing the LED drivers.
Depending upon embodiment, one or more benefits may be achieved. These benefits and various additional objects, features and advantages of the present invention can be fully appreciated with reference to the detailed description and accompanying drawings that follow.



4. BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1(a) is a simplified diagram showing a system for synchronizing multiple LED drivers based on a clock signal generated by a master LED driver according to one embodiment of the present invention.
FIG. 1(b) is a simplified diagram showing a system for synchronizing multiple LED drivers based on an external clock signal according to another embodiment of the present invention.
FIG. 2 is a simplified diagram showing certain components of an LED driver as part of the system as shown in FIG. 1(a) or the system as shown in FIG. 1(b) according to one embodiment of the present invention.
FIG. 3 is a simplified diagram showing certain components of the selection component as part of the LED driver as shown in FIG. 2 according to one embodiment of the present invention.
FIG. 4(a) is a simplified diagram showing certain components of the slave oscillator as part of the LED driver as shown in FIG. 2 according to one embodiment of the present invention.
FIG. 4(b) is a simplified timing diagram for the slave oscillator as shown in FIG. 4(a) according to one embodiment of the present invention.
FIG. 5(a) is a simplified diagram showing certain components of the adaptive current generator as part of the slave oscillator in the LED driver as shown in FIG. 2 according to one embodiment of the present invention.
FIG. 5(b) is a simplified timing diagram for the adaptive current generator as shown in FIG. 5(a) according to one embodiment of the present invention.
FIG. 6(a) is a simplified diagram showing certain components of the slave oscillator as part of the LED driver as shown in FIG. 2 according to another embodiment of the present invention.
FIG. 6(b) is a simplified timing diagram for the slave oscillator as shown in FIG. 6(a) according to another embodiment of the present invention.



5. DETAILED DESCRIPTION OF THE INVENTION
The present invention is directed to integrated circuits. More particularly, the invention provides systems and methods for signal synchronization. Merely by way of example, the invention has been applied to light-emitting-diode (LED) drivers. But it would be recognized that the invention has a much broader range of applicability.
FIG. 1(a) is a simplified diagram showing a system for synchronizing multiple LED drivers based on a clock signal generated by a master LED driver according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
The system 100 includes multiple LED drivers 102, 1041, . . . , 104n, and LED strings 144, 1461, . . . , 146n. n is an positive integer. The LED driver 102 includes terminals 106 (e.g., MS), 108 (e.g., SYNC), 110 (e.g., GATE), 112 (e.g., CS), 114 (e.g., Fault), 116 (e.g., FB), 118 (e.g., GND), and 120 (e.g., VCC). Similarly, the LED drivers 1041, . . . , 104n include terminals 1221, . . . , 122n (e.g., MS), 1241, . . . , 124n (e.g., SYNC), 1261, . . . , 126n (e.g., GATE), 1281, . . . , 128n (e.g., CS), 1301, . . . , 130n (e.g., Fault), 1321, . . . , 132n (e.g., FB), 1341, . . . , 134n (e.g., GND), and 1361, . . . , 136n (e.g., VCC), respectively. For example, the switches 140, 1411, . . . , 141n are transistors. In another example, the switches 148, 1491, . . . , 149n are transistors.
According to one embodiment, a resistor 154 is coupled between the terminal 106 (e.g., MS) and a chip-ground 119, so the LED driver 102 is configured to operate as a master LED driver. For example, an internal clock-signal generator in the LED driver 102 generates at least a clock signal 156 with a K % duty cycle. In yet another example, the signal 156 is output through the terminal 108 (e.g., SYNC). In yet another example, the frequency of the signal 156 depends on the resistance of the resistor 154.
According to another embodiment, the terminals 1221, . . . , 122n are floating, and the LED drivers 1041, . . . , 104n each are configured to operate as a slave LED driver. For example, internal slave oscillators of the LED drivers 1041, . . . , 104n are activated, respectively. In another example, the LED drivers 1041, . . . , 104n receive the clock signal 156 at the terminals 1241, . . . , 124n (e.g., SYNC), respectively. In yet another example, in response, the LED drivers 1041, . . . , 104n generate clock signals that are with the same frequency as the signal 156 for driving the switches 1411, . . . , 141n, respectively. In yet another example, the generated clock signals are synchronized (e.g., in terms of timing) to the received signal 156.
FIG. 1(b) is a simplified diagram showing a system for synchronizing multiple LED drivers based on an external clock signal according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
The system 200 includes multiple LED drivers 2021, . . . , 202n, and LED strings 2041, . . . , 204n. n is a positive integer. The LED drivers 2021, . . . , 202n include terminals 2221, . . . , 222n (e.g., MS), 2241, . . . , 224n (e.g., SYNC), 2261, . . . , 226n (e.g., GATE), 2281, . . . , 228n (e.g., CS), 2301, . . . , 230n (e.g., Fault), 2321, . . . , 232n (e.g., FB), 2341, . . . , 234n (e.g., GND), and 2361, . . . , 236n (e.g., VCC), respectively. For example, the switches 2411, . . . , 241n are transistors. In yet another example, the switches 2491, . . . , 249n are transistors.
According to one embodiment, the terminals 2221, . . . , 222n are floating, and the LED drivers 2021, . . . , 202n are each configured to operate as a slave LED driver. For example, internal slave oscillators of the LED drivers 2021, . . . , 202n are activated. In another example, the LED drivers 2021, . . . , 202n receive an external clock signal 256 (e.g., Clock) at the terminals 2241, . . . , 224n (e.g., SYNC), respectively. In yet another example, in response, the LED drivers 2021, . . . , 202n generate clock signals that are with the same frequency as the external clock signal 256 (e.g., Clock) for driving the switches 2411, . . . , 241n, respectively. In yet another example, the generated clock signals are synchronized (e.g., in terms of timing) to the external clock signal 256.
FIG. 2 is a simplified diagram showing certain components of an LED driver as part of the system 100 or the system 200 according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
The LED driver 300 includes three terminals 302, 304 and 306, a selection component 308, a master oscillator 310, a slave oscillator 312, a gate driving component 314, and a multiplexer 316. For example, each of the LED driver 102, 1041, . . . , 104n is the same as the LED driver 300. In another example, each of the LED driver 2021, . . . , or 202n is the same as the LED driver 300.
According to one embodiment, if a resistor is coupled between the terminal 302 (e.g., MS) and a chip ground of the LED driver 300 (not shown in FIG. 2), the LED driver 300 is configured as a master LED driver. For example, the selection component 308 receives a signal 318 from the terminal 302 (e.g., MS) and generates a selection signal 320 (e.g., Config_out). In another example, the selection signal 320 is at a logic high level which indicates that the LED driver 300 is in the master mode. In yet another example, in response to the selection signal 320, the master oscillator 310 is activated and the slave oscillator 312 enters a power-down mode. In yet another example, the master oscillator 310 outputs a clock signal 322 and a slope signal 324 to the gate driving component 314 for driving LED strings. In yet another example, the slope signal 324 ramps up at a time corresponding to a rising edge of the clock signal 322. In yet another example, the slope signal 324 reduces in magnitude to a low value (e.g., 0) at a time corresponding to a falling edge of the clock signal 322.
According to another embodiment, in response to the selection signal 320 that indicates that the LED driver 300 is configured as a master LED driver, the multiplexer 316 receives the clock signal 322 and outputs a signal 326 to other LED drivers that are configured as slave LED drivers via the terminal 304 (e.g., SYNC). For example, the signal 326 serves as an external clock signal to which other slave LED drivers can be synchronized. In another example, the clock signal 322 has a same frequency as the signal 326. In yet another example, a rising edge of the clock signal 322 and a rising edge of the signal 326 appear at a same time. In yet another example, the duty cycle of the clock signal 322 is different from that of the signal 326. In yet another example, the duty cycle of the clock signal 322 is the same as that of the signal 326. In yet another example, the slope signal 324 has a same amplitude as slope signals generated by the salve LED drivers that are synchronized to the LED driver 300. In yet another example, the slope signal 324 ramps up at the same time as slope signals generated by the slave LED drivers that are synchronized to the LED driver 300. In yet another example, the slope signal 324 reduces in magnitude to a low value (e.g., 0) at the same time as the slope signals generated by the slave LED drivers that are synchronized to the LED driver 300.
If the terminal 302 (e.g., MS) is floating (e.g., not coupled to a resistor), the LED driver 300 is configured as a slave LED driver according to certain embodiments. For example, the selection signal 320 generated by the selection component 308 is at a logic low level which indicates that the LED driver 300 is in the slave mode. In another example, in response to the selection signal 320, the slave oscillator 312 is activated and the master oscillator 310 enters a power-down mode. In yet another example, the multiplexer 316 receives an external clock signal 332 and outputs a signal 334 (e.g., CLKI) to the slave oscillator 312. In yet another example, in response to the signal 334, the slave oscillator 312 outputs a clock signal 330 and a slope signal 328 to the gate driving component 314 for driving LED strings. In yet another example, the slope signal 328 ramps up at a time corresponding to a rising edge of the clock signal 330. In yet another example, the slope signal 328 reduces in magnitude to a low value (e.g., 0) at a time corresponding to a falling edge of the clock signal 330. In yet another example, the signal 334 is the same as the external clock signal 332. In yet another example, the clock signal 330 has a same frequency as the external clock signal 332. In yet another example, a rising edge of the clock signal 330 and a rising edge of the external clock signal 332 appear at a same time. In yet another example, the duty cycle of the clock signal 330 is different from that of the external clock signal 332. In yet another example, the duty cycle of the clock signal 330 is the same as that of the external clock signal 332. In yet another example, the slope signal 328 has a same amplitude as slope signals generated by other slave LED drivers that are synchronized based on the external clock signal 332 or synchronized to a master LED driver that provides the external clock signal 332. In yet another example, the slope signal 328 ramps up at the same time as slope signals generated by other slave LED drivers that are synchronized based on the external clock signal 332 or synchronized to a master LED driver that provides the external clock signal 332. In yet another example, the slope signal 328 reduces in magnitude to a low value (e.g., 0) at the same time as the slope signals generated by other slave LED drivers that are synchronized based on the external clock signal 332 or synchronized to a master LED driver that provides the external clock signal 332.
FIG. 3 is a simplified diagram showing certain components of the selection component 308 as part of the LED driver 300 according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
The selection component 308 includes a buffer amplifier 336, a comparator 338, three transistors 340, 342 and 344, a resistor 346, and a capacitor 348. For example, the transistors 340 and 342 are P-channel field-effect transistors (FETs). In another example, the transistor 344 is a N-channel FET.
According to one embodiment, if the LED driver 300 is powered up, the selection signal 320 is initialized to the logic low level. For example, if a resistor (e.g., the resistor 154 as shown in FIG. 1(a)) is coupled between the terminal 302 (e.g., MS) and the chip ground of the LED driver 300, the buffer amplifier 336 receives the signal 318 at an inverting terminal and a reference signal 350 at a non-inverting terminal. In another example, the buffer amplifier 336 outputs a signal 351 to turn on the transistor 344. In yet another example, a current 352 flows through the transistors 344 and 340. In yet another example, the current 352 is mirrored by the transistor 342, with a predetermined ratio α, to generate a current 354. In yet another example, the current 354 charges the capacitor 348 to ramp up a voltage 356 (e.g., VC) at a terminal of the capacitor 348. In yet another example, the comparator 338 receives the voltage 356 at a non-inverting terminal and the threshold voltage 358 at an inverting terminal. In yet another example, if the voltage 356 exceeds a threshold voltage 358 in magnitude, the comparator 338 changes the selection signal 320 from the logic low level to the logic high level that indicates the LED driver 300 is configured as a master LED driver.
According to another embodiment, if the terminal 302 (e.g., MS) is floating, there is no or little current flowing through the transistors 340 and 344. For example, there is no current flowing through the transistor 354 to charge the capacitor 348. In another example, if the voltage 356 (e.g., VC) is lower than the threshold voltage 358 in magnitude, the comparator 338 outputs the selection signal 320 at the logic low level that indicates the LED driver 300 is configured as a slave LED driver.
A slave LED driver often needs to provide slope compensation of a same duty cycle as a master LED driver. But as shown in FIG. 3, a slave LED driver usually receives an external clock signal 332 either from a master LED driver or other external sources. The frequency of the external clock signal 332 is often not fixed. The slope signal 328 usually needs to track the frequency of the external clock signal 332.
FIG. 4(a) is a simplified diagram showing certain components of the slave oscillator 312 as part of the LED driver 300 according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The slave oscillator 312 includes an adaptive current generator 434, a comparator 402, a D flip-flop 404, a capacitor 406, and a switch 408. For example, the switch 408 (e.g., SW1) is a transistor.
According to one embodiment, if the switch 408 is open (e.g., off), an adaptive current 410 (e.g., I) generated by the adaptive current generator 434 charges the capacitor 406 (e.g., C1) to ramp up a voltage signal 418 (e.g., Slop) at one terminal of the capacitor 406. For example, the comparator 402 receives the signal 418 at an inverting terminal and the reference voltage 412 at a non-inverting terminal, and outputs a comparison signal 414 to a terminal 422 (e.g., R) of the D flip-flop 404. In another example, if the signal 418 exceeds the reference voltage 412 in magnitude, the comparison signal 414 is output at a logic low level. In yet another example, the D flip-flop 404 is reset in response to the comparison signal 414. In yet another example, the D flip-flop 404 outputs a selection signal 416 (e.g., SEL) at a terminal 426 (e.g., QN), and in response, the switch 408 is closed (e.g., on). In yet another example, the capacitor 406 discharges through the closed switch 408, and the voltage signal 418 decreases in magnitude to a low value (e.g., 0). In yet another example, if the voltage signal 418 reduces in magnitude to be lower than the reference voltage 412 in magnitude, the comparator 402 outputs the comparison signal 414 at a logic high level. In yet another example, the D flip-flop 404 is set in response to the comparison signal 414.
According to another embodiment, the D flip-flop 404 receives a voltage signal 432 (e.g., AVDD) at a terminal 423 (e.g., D). For example, if a rising edge of an input signal 420 (e.g., SYNC) arrives at a terminal 424 of the D flip-flop 404, the D flip-flop 404 outputs, at a terminal 428 (e.g., Q), a clock signal 430 (e.g., CLK) that tracks the voltage signal 432 (e.g., AVDD). In another example, the clock signal 430 is at the logic high level, and the selection signal 416 is at the logic low level. In yet another example, in response, the switch 408 is opened (e.g., off), and the adaptive current 410 charges the capacitor 406 again. In yet another example, the clock signal 430 (e.g., CLK) has a same frequency as the input signal 420 (e.g., SYNC). In yet another example, the duty cycle of the clock signal 430 (e.g., CLK) is the same as or different from that of the input signal 420 (e.g., SYNC). In yet another example, the input signal 420 (e.g., SYNC) represents an external clock signal from a master LED driver or other external sources.
According to yet another embodiment, the adaptive current 410 can be determined based on the following equation.




  
    
      
        
          I
          self
        
        =
        
          
            100
            K
          
          ×
          
            C
            1
          
          ×
          
            V
            
              R
              ⁢
              
                
              
              ⁢
              1
            
          
          ×
          
            f
            SYNC
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          1
        
        )
      
    
  




where Iself represents the adaptive current 410, C1 represents the capacitance of the capacitor 406, and VR1 represents the reference voltage 412. Additionally, fSYNC represents the frequency of the input signal 420, and 100/K represents a ratio. As shown in Equation 1, the adaptive current 410 is proportional to the frequency of the input signal 420 in magnitude.

FIG. 4(b) is a simplified timing diagram for the slave oscillator 312 as shown in FIG. 4(a) according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform 440 represents the input signal 420 as a function of time, the waveform 442 represents the clock signal 430 as a function of time, and the waveform 444 represents the voltage signal 418 as a function of time.
Four time periods TA, TB, TC, and TD are shown in FIG. 4(b). The time period TA starts at time t0 and ends at time t1, the time period TB starts at time t1 and ends at time t2, the time period TC starts at time t2 and ends at time t3, and the time period TD starts at time t3 and ends at time t4. For example, t0≦t1≦t2≦t3≦t4.
According to one embodiment, during the time period TA, the input signal 420 (e.g., SYNC) is at a logic low level as shown by the waveform 440. For example, the clock signal 430 is at the logic low level as shown by the waveform 442. In yet another example, the voltage signal 418 has a low magnitude (e.g., 0) as shown by the waveform 444.
According to another embodiment, at the beginning of the time period TB (e.g., t1), the input signal 420 (SYNC) changes from the logic low level to the logic high level (e.g., as shown by a rising edge of the waveform 440). For example, in response, the D flip-flop 404 changes the clock signal 430 from the logic low level to the logic high level (e.g., as shown by the waveform 442), and changes the selection signal 416 from the logic high level to the logic low level. In another example, the switch 408 is open (e.g., off), and the adaptive current 410 charges the capacitor 406. In yet another example, the voltage signal 418 ramps up (e.g., as shown by the waveform 444).
According to yet another embodiment, during the time period TB, the adaptive current 410 continues to charge the capacitor 406, and the voltage signal 418 continues to increase in magnitude as shown by the waveform 444. For example, at the end of the time period TB (e.g., at t2), if the magnitude of the voltage signal 418 exceeds the reference voltage 412 (e.g., VR1), the comparator 402 changes the comparison signal 414, and the D flip-flop 404 is reset in response to the comparison signal 414. In another example, the clock signal 430 changes from the logic high level to the logic low level (e.g., as shown by the waveform 442), and the selection signal 416 changes from the logic low level to the logic high level at the end of the time period TB (e.g., at t2). In yet another example, the switch 408 is closed (e.g., on), and the capacitor 406 discharges through the closed switch 408. In yet another example, the voltage signal 418 decreases in magnitude to a low value (e.g., 0) (e.g., at t2 as shown by the waveform 444).
According to yet another embodiment, during the time period TC, the clock signal 430 remains at the logic low level (e.g., as shown by the waveform 442). For example, the voltage signal 418 has a low magnitude (e.g., 0) as shown by the waveform 444.
A next rising edge of the input signal 420 arrives at the terminal 424 (e.g., CLK) of the D flip-flop 404 at the beginning of the time period TD (e.g., at t3) as shown by the waveform 440 according to certain embodiments. For example, the clock signal 430 changes from the logic low level to the logic high level again (e.g., as shown by the waveform 442). In another example, the switch 408 is open (e.g., off), and the adaptive current 410 charges the capacitor 406 again. In yet another example, the voltage signal 418 ramps up again (e.g., as shown by the waveform 444).
FIG. 5(a) is a simplified diagram showing certain components of the adaptive current generator 434 as part of the slave oscillator 312 in the LED driver 300 according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
The adaptive current generator 434 includes a peak detector 542, an error amplifier 544, a half-frequency component 546, a switch 548, four transistors 550, 552, 554 and 556, and two capacitors 560 and 562. For example, the transistors 550, 552 and 554 are P-channel FETs. In another example, the transistor 556 is a N-channel FET.
According to one embodiment, the half-frequency component 546 receives an input signal 520 (e.g., SYNC), and generates a signal 564 (e.g., Pha). For example, the signal 564 is a 50% duty cycle square wave, and has a frequency that is half of the frequency of the input signal 520. In another example, a rising edge of the signal 564 appears at the same time as that of the input signal 520. In yet another example, if the signal 564 (e.g., Pha) is at a logic low level, the switch 548 (e.g., S0) is open (e.g., off). In yet another example, a current 566 (e.g., I1) that flows through the transistor 550 charges the capacitor 560, and the voltage signal 558 (e.g., Slop1) ramps up.
According to another embodiment, the peak detector 542 detects the voltage signal 548 right before a rising edge of the signal 564 arrives, and outputs a detection signal 568 (e.g., Vp) that represents a peak value of the voltage signal 548. For example, the detection signal 568 is stored at the capacitor 562. In another example, the error amplifier 544 receives the detection signal 568 at an inverting input terminal and a reference signal 570 (e.g., VR2) at a non-inverting input terminal, and outputs an integrated signal 572 (e.g., Vo) to drive the transistor 556. In yet another example, the integrated signal 572 affects a current 574 that flows through the transistors 552 and 556. In yet another example, the current 574 is mirrored by the transistor 550, with a predetermined ratio β, to generate the current 566 (e.g., I1). In yet another example, the integrated signal 572 affects the current 566 through a closed loop. In yet another example, the current 566 is mirrored by the transistor 554, with a predetermined ratio γ, to generate an adaptive current 510.
According to yet another embodiment, the current 566 (e.g., I1) can be determined based on the following equation.

I1=C2×VR2×fSYNC  (Equation 2)

where I1 represents the current 566, C2 represents the capacitance of the capacitor 560, VR2 represents the reference signal 570, and fSYNC represents the frequency of the input signal 520.

For example, the adaptive current 510 can be determined based on Equation 1. In another example, based on Equation 1 and Equation 2, the ratio between the size of the transistor 554 and the size of the transistor 550 can be determined using the following equation.




  
    
      
        
          
            
              (
              
                W
                ⁢
                
                  /
                
                ⁢
                L
              
              )
            
            
              M
              ⁢
              
                
              
              ⁢
              4
            
          
          
            
              (
              
                W
                ⁢
                
                  /
                
                ⁢
                L
              
              )
            
            
              M
              ⁢
              
                
              
              ⁢
              1
            
          
        
        =
        
          
            100
            K
          
          ×
          
            
              
                C
                1
              
              ⁢
              
                V
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            
              
                C
                2
              
              ⁢
              
                V
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          3
        
        )
      
    
  




where (W/L)M1 represents the size of the transistor 550, (W/L)M4 represents the size of the transistor 554, and C1 represents the capacitance of the capacitor 406. Additionally, VR1 represents the reference voltage 412, C2 represents the capacitance of the capacitor 560, VR2 represents the reference signal 570, and 100/K represents a ratio.

According to yet another embodiment, the variation of the detection signal 568 (e.g., Vp) that represents the peak value of the voltage signal 558 (e.g., Slop1) satisfies the following equation under a stable-loop condition.




  
    
      
        
          
            Δ
            ⁢
            
              
            
            ⁢
            V
            ⁢
            
              
            
            ⁢
            2
          
          
            Δ
            ⁢
            
              
            
            ⁢
            V
            ⁢
            
              
            
            ⁢
            1
          
        
        =
        
          
            
              n
              ×
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
            
            
              τ
              ×
              
                C
                2
              
              ×
              
                f
                SYNC
                2
              
            
          
          <
          1
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          4
        
        )
      
    
  




where ΔV1 represents the variation of the detection signal 568 (e.g., Vp) during a first predetermined period of time T0, ΔV2 represents the variation of the detection signal 568 (e.g., Vp) during a second predetermined period of time T1, and n represents the ratio between the size of the transistor 550 and the size of the transistor 554. In addition, gm3 represents the conductance of the transistor 556, C2 represents the capacitance of the capacitor 560, fSYNC represents the frequency of the input signal 520, and τ represents the time constant of the error amplifier 544.

For example, the time interval between the first predetermined period of time T0 and the second predetermined period of time T1 is two periods of the input signal 520. In another example, if the frequency of the input signal 520 (e.g., fSYNC) is low, the time constant of the error amplifier 544 (e.g., τ) often needs to be large to keep the detection signal 568 approximately equal to the reference signal 570 in magnitude. In yet another example, the time constant of the integrate 544 can be determined based on the following equation.




  
    
      
        τ
        >
        
          
            n
            ×
            
              g
              
                m
                ⁢
                
                  
                
                ⁢
                3
              
            
          
          
            
              C
              2
            
            ×
            
              f
              SYNC
              2
            
          
        
      
    
    
      
        (
        
          Equation
          ⁢
          
            
          
          ⁢
          5
        
        )
      
    
  




where τ represents the time constant of the error amplifier 544, n represents the ratio between the size of the transistor 550 and the size of the transistor 554, and gm3 represents the conductance of the transistor 556. In addition, C2 represents the capacitance of the capacitor 560, and fSYNC represents the frequency of the input signal 520.

FIG. 5(b) is a simplified timing diagram for the adaptive current generator 434 as shown in FIG. 5(a) according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform 590 represents the input signal 520 as a function of time, and the waveform 592 represents the voltage signal 558 as a function of time.
Three time periods TE, TF, and TG are shown in FIG. 5(b). The time period TE starts at time t5 and ends at time t6, the time period TF starts at time t6 and ends at time t7, and the time period TG starts at time t7 and ends at time t8. For example, t5≦t6≦t7≦t8.
According to one embodiment, during the time period TE, the input signal 520 is at a logic high level as shown by the waveform 590. For example, the signal 564 is at a logic low level. In another example, the switch 548 is open (e.g., off), and the current 566 charges the capacitor 560. In yet another example, the voltage signal 558 ramps up (e.g., at t5).
According to another embodiment, the input signal 520 changes from the logic high level to a logic low level at the beginning of the time period TF (e.g., at t6), and keeps at the logic low level during the time period TF (e.g., as shown by the waveform 590). For example, the frequency of the signal 564 is about half of the frequency of the input signal 520. In another example, the signal 564 keeps at the logic low level during the time period TF. In yet another example, the switch 548 remains open (e.g., off), and the current 566 continues to charge the capacitor 560. In yet another example, the voltage signal 558 continues to increase in magnitude during the time period TF (e.g., as shown by the waveform 592).
According to yet another embodiment, at the beginning of the time period TG (e.g., t7), the input signal 520 changes from the logic low level to the logic high level (e.g., as shown by a rising edge of the waveform 590). For example, the signal 564 changes from the logic low level to the logic high level, and the switch 548 is closed (e.g., on). In another example, the capacitor 560 discharges through the closed switch 548, and the voltage signal 558 decreases in magnitude from a high value (e.g., VR2) to a low value (e.g., 0) at the beginning of the time period TG (e.g., t7) as shown by the waveform 592.
According to yet another embodiment, during the time period TG, the signal 564 keeps at the logic high level, and the switch remains closed (e.g., on). For example, the magnitude of the voltage signal 558 remains at the low value (e.g., 0) as shown by the waveform 592.
If a next rising edge of the input signal 520 (SYNC) arrives (e.g., at t8 as shown by the waveform 590), the signal 564 changes from the logic high level to the logic low level, and the switch 548 is open (e.g., off) again according to certain embodiments. For example, the current 566 charges the capacitor 560 again, and the voltage signal 558 ramps up again (e.g., at t8 as shown by the waveform 592).
FIG. 6(a) is a simplified diagram showing certain components of the slave oscillator 312 as part of the LED driver 300 according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.
The slave oscillator 312 includes a slope signal generator 600 and an adaptive current generator 601. The slope signal generator 600 includes a comparator 602, a D flip-flop 604, a capacitor 606, and a switch 608. The adaptive current generator 601 includes an error amplifier 644, a half-frequency component 646, a phase generator 647, two switches 642 and 648, four transistors 650, 652, 654 and 656, and two capacitors 660 and 662.
For example, the switches 608 and 648 are transistors. In another example, the transistors 650, 652 and 654 are P-channel FETs. In yet another example, the transistor 656 is a N-channel FET. In yet another example, the comparator 602, the D flip-flop 604, the capacitor 606, and the switch 608 are the same as the comparator 402, the D flip-flop 404, the capacitor 406, and the switch 408, respectively. In yet another example, the error amplifier 644, the half-frequency component 646, the switch 648, the transistors 650, 652, 654 and 656, and the capacitors 660 and 662 are the same as the error amplifier 544, the half-frequency component 546, the switch 548, the transistors 550, 552, 554 and 556, and the capacitors 560 and 562, respectively. In yet another example, the phase generator 647 and the switch 642 are used to form the peak detector 542 (e.g., through pulse sampling).
According to one embodiment, the half-frequency component 646 receives an input signal 620 (e.g., SYNC), and generates a signal 664 (e.g., Pha). For example, the signal 664 is a 50% duty cycle square wave, and has a frequency that is half of the frequency of the input signal 620. In another example, a rising edge of the signal 664 appears at the same time as that of the input signal 620. In yet another example, the phase generator 647 receives the signal 664, and outputs a first drive signal 676 (e.g., Ph1) and a second drive signal 678 (e.g., Ph2). In yet another example, the frequency of the first drive signal 676 (e.g., Ph1) is a 50% duty cycle square wave, and has a frequency that is half of the frequency of the input signal 620 (e.g., SYNC). In yet another example, the second drive signal 678 (e.g., Ph2) is a pulse signal with a small pulse width, and has a frequency that is half of the frequency of the input signal 620 (e.g., SYNC).
According to another embodiment, if the first drive signal 676 (e.g., Ph1) is at a logic low level, the switch 648 (e.g., S0) is open (e.g., off). For example, a current 666 (e.g., I1) that flows through the transistor 650 charges the capacitor 660, and the voltage signal 658 (e.g., Slop1) ramps up. In another example, the switch 642 is closed (e.g., on) in response to the second drive signal 678 right before a rising edge of the signal 676.
According to yet another embodiment, the capacitor 662 stores a detection signal 668 (e.g., Vp) that represents a peak value of the voltage signal 648. For example, the error amplifier 644 receives the detection signal 668 at an inverting input terminal and a reference signal 670 (e.g., VR2) at a non-inverting input terminal, and outputs an integrated signal 672 (e.g., Vo) to drive the transistor 656. In another example, the integrated signal 672 affects a current 674 that flows through the transistors 652 and 656. In yet another example, the current 674 is mirrored by the transistor 650, with a predetermined ratio δ, to generate the current 666 (e.g., I1). In yet another example, the integrated signal 672 affects the current 666 through a closed loop. In yet another example, the current 666 is mirrored by the transistor 654, with a predetermined ratio ε, to generate an adaptive current 610. In yet another example, the ratio δ is the same as the ratio β. In yet another example, the ratio ε is the same as the ratio γ.
If the switch 608 is open (e.g., off), the adaptive current 610 charges the capacitor 606 (e.g., C1) to ramp up a voltage signal 618 (e.g., Slop) in magnitude according to certain embodiments. For example, the comparator 602 receives the voltage signal 618 at an inverting terminal and the reference voltage 612 at a non-inverting terminal, and outputs a comparison signal 614 to a terminal 622 (e.g., R) of the D flip-flop 604. In yet another example, if the voltage signal 618 exceeds the reference voltage 612 in magnitude, the comparison signal 614 is output at a logic low level. In yet another example, the D flip-flop 604 is reset in response to the comparison signal 614. In yet another example, the D flip-flop 604 outputs a selection signal 616 (e.g., SEL) at a terminal 626 (e.g., QN), and in response, the switch 608 is closed (e.g., on). In yet another example, the capacitor 606 discharges through the closed switch 608, and the voltage signal 618 decreases in magnitude to a low value (e.g., 0). In yet another example, if the voltage signal 618 reduces in magnitude to be lower than the reference voltage 612 in magnitude, the comparator 602 outputs the comparison signal 614 at a logic high level. In yet another example, the D flip-flop 604 is set in response to the comparison signal 614.
According to another embodiment, the D flip-flop 604 receives a voltage signal 632 (e.g., AVDD) at a terminal 623 (e.g., D). For example, if a rising edge of an input signal 620 (e.g., SYNC) arrives at a terminal 624 of the D flip-flop 604, the D flip-flop 604 outputs, at a terminal 628 (e.g., Q), a clock signal 630 (e.g., CLK) that tracks the voltage signal 632 (e.g., AVDD). In another example, the clock signal 630 is at the logic high level, and the selection signal 616 is at the logic low level. In yet another example, in response, the switch 608 is opened (e.g., off), and the adaptive current 610 charges the capacitor 606 again. In yet another example, the clock signal 630 (e.g., CLK) has a same frequency as the input signal 620 (e.g., SYNC). In yet another example, the duty cycle of the clock signal 630 (e.g., CLK) is the same as or different from that of the input signal 620 (e.g., SYNC). In yet another example, the input signal 620 (e.g., SYNC) represents an external clock signal from a master LED driver or other external sources. In yet another example, the slave oscillator 312 outputs the clock signal 630 (e.g., CLK) and the voltage signal 618 (e.g., Slop) and has a K % duty cycle.
FIG. 6(b) is a simplified timing diagram for the slave oscillator 312 as shown in FIG. 6(a) according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform 702 represents the input signal 620 as a function of time, the waveform 704 represents the first drive signal 676 as a function of time, and the waveform 706 represents the second drive signal 678 as a function of time. Additionally, the waveform 708 represents the voltage signal 658 as a function of time, the waveform 710 represents the slope signal 608 as a function of time, and the waveform 712 represents the clock signal 630 as a function of time.
Three time periods TH, TI and TJ are shown in FIG. 6(b). The time period TH starts at time t10 and ends at time t11, the time period TI starts at time t11 and ends at time t14, and the time period TJ starts at time t14 and ends at time t16. For example, the times t12 and t13 are within the time period TI. In another example, the time t15 is within the time period TJ. In yet another example, t10≦t11≦t12≦t13≦t14≦t15≦t16.
According to one embodiment, during the time period TH, the input signal 620 (e.g., SYNC) is at the logic low level (e.g., as shown by the waveform 702). For example, the first drive signal 676 (e.g., Ph1) generated by the phase generator 647 is at the logic high level (e.g., as shown by the waveform 704). In another example, the switch 648 is closed (e.g., on) in response to the first drive signal 676, and the capacitor 660 discharges through the closed switch 648. In yet another example, the voltage signal 658 (e.g., Slop1) has a low magnitude (e.g., as shown by the waveform 708). In yet another example, the second drive signal 678 (e.g., Ph2) is at the logic low level (e.g., as shown by the waveform 706), and the switch 642 is open (e.g., off). In yet another example, in response to the input signal 620 (e.g., SYNC), the clock signal 630 (e.g., CLK) generated by the D flip-flop 604 is at the logic low level (e.g., as shown by the waveform 712). In yet another example, the selection signal 616 (e.g., SEL) generated by the D flip-flop 604 is at the logic high level, and the switch 608 is closed (e.g., on). In yet another example, the voltage signal 618 (e.g., Slop) is at the logic low level (e.g., as shown by the waveform 710).
According to another embodiment, at the beginning of the time period TI (e.g., at t11), the input signal 620 (e.g., SYNC) changes from the logic low level to the logic high level (e.g., as shown by a rising edge of the waveform 702). For example, in response, the first drive signal 676 (e.g., Ph1) changes from the logic high level to the logic low level (e.g., as shown by the waveform 704). In another example, the switch 648 is open (e.g., off), and the current 666 (e.g., I1) charges the capacitor 660. In yet another example, the voltage signal 658 (e.g., Slop1) ramps up (e.g., as shown by the waveform 708). In yet another example, in response to the input signal 620 (e.g., SYNC), the clock signal 630 (e.g., CLK) changes from the logic low level to the logic high level (e.g., as shown by a rising edge of the waveform 712). In yet another example, the selection signal 616 changes to the logic low level, and the switch 608 is open (e.g., off). In yet another example, the adaptive current 610 charges the capacitor 606, and the voltage signal 618 (e.g., Slop) ramps up (e.g., as shown by the waveform 710).
According to yet another embodiment, the adaptive current 610 continues to charge the capacitor 606, and the magnitude of the voltage signal 618 (e.g., Slop) continues to increase. For example, if the magnitude of the voltage signal 618 exceeds that of the reference signal 612, the comparator 602 changes the comparison signal 614, and the D flip-flop 604 is reset in response to the comparison signal 614. In another example, the clock signal 630 changes from the logic high level to the logic low level (e.g., as shown by the waveform 712). In yet another example, the selection signal 616 changes from the logic low level to the logic high level. In yet another example, the switch 608 is closed (e.g., on), and the capacitor 606 discharges through the closed switch 608. In yet another example, the voltage signal 618 decreases in magnitude to a low value (e.g., 0 at t12) as shown by the waveform 710.
According to yet another embodiment, right before the end of the time period TI(e.g., at t13), the second drive signal 678 (e.g., Ph2) has a pulse for sampling the voltage signal 658 (e.g., as shown by the waveform 706). For example, the peak value of the voltage signal 658 (e.g., Slop1) is held at the capacitor 662 and fed into the error amplifier 644 for closed-loop control of the current 666 (e.g., I1).
According to yet another embodiment, at the beginning of the time period TJ (e.g., at t14), the input signal 620 (e.g., SYNC) changes from the logic low level to the logic high level (e.g., as shown by a rising edge of the waveform 702). For example, the first drive signal 676 (e.g., Ph1) changes from the logic low level to the logic high level (e.g., as shown by the waveform 704). In another example, the switch 648 is closed (e.g., on), and the capacitor 660 discharges through the closed switch 648. In yet another example, the voltage signal 658 (e.g., Slop1) decreases in magnitude to a low value (e.g., as shown by the waveform 708). In yet another example, in response to the input signal 620 (e.g., SYNC), the D flip-flop 604 changes the clock signal 630 (e.g., CLK) from the logic low level to the logic high level (e.g., as shown by the waveform 712). In yet another example, the selection signal 616 changes to the logic low level, and the switch 608 is open (e.g., off). In yet another example, the adaptive current 610 charges the capacitor 606 again. In yet another example, the voltage signal 618 (e.g., Slop) ramps up again (e.g., as shown by the waveform 710).
According to yet another embodiment, during the time period TJ, the first drive signal 676 (e.g., Ph1) keeps at the logic high level (e.g., as shown by the waveform 704). For example, the voltage signal 658 (e.g., Slop1) is held at the low value (e.g., as shown by the waveform 708). In another example, the adaptive current 610 charges the capacitor 606 to increase the voltage signal 618 (e.g., Slop) in magnitude. In yet another example, if the voltage signal 618 exceeds the reference signal 612 in magnitude (e.g., at t15), the comparator 602 changes the comparison signal 614, and the D flip-flop 604 is reset in response to the comparison signal 614. In yet another example, the clock signal 630 changes from the logic high level to the logic low level again (e.g., at t15) as shown by the waveform 712. In yet another example, the voltage signal 618 decreases in magnitude to the low value again (e.g., at t15) as shown by the waveform 710.
According to another embodiment, a system for signal synchronization includes a first selection component, a first signal generator, a second signal generator, and a first gate drive component. The first selection component is configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal, the first selection signal indicating a first operation mode. The first signal generator configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal, the first input signal including a first input rising edge and being associated with a first input frequency, the first clock signal including a first clock rising edge and being associated with a first clock frequency. The second signal generator configured to, if the first selection signal satisfies one or more second conditions, generate at least a second clock signal, the second clock signal including a second clock rising edge and being associated with a second clock frequency. Additionally, the first gate drive component configured to, if the first selection signal satisfies the one or more first conditions, receive at least the first clock signal and output a first drive signal to a first switch based on at least information associated with the first clock signal. Further, the first gate drive component configured to, if the first selection signal satisfies the one or more second conditions, receive at least the second clock signal and output a second drive signal to the first switch based on at least information associated with the second clock signal. In addition, the first input frequency and the first clock frequency are the same. The first input rising edge and the first clock rising edge both correspond to a first time. Moreover, the one or more second conditions are different from the one or more first conditions. For example, the system is implemented according to FIG. 1(a), FIG. 1(b), FIG. 2, FIG. 3, FIG. 4(a), FIG. 4(b), FIG. 5(a), FIG. 5(b), FIG. 6(a) and/or FIG. 6(b).
According to another embodiment, a method for signal synchronization includes receiving a mode signal, processing information associated with the mode signal, and generating a selection signal based on at least information associated with the mode signal, the selection signal indicating an operation mode. Additionally, the method includes if the selection signal satisfies one or more first conditions, receiving an input signal, processing information associated with the input signal, and generating at least a first clock signal based on at least information associated with the input signal, the input signal including a first input rising edge and being associated with a first input frequency, the first clock signal including a first clock rising edge and being associated with a first clock frequency. The method further includes receiving at least the first clock signal, processing information associated with the first clock signal, and outputting a first drive signal to a first switch based on at least information associated with the first clock signal. Moreover, the method includes, if the selection signal satisfies one or more second conditions, generating at least a second clock signal, the second clock signal including a second clock rising edge and being associated with a second clock frequency, receiving at least the second clock signal, processing information associated with the second clock signal, and outputting a second drive signal to the first switch based on at least information associated with the second clock signal. Furthermore, the first input frequency and the first clock frequency are the same, and the first input rising edge and the first clock rising edge both correspond to a first time. The one or more second conditions are different from the one or more first conditions. For example, the method is implemented according to FIG. 1(a), FIG. 1(b), FIG. 2, FIG. 3, FIG. 4(a), FIG. 4(b), FIG. 5(a), FIG. 5(b), FIG. 6(a) and/or FIG. 6(b).
For example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. In another example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. In yet another example, various embodiments and/or examples of the present invention can be combined.
Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments, but only by the scope of the appended claims.

## Claims

1. A system for signal synchronization, the system comprising:
a first signal generator configured to, in response to a first selection signal associated with a first operation mode satisfying one or more first conditions, generate a first clock signal based on at least information associated with a first input signal, the first input signal including an input rising edge and being associated with an input frequency, the first clock signal including a first clock rising edge and being associated with a first clock frequency;
a second signal generator configured to, in response to the first selection signal satisfying one or more second conditions, generate a second clock signal, the second clock signal including a second clock rising edge and being associated with a second clock frequency; and
a first gate drive component configured to,
in response to the first selection signal satisfying the one or more first conditions, output a first drive signal to a first switch based on at least information associated with the first clock signal; and
in response to the first selection signal satisfying the one or more second conditions, output a second drive signal to the first switch based on at least information associated with the second clock signal;

wherein:
the input frequency and the first clock frequency are the same;
the input rising edge and the first clock rising edge both correspond to a first time; and
the one or more second conditions are different from the one or more first conditions.

2. The system of claim 1 wherein:
the first operation mode is a slave mode in response to the first selection signal satisfying the one or more first conditions; and
the first operation mode is a master mode in response to the first selection signal satisfying the one or more second conditions.

3. The system of claim 2 wherein:
the first selection signal satisfies the one or more first conditions in response to the first selection signal being at a logic high level; and
the first selection signal satisfies the one or more second conditions in response to the first selection signal being at a logic low level.

4. The system of claim 1, and further comprising:
a selection component configured to receive a mode signal and generate a second selection signal based on at least information associated with the mode signal, the second selection signal indicating a second operation mode;
a third signal generator configured to, in response to the second selection signal satisfying one or more third conditions, receive a second input signal associated with the second clock signal and generate a third clock signal based on at least information associated with the second clock signal, the third clock signal including a third clock rising edge and being associated with a third clock frequency; and
a second gate drive component configured to, in response to the second selection signal satisfying the one or more third conditions, receive the third clock signal and output a second drive signal to a second switch based on at least information associated with the third clock signal;
wherein:
the second clock frequency and the third clock frequency are the same; and
the second clock rising edge and the third clock rising edge both correspond to a second time.

5. The system of claim 4 wherein:
the first operation mode is a master mode in response to the first selection signal satisfying the one or more second conditions; and
the second operation mode is a slave mode in response to the second selection signal satisfying the one or more third conditions.

6. The system of claim 4 wherein the one or more first conditions and the one or more third conditions are the same.

7. The system of claim 4 wherein:
the second clock signal is associated with a first duty cycle;
the third clock signal is associated with a second duty cycle; and
the first duty cycle and the second duty cycle are the same.

8. The system of claim 4 wherein:
the second clock signal is associated with a first duty cycle;
the third clock signal is associated with a second duty cycle; and
the first duty cycle and the second duty cycle are different.

9. The system of claim 1, and further comprising a multiplexing component configured to:
in response to the first selection signal satisfying the one or more first conditions, receive a second input signal and generate the first input signal based on at least information associated with the second input signal; and
in response to the first selection signal satisfying the one or more second conditions, receive the second clock signal from the second signal generator and generate an output signal based on at least information associated with the second clock signal.

10. The system of claim 9, and further comprising:
a selection component configured to receive a mode signal and generate a second selection signal based on at least information associated with the mode signal, the second selection signal indicating a second operation mode; and
a third signal generator configured to, in response to the second selection signal satisfying one or more third conditions, receive the output signal associated with the second clock signal and generate a third clock signal based on at least information associated with the second clock signal, the third clock signal including a third clock rising edge and being associated with a third clock frequency;
wherein:
the second clock frequency and the third clock frequency are the same; and
the second clock rising edge and the third clock rising edge both correspond to a second time.

11. The system of claim 1 wherein the first signal generator includes a first current generator configured to receive the first input signal and generate an adaptive current based on at least information associated with the first input signal, the adaptive current being proportional to the input frequency in magnitude.

12. The system of claim 11 wherein the first current generator includes:
a frequency-dividing component configured to receive the first input signal and generate a processed signal based on at least information associated with the first input signal;
a voltage generator configured to receive the processed signal and a first current and generate a first voltage signal based on at least information associated with the processed signal and the first current;
an error amplifier configured to receive the first voltage signal and a second voltage signal and generate an amplified signal based on at least information associated with a difference between the first voltage signal and the second voltage signal; and
a second current generator configured to receive the amplified signal and generate a second current and the adaptive current based on at least information associated with the amplified signal, each of the second current and the adaptive current being proportional to the first current in magnitude.

13. The system of claim 12 wherein the second current generator is further configured to affect the first current based on at least information associated with the amplified signal.

14. The system of claim 13 wherein the second current generator includes a current mirror circuit configured to mirror the second current, with a predetermined ratio, to generate the first current.

15. The system of claim 12 wherein the processed signal is associated with a processed frequency, the processed frequency being equal to half of the input frequency.

16. The system of claim 15 wherein the voltage generator includes a peak detector configured to detect a ramping signal and generate the first voltage signal based on at least information associated with the ramping signal, the ramping signal being associated with at least the processed signal and the first current, the first voltage signal representing a peak value of the ramping signal.

17. The system of claim 16 wherein the peak detector is further configured to detect the ramping signal at a detection time, the detection time preceding, by a delay period, a rising edge of the processed signal.

18. The system of claim 17 wherein the peak detector includes:
a detection signal generator configured to receive the processed signal and generate a detection signal based on at least information associated with the processed signal, the detection signal including a pulse corresponding to the detection time; and
a detection component configured to receive the detection signal and detect the ramping signal in response to at least the pulse.

19. The system of claim 1 wherein:
the first signal generator is further configured to, in response to the first selection signal satisfying the one or more first conditions, generate a first ramping signal based on at least information associated with the first input signal, the first ramping signal ramping up at a second time corresponding to the first clock rising edge;
the second signal generator is further configured to, in response to the first selection signal satisfying the one or more second conditions, generate a second ramping signal, the second ramping signal ramping up at a third time corresponding to the second clock rising edge; and
the first gate drive component is further configured to,
in response to the first selection signal satisfying the one or more first conditions, receive the first ramping signal and output the first drive signal based on at least information associated with the first clock signal and the first ramping signal; and
in response to the first selection signal satisfying the one or more second conditions, receive the second ramping signal and output the second drive signal based on at least information associated with the second clock signal and the second ramping signal.

20. The system of claim 1 wherein the first operation mode is a slave mode in response to a mode signal related to the first selection signal being received from a floating terminal.

21. The system of claim 1 wherein the first operation mode is a master mode in response to a mode signal related to the first selection signal being received from a resistor, the resistor including a first resistor terminal and a second resistor terminal, the first resistor terminal being biased to a predetermined voltage and the second resistor terminal being configured to output the mode signal.

22. A method for signal synchronization, the method comprising:
receiving a selection signal indicating an operation mode;
in response to the selection signal satisfying one or more first conditions,
receiving an input signal;
processing information associated with the input signal;
generating a first clock signal based on at least information associated with the input signal, the input signal including an input rising edge and being associated with an input frequency, the first clock signal including a first clock rising edge and being associated with a first clock frequency;
receiving the first clock signal;
processing information associated with the first clock signal;
outputting a first drive signal to a switch based on at least information associated with the first clock signal; and

in response to the selection signal satisfying one or more second conditions,
generating a second clock signal, the second clock signal including a second clock rising edge and being associated with a second clock frequency;
receiving the second clock signal;
processing information associated with the second clock signal; and
outputting a second drive signal to the switch based on at least information associated with the second clock signal;

wherein:
the input frequency and the first clock frequency are the same;
the input rising edge and the first clock rising edge both correspond to a time; and
the one or more second conditions are different from the one or more first conditions.