# Patent

## Title
DC-DC controller and control method thereof

## Abstract

A DC-DC controller and a control method thereof are provided. The DC-DC controller is coupled to an output stage. The output stage receives an input voltage and provides an output voltage. The DC-DC controller includes a transient boost circuit, a ramp oscillator, a combination logic circuit, a first comparator and a pulse width modulation (PWM) generator. The transient boost circuit generates an adjusting signal according to a variation of the output voltage. The combination logic circuit controls the ramp oscillator to generate a ramp signal according to the adjusting signal. The first comparator generates a first signal according to the ramp signal and an outputted feedback voltage related to the output voltage. The PWM generator generates a PWM signal according to the first signal, so as to control the operations of the output stage.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 101149170, filed on Dec. 21, 2012. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
TECHNICAL FIELD
The invention relates to a direct current (DC)-DC control technique, and more particularly, to a DC-DC controller and a control method thereof.
BACKGROUND
FIG. 1 is a schematic circuit block diagram illustrating a current DC-DC converter. The DC-DC converter 100 converts an input voltage VDD to an output voltage VOUT, and the DC-DC converter 100 includes a detection circuit 110 for detecting the output voltage VOUT, in which when the output voltage VOUT having a rapid load transient phenomenon is detected, a logic high level is outputted to a logic circuit 120. Subsequently, according to the logic high level, the logic circuit 120 forces to turn on a metal oxide semiconductor in an output stage 130 and passes through a buck circuit 140 to provide the required current for a load terminal.
The DC-DC converter 100 includes two loops, in which one of the loops is through a feedback circuit 150 while the other one loop is through the detection circuit 110. In the conventional driving method, due to the two loops being applied, the logic circuit 120 forces the output stage 130 to turn on according to the logic high level of the detection circuit 110. Such method affects the output of the feedback circuit 150 becoming less significant. Therefore, the overall method is crude and is also unable to maintain the integrity of the single loop of the feedback circuit 150. Hence, the conventional driving technique can still be improved.
SUMMARY
Accordingly, the invention is directed to a controller, a converter, a multiphase controller and a multiphase converter applying a direct current (DC)-DC technique, so as to solve the issues afore-described in the related art.
The invention provides a DC-DC controller which is coupled to an output stage. The output stage receives an input voltage and provides an output voltage. The DC-DC controller includes a transient boost circuit, a ramp oscillator, a combination logic circuit, a first comparator and a pulse width modulation (PWM) generator. The transient boost circuit generates an adjusting signal according to a variation of the output voltage. The combination logic circuit is coupled to the transient boost circuit, and controls the ramp oscillator to generate a ramp signal according to the adjusting signal. The first comparator is coupled to the combination logic circuit, and generates a first signal according to the ramp signal and an outputted feedback voltage related to the output voltage. The PWM generator is coupled to the first comparator, and generates a PWM signal to control the operation of the output stage according to the first signal.
In an embodiment of the invention, the transient boost circuit includes a compensation adjustment circuit and a second comparator. The compensation adjustment circuit receives the output voltage to generate a transient boost voltage, in which the transient boost voltage has a voltage compensation corresponding to a steady state of the output voltage. The second comparator compares the output voltage and the transient boost voltage to generate the adjusting signal. Moreover, when the transient boost voltage is higher than the output voltage, the adjusting signal has a logic high level, and when the transient boost voltage is lower than the output voltage, the adjusting signal has a logic low level.
In an embodiment of the invention, when the adjusting signal has the logic high level, the combination logic circuit maintains the ramp signal at a first predetermined level, in which the first predetermined level is lower than a level of an error signal related to the output voltage.
In an embodiment of the invention, the compensation adjustment circuit includes a first capacitor, a current source and a resistor. The first capacitor is coupled to a first input terminal of the second comparator, and is configured to maintain the transient boost voltage. The current source is coupled to the first input terminal of the second comparator, and is configured to generate a current. The resistor is coupled between the first input terminal and a second input terminal of the second comparator, and is configured to generate the voltage compensation, in which the resistance of the resistor is multiplied by the current so as to generate the voltage compensation.
In an embodiment of the invention, the transient boost circuit includes a second capacitor and a third comparator. The second capacitor is configured to maintain a transient boost voltage. The third comparator has a first input terminal coupled to the output voltage and a second input terminal coupled to the second capacitor, and has a compensation voltage source between the first input terminal and the second input terminal of the third comparator. The third comparator compares the output voltage and the transient boost voltage to generate the adjusting signal, in which when the transient boost voltage is higher than the output voltage, the adjusting signal has a logic high level, and when the transient boost voltage is lower than the output voltage, the adjusting signal has a logic low level.
The invention provides another DC-DC control method which is configured to employ an output stage to provide an output voltage after receiving an input voltage. The DC-DC control method includes the following steps: generating an adjusting signal according to a variation of the output voltage; providing a ramp signal according to the adjusting signal and an output from a ramp oscillator; generating a first signal according to the ramp signal and an outputted feedback voltage related to the output voltage; and generating a pulse width modulation (PWM) signal to control the operation of the output stage according to the first signal.
In an embodiment of the invention, the step of generating the adjusting signal according to the variation of the output voltage further includes: receiving the output voltage to generate a transient boost voltage, in which the transient boost voltage has a voltage compensation corresponding to a steady state of the output voltage; and comparing the output voltage and the transient boost voltage to generate the adjusting signal.
In an embodiment of the invention, when the transient boost voltage is higher than the output voltage, the adjusting signal has a logic high level, and when the transient boost voltage is lower than the output voltage, the adjusting signal has a logic low level.
In an embodiment of the invention, when the adjusting signal has the logic high level, the step of providing the ramp signal according to the adjusting signal and the output from the ramp oscillator further includes: maintaining the ramp signal at a first predetermined level, in which the first predetermined level is lower than a level of an error signal related to the output voltage.
Based on the above, in the invention, because of employing the detected transient variation of the output voltage to generate the ramp signal, the combination logic circuit provides the ramp signal according to the adjusting signal and the output of the ramp oscillator. When the adjusting signal has the logic high level, the combination logic circuit maintains the ramp signal at the first predetermined level, in which the first predetermined level is lower than the level of the error signal related to the output voltage (for instance, pulling the ramp signal rapidly to zero) and is maintained over a predetermined time. After the predetermined time, when the adjusting signal is returned to the logic low level, the ramp signal is then generated periodically. Thus, the invention is capable of enhancing the transient response and providing the current rapidly. On the other hand, the impact on the closed-loop control of the feedback circuit through the conventional open-loop method can also be avoided, and the integrity of the single-loop control can be maintained.
In order to make the aforementioned and other features and advantages of the invention comprehensible, several exemplary embodiments accompanied with figures are described in detail below.



BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic circuit block diagram illustrating a current DC-DC converter.
FIG. 2 is a schematic diagram illustrating a single-phase DC-DC converter according to an embodiment of the invention.
FIG. 3 is a schematic diagram illustrating waveforms under a constant frequency structure according to an embodiment of the invention.
FIG. 4 is a schematic diagram illustrating a transient boost circuit according to an embodiment of the invention.
FIG. 5 is a schematic diagram illustrating a waveform of a transient boost circuit according to an embodiment of the invention.
FIG. 6 is a schematic diagram illustrating a transient boost circuit according to another embodiment of the invention.
FIG. 7 is a schematic diagram illustrating waveforms under a constant on time (COT) structure according to an embodiment of the invention.
FIG. 8 is a schematic diagram illustrating a multi-phase DC-DC converter according to an embodiment of the invention.
FIG. 9 is a flowchart diagram illustrating a DC-DC control method according to an embodiment of the invention.



DESCRIPTION OF THE EMBODIMENTS
Detailed reference is made to the embodiments of the present invention and the examples of the embodiments are illustrated in the accompanying drawings. In addition, the elements/members with the same or similar numbers are used in the drawings and implementation manners to represent the same or similar parts.
FIG. 2 is a schematic diagram illustrating a single-phase direct current (DC)-DC converter according to an embodiment of the invention. Referring to FIG. 2, the single-phase DC-DC converter 200 includes a DC-DC controller 210, an output stage 270, a buck circuit 280, a feedback circuit 290 and an error amplifier 292. The DC-DC converter 200 is applicable to convert an input voltage VDD to an output voltage VOUT. Moreover, the DC-DC controller 210 includes a transient boost circuit 220, a combination logic circuit 230, a ramp oscillator 240, a first comparator 250 and a pulse width modulation (PWM) generator 260.
More specifically, the combination logic circuit 230 is coupled to the transient boost circuit 220 and the ramp oscillator 240. The first comparator 250 is coupled to the output of the combination logic circuit 230. The PWM generator 260 is coupled to the output of the first comparator 250. The output stage 270 is coupled to the output of the PWM generator 260. The buck circuit 280 is coupled to the output of the output stage 270.
The feedback circuit 290 includes a plurality of resistors (not shown), in which the resistors are configured to divide the output voltage VOUT and generate a feedback voltage VFB. The error amplifier 292 receives the feedback voltage VFB and a reference voltage VREF, and generates an error signal VCOMP related to the output voltage VOUT (i.e., an outputted feedback voltage).
FIG. 3 is a schematic diagram illustrating waveforms under a constant frequency structure according to an embodiment of the invention. Referring to FIG. 2 and FIG. 3 together, the transient boost circuit 220 receives the output voltage VOUT and generates an adjusting signal VADJ according to a variation of the output voltage VOUT, in which indicates a load transient phenomenon being detected when the adjusting signal VADJ has a logic high level. The combination logic circuit 230 provides a ramp signal VRAMP according to the adjusting signal VADJ and an output of the ramp oscillator 240, and the waveform of the ramp signal VRAMP may be serrated or triangular. When the adjusting signal VADJ has the logic high level, the combination logic circuit 230 maintains the ramp signal VRAMP at a first predetermined level, in which the first predetermined level is lower than a level of an error signal VCOMP related to the output voltage. For instance, the ramp signal VRAMP is pulled to zero (or is pulled to the lowest), and is maintained in a predetermined time t1. After the predetermined time t1, when the adjusting signal VADJ is returned to the logic low level, the serrated or triangular ramp signal VRAMP is then generated periodically.
Moreover, the transient boost circuit 220 includes a compensation adjustment circuit 222 and a comparator 224. The compensation adjustment circuit 222 receives the output voltage VOUT and then generates a transient boost voltage TB. The transient boost voltage TB has a compensation voltage corresponding to the output voltage VOUT. A first terminal of the comparator 224 receives the output voltage VOUT, and a second terminal of the comparator 224 receives the transient boost voltage TB. The comparator 224 compares the output voltage VOUT and the transient boost voltage TB to generate the adjusting signal VADJ.
The comparator 250 generates a first signal V1 according to the ramp signal VRAMP and the error signal VCOMP related to the output voltage VOUT. When the error signal VCOMP is higher than the ramp signal VRAMP, the first signal V1 generated by the comparator 250 is a pulse having the logic high level. The PWM generator 260 generates a pulse width modulation (PWM) signal SPWM1 according to the first signal V1, in which the PWM signal SPWM1 is configured to drive the output stage 270. In view of the entire circuit, the utilization of the combination logic circuit 230 is capable of preventing the priority of the adjusting signal VADJ higher than that of the error signal VCOMP, so that the control of the DC-DC controller 210 is smoother, and may be controlled by a single-loop.
Subsequently, the output stage 270 converts the input voltage VDD to a driving signal SDRIVE according to the PWM signal SPWM1, so that the buck circuit 280 may generate the output voltage VOUT according to the driving signal SDRIVE. The output voltage VOUT may be supplied to the load driven by the direct current.
In the embodiment, the output stage may include drivers 272, 274 and N-type metal oxide semiconductor (NMOS) transistors 276, 278. The drivers 272 and 274 receive the PWM signal SPWM1 which is converted to a switching signal configured to turn on one of the NMOS transistors 276 and 278. The NMOS transistors 276 and 278 may convert the input voltage VDD to a driving signal SDRIVE according to the switching signal, in which the driving signal SDRIVE is a node voltage located between the metal oxide semiconductor transistors 276 and 278. Therefore, when the metal oxide semiconductor transistors 276 is turned on and the metal oxide semiconductor transistors 278 is turned off, the driving signal SDRIVE is equal to the input voltage VDD; and when the metal oxide semiconductor transistors 278 is turned on and the metal oxide semiconductor transistors 276 is turned off, the driving signal SDRIVE is equal to the ground voltage GND.
FIG. 4 is a schematic diagram illustrating a transient boost circuit 220 according to an embodiment of the invention. Referring to FIG. 4, the compensation adjustment circuit 222 may include a current source 202, a resistor 204 and a capacitor 206. An inputted compensation voltage VOFFSET between the output voltage VOUT and the transient boost voltage TB is determined by the resistance of the resistor 204 and the current generated by the current source 202. The resistor 204 and the capacitor 206 together form a low pass filter (LPF) to stabilize the transient boost voltage TB, so that the steady compensation voltage VOFFSET corresponding to the input voltage VDD may be utilized to correct the transient boost voltage TB. Referring to FIG. 5, the output voltage VOUT is initially maintained at a steady state when the load connected to the DC-DC converter 200 is unchanged, and the transient boost circuit 220 has the transient boost voltage TB corresponding to the compensation voltage VOFFSET of the input voltage VDD. When the output voltage VOUT drops due to the current load, the transient boost voltage TB may not respond immediately because of the LPF. Therefore, if the output voltage VOUT drops to lower than the transient boost voltage TB, the comparator 224 generates a logic high level signal to serve as the adjusting signal VADJ. Contrarily, if the output voltage VOUT becomes higher than the transient boost voltage TB, the comparator 224 generates a logic low level signal to serve as the adjusting signal VADJ. The positive pulse of the adjusting signal VADJ forces the metal oxide semiconductor transistors 276 to turn on, so as to pull up the output voltage VOUT to supply more current to the load. One of the advantages in the embodiment is that the transient boost circuit 220 has a quicker response to the current load event than to the PWM signal SPWM1, which is because the error signal VCOMP varies along with the output voltage VOUT (that has a time delay).
FIG. 6 is a schematic diagram illustrating a transient boost circuit 220 according to another embodiment of the invention. Referring to FIG. 6, the comparator 224A may execute the operation of compensation adjustment. The comparator 224A includes a compensation voltage source 208 and a capacitor 212 inside, in which the compensation voltage source 208 is usually located between the inputted output voltage VOUT and the inputted transient boost voltage TB so as to supply an inputted compensation voltage VOFFSET1, and the capacitor 212 is usually configured to stabilize the transient boost voltage TB. For the compensation voltage source 208 being executed inside the comparator 224A, the size of the input stage transistor in the comparator 224A may be fabricated to be mismatched so as to generate an input compensation. For instance, the compensation voltage may be set to 100 ̃200 mV, in which the compensation value may be determined according to the actual executed design rule.
Referring to FIG. 3 again, the dash line depicted in FIG. 3 is the waveform under the conventional structure depicted in FIG. 1, and the solid line is the waveform under the structure of the embodiment of the invention. The triangle-wave under the constant frequency structure occurs periodically, and when the adjusting signal VADJ is generated, it indicates the transient of the output voltage VOUT occurs. The combination logic circuit 230 rapidly pulls the ram signal VRAMP to zero (or pulls down to the lowest) and maintains over the predetermined time t1. Therefore, during the predetermined time t1, the solid line for the ramp signal is zero, and the error signal VCOMP is regardlessly higher than the ram signal VRAMP. The PWM signal SPWM1 generated by the PWM generator 260 depicted in FIG. 2 during such duration is capable of extending the time being at logic high level, which resulting in a quicker transient response. When the adjusting signal VADJ is returned to the logic low level, the PWM generator 260 generates the PWM waveform of the normal pulse.
Based on the above, the PWM signal SPWM2 depicted in FIG. 3 is a waveform for comparison, and the PWM signal SPWM2 is the output of the logic circuit 120 depicted in FIG. 1. The PWM signal SPWM1 of the embodiment in the invention may maintain at the logic high level over a longer duration during the transient occurs, such that the DC-DC converter 200 is capable of supplying more current to the load.
FIG. 7 is a schematic diagram illustrating waveforms under a constant on time (COT) structure according to an embodiment of the invention. Referring to FIG. 7, the waveform of the ramp signal VRAMP here is an inverted triangle as compared to the waveform depicted in FIG. 3. The DC-DC converter 200 is applied under the COT structure, so that when a load current ILOAD is increased, namely, the transient boost voltage TB occurs, the positive pulse of the adjusting signal VADJ is generated. The combination logic circuit 230 may rapidly pull the ramp signal VRAMP to the lowest of the waveform and maintains over a fixed predetermined time t1. During the duration being pulled to the lowest of the waveform, the comparator 250 may obtain that the error signal VCOMP is higher than the ramp signal VRAMP according to the comparison of the two signals, and may cause the PWM generator 260 to continuously generate the PWM signal SPWM1 with the PWM pulse. In the embodiment, as compared to the conventional PWM signal SPWM1, there is an additional PWM pulse existed during the transient period. Moreover, the on-time TON for each of the PWM pulses being at high level is fixed, and is at least separated by one of the minimum off-times, instead of directly extending the time being at logic high level (as shown in FIG. 3).
Furthermore, as compared to the conventional techniques, the PWM signal SPWM1 depicted in FIG. 7 may maintain at the logic high level over a longer duration during the transient occurs, such that the DC-DC converter 200 being applied under the COT structure is capable of supplying more current to the load.
FIG. 8 is a schematic diagram illustrating a multi-phase DC-DC converter according to an embodiment of the invention. Referring to FIG. 8, the structure and the operation of the multi-phase DC-DC converter 800 are similar to the DC-DC converter 200 depicted in FIG. 2. The DC-DC converter 800 includes a DC-DC controller 810, a plurality of output stages 872 ̃878, a buck circuit 880, a feedback circuit 890, an error amplifier 892. The DC-DC converter 800 is applicable to convert the input voltages VDD to the output voltage VOUT by the multi-phase channels, in which the output of each of the output stages is equivalent to a single-phase channel, and the outputs of the plurality of output stages form the multi-phase channels. Moreover, the DC-DC controller 810 includes a transient boost circuit 820, a combination logic circuit 830, a ramp oscillator 840, a plurality of comparators 852 ̃858 and a PWM generator 860.
The combination logic circuit 830 is coupled to the transient boost circuit 820 and the ramp oscillator 840. The comparators 852 ̃858 are coupled to the combination logic circuit 830 and the PWM generator 860. The output stages 872 ̃878 are coupled to the PWM generator 860. The buck circuit 880 is coupled to the outputs of the output stages 872 ̃878.
The feedback circuit 890 may include a plurality of resistors (not shown), the resistors are configured to divide the output voltage VOUT, and to generate the feedback voltage VFB. The error amplifier 892 receives the feedback voltage VFB and the reference voltage VREF to generate the error signal VCOMP related to the output voltage VOUT. The operating principle of the transient boost circuit 820 is the same as the transient boost circuit 220 depicted in FIG. 2, which may generate the adjusting signal VADJ according to a variation of the output voltage VOUT. The transient boost circuit 820 includes the compensation adjustment circuit 822 and the comparator 824. The compensation adjustment circuit 822 receives the output voltage VOUT, and then generates a transient boost voltage TB, in which such voltage has a compensation voltage corresponding to the output voltage VOUT. The comparator 824 receives the output voltage VOUT at a first terminal and receives the transient boost voltage TB at a second terminal, and compares the output voltage VOUT and the transient boost voltage TB to generate the adjusting signal VADJ.
The combination logic circuit 830 provides a plurality of ramp signals VRAMP1 ̃VRAMP4 to the first terminals corresponding to the first comparators 852 ̃858 according to the adjusting signal VADJ and an output of the ramp oscillator 840. The second terminal of each of the comparators 852 ̃858 receives the error signal VCOMP related to the output voltage VOUT. Each of the comparators 852 ̃858 respectively generates the first signal (i.e., V11 ̃V14) according to the error signal VCOMP related to the output voltage VOUT and one of the corresponding ramp signals VRAMP1 ̃VRAMP4. The PWM generator 860 generates a plurality of PWM signals SPWM11 ̃SPWM14 according to the first signals V11 ̃V14. The output stages 872 ̃878 convert the input voltages VDD to the driving signals SDRIvE1 ̃SDRIVE4 by the multiple channels according to the PWM signals SPWM11 ̃SPWM14. Subsequently, the buck circuit 880 outputs the energies to the load terminal according to the driving signals SDRIVE1 ̃SDRIVE4, so as to generate the full amount of the output voltage VOUT.
It is noted that four of the first comparators 852 ̃858 are employed in the embodiment of FIG. 8 and followed by generating four PWM signals SPWM11 ̃SPWM14 with the PWM phase. The multi-phase DC-DC converter in the embodiment is taken as an example for illustration purpose. The number of multi-phase may be varied such as eight phases or sixteen phases without being limited to four phases, where the number can be determined depending upon the actual design requirement, although the invention is not limited thereto.
Based on the foregoing description of the embodiments, a generic DC-DC control method may be summarized. To be specific, FIG. 9 is a flowchart diagram illustrating a DC-DC control method according to an embodiment of the invention. Referring to FIG. 2 and FIG. 9 together for being convenient to illustrate, the DC-DC control method of the embodiment may include the following steps:
As shown in step S901, generating an adjusting signal VADJ according to a variation of an output voltage VOUT.
Next, as shown in step S903, generating a ramp signal VRAMP according to the adjusting signal VADJ.
Subsequently, as shown in step S905, generating a first signal V1 according to the ramp signal VRAMP and the outputted feedback voltage related to the output voltage (such as an error signal VCOMP).
Then, as shown in step S907, generating a PWM signal SPWM1 according to the first signal V1, so as to control the operation of the output stage 270.
In addition, the method of executing step S901 may be described in detail as follows: receiving the output voltage VOUT to generate a transient boost voltage TB, in which the transient boost voltage TB has a voltage compensation corresponding to a steady state of the output voltage VOUT; and comparing the output voltage VOUT and the transient boost voltage TB to generate the adjusting signal VADJ.
In addition, when the transient boost voltage TB is higher than the output voltage VOUT, the adjusting signal VADJ has a logic high level, and when the transient boost voltage TB is lower than the output voltage VOUT, the adjusting signal VADJ has a logic low level. Furthermore, when the adjusting signal VADJ has the logic high level, the ramp signal VRAMP is capable of being maintained at a first predetermined level, in which the first predetermined level has to be lower than a level of the error signal VCOMP related to the output voltage VOUT.
In view of the foregoing, in the embodiments of the invention, because of employing the detected transient variation of the output voltage to generate the adjusting signal, the combination logic circuit provides the ramp signal according to the adjusting signal and the output of the ramp oscillator. When the adjusting signal has the logic high level, the combination logic circuit maintains the ramp signal at the first predetermined level, in which the first predetermined level is lower than the level of the error signal related to the output voltage (such as, pulling the ramp signal rapidly to zero) and is maintained over a predetermined time. After the predetermined time, when the adjusting signal is returned to the logic low level, the ramp signal is then generated periodically. Thus, the invention is capable of enhancing the transient response and providing the current rapidly. On the other hand, the impact on the closed-loop control of the feedback circuit through the conventional open-loop method can also be avoided, and the integrity of the single-loop control can be maintained.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

## Claims

1. A direct current (DC)-DC controller coupled to an output stage where the output stage receives an input voltage and provides an output voltage, the DC-DC controller comprising:
a transient boost circuit, generating an adjusting signal according to a variation of the output voltage;
a ramp oscillator;
a combination logic circuit, coupled to the transient boost circuit and the ramp oscillator, and providing a ramp signal according to the adjusting signal and an output of the ramp oscillator, wherein when the adjusting signal has a first logic level, the combination logic circuit adjusts the ramp signal so that the ramp signal is maintained at a first predetermined level for a predetermined time, wherein the first predetermined level is lower than a level of an error signal related to the output voltage;
a first comparator, coupled to the combination logic circuit, and generating a first signal according to the error signal and the ramp signal; and
a pulse width modulation (PWM) generator, coupled to the first comparator, and generating a PWM signal to control the operation of the output stage according to the first signal.

2. The DC-DC controller according to claim 1, wherein the transient boost circuit comprises:
a compensation adjustment circuit, receiving the output voltage to generate a transient boost voltage, wherein the transient boost voltage has a voltage compensation corresponding to a steady state of the output voltage; and
a second comparator, comparing the output voltage and the transient boost voltage to generate the adjusting signal.

3. The DC-DC controller according to claim 2, wherein when the transient boost voltage is higher than the output voltage, the adjusting signal has the first logic level, and when the transient boost voltage is lower than the output voltage, the adjusting signal has a second logic level.

4. The DC-DC controller according to claim 3, wherein when the adjusting signal has the second logic level, the combination logic circuit maintains the ramp signal, so that the ramp signal provided by the ramp oscillator is provided to the first comparator.

5. The DC-DC controller according to claim 2, wherein the compensation adjustment circuit comprises:
a first capacitor, coupled to a first input terminal of the second comparator, and configured to maintain the transient boost voltage;
a current source, coupled to the first input terminal of the second comparator, and configured to generate a current; and
a resistor, coupled between the first input terminal and a second input terminal of the second comparator, and configured to generate the voltage compensation.

6. The DC-DC controller according to claim 5, wherein the resistance of the resistor is multiplied by the current so as to generate the voltage compensation.

7. The DC-DC controller according to claim 1, wherein the transient boost circuit comprises:
a second capacitor, configured to maintain a transient boost voltage; and
a third comparator, having a first input terminal coupled to the output voltage and a second input terminal coupled to the second capacitor, and having a compensation voltage source between the first input terminal and the second input terminal of the third comparator, and the third comparator compares the output voltage and the transient boost voltage to generate the adjusting signal.

8. The DC-DC controller according to claim 7, wherein when the transient boost voltage is higher than the output voltage, the adjusting signal has the first logic level, and when the transient boost voltage is lower than the output voltage, the adjusting signal has a second logic level.

9. A DC-DC control method, configured to employ an output stage to provide an output voltage after receiving an input voltage, the DC-DC control method comprising:
generating an adjusting signal according to a variation of the output voltage;
providing a ramp signal according to the adjusting signal and an output of a ramp oscillator;
when the adjusting signal has a first logic level, maintaining the ramp signal at a first predetermined level for a predetermined time, wherein the first predetermined level is lower than a level of an error signal related to the output voltage;
generating a first signal according to the error signal and the ramp signal; and
generating a PWM signal to control the operation of the output stage according to the first signal.

10. The DC-DC control method according to claim 9, wherein the step of generating the adjusting signal according to the variation of the output voltage further comprises:
receiving the output voltage to generate a transient boost voltage, wherein the transient boost voltage has a voltage compensation corresponding to a steady state of the output voltage; and
comparing the output voltage and the transient boost voltage to generate the adjusting signal.

11. The DC-DC control method according to claim 10, wherein when the transient boost voltage is higher than the output voltage, the adjusting signal has the first logic level, and when the transient boost voltage is lower than the output voltage, the adjusting signal has a second logic level.

12. The DC-DC control method according to claim 11, wherein when the adjusting signal has the second logic level, the ramp signal is maintained and outputted.

13. A direct current (DC)-DC controller coupled to an output stage where the output stage receives an input voltage and provides an output voltage, the DC-DC controller comprising:
a transient boost circuit, generating an adjusting signal having a logic level according to a variation of the output voltage;
a ramp oscillator;
a combination logic circuit, coupled to the transient boost circuit and the ramp oscillator, and providing a ramp signal according to the adjusting signal and an output of the ramp oscillator, the combination logic circuit adjusting a level of the ramp signal according to the logic level of the adjusting signal, wherein when the adjusting signal has the first logic level, the combination logic circuit adjusts the ramp signal so that the ramp signal is maintained at a first predetermined level for a predetermined time, wherein the first predetermined level is lower than a level of an error signal related to the output voltage;
a first comparator, coupled to the combination logic circuit, and generating a first signal according to an error signal and the ramp signal; and
a pulse width modulation (PWM) generator, coupled to the first comparator, and generating a PWM signal to control the operation of the output stage according to the first signal.

14. The DC-DC controller according to claim 13, wherein the transient boost circuit comprises:
a compensation adjustment circuit, receiving the output voltage to generate a transient boost voltage, wherein the transient boost voltage has a voltage compensation corresponding to a steady state of the output voltage; and
a second comparator, comparing the output voltage and the transient boost voltage to generate the adjusting signal.

15. The DC-DC controller according to claim 14, wherein when the transient boost voltage is higher than the output voltage, the adjusting signal has a first logic level, and when the transient boost voltage is lower than the output voltage, the adjusting signal has a second logic level.

16. The DC-DC controller according to claim 15, wherein when the adjusting signal has the second logic level, the combination logic circuit outputs the ramp signal of the ramp oscillator.

17. A DC-DC control method, configured to employ an output stage to provide an output voltage after receiving an input voltage, the DC-DC control method comprising:
generating an adjusting signal according to a variation of the output voltage;
providing a ramp signal according to a logic level of the adjusting signal and an output of a ramp oscillator, wherein when the adjusting signal has the first logic level, the step of providing the ramp signal according to the logic level of the adjusting signal and the output of the ramp oscillator further comprises:
maintaining the ramp signal at a first predetermined level for a predetermined time, wherein the first predetermined level is lower than a level of an error signal related to the output voltage;

generating a first signal according to an error signal and the ramp signal; and
generating a PWM signal to control the operation of the output stage according to the first signal.

18. The DC-DC control method according to claim 17, wherein the step of generating the adjusting signal according to the variation of the output voltage further comprises:
receiving the output voltage to generate a transient boost voltage, wherein the transient boost voltage has a voltage compensation corresponding to a steady state of the output voltage; and
comparing the output voltage and the transient boost voltage to generate the adjusting signal.

19. The DC-DC control method according to claim 18, wherein when the transient boost voltage is higher than the output voltage, the adjusting signal has a first logic level, and when the transient boost voltage is lower than the output voltage, the adjusting signal has a second logic level.

20. The DC-DC control method according to claim 19, wherein when the adjusting signal has second logic level, the step of generating the ramp signal according to the logic level of the adjusting signal further comprises:
outputting the ramp signal.