# Patent

## Title
Pipeline A/D converter and A/D converting method

## Abstract

An A-type converter circuit compares an input voltage with multiple threshold voltages, judges which segment it belongs to, and generates first and second voltages with the input voltage segment between them. The A-type converter circuit generates third and fourth voltages by amplifying the differences between the first and the input voltages and between the second and the input voltages. A B-type converter circuit divides the range between the third and fourth voltages into multiple segments, and judges which segment includes the common voltage. Subsequently, the B-type converter circuit generates fifth and sixth voltages with the common voltage segment between them. The B-type converter circuit generates a seventh (the next stage's third voltage) and an eighth voltage by amplifying the differences between the fifth and the common voltages and between the sixth and the common voltages.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pipeline AD/converter.
2. Description of the Related Art
In order to convert an analog voltage into a digital signal, a pipeline A/D converter is employed. FIGS. 1A through 1C are block diagrams showing a configuration of a typical pipeline A/D converter and a graph showing its input/output characteristics. An A/D converter 1100 includes multiple (n stages of) unit converter circuits UC1 through UCn connected to one another in a cascade manner.
The unit converter circuits UC1 through UCn sequentially execute A/D conversion in units of m bits from the most significant bit MSB to the least significant bit LSB. FIG. 1B shows a configuration of a unit converter circuit UC. Each unit converter circuit UC includes an operational amplifier OA1, a switch circuit SW, and a sub-A/D converter SADC, and is configured to alternately and repeatedly switch its state between a sampling state φ0 and a differential amplification state φ1 in a time sharing manner in synchronization with a clock signal. When a given stage of such a unit converter circuit UC is in the sampling state φ0, the adjoining stage of such a unit converter circuit is in the differential amplification state φ1.
An input voltage Vin is input to an input terminal Pi of each stage, from the immediately upstream stage. The input voltage is configured in a range between −Vref and +Vref. In the sampling stage φ0, the sub-A/D converter SADC is configured to compare the input voltage Vin with multiple reference voltages, and to generate comparison data D1 which represents the comparison result k. With such an example, the comparison data D1 has a 6-valued, i.e., approximately 2.5-bit, redundant data structure. Thus, the input voltage Vin is sampled (quantized) as follows.

When −Vref<Vin<−5⁄8×Vref, k=−3.

When −5⁄8×Vref<Vin<−3⁄8×Vref, k=−2.

When −3⁄8×Vref<Vin<−1⁄8×Vref, k=−1.

When −1⁄8×Vref<Vin<+1⁄8×Vref, k=0.

When +1⁄8×Vref<Vin<+3⁄8×Vref, k=1.

When +3⁄8×Vref<Vin<+5⁄8×Vref, k=2.

When +5⁄8×Vref<Vin<+Vref k=3.

Furthermore, in the sampling state φ0, a switch S1 is turned on, and a switch S2 is switched to the input terminal Pi side. Moreover, the switch circuit SW selects the input voltage Vin, and applies the input voltage Vin thus selected to one terminal of each of input capacitors CS1 through CS3. As a result, a feedback capacitor Cf and the input capacitors CS1 through CS3 are each charged by the same input voltage Vin.
The next time the phase of the clock signal is switched, the state is switched to the differential amplification state φ1 in which the switch S1 is turned off, and the switch S2 is switched to the output terminal Po side of the operational amplifier OA. Furthermore, the sub-A/D converter SADC outputs the comparison result to the switch circuit SW. The switch circuit SW is configured to select one from among a set of reference voltages +Vref, −Vref, and GND, according to the comparison result, and to apply the reference voltage thus selected to one terminal of each of the input capacitors CS1 through CS3. As described above, the converted value k that represents the comparison result is switchable to any one of seven values in a range between −3 and +3. When k is positive, the switch circuit SW applies the reference voltage +Vref to each of k input capacitors CS, and applies the ground voltage GND to each of the other input capacitors CS. Conversely, when k is negative, the switch circuit SW applies the reference voltage −Vref to each of (−k) input capacitors CS, and applies the ground voltage GND to the other input capacitors. When k=0, the switch circuit SW applies the ground voltage GND to all the input capacitors C31 through CS3.
Assuming that all the capacitors Cf and CS1 through CS3 each have the same capacitance C0, the charge Q held by the inverting input terminal (−) of the operational amplifier OA is represented by the following Expression.

Q=−4C0·Vin  (1)

With the electric potential of the inverting input terminal (−) of the operational amplifier OA as vi, with the output voltage thereof as vo, and with the gain thereof as G, the following Expression holds true.

(vi−Vref)×k×C0+(vi−vo)C0=Q=−4C0·Vin  (2a)

Vo=−G·vi  (2b)

Thus, in the differential amplification state φ1, the output voltage Vout (=vo) of each unit converter circuit UC is represented by the following Expression (3).

Vout=4(Vin−k/4×Vref)/{1+(k+1)/G}  (3)

Now, assuming that G is infinite, the following Expression (3′) that represents the input/output characteristics of each unit converter circuit UC is derived.

Vout=4·(Vin−k×Vref/4)  (3′)

FIG. 1C shows the input/output characteristics of the unit converter circuit UC, which is represented by Expression (3). Each open circle represents the corresponding reference voltage used by the sub-A/D converter SADC. In the drawing, each solid circle represents the corresponding offset voltage in the x-axis direction, which is represented by the second term of the right side of Expression (3′), i.e., (k×Vref). That is to say, the unit converter circuit UC is configured to amplify the difference between the input voltage Vin and the offset voltage with a gain of 4.
The output voltage Vout is supplied as the input voltage Vin to the next-stage unit converter circuit UC. As shown in FIG. 1A, the multiple unit converter circuits UC perform a pipeline operation in synchronization with the clock signal, thereby outputting, via the respective unit converter circuits UC, the data D1, D2, and so forth, each representing the corresponding converted value k. It should be noted that the final-stage unit converter circuit UC is not required to perform the differential amplification. Thus, the final stage unit converter circuit UC may be configured as a comparator array (sub-A/D converter) alone.
RELATED ART DOCUMENTS
Patent Documents
[Patent Document 1]
Japanese Patent Application Laid Open No. 2006-54608
Non-Patent Document
[Non-Patent Document 1]
K. Sushihara and A. Matsuzawa, “A 7b 450MSPS 50 mW CMOS ADC in 0.3 mm2”, IEEE International Solid-State Circuits Conference, Digest of Technical, 2002, pp. 170-171.
[Non-Patent Document 2]
Yusuke Asada, Kei Yoshihara, Tatsuya Urano, Masaya Miyahara, and Akira Matsuzawa, “A 6-bit, 7-mA, 250-fJ, 700-MS/s Subranging ADC,” IEEE Asian Solid-state Circuits Conference (A-SSCC), Taiwan, November 2009, 5-3, pp. 141-144.
The conversion accuracy of such a conventional pipeline A/D converter 1100 as shown in FIG. 1 depends on the gain accuracy of the circuit system. Specifically, the conversion accuracy depends on the accuracy of the capacitance ratio between the capacitors Cf and Cs1 through Cs3, and the gain of the operational amplifier OA1. Description has been made above assuming that the gain G of the operational amplifier OA1 is infinite. However, in actuality, such an operational amplifier has a limited gain. In addition, in recent years, as the fine semiconductor process has been advanced, there is a tendency for the gain of such an operational amplifier to become smaller. With the resolution as N bit, and with the conversion error as 1⁄4LSB, the required gain G is on the order of the value represented by the following Expression (4).

G (dB)>6N+10  (4)

Thus, when the resolution is 10 bit, the required gain G is 70 dB or more. Furthermore, when resolution is 12 bit, the required gain G is 82 dB or more. In recent years, such an operational amplifier employing a fine CMOS device has a gain of on the order of 60 dB at most. That is to say, it is difficult for such a fine CMOS process to provide such a high gain.
Furthermore, such a conversion system requires negative feedback amplification using an operational amplifier. With such a negative feedback circuit including an operational amplifier having a high gain, such a circuit system is configured such that its accuracy is determined according to the accuracy of its capacitance ratio. However, in many cases, such a negative feedback circuit leads to undesired oscillation or otherwise an increase in the settling time, which is a great challenge for providing a high-speed A/D converter.
SUMMARY OF THE INVENTION
The present invention has been made in order to solve such a problem. Accordingly, it is an exemplary purpose of an embodiment of the present invention to provide a pipeline A/D converter without utilizing a negative feedback circuit.
An embodiment of the present invention relates to an A/D converting method for converting an analog input voltage into digital data. The operation employing this method comprises:
1) a first step in which the input voltage is compared with multiple threshold voltages, and judgment is made regarding which one from among multiple segments the input voltage belongs to;
2) a second step in which a first voltage and a second voltage are generated such that the segment to which the input voltage belongs is sandwiched between the first voltage and the second voltage;
3) a third step in which a third voltage is generated by amplifying the difference between the first voltage and the input voltage with a predetermined common voltage as a base;
4) a fourth step in which a fourth voltage is generated by amplifying the difference between the second voltage and the input voltage with the common voltage as a base;
5) a fifth step in which a region between the third voltage and the fourth voltage is divided into multiple segments, and judgment is made regarding which one from among the multiple segments the common voltage belongs to;
6) a sixth step in which a fifth voltage and a sixth voltage are generated such that the segment to which the common voltage belongs is sandwiched between the fifth voltage and the sixth voltage;
7) a seventh step in which a seventh voltage is generated by amplifying the difference between the fifth voltage and the common voltage with the common voltage as a base; and
8) an eighth step in which an eighth voltage is generated by amplifying the difference between the sixth voltage and the common voltage with the common voltage as a base. With such an operation, the fifth step through the eighth step are repeatedly executed. When the flow returns from the eighth step to the fifth step, the seventh voltage obtained in the seventh step in the previous loop is used as the third voltage in the fifth step in the subsequent loop, and the eighth voltage obtained in the eighth step in the previous loop is used as the fourth voltage in the fifth step in the subsequent loop.
Such an embodiment provides high-speed A/D conversion.
Also, in the sixth step, the fifth voltage and the sixth voltage may each be generated by interpolation of a range between the third voltage and the fourth voltage.
Also, the first voltage through the eighth voltage may each be generated as a differential signal.
Also, in the sixth step, the fifth voltage and the sixth voltage may each be generated by performing extrapolation from the third voltage and the fourth voltage.
Another embodiment of the present invention relates to a pipeline A/D converter. The A/D converter comprises an A-type converter circuit, at least one B-type converter circuit, and a comparator array, connected in series.
The A-type converter circuit comprises: a first sub-A/D converter configured to compare the input voltage with multiple threshold voltages, and to judge which one from among multiple segments the input voltage belongs to; a first amplifier circuit configured to generate a first voltage having a voltage level that is equal to or greater than the upper limit of the segment to which the input voltage belongs, to generate a third voltage by amplifying the difference between the first voltage and the input voltage with a predetermined common voltage as a base, and to output the third voltage to the B-type converter circuit arranged as a downstream stage; and a second amplifier circuit configured to generate a second voltage having a voltage level that is equal to or smaller than the lower limit of the segment to which the input voltage belongs, to generate a fourth voltage by amplifying the difference between the second voltage and the input voltage with the common voltage as a base, and to output the fourth voltage to the B-type converter circuit arranged as a downstream stage.
The B-type converter circuit comprises: a second-sub A/D converter configured to divide a range between the third voltage and the fourth voltage received from the upstream stage into multiple segments, and to judge which one from among the multiple segments the common voltage belongs to; a third amplifier circuit configured to generate a seventh voltage by amplifying the difference between the common voltage and a fifth voltage having a voltage level that is equal to or greater than the upper limit of the segment to which the common voltage belongs, and to output the seventh voltage as the third voltage to the B-type converter circuit arranged as the downstream stage; and a fourth amplifier circuit configured to generate an eighth voltage by amplifying the difference between the common voltage and a sixth voltage having a voltage level that is equal to or smaller than the lower limit of the segment to which the common voltage belongs, and to output the eighth voltage as the fourth voltage to the B-type converter circuit arranged as the downstream stage. The comparator array is configured to divide a range between the third voltage and the fourth voltage received from the B-type converter circuit arranged as the immediately upstream stage into multiple segments, and to judge which one from among multiple segments the common voltage belongs to.
Such an embodiment provides high-speed A/D conversion.
Also, the first amplifier circuit may comprise: a first capacitor array comprising multiple first capacitors arranged such that their first terminals are connected together; a first switch circuit configured to apply the input voltage to second terminals of the first capacitor array in a sampling state, and to apply, in an interpolation amplification state, a reference voltage to the second terminals of certain first capacitors from among the first capacitor array, the number of which is determined according to the judgment result obtained by the first sub-A/D converter; a first switch arranged between the first terminal of the first capacitor array and a fixed voltage terminal, and configured to be turned on in the sampling state, and to be turned off in the interpolation amplification state; and a first amplifier arranged such that the common voltage is input to its first input terminal, and its second input terminal is connected to the first terminal of the first capacitor array. Also, the second amplifier circuit may be configured in the same manner as that of the first amplifier circuit.
Also, the third amplifier circuit and the fourth amplifier circuit may be respectively configured to generate the fifth voltage and the sixth voltage by interpolating from the third voltage and the fourth voltage.
Also, the third amplifier circuit may comprise: a third capacitor array comprising multiple third capacitors arranged such that their first terminals are connected together; a fourth capacitor array arranged such that their first terminals are connected together to the first terminals of the third capacitor array; a third switch circuit configured to apply the third voltage to the second terminals of the third capacitor array in a sampling state, and to apply, in an interpolation amplification state, a fixed voltage to the second terminals of certain third capacitors from among the third capacitor array, the number of which is determined according to the judgment result obtained by the second sub-A/D converter; a fourth switch circuit configured to apply the fourth voltage to the second terminals of the fourth capacitor array in the sampling state, and to apply, in the interpolation amplification state, a fixed voltage to the second terminals of the certain fourth capacitors from among the fourth capacitor array, the number of which is determined according to the judgment result obtained by the second sub-A/D converter; a third switch arranged between the fixed voltage terminal and the connected-together first terminals of the third capacitor array and the fourth capacitor array, and configured to be turned on in the sampling state, and to be turned off in the interpolation amplification state; and a third amplifier arranged such that the common voltage is input to its first input terminal, and its second input terminal is connected to the first terminals of the third capacitor array and the fourth capacitor array to which they are connected together. Also, the fourth amplifier circuit may be configured in the same manner as that of the aforementioned third amplifier circuit.
Also, the third switch circuit may be configured to apply the third voltage received from its upstream stage as the fixed voltage when the fixed voltage is to be applied to the third capacitor array in the interpolation amplification state, and the fourth switch circuit may be configured to apply the fourth voltage received from its upstream stage as the fixed voltage when the fixed voltage is to be applied to the fourth capacitor array in the interpolation amplification state, thereby canceling the offset voltage of the amplifier of the converter circuit of the upstream stage.
It should be noted that any combination of the aforementioned components or any manifestation thereof may be mutually substituted between a method, apparatus, and so forth, which are effective as an embodiment of the present invention.



BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments will now be described, by way of example only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures, in which:
FIGS. 1A through 1C are block diagrams showing a configuration of a typical pipeline A/D converter and a graph showing its input/output characteristics;
FIG. 2 is a block diagram which shows a configuration of a pipeline A/D converter according to an embodiment;
FIG. 3 is a diagram for describing the function of the A-type converter circuit;
FIG. 4 is a graph which shows the input/output characteristics of the A-type converter circuit;
FIG. 5 is a circuit diagram which shows a configuration of the A-type converter circuit;
FIG. 6 is a diagram for describing the function of the B-type converter circuit;
FIG. 7 is a graph showing the input/output characteristics of the A/D converter;
FIG. 8 is a circuit diagram which shows a configuration of the B-type converter circuit;
FIG. 9 is a circuit diagram which shows a configuration of a B-type converter circuit according to a modification;
FIG. 10 is a circuit diagram which shows a configuration of a B-type converter circuit according to a second modification;
FIGS. 11A and 11B are diagrams for describing the operation of the B-type converter circuit shown in FIG. 10;
FIGS. 12A and 12B are graphs showing the input/output characteristics of the A-type converter circuit and the B-type converter circuit employing such differential amplifiers;
FIG. 13 is a circuit diagram which shows a part of a configuration of a B-type converter circuit according to a third modification;
FIG. 14 is a diagram which shows the input/output characteristics of the B-type converter circuit shown in FIG. 13;
FIG. 15 is a circuit diagram which shows a configuration of a dynamic differential amplifier;
FIG. 16 is a waveform diagram showing the operation of the dynamic differential amplifier shown in FIG. 15;
FIG. 17 is a circuit diagram which shows a configuration of an amplifier according to a comparison technique;
FIGS. 18A and 18B are circuit diagrams showing a specific example configuration of the dynamic differential amplifier shown in FIG. 15;
FIGS. 19A and 19B are circuit diagrams each showing another specific example of the dynamic differential amplifier; and
FIG. 20 is a circuit diagram which shows a modification of the dynamic differential amplifier shown in FIG. 15.



DETAILED DESCRIPTION OF THE INVENTION
Description will be made below regarding preferred embodiments according to the present invention with reference to the drawings. The same or similar components, members, and processes are denoted by the same reference numerals, and redundant description thereof will be omitted as appropriate. The embodiments have been described for exemplary purposes only, and are by no means intended to restrict the present invention. Also, it is not necessarily essential for the present invention that all the features or a combination thereof be provided as described in the embodiments.
In the present specification, the state represented by the phrase “the member A is connected to the member B” includes a state in which the member A is indirectly connected to the member B via another member that does not affect the electric connection therebetween, in addition to a state in which the member A is physically and directly connected to the member B.
Similarly, the state represented by the phrase “the member C is provided between the member A and the member B” includes a state in which the member A is indirectly connected to the member C, or the member B is indirectly connected to the member C via another member that does not affect the electric connection therebetween, in addition to a state in which the member A is directly connected to the member C, or the member B is directly connected to the member C.
FIG. 2 is a block diagram which shows a configuration of a pipeline A/D converter 100 according to an embodiment. The A/D converter 100 is configured to convert an analog input voltage VI into a digital data DOUT. Description will be made assuming that the analog input voltage VI is configured in a range between −Vref and +Vref.
The A/D converter 100 includes an A-type converter circuit UCA and at least one or more B-type converter circuits UCB1 through UCBn, and a comparator array CA, which are connected in series. The comparator array CA configured as the final stage is configured to perform the same processing as that of a second sub-A/D converter 20 of the B-type converter circuit described later. Thus, the comparator array CA configured as the final stage may be configured as a part of the (n+1)-th stage B-type converter circuit UCBn+1. Also, the comparator array CA may be configured as a separate comparator array.
The converter circuits UCA and UCB1 through UCBn, and the comparator array CA sequentially execute A/D conversion in units of m bits from the upper most significant bit MSB up to the least significant bit LSB.
Each of the unit converter circuits UCA and UCB1 through UCBn is configured to alternately and repeatedly switch its state between a sampling state φ0 and a differential amplification state (interpolation amplification state) φ1 in a time sharing manner in synchronization with a clock signal. When a given stage of such a converter circuit is in the sampling state φ0, the adjoining stage of such a unit converter circuit is in the differential amplification state (interpolation amplification state) φ1.
[A-Type Converter Circuit]
First, description will be made regarding the A-type converter circuit UCA arranged as the first stage.
FIG. 3 is a diagram for describing the function of the A-type converter circuit UCA. The A-type converter circuit UCA is configured to receive the input voltage VI and the reference voltage set VREF (e.g., a set of the three voltages +Vref, −Vref, and GND=0 V). The A-type converter circuit UCA is configured to alternately and repeatedly switch its state between the sampling state φ0 and the differential amplification state φ1.
In the sampling state φ0, the A-type converter circuit UCA is configured to divide the range between the reference voltages −Vref and +Vref into multiple segments SEG, and to judge which segment the input voltage VI belongs to (sampling).
Specifically, the A-type converter circuit UCA is configured to compare the input voltage VI with multiple threshold voltages Vth defined at intervals ΔV (=Vref/M) between the reference voltages −Vref and +Vref, and to output conversion data D1 which represents the comparison result. The conversion data D1 is configured to represent the identification number k of the segment to which the input voltage VI belongs. FIG. 3 shows a case in which the input voltage VI belongs to the segment SEG0.
In the next stage after the phase of the clock signal is switched, the A-type converter circuit UCA enters the differential amplification state φ1. The A-type converter circuit UCA is configured to generate two intermediate voltages Vma and Vmb according to the input voltage VI.
The first intermediate voltage Vma is represented by the following Expression (5a) using a predetermined common voltage Vc and an integer parameter ka.

Vma=Vc+ka×Vref/M  (5a)

The first intermediate voltage Vma is configured as a voltage that is higher than the upper threshold voltage of the segment SEGk to which the input voltage VI belongs.
The second intermediate voltage Vmb is represented by the following Expression (5b) using an integer parameter kb.

Vmb=Vc+kb×Vref/M  (5b)

The second intermediate voltage Vmb is configured as a voltage that is lower than the lower threshold voltage of the segment SEGk to which the input voltage VI belongs. That is to say, the intermediate voltages Vma and Vmb are determined such that the segment SEGk is positioned between the intermediate voltages Vma and Vmb.
It should be noted that the intermediate voltages Vma and Vmb are preferably offset with respect to the respective threshold voltages that define the segment SEG. The offset amount is preferably set to Vref/(2M).
Next, the A-type converter circuit UCA amplifies the difference between the input voltage VI and the intermediate voltage Vma by the gain G with the common voltage Vc as the base, so as to generate a first output voltage Va. In the same way, the A-type converter circuit UCA is configured to amplify the difference between the input voltage VI and the intermediate voltage Vmb by the gain G with the common voltage Vc as the base so as to generate a second output voltage Vb. The output voltage Va and the second output voltage Vb are output via the first output terminal Poa and the second output terminal Pob, respectively.




  
    
      
        
          
            
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That is to say, it can be understood that the differential amplification processing represented by Expression (6a) or (6b) is processing in which the input voltage VI is shifted (offset) to the common voltage Vc, and the voltage difference between the intermediate voltage Vma and the input voltage VI thus offset is amplified so as to generate the voltage Va, and the voltage difference between the intermediate voltage Vmb and the input voltage VI thus offset is amplified so as to generate the voltage Vb.
FIG. 4 is a graph which shows the input/output characteristics of the A-type converter circuit UCA. For simplicity of description and ease of understanding, description will be made below assuming that the common voltage Vc is set to the ground voltage GND (=0 V).
The first output voltage Va and the second output voltage Vb are represented by the following Expressions.

Va=G×(VI−ka/M·Vref)  (7a)

Vb=G×(VI−kb/M·Vref)  (7b)

Here, ka and kb represent integer parameters determined such that the voltage range of the input voltage VI is sandwiched between the two lines Va and Vb. Expression (7a) represents a line having a slope G and x-intercept (ka/M·Vref), and Expression (7b) represents a line having a slope G and x-intercept (kb/M·Vref). The x-intercept (ka/M·Vref) will be referred to as the “first offset voltage”, and the x-intercept (kb/M·Vref) will be referred to as the “second offset voltage”, hereafter.
The values ka and kb may be determined as follows using an integer parameter α (α≧1).

Ka=(k+α)

Kb=(k−α)

As can be clearly understood with reference to FIG. 4 and Expressions (7a) and (7b), the difference between the two output voltages Va and Vb, i.e., (Vb−Va) is represented by the following Expression (8).

Vb−Va=G×(ka−kb)/M·Vref=G×2α/M·Vref  (8)

That is to say, the voltage difference (Vb−Va) is maintained at an approximately constant value regardless of the input voltage VI. For example, the values of a, M, and G, may be preferably determined such that the following Expression (8a) is satisfied, i.e., such that the relation G×2α/M=1 is satisfied.

Vb−Va=Vref  (8a)

FIG. 4 shows a case in which M=4 and G=2, and each threshold voltage Vth is represented by an open circle. For example, when judgment is made in the sampling state φ0 that the input voltage VI corresponds to k=0, i.e., that −Vref/8<VI<Vref/8 is satisfied, the output voltages Va and Vb represented by the following Expressions (9a) and (9b) are output.

Va=G×(VI−1/M·Vref)  (9a)

Vb=G×(VI−1/M·Vref)  (9b)

Here, description is being made regarding an arrangement in which the integer parameter a is set to 1.
Next, description will be made regarding a specific example configuration of the A-type converter circuit UCA.
FIG. 5 is a circuit diagram which shows a configuration of the A-type converter circuit UCA. The A-type converter circuit UCA includes a first sub-A/D converter 10, a first amplifier circuit 11a, and a second amplifier circuit 11b. 
In the sampling state φ0, the first sub-A/D converter 10 is configured to compare the input voltage VI with a set of threshold voltages Vth, to judge which one from among the multiple segments the input voltage VI belongs to, and to generate the conversion data D1 which represents the comparison result. For example, the threshold voltage set Vth may be determined such that the following Expression (10) is satisfied.

Vthj=Vref/(2M)+j×Vref/M  (10)

Here, j represents an integer ranging between −M and M.
The input voltage VI is sampled as follows by means of the first sub-A/D converter 10.

When −Vref<VI<−5⁄8×Vref, k=−3.

When −5⁄8×Vref<VI<−3⁄8×Vref, k=−2.

When −3⁄8×Vref<VI<−1⁄8×Vref, k=−1.

When −1⁄8×Vref<VI<+1⁄8×Vref, k=0.

When +1⁄8×Vref<VI<+3⁄8×Vref, k=1.

When +3⁄8×Vref<VI<+5⁄8×Vref, k=2.

When +5⁄8×Vref<VI<+Vref, k=3.

The configuration of the first sub-A/D converter 10 is not restricted in particular. Rather, various kinds of currently-available or prospectively-available techniques may preferably be employed. For example, a comparators described in the non-patent document 1 or 2, which has been proposed by the present inventor, may preferably be employed as the first sub-A/D converter 10 according to the present invention. Alternatively, an arrangement may be made in which a threshold voltage Vth is generated by dividing the reference voltages −Vref, GND, and Vref by means of resistors, and voltage comparison is performed using a comparator array.
The first amplifier circuit 11a is configured to generate a first voltage Vma having a voltage level that is equal to or greater than the upper limit of the segment to which the input voltage VI belongs, and to amplify the difference between the first voltage Vma and the input voltage VI with a predetermined common voltage Vc as the base, so as to generate a third voltage Va.
The second amplifier circuit 11b is configured to generate a second voltage Vmb having a voltage level that is equal to or smaller than the lower limit of the segment to which the input voltage VI belongs, and to amplify the difference between the second voltage Vmb and the input voltage VI with a predetermined common voltage Vc as the base, so as to generate a fourth voltage Vb. The first voltage Vma and the second voltage Vmb are respectively generated such that the segment to which the input voltage VI belongs is sandwiched between them.
The first amplifier circuit 11a includes a first switch circuit 12a, a first amplifier 14a, a first capacitor array Ca1 through CaM, and a first switch S1a. Similarly, the second amplifier circuit 11b includes a second switch circuit 12b, a second amplifier 14b, a second capacitor array Cb1 through CbM, and a second switch S1b.
First, description will be made regarding the first amplifier circuit 11a. The first amplifier 14a is configured as an inverting amplifier having a gain (−G). The first amplifier 14a is arranged such that the common voltage Vc (ground voltage GND) is applied to the non-inverting input terminal thereof. When the voltage applied to the inverting input terminal of the first amplifier 14a is Vi, the output voltage Va thereof is represented by the following Expression (11).

Va=−G×Vi  (11)

The first switch S1a is arranged between the inverting input terminal of the first amplifier 14a and a fixed voltage terminal (ground terminal). In the sampling state φ0, the first switch S1a is turned on, and in the differential amplification state φ1, the first switch S1a is turned off.
One terminal (first terminal) of each of the capacitors of the first capacitor array Ca1 through CaM is connected together to the inverting input terminal of the first amplifier 14a. Description will be made assuming that the capacitances of the capacitors Ca1 through CaM are each set to the same capacitance C0.
The first switch circuit 12a is configured to receive the comparison result obtained by the first sub-A/D converter 10, i.e., the conversion data D1 which represents the value k or a control signal that corresponds to the conversion data D1. The first switch circuit 12a is configured as a switch matrix, within which multiple switches are included. The first switch circuit 12a is configured to selectively apply, according to the value k represented by the conversion data D1, one from among the input voltage VI, and the reference voltages Vref, GND and −Vref, to the other terminal (second terminal) of each of the capacitors Ca1 through CaM of the first capacitor array.
Specifically, in the sampling state φ0, the first switch circuit 12a applies the input voltage VI to the second terminals of all the capacitors Ca1 through CaM. In this state, the first switch S1a is turned on. Thus, the capacitors Ca1 through CaM are each charged by the input voltage VI. The total amount of charge Q stored in these capacitors Ca1 through CaM is represented by the following Expression (12).

Q=−M·C0·VI  (12)

In the differential amplification state φ1, the first switch circuit 12a is configured to apply the reference voltage Vref to the second terminals of j capacitors selected from among the capacitors Ca1 through CaM, and to apply the ground voltage GND to the second terminals of the other capacitors. The number j is determined by the value k. In this case, with the electric potential at the inverting input terminal of the first amplifier 14a as vi, the following Expression (13) holds true using the law of conservation of charge.

j·C0·(vi−Vref)+(M−j)·C0·vi=Q=−M·C0·VI  (13)

Expression (13) is solved for vi, thereby obtaining the following Expression (14).

vi=−(VI−j·Vref/M)  (14)

From Expressions (11) and (14), the first output voltage Va is represented by the following Expression (15).

Va=−G×vi=G×(VI−j·Vref/M)  (15)

When the first switch circuit 12a applies the reference voltage −Vref to the second terminals of j capacitors, and applies the ground voltage GND to the second terminals of the other capacitors, the first output voltage Va is represented by the following Expression (16).

Va =−G×vi=G×(VI+j·Vref/M)  (16)

That is to say, with the A-type converter circuit UCA shown in FIG. 5, such an arrangement is capable of generating the first output voltage Va so as to satisfy the aforementioned Expression (7a). In a case in which ka=k+1 in Expression (7a), the state of the first switch circuit 12a is determined as follows.
(1) When k≧0, the first switch circuit 12a applies −Vref to (k+1) capacitors, and applies the ground voltage GND to the other (M−(k+1)) capacitors.
(2) When k=−1, the first switch circuit 12a applies the ground voltage GND to all M capacitors.
(3) When k≦−2, the first switch circuit 12a applies the reference voltage Vref to (−k+1) capacitors, and applies the ground voltage GND to the other (M−(k+1)) capacitors.
With generalization such that ka=k+a, the state of the first switch circuit 12a is determined as follows.
(1) When ka≧1, the first switch circuit 12a applies −Vref to ka capacitors, and applies the ground voltage GND to the other (M−ka) capacitors.
(2) When ka=0, the first switch circuit 12a applies the ground voltage GND to all M capacitors.
(3) When ka≦−1, the first switch circuit 12a applies the reference voltage Vref to ka capacitors, and applies the ground voltage GND to the other (M−ka) capacitors.
A circuit group including the second switch circuit 12b, the second amplifier 14b, the capacitors Cb1 through CbM, and the second switch S1b, is configured to generate the second output voltage Vb in the same way as the aforementioned circuit group configured to generate the first output voltage Va, thereby generating the second output voltage Vb so as to satisfy Expression (7b).
In a case in which kb=k−1 in the Expression (7b), the state of the second switch circuit 12b is determined as follows.
(1) When k≧2, the second switch circuit 12b applies −Vref to (k−1) capacitors, and applies the ground voltage GND to the other (M−(k−1)) capacitors.
(2) When k=1, the second switch circuit 12b applies the ground voltage GND to all M capacitors.
(3) When k≦0, the second switch circuit 12b applies the reference voltage Vref to (−k+1) capacitors, and applies the ground voltage GND to the other (M−(−k+1)) capacitors.
With generalization such that kb=k−a, the state of the second switch circuit 12b is determined as follows.
(1) When kb≧1, the second switch circuit 12b applies −Vref to kb capacitors, and applies the ground voltage GND to the other (M−kb) capacitors.
(2) When kb=0, the second switch circuit 12b applies the ground voltage GND to all M capacitors.
(3) When kb≦−1, the second switch circuit 12b applies the reference voltage Vref to (−kb) capacitors, and applies the ground voltage GND to the other (M+kb) capacitors.
The above is the configuration of the A-type converter circuit UCA. In a case in which a voltage that differs from the ground voltage GND is used as the common voltage Vc, such a configuration can be made by replacing the ground terminal shown in the drawing with the common voltage terminal.
[B-Type Converter Circuit]
The B-type converter circuit UCB is configured to receive the first input voltage (third voltage) Via and the second input voltage (fourth voltage) Vib from the immediately upstream A-type converter circuit UCA or B-type converter circuit UCB. For ease of understanding, description will be made below regarding an arrangement in which an A-type converter circuit UCA is arranged as the upstream stage.
First, description will be made regarding the function of the B-type converter circuit UCB. The B-type converter circuit UCB is configured to alternately and repeatedly switch its state between the sampling state φ0 and the interpolation amplification state φ1. FIG. 6 is a diagram for describing the function of the B-type converter circuit UCB. FIG. 7 is a graph showing the input/output characteristics of the A/D converter 100.
As described above, the input voltages Via and Vib generated by the upstream-stage A-type converter circuit UCA are voltage converted such that the input voltage VI matches the common voltage Vc. Thus, in the sampling state φ0, the B-type converter circuit UCB is configured to divide the range between the two input voltages Via and Vib into multiple segments SEG1 through SEG7, and to judge which one from among the multiple segments SEG the common voltage Vc (GND) belongs to. The length of each segment SEG is set to the same voltage difference ΔV represented by the following Expression (17).

ΔV=(Vib−Via)/L  (17)

Here, L represents an integer of 2 or more. As described above, the difference between the two voltages Via (Va) and Vib (Vb) received from the upstream stage is represented by Expression (8). Thus, the segment length ΔV of each segment SEG is represented by the following Expression (18), which means that the segment length ΔV is proportional to the initial reference voltage Vref.

ΔV=G×2α/M·Vref/L  (18)

When Expression (8a) holds true, the following Expression (18a) holds true.

ΔV=Vref/L  (18a)

FIG. 6 shows an arrangement in which L=8. The B-type converter circuit UCB is configured to perform sampling (quantization) using the input voltages Via and Vib without utilizing the reference voltages Vref and −Vref received from an external circuit, which is one of the features of the B-type converter circuit UCB.
When the common voltage Vc (GND) belongs to the j-th segment SEGj, the B-type converter circuit UCB outputs the conversion data D2 which indicates the value j. FIG. 6 shows a state in which the ground voltage GND belongs to the fourth segment SEG0 (j=4).
The sampling performed by the B-type converter circuit UCB is equivalent to judgment of which segment the input voltage VI belongs to when the range between the two offset voltages (ka×Vref/M) and (kb×Vref/M) is divided into multiple segments.
When the phase of the clock signal is switched in the next stage, the B-type converter circuit UCB is switched to the interpolation amplification state φ1. In the interpolation amplification state φ1, the B-type converter circuit UCB outputs the seventh voltage (first output voltage) Voa and the eighth voltage (second output voltage) Vob, which are represented by the following Expressions (19a) and (19b), respectively.

Voa=−H×Vma 

Vma={(L−ja)·Via+ja·Vib)}/L  (19a)

Vob=−H×Vmb 

Vmb={(L−jb)·Via+Vib·Vib)}/L  (19b)

Here, ja and jb are integers determined according to the conversion value j. For example, the values ja and jb may be determined as follows using an integer parameter β (β≧1).

ja=(j−β)  (20a)

jb=(j+β)  (20b)

Specifically, an arrangement may be made in which 0=1.
The fifth voltage (which will be referred to as the “first intermediate voltage”) Vma, which appears in Expression (19a), is configured to provide internal division of the range between the two input voltages Via and Vib with a ratio of (ja:(L−ja)). On the other hand, the sixth voltage (which will be referred to as the “second intermediate voltage”) Vmb, which appears in Expression (19b), is configured to provide internal division of the range between the two input voltages Via and Vib with a ratio of (jb :(L−jb)).
The B-type converter circuit UCB is configured to determine the internal division points ja and jb such that the segment SEGj to which the common voltage Vc (GND) belongs is sandwiched between the two intermediate voltages Vma and Vmb. Furthermore, the B-type converter circuit UCB is configured to perform inverting amplification of the two intermediate voltages Vma and Vmb with a gain of −H with the common voltage Vc as the base so as to generate the output voltages Voa and Vob. FIG. 6 shows an arrangement in which H=4.
Directing attention to the difference between the two output voltages Voa and Vob, the following Expression (21) holds true based upon the Expressions (19a) and (19b).

Vob−Voa=−H×{(ja−jb)·Vai+(jb−ja)·Vbi}/L  (21)

By substituting the Expressions (20a) and (20b) into the Expression (21), the following Expression (22) is obtained.

Vob−Voa=−H×{−2β·(Vbi−Vai)}/L  (22)

By substituting the Expression (8) into the Expression (22), the following Expression (23) is obtained.

VOb−Voa=−H×{−2β·G×2α/M·Vref}/L  (23)

When the Expressions β=1, H=4, G×2α/M=1, and L=8 hold true, the Expression Vob−Voa=Vref holds true. That is to say, the input voltage range set for each downstream B-type converter circuit UCB is set to a uniform value.
The B-type converter circuits configured as the second stage and the subsequent stages are each configured to repeatedly perform the same processing. As a result, such an arrangement is capable of providing high-resolution A/D conversion by means of pipeline processing.
The above is the function of the B-type converter circuit UCB. Next, description will be made regarding the configuration of the B-type converter circuit UCB configured to provide such a function. FIG. 8 is a circuit diagram which shows a configuration of the B-type converter circuit UCB.
The B-type converter circuit UCB includes a second sub-A/D converter 20, a third amplifier circuit 21a configured to generate the seventh voltage (first output voltage) Voa, and a fourth amplifier circuit 21b configured to generate the eighth voltage (second output voltage) Vob.
In the sampling state φ0, the second sub-A/D converter 20 is configured to divide the range between the negative input voltage (fifth voltage) Via and the positive input voltage (sixth voltage) Vib into multiple segments SEG0 through SEG8, and to judge which segment SEG the common voltage Vc (GND) belongs to. The second sub-A/D converter 20 is configured to output the conversion data D2 which represents the value j when the common voltage Vc (GND) belongs to the j-th segment SEGj.
The configuration of the second sub-A/D converter 20 is not restricted in particular. Rather, various kinds of known or prospectively available techniques may preferably be employed. The second sub-A/D converter 20 may be configured to generate multiple threshold voltages Vth1 through Vth8 by dividing the voltage difference between the two input voltages Via and Vib as shown in FIG. 6, and to compare the ground voltage GND with the respective threshold voltages Vth1 through Vth8 so as to perform sampling processing. In this case, the second sub-A/D converter 20 may be configured as a comparator array. As such a second sub-A/D converter 20, a comparator described in Non-patent document 1 or 2 proposed by the present inventor may be employed.
The third amplifier circuit 21a is configured to amplify the difference between the common voltage Vc and the fifth voltage Vma having a voltage level that is equal to or greater than the upper limit of the segment to which the common voltage Vc belongs, with the common voltage Vc as the base voltage, thereby generating the seventh voltage VOa.
Similarly, the fourth amplifier circuit 21b is configured to amplify the difference between the common voltage Vc and the sixth voltage Vmb having a voltage level that is equal to or smaller than the lower limit of the segment to which the common voltage Vc belongs, with the common voltage Vc as the base voltage, thereby generating the eighth voltage VOb.
The seventh voltage VOa and the eighth voltage VOb thus generated are respectively used as the third voltage Via, and the fourth voltage Vib to be supplied to the downstream stage.
Directing attention to the third amplifier circuit 21a, description will be made regarding the configuration thereof.
The third amplifier circuit 21a includes a third switch circuit 22aa, a fourth switch circuit 22ab, a third amplifier 24a, a third capacitor array Caa1 through CaaL, a fourth capacitor array Cab1 through CabL, and a third switch S1a. The fourth amplifier circuit 21b includes a fifth switch circuit 22ba, a sixth switch circuit 22bb, a fourth amplifier 24b, a fifth capacitor array Cba1 through CbaL, a sixth capacitor array Cbb1 through CbbL, and a fourth switch S1b. The third amplifier circuit 21a and the fourth amplifier circuit 21b each have the same configuration.
The third amplifier 24a is configured as an inverting amplifier having a gain of (−H).
The third switch S1a is arranged between the inverting input terminal of the third amplifier 24a and the fixed voltage terminal (ground terminal). The third switch S1a is configured to switch on in the sampling state φ0, and to switch off in the interpolation amplification state φ1.
The capacitors Caa1 through CaaL that form the third capacitor array and the capacitors Cab1 through CabL that form the fourth capacitor array are arranged such that one terminal (first terminal) of each of the capacitors is connected together to the inverting input terminal of the third amplifier 24a. Description will be made below assuming that the capacitances of the capacitors Caa1 through CaaL and Cab1 through CabL are each set to a uniform value C0.
The third switch circuit 22aa and the fourth switch circuit 22ab are each configured to receive the sampling result obtained by the first sub-A/D converter 10, i.e., the conversion data D which represents the value j, or otherwise a control signal that corresponds to the conversion data D. The third switch circuit 22aa and the fourth switch circuit 22ab are each configured as a switch matrix including multiple switches therewithin.
In the sampling state φ0, the third switch circuit 22aa connects the other terminal (second terminal) of each of the capacitors Caa1 through CaaL that form the third capacitor array to the first input terminal Pia, and the fourth switch circuit 22ab connects the other terminal (second terminal) of each of the capacitors Cab1 through CabM that form the fourth capacitor array to the second input terminal Pib. As a result, the third capacitor array Caa is charged by the first input voltage Via, and the fourth capacitor array Cab is charged by the second input voltage Vib.
In the interpolation amplification state φ1, the third switch circuit 22aa connects the second terminal of each of (L−ja) capacitors selected from among the L capacitors Caa1 through CaaL that form the third capacitor array to the fixed voltage terminal (ground terminal), and switches the other ja capacitors to the open state or otherwise to the short-circuit state.
In the interpolation amplification state φ1, the fourth switch circuit 22ab connects the second terminal of each of ja capacitors selected from among L capacitors Cab1 through CabL that form the fourth capacitor array to the fixed voltage terminal (ground terminal PGND), and switches the other (L−ja) capacitors to the open state or otherwise to the short-circuit state. In this state, the charge amount Q at the inverting input terminal of the third amplifier 24a is represented by the following Expression (24a).

Q=−C0·Via·(L−ja)−C0·Vib·ja  (24a)

With such an arrangement, the capacitance Ctot is represented by the following Expression (25)

Ctot=L·C0  (25)

Thus, the electric potential Vma at the inverting input terminal of the third amplifier 24a is represented by the following Expression (26b), which matches Expression (19a).

Vma=Q/Ctot={(L−ja)·Via+ja·Vib}/L  (26a).

The third amplifier 24a is configured to perform inverting amplification of the electric potential Vma at the inverting input terminal with a gain (−H), and to output the amplified voltage as the first output voltage VOa via the first output terminal Poa.

Voa=(−H)×Vma  (27)

Description will be made regarding the fourth amplifier circuit 21b. In the sampling state φ0, the fifth switch circuit 22ba connects the other terminal (second terminal) of each of the capacitors Cba1 through CbaL that form the fifth capacitor array to the first input terminal Pia, and the sixth switch circuit 22bb connects the other terminal (second terminal) of each of the capacitors Cbb1 through CbbL that form the sixth capacitor array to the second input terminal Pib. As a result, the fifth capacitor array Cba is charged by the first input voltage Via, and the sixth capacitor array Cbb is charged by the second input voltage Vib.
In the interpolation amplification state φ1, the fifth switch circuit 22ba connects the second terminal of each of (L−jb) capacitors from among the L capacitors Cba1 through CbaL that form the fifth capacitor array to the fixed voltage terminal (ground terminal PGND), and switches the other jb capacitors to the open state or otherwise the short-circuit state.
In the interpolation amplification state φ1, the sixth switch circuit 22bb connects the second terminal of each of jb capacitors from among L capacitors Cbb1 through CbbL, that form the sixth capacitor array to the fixed voltage terminal (ground terminal PGND), and switches the other (L−jb) capacitors to the open state or otherwise the short-circuit state. In this state, the charge amount Q at the inverting input terminal of the fourth amplifier 24b is represented by the following Expression (24b).

Q=−C0·Via·(L−jb)−C0·Vib·jb  (24b)

Thus, the electric potential Vmb at the fourth amplifier 24b is represented by the following Expression (26b), which matches the Expression (19b).

Vmb=Q/Ctot={(L−jb)·Vib+jb·Vib}/L  (26b).

The above is the configuration of the B-type converter circuit UCB.
With the A/D converter 100 according to the embodiment, such an arrangement requires only a low gain on the order of 2 to 8 as the gain G of the A-type converter circuit UCA and the gain H of the B-type converter circuit UCB. Furthermore, unlike conventional arrangements, such an arrangement does not require severe gain accuracy. Thus, as such an amplifier, an open-loop type wideband amplifier may be employed without utilizing negative feedback. In a case in which an arrangement employing a negative feedback system is made, there is a need to give sufficient consideration to the circuit stability (occurrence of oscillation), leading to an increase in the difficulty of design, and to a problem of increased settling time. In contrast, the A/D converter 100 according to the embodiment can be configured as an open-loop system, thereby solving such a problem. Thus, such an arrangement provides a high-speed and high-precision A/D converter in a simple manner even if fine CMOS techniques are employed.
It is needless to say that, if such problems involved in employing a negative feedback circuit can be solved, a negative-feedback amplifier may be employed in the A/D converter 100 according to the embodiment.
Description will be made below regarding modifications of the A/D converter 100.
[First Modification]
FIG. 9 is a circuit diagram which shows a configuration of a B-type converter circuit according to a modification. As described above, with the A/D converter 100 according to the embodiment, as compared with conventional arrangements, such an arrangement requires only low precision of the amplifier gain. However, such an arrangement requires a certain degree of relative precision for the gain H of each of the third amplifier 24a and the fourth amplifier 24b that belong to the same converter circuit. In general, it is well known that such relative precision can be obtained using semiconductor circuit techniques (e.g., pairing of the corresponding circuit elements, etc.). In a case in which such an arrangement requires higher relative precision, the circuit shown in FIG. 9 is effectively employed.
The B-type converter circuit UCB shown in FIG. 9 further includes a gain adjustment circuit 26, in addition to the components of the B-type converter circuit UCB shown in FIG. 8. The third amplifier 24a and the fourth amplifier 24b are each configured as a variable gain amplifier. The gain adjustment circuit 26 is configured to digitally adjust the gain H of each of the third amplifier 24a and the fourth amplifier 24b, thereby reducing linearity error.
Also, a method may be effectively made in which differential amplification processing is performed while swapping the third amplifier 24a and the fourth amplifier 24b, in addition to or otherwise instead of the adjustment performed by the gain adjustment circuit 26. Input switches 28a and 28b are configured to swap the two input terminals Pia and Pib of the B-type converter circuit UCB to which the input voltages Via and Vib are to be input. Similarly, the output switches 29a and 29b are configured to swap the two output terminals Poa′ and Pob′ via which the voltages output via the output terminals Poa and Pob of the B-type converter circuit UCB are to be output.
In a case in which the gain of the third amplifier 24a is equal to the gain of the fourth amplifier 24b, the conversion characteristics are maintained at a constant value even if swapping is performed. In a case in which there is a mismatch between the gains, by making a combination with the gain adjustment circuit 26, such an arrangement provides conversion characteristics matching.
[Second Modification]
Description has been made assuming that the offset voltage of each amplifier is zero. However, in actuality, such an amplifier has a certain amount of offset voltage, which degrades the precision. Thus, such an arrangement requires a countermeasure. With a second modification, by modifying the switching operation of the amplifier, such a second modification provides a solution for solving the problem due to the offset voltage.
FIG. 10 is a circuit diagram which shows a configuration of a B-type converter circuit according to a second modification. In the arrangement shown in FIG. 8, the switch circuits 22aa, 22ab, 22ba, and 22bb are configured to apply the ground voltage GND to the capacitor array Caa, Cab, Cba, and Cbb. In contrast, in the modification shown in FIG. 10, the switch circuits 22aa, 22ab, 22ba, and 22bb are configured to apply the input voltages Via and Vib, which are received from the upstream stage, to the capacitor array Caa, Cab, Cba, and Cbb.
FIGS. 11A and 11B are diagrams for describing the operation of the B-type converter circuit shown in FIG. 10.
FIG. 11A shows the sampling state φ0, and FIG. 11B shows the interpolation state φ1.
Description will be made with reference to FIG. 11A. When the B-type converter circuit UCBi, which is a device of interest, is in the sampling state φ0, the immediately upstream stage is in the interpolation amplification state φ1. In this state, the switches S1a and S1b included in the immediately upstream stage are each off. When the third amplifier 24a (14a) and the fourth amplifier 24b (14b) of the immediately upstream stage have offset voltages Voff—a and Voff—b, respectively, the voltages Via and Vib received from the immediately upstream stage are equal to voltages obtained by superimposing the offset voltages Voff—a and Voff—b on the signal components Vsig—a and Vsig—b, respectively. In the B-type converter circuit UCBi, the capacitor arrays are charged by (Vsig—a+Voff—a) and (Vsig—b+Voff—b). Thus, the charge amount stored at the node x is represented by the following Expression (27).

Qx=−(Vsig—a+Voff—a)·C0·(L−j)−(Vsig—b+Voff—b)·C0·j  (27)

Subsequently, the B-type converter circuit UCBa of interest transits to the interpolation amplification state φ1. In this state, the converter circuit of the immediately upstream stage enters the sampling state in which the switches S1a and S1b are each turned on. In this state, the input voltages Via and Vib of the B-type converter circuit UCBi are set to the offset voltages Voff—a and Voff—b, respectively. In the interpolation amplification state φ1 shown in FIG. 11B, the following relation Expression (28) holds true. Here, Vx represents the voltage at the node x.

(Vx−Voff—a)·C0·(L−j)+(Vx+Voff—b)·C0·j=Qx=−(Vsig—a+Voff—a)·C0·(L−j)−(Vsig—b+Voff—b)·C0·j  (28)

Thus, the following Expression (29) holds true.

(−Voff—a)·C0·(L−j)+(Vx+Voff—b)·C0·j=Qx 

Vx=−{Vsig—a·(L−j)+Vsig—b·j}/L  (29)

Thus, such an arrangement is capable of removing the effects of the offset voltages Voff—a and Voff—b, thereby providing high-precision A/D conversion.
[Third Modification]
Description has been made above regarding an embodiment employing a single-ended amplifier. Also, a differential amplifier can be employed in such an arrangement, which can be clearly understood by those skilled in this art.
FIGS. 12A and 12B are graphs showing the input/output characteristics of the A-type converter circuit and the B-type converter circuit employing such differential amplifiers.
Such an arrangement employing such a differential circuit is capable of providing an inverted signal with the common voltage Vc as the center, thereby enabling an external division method (extrapolation) to be employed, in addition to an internal division method (interpolation) described in the embodiment. FIG. 13 is a circuit diagram which shows a part of a configuration of a B-type converter circuit according to a third modification. FIG. 13 shows only a third amplifier circuit 21a that corresponds to the amplifier a. FIG. 14 is a diagram which shows the input/output characteristics of the B-type converter circuit shown in FIG. 13.
With the configuration shown in FIG. 8, such an arrangement is capable of providing only lines Vin—p that are within a range between the lines Vap and Vbp indicated by the heavy lines in FIG. 14. In contrast, with such a configuration shown in FIG. 13, such an arrangement is capable of providing lines Vex—p outside of the range between the lines Vap and Vbp.
The B-type converter circuit UCB shown in FIG. 13 is configured to receive first input voltages Viap and Vian as a differential signal, and second input voltages Vibp and Vibn as a differential signal. The third amplifier circuit 21a included in the B-type converter circuit UCB includes a second sub-A/D converter 20, third switch circuits 22ap and 22an, a third amplifier 24a, a capacitor array Cap and Can, and a switch S1a.
The switch S1a is arranged between the input terminals of the third amplifier 24a. 
The capacitor array Cap includes a third capacitor array Caa1 through CaaL and a fourth capacitor array Cab1 through CabL. The capacitor array Can has a similar configuration.
The third switch circuits 22ap and 22an are each configured as a matrix switch, and are respectively configured to charge the capacitor arrays Cap and Can according to a control signal received from the second sub-A/D converter 20.
In a case in which the voltage is to be generated by means of an internal division method, in the sampling state φ0, the third switch circuit 22ap is preferably configured to apply the non-inverted input voltage Vap to the capacitor array Caa, and to apply the non-inverted input voltage Vbp to the capacitor array Cab. Furthermore, in this state, the third switch circuit 22ap is preferably configured to apply the inverted input voltage Van to the capacitor array Cba, and to apply the inverted input voltage Vbn to the capacitor array Cbb. Such an operation is equivalent to the operation performed by the configuration shown in FIG. 8 By means of such an internal division method, such an arrangement is capable of generating the voltages Vin—p and Vin—n.

Vin—p={(L−j)·Vap+j·Vbp}/L  (30p)

Vin—n={(L−j)·Van+j·Vbn}/L  (30n)

In a case in which the voltage is to be generated by means of an external division method, in the sampling state φ0, the third switch circuit 22ap may be preferably configured to apply the non-inverted input voltage Vap to the capacitor array Caa, and to apply the inverted input voltage Vbn to the capacitor array Cab.
In the interpolation amplification state φ1, (L+j) capacitors of the third capacitor array Caa are each grounded, and j capacitors of the fourth capacitor array Cab are each grounded, whereby a voltage occurs at the input terminal of the third amplifier 24a, which is represented by the following Expression (31p).

Vex—p={(L+j)·Vap+j·Vbn}/L  (31p)

Here, the relation Vbn=−Vbp holds true, and accordingly Expression (31p) can be transformed into the following Expression (31p).

Vex—p={(L+j)·Vap−j·Vbp}/L  (31p)

That is to say, the voltage Vex—p corresponds to a point obtained by performing external division of a range between the two voltages Vap and Vbp at a ratio of (j:(L+j)).
The third switch circuit 22an may be preferably configured to apply the inverted input voltage Van to the capacitor array Cba, and to apply the inverted input voltage Vbn to the capacitor array Cbb. As a result, the voltage Vex—n represented by the following Expression (31n) is obtained.

Vex—n={(L+j)·Van−j·Vbn}/L  (31n)

That is to say, the voltage Vex—n corresponds to a point obtained by performing external division of a range between the two inverted voltages Van and Vbn at a ratio of (j:(L+j)).
That is to say, with the B-type converter circuit UCB shown in FIG. 13, the voltage to be applied to the capacitor array is preferably extended so as to be capable of providing an inverted voltage (n), and the number of capacitors is preferably increased as needed. With such an arrangement employing such an external division method, such an arrangement allows the designer to further reduce the gain H of each of the third amplifier 24a and the fourth amplifier 24b. 
Description has been made in the embodiment regarding an arrangement in which the common voltage Vc is set to the ground voltage GND. However, the present invention is not restricted to such an arrangement. In a case in which it is desired to operate the circuit in a positive voltage range, the common voltage Vc may be set to the midpoint voltage Vdd/2 of the power supply voltage Vdd. Alternatively, in a case in which a reference voltage Vref is supplied, the common voltage may be set to Vref/2.
As described above, such an arrangement requires relative precision of the gain (−G) between the first amplifier 14a and the second amplifier 14b that belong to the same converter circuit. However, such an arrangement does not require absolute precision of the gain for the first amplifier 14a and the second amplifier 14b. Furthermore, such an arrangement requires only a low gain on the order of ten or less, or otherwise at most several tens, which is another advantage. The same can be said of the third amplifier 24a and the fourth amplifier 24b. Accordingly, description will be made regarding a preferable configuration of a dynamic differential amplifier having such characteristics.
FIG. 15 is a circuit diagram which shows a configuration of a dynamic differential amplifier 30. The dynamic differential amplifier 30 is configured to amplify signals Vi1 and Vi2 respectively input to the first input terminal Pi1 and the second input terminal Pi2, and to output the amplified signals as signals Vo1 and Vo2 via the first output terminal Po1 and the second output terminal Po2.
The dynamic differential amplifier 30 includes a first load capacitor CL1, a second load capacitor CL2, an input differential pair 32, an initializing circuit 34, a control circuit 36, and a tail current source M0.
The first load capacitor CL1 is arranged between the first output terminal Po1 and the fixed voltage terminal (ground terminal). The second load capacitor CL2 is arranged between the second output terminal Po2 and the ground terminal.
The initializing circuit 34 is configured to initialize the charge amount stored in the first load capacitor CL1 and the second load capacitor CL2. The initializing circuit 34 includes initializing transistors M3 and M4, for example. The initializing transistor M3 is arranged between the first load capacitor CL1 and the second fixed voltage terminal (power supply terminal). Similarly, the initializing transistor M4 is arranged between the second load capacitor CL2 and the power supply terminal. The on/off operations of the initializing transistors M3 and M4 are each controlled in synchronization with a control clock VCLK that transits to low level at a predetermined cycle. When the initializing transistors M3 and M4 are turned on, the first load capacitor CL1 and the second load capacitor CL2 are charged by the power supply voltage VDD, thereby initializing the charge amount stored in each load capacitor.
The input differential pair 32 includes an input transistor M1 and an input transistor M2. The input transistor M1 is arranged such that the first load capacitor CL1 functions as a load, and such that the first input signal Vi1 is input via its control terminal (gate). Similarly, the input transistor M2 is arranged such that the second load capacitor CL2 functions as a load, and such that the second input signal Vi2 is input via its gate. The tail current source M0 is configured to supply an operation current (tail current) I0=ID1+ID2 to the input differential pair 32.
When the midpoint voltage (Vo1+Vo2)/2 of the electric potentials Vo1 and Vo2 that respectively occur at the first output terminal Po1 the second output terminal Po2 reaches a predetermined threshold voltage Vth, the control circuit 36 disconnects the charging/discharging path for the first load capacitor CL1 and the second load capacitor CL2.
In order to provide a function for disconnecting the charging/discharging path for the first load capacitor CL1 and the second load capacitor CL2, a first switch SW1 and a second switch SW2 are arranged. The first switch SW1 is arranged between the load capacitor CL1 and the input transistor M1. The second switch SW2 is arranged between the second load capacitor CL2 and the input transistor M2.
The control circuit 36 is configured to switch the on/off states of the first switch SW1 and the second switch SW2, thereby switching the connection/disconnection state of the charging/discharging path for the first load capacitor CL1 and the second load capacitor CL2.
The above is the basic configuration of the dynamic differential amplifier 30. Next, description will be made regarding the operation thereof. FIG. 16 is a waveform diagram showing the operation of the dynamic differential amplifier 30 shown in FIG. 15. The horizontal axis represents time, and the vertical axis represents the output voltages Vo1 and Vo2.
1. Initializing State.
Before the amplification, the dynamic differential amplifier 30 is set to the initializing state (t<t0). In the initializing state, the control clock VCLK is set to low level, and the initializing transistors M3 and M4 are each turned on. Furthermore, the control circuit 36 turns on the first switch SW1 and the second switch SW2. As a result, the power supply voltage VDD is applied to the first load capacitor CL1 and the second load capacitor CL2, thereby initializing the output voltages Vo1 and Vo2 to the power supply voltage VDD.
2. Amplification State.
When the control clock VCLK is switched to high level, the initializing transistors M3 and M4 are each turned off, and the state is switched to the amplification state (t0<t<t1). In the amplification state, a current ID1 that corresponds to the input voltage Vi1 and a current ID2 that corresponds to the input voltage Vi2 flow through the input transistors M1 and M2, respectively. With the transconductance of the input transistor M1 and the input transistor M2 as gm, and with the tail current as I0, the currents ID1 and ID2 are represented by the following Expressions (32a) and (32b), respectively.

ID1=I0/2+gm×(Vi1−Vi2)/2  (32a)

ID2=I0/2−gm×(Vi1−Vi2)/2  (32b)

It should be noted that the relation Expression I0=ID1+ID2 holds true.
With the time elapsed from the start of the amplification as t, the output voltages Vo1 and Vo2 are represented by the following Expressions (33a) and (33b), respectively.

Vo1=VDD−ID1/CL1·t  (33a)

Vo2=VDD−ID2/CL2·t  (33b)

The control circuit 36 is configured to monitor the midpoint voltage Vx=(Vo1+Vo2)/2 of the output voltages Vo1 and Vo2. When the midpoint voltage Vx thus monitored reaches a predetermined threshold voltage Vth at the time point t1, the control circuit 36 turns off the first switch SW1 and the second switch SW2. Assuming that the first load capacitor CL1 and the second load capacitor CL2 each have the same capacitance CL, the midpoint voltage Vx is represented by the following Expression (34).

Vx=VDD−I0×t/(2×CL)  (34)

In a case in which the threshold voltage Vth is set to the midpoint voltage VDD/2 of the power supply voltage, the period T is represented by the following Expression (35).

T=CL×VDD/I0  (35)

In this case, the output voltages Vo1 and Vo2 are represented by the following Expressions (36a) and (36b), respectively.

Vo1=VDD/2−gm1/2×(Vi1−Vi2)/I0×VDD  (36a)

Vo2=VDD/2−gm2/2×(Vi1−Vi2)I0×VDD  (36b)

Thus, the differential gain G of the dynamic differential amplifier 30 is represented by the following Expression (37).




  
    
      
        
          
            
              
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The transconductance of the input transistor M1 and the transconductance of the input transistor M2 are represented by the following Expressions (38a) and (38b), respectively.

gm1=2×ID1/Veff  (38a)

gm2=2×ID2/Veff  (38b)

The relation Expressions are substituted into the Expression (37), thereby obtaining the following Expression (39).

G=−VDD/Veff  (39)

It should be noted that Veff is represented by Veff=VGS−Vt. Here, VGS represents the gate-source voltage, and Vt represents the gate-source threshold voltage of the MOSFET.
The energy consumption required for the dynamic differential amplifier 30 shown in FIG. 15 to perform amplification once is represented by the following Expression (40).

Ec=Q·VDD=2·ID·T·VDD·CL·VDD2  (40)

Thus, with the cyclic frequency as fc, power consumption Pd is represented by the following Expression (41)

Pd=fc·Ec=fc·CL·VDD2  (41)

The advantage of the dynamic differential amplifier 30 shown in FIG. 15 can be clearly understood by comparison with the amplifier shown in FIG. 17. FIG. 17 is a circuit diagram which shows a configuration of an amplifier 1030 according to a comparison technique. The amplifier 1030 includes load resistors RL1 and RL2, instead of the initializing circuit. Capacitors CL1 and CL2, and switches SW1 and SW2 are arranged in order to perform sampling of the drain voltages of the transistors M1 and M2. It should be noted that such a configuration provides a function that differs from that provided by the dynamic differential amplifier 30 shown in FIG. 15.
With such an amplifier 1030, the drain currents of the input transistors M1 and M2 steadily flow through the load resistors RL1 and RL2, respectively. In the bias state, the output voltages Vo1 and Vo2 are designed to be on the order of half the power supply voltage VDD. Thus, the following Expression (42) holds true for the resistances RL1 and RL2.

RL=VDD/2ID  (42)

Here, the relation Expressions RL=RL1=RL2 and ID=(ID1+ID2)/2 hold true. Based upon the relation expression which represents the relation between the voltage and current in a saturation range of the MOS transistor, the transconductance gm of the transistors M1 and M2 is represented by the following Expression (43).

gm=2·ID/Veff  (43)

Thus, the differential gain G of this circuit is represented by the following Expression (44).

G=−gm·RL=−VDD/Veff  (44)

That is to say, the dynamic differential amplifier 30 shown in FIG. 15 has the same gain as that of the amplifier 1030 shown in FIG. 17.
Description will be made regarding the power consumption of the amplifier shown in FIG. 17. Typically, the voltage Veff is on the order of 0.2 V. Thus, assuming that VDD=1 V, the gain is approximately 5. The time response of the amplifier 1030 is represented by the following Expression (45).

Vo1−Vo2=G·(Vi1−Vi2)·(1−e1/τ)  (45)

where τ=RL·CL 
Giving consideration to the fact that the constant current (2·ID) flows through this circuit, the power consumption PD of this circuit is represented by the following Expression (46).

PD=2−ID·VDD=VDD2/RL=CL·VDD2/τ  (46)

As can be clearly understood from Expression (45), the response time constant τ of the amplifier 1030 is determined by the product of the resistance and the capacitance. Thus, in a case in which the response speed is to be raised, i.e., in a case in which the time constant τ is to be reduced, there is a need to reduce the resistance. However, if the resistance is reduced, the power consumption represented by Expression (46) increases in inverse proportion to the resistance.
Assuming that 1% settling time is required, the amplifier shown in FIG. 17 requires a period of time of at least (5·τ) as settling time for each half cycle. Thus, the power consumption PD is represented by the following Expression (47).

PD=CL·VDD2/τ=10·fc·CL·VDD2  (47)

By making a comparison between the amplifier shown in FIG. 17 and the amplifier shown in FIG. 15, the advantage of the dynamic differential amplifier 30 shown in FIG. 15 can be clearly understood as follows.
First, with the dynamic differential amplifier 30 shown in FIG. 15, the power consumption PD is represented by Expression (41). Thus, it can be understood that the dynamic differential amplifier 30 shown in FIG. 15 has an advantage of low power consumption, which is on the order of 1/10 the power consumption PD of the amplifier 1030 shown in FIG. 17, which is represented by Expression (47).
With the circuit shown in FIG. 17, by designing the load resistor RL to have a resistance in inverse proportion to the cyclic frequency fc, such an arrangement allows the power consumption to be reduced. However, it is difficult for such an arrangement to provide such a resistance value as a variable resistance which can be adjusted over a wide frequency range. Thus, such an arrangement is impractical. That is to say, in practice, such an arrangement requires a sufficiently low resistance RL so as to provide a sufficient response speed for the possible maximum cyclic frequency fcmax. This leads to increased power consumption as represented by Expression (47). In contrast, with the configuration shown in FIG. 15, there is no relation between the power consumption and the operation current as represented by Expression (41). Thus, such an arrangement has an advantage in that the power consumption does not increase even if the operation current is increased in order to provide a high-speed operation. Furthermore, in a case in which the frequency fc is reduced, such an arrangement provides an amplifier which requires only very low power consumption to operate.
Next, description will be made regarding a more specific example configuration of the dynamic differential amplifier 30.
FIGS. 18A and 18B are circuit diagrams showing a specific example configuration of the dynamic differential amplifier 30 shown in FIG. 15.
With a dynamic differential amplifier 30a shown in FIG. 18A, a control circuit 36 includes a first dividing capacitor C1, a second dividing capacitor C2, and a comparator 38. The first dividing capacitor C1 and the second dividing capacitor C2 are arranged in series between the first output terminal Po1 and the second output terminal Po2. The first dividing capacitor C1 and the second dividing capacitor C2 each have the same capacitance C0. The comparator 38 is configured to compare the electric potential V, at a connection node that connects the first dividing capacitor C1 and the second dividing capacitor C2 with a predetermined threshold voltage Vth, and to control switches SW1 and SW2 according to a signal that corresponds to the comparison result.
As shown in the lower circuit diagram in FIG. 18A, the comparator 38 may include inverters 39. Each inverter 39 is arranged to receive the power supply voltage VDD and the ground voltage GND, and is configured such that its threshold voltage Vth is set to VDD/2. The number of inverter 39 stages is preferably designed according to the control logic of the switches SW1 and SW2.
An initializing circuit 34a is configured to initialize the electric potential Vx at the connection node Nx that connects the first dividing capacitor C1 and the second dividing capacitor C2 to the power supply voltage VDD, in the same way as the first output terminal Po1 and the second output terminal Po2. Specifically, an initializing transistor M5 is arranged between the node Nx and the power supply terminal. By turning on the initializing transistor M5, such an arrangement is capable of initializing the electric potential at the node N.
By performing initialization, the charge amounts of the capacitors C1 and C2 are each initialized to zero. After the pre-charge charge is released, amplification is started. When the output voltages V1 and V2 respectively develop at the first output terminal Po1 and the second output terminal Po2, the following Expression (48) holds true, assuming that parasitic capacitance can be ignored.

C0·(Vx−V1)=C0·(Vx−V2)  (48)

Expression (48) is solved for Vx, thereby obtaining the following Expression (49).

Vx=(V1+V2)/2  (49)

That is to say, the electric potential V, at the connection node Nx is equal to the midpoint voltage of the two output voltages Vo1 and Vo2. Thus, such an arrangement allows the midpoint voltage V to be compared with a threshold voltage in the same way as with the circuit shown in FIG. 15.
Furthermore, the control clock VCLK is input to the gate of the tail current source M0. Such an arrangement allows the tail current source M0 to be turned off in the initialization state, thereby further reducing power consumption.
A dynamic differential amplifier 30b shown in FIG. 18B includes a logical gate 40, in addition to the configuration of the dynamic differential amplifier 30a shown in FIG. 18A. The logical gate 40 is configured to supply the logical AND of the output signal CNT of the control circuit 36 and the control clock VCLK to the gate of the tail current source M0. With such a configuration, such an arrangement is capable of disconnecting the charging/discharging path for the first load capacitor CL1 and the second load capacitor CL2 in a surer manner than with an arrangement shown in FIG. 18A. Moreover, by turning off the tail current source M0, the electric potentials at the first output terminal Po1 and the second output terminal Po2 do not fall to the ground potential (0 V). Thus, such an arrangement is capable of further reducing power consumption in comparison with an arrangement shown in FIG. 18A.
FIGS. 19A and 19B are circuit diagrams each showing another specific example of the dynamic differential amplifier. With a dynamic differential amplifier 30c shown in FIG. 19A, a control circuit 36c is configured as a logical gate. Specifically, the control circuit 36c is configured as an AND gate. FIG. 19B is a circuit diagram which shows a specific configuration of the control circuit 36c. The control circuit 36c includes a NAND gate 42 and an inverter (NOT gate) 44 arranged as a downstream stage of the NAND gate 42.
The NAND gate 42 includes P-channel transistors MP1 and MP2, and N-channel transistors MN1, MN2, MN3, and MN4. The first P-channel transistor MP1, the first N-channel transistor MN1, and the second N-channel transistor MN2 are sequentially stacked between the power supply terminal and the ground terminal so as to form a first path. The second P-channel transistor MP2, the third N-channel transistor MN3, and the fourth N-channel transistor MN4 are sequentially stacked between the power supply terminal and the ground terminal so as to form a second path arranged in parallel with the first path.
A first input signal V1 is applied to the gates of the first P-channel transistor MP1, the first N-channel transistor MN1, and the fourth N-channel transistor MN4. A second input signal V2 is applied to the gates of the second P-channel transistor MP2, the second N-channel transistor MN2, and the third N-channel transistor MN3. The output terminal of the NAND gate 42 is connected to the drains of the first P-channel transistor MP1 and the second P-channel transistor MP2.
With the average drain current of the N-channel transistor as IDN, and with the average drain current of the P-channel transistor as IDP, the voltage-current characteristics can be approximated by the following Expressions (50a) and (50b), assuming that such a transistor has a fine structure.

IDN=KN·(VGS−VTN)  (50a)

IDP=−KP·(VGS−VTP)  (50b)

When the total current that flows through the P-channel transistors is equal to the total current that flows through the N-channel transistors, the logical state of the output of the NAND gate 42 transits. Thus, the following Expressions (51a) and (51b) hold true.

IDN=KN·(V1−VTN)+KN·(V2−VTN)=2·KN·{(V1+V2)/2−VTN}  (51a)

IDP=KP·(VDD−V1−VTP)+KP·(VDD−V2−VTP)=2·KP·{−(V1+V2)/2+VDD+VTP}  (51b)

Based upon the aforementioned Expressions, it can be understood that the input voltages V1 and V2 that provide IDN=IDP satisfies the following relation Expression (52).

(V1+V2)/2=(KN·VTN+KP·VTP)/(KN+KP)+KP/(KN+KP)·VDD  (52)

Thus, it can be understood that the output logical state transits at the midpoint voltage of V1 and V2. As described above, by employing such a NAND gate 42 shown in FIG. 19B instead of the dividing capacitors C1 and C2, such an arrangement also allows the midpoint voltage to be compared with the threshold voltage Vth.
It should be noted that description has been made with reference to FIGS. 15 through 19 regarding an arrangement in which the input differential pair 32 has a configuration using N-channel MOSFETs. Also, the input differential pair 32 may be configured using P-channel MOSFETs. In this case, the power supply voltage and the ground voltage are preferably reversed, in addition to the N-channel transistors being replaced by P-channel transistors. Furthermore, the gate signal to be applied to each transistor may be preferably inverted as necessary.
Description has been made in the embodiment regarding an arrangement in which the charging/discharging path for the load capacitors CL1 and CL2 is disconnected according to the midpoint voltage Vx of the output voltage Vo1 and Vo2. Also, the control circuit 36 may be configured as a timer circuit configured to count the time elapsed from the start of charging.
FIG. 20 is a circuit diagram which shows a modification of the dynamic differential amplifier 30 shown in FIG. 15. The dynamic differential amplifier 30 shown in FIG. 15 includes the tail current source M0 in order to set the operation current for the input transistors M1 and M2. Such an arrangement requires a drain-source voltage of 0.2 V or more for the tail current source M0, leading to difficulty in employing such a tail current source in a situation in which only a low power supply voltage VDD can be used. In order to solve such a problem, a dynamic differential amplifier 30d shown in FIG. 20 is configured as a pseudo-differential circuit having a configuration obtained by eliminating the tail current source M0 shown in FIG. 15. The dynamic differential amplifier 30d includes switch transistor M5 and M6, the on/off state of each of which is controlled in synchronization with the control clock VCLK, on the respective drain sides of the input transistors M1 and M2. In the initialization state, the switch transistors M5 and M6 are each turned off. In the amplification state, the switch transistors M5 and M6 are each turned on.
With the dynamic differential amplifier 30d shown in FIG. 20, by controlling the gate voltages Vi1 and Vi2, such an arrangement is configured to control the operation currents of the input transistor M1 and the input transistor M2. The switching transistors M5 and M6 are each configured as a switch that switches between two states, i.e., an on state and an off state. Thus, in the operation state, the drain-source voltage Vds of each switching transistor is substantially zero. Thus, such an arrangement allows the dynamic differential amplifier 30d to operate even if the power supply voltage VDD is reduced by the drain-source voltage Vds (which is on the order of 0.2 V) that is required for the tail current source M0 shown in FIG. 15.
Also, an arrangement may be made in which the transistors M5 and M6 are eliminated from the configuration shown in FIG. 20, and the gate voltages Vi1 and Vi2 are controlled so as to turn off the input transistors M1 and M2, respectively, in a period in which they are to be turned off.
Also, the configuration shown in FIG. 20 and the configuration shown in FIG. 18B may be combined. With such an arrangement, the output of the gate 40 shown in FIG. 18B may be preferably input to the gates of the respective transistors M5 and M6 shown in FIG. 20.
The dynamic differential amplifiers described with reference to FIGS. 15 through 20 can be preferably employed in the aforementioned A/D converters. However, the usage thereof is not restricted in particular. Such a dynamic differential amplifier can be employed in various kinds of applications which do not require absolute gain precision, but which require relative gain precision, thereby providing an advantage of reduced power consumption.
Description has been made regarding the present invention with reference to the embodiment using specific terms. However, the above-described embodiments show only the mechanisms and applications of the present invention for exemplary purposes only, and are by no means intended to be interpreted restrictively. Rather, various modifications and various changes in the layout can be made without departing from the spirit and scope of the present invention defined in appended claims.

## Claims

1. An A/D converting method for converting an analog input voltage into digital data, comprising:
a first step in which the input voltage is compared with a plurality of threshold voltages, and judgment is made regarding which one from among a plurality of segments the input voltage belongs to;
a second step in which a first voltage and a second voltage are generated such that the segment to which the input voltage belongs is sandwiched between the first voltage and the second voltage;
a third step in which a third voltage is generated by amplifying the difference between the first voltage and the input voltage with a predetermined common voltage as a base;
a fourth step in which a fourth voltage is generated by amplifying the difference between the second voltage and the input voltage with the common voltage as a base;
a fifth step in which a region between the third voltage and the fourth voltage is divided into a plurality of segments, and judgment is made regarding which one from among the plurality of segments the common voltage belongs to;
a sixth step in which a fifth voltage and a sixth voltage are generated such that the segment to which the common voltage belongs is sandwiched between the fifth voltage and the sixth voltage;
a seventh step in which a seventh voltage is generated by amplifying the difference between the fifth voltage and the common voltage with the common voltage as a base; and
an eighth step in which an eighth voltage is generated by amplifying the difference between the sixth voltage and the common voltage with the common voltage as a base,
wherein the fifth step through the eighth step are repeatedly executed,
and wherein, when the flow returns from the eighth step to the fifth step, the seventh voltage obtained in the seventh step in the previous loop is used as the third voltage in the fifth step in the subsequent loop, and the eighth voltage obtained in the eighth step in the previous loop is used as the fourth voltage in the fifth step in the subsequent loop.

2. An A/D converting method according to claim 1, wherein, in the sixth step, the fifth voltage and the sixth voltage are each generated by interpolation of a range between the third voltage and the fourth voltage.

3. An A/D converting method according to claim 1, wherein the first voltage through the eighth voltage are each generated as a differential signal.

4. An A/D converting method according to claim 3, wherein, in the sixth step, the fifth voltage and the sixth voltage are each generated by performing extrapolation from the third voltage and the fourth voltage.

5. A pipeline A/D converter configured to convert an analog input voltage into digital data, the pipeline A/D converter comprising an A-type converter circuit, at least one B-type converter circuit, and a comparator array, connected in series,
wherein the A-type converter circuit comprises:
a first sub-A/D converter configured to compare the input voltage with a plurality of threshold voltages, and to judge which one from among a plurality of segments the input voltage belongs to;
a first amplifier circuit configured to generate a first voltage having a voltage level that is equal to or greater than the upper limit of the segment to which the input voltage belongs, to generate a third voltage by amplifying the difference between the first voltage and the input voltage with a predetermined common voltage as a base, and to output the third voltage to the B-type converter circuit arranged as a downstream stage; and
a second amplifier circuit configured to generate a second voltage having a voltage level that is equal to or smaller than the lower limit of the segment to which the input voltage belongs, to generate a fourth voltage by amplifying the difference between the second voltage and the input voltage with the common voltage as a base, and to output the fourth voltage to the B-type converter circuit arranged as a downstream stage,

and wherein the B-type converter circuit comprises:
a second-sub A/D converter configured to divide a range between the third voltage and the fourth voltage received from the upstream stage into a plurality of segments, and to judge which one from among the plurality of segments the common voltage belongs to;
a third amplifier circuit configured to generate a seventh voltage by amplifying the difference between the common voltage and a fifth voltage having a voltage level that is equal to or greater than the upper limit of the segment to which the common voltage belongs, and to output the seventh voltage as the third voltage to the B-type converter circuit arranged as the downstream stage; and
a fourth amplifier circuit configured to generate an eighth voltage by amplifying the difference between the common voltage and a sixth voltage having a voltage level that is equal to or smaller than the lower limit of the segment to which the common voltage belongs, and to output the eighth voltage as the fourth voltage to the B-type converter circuit arranged as the downstream stage,

and wherein the comparator array is configured to divide a range between the third voltage and the fourth voltage received from the B-type converter circuit arranged as the immediately upstream stage into a plurality of segments, and to judge which one from among a plurality of segments the common voltage belongs to.

6. An A/D converter according to claim 5, wherein the first amplifier circuit comprises:
a first capacitor array comprising a plurality of first capacitors arranged such that their first terminals are connected together;
a first switch circuit configured to apply the input voltage to second terminals of the first capacitor array in a sampling state, and to apply, in an interpolation amplification state, a reference voltage to the second terminals of certain first capacitors from among the first capacitor array, the number of which is determined according to the judgment result obtained by the first sub-A/D converter;
a first switch arranged between the first terminal of the first capacitor array and a fixed voltage terminal, and configured to be turned on in the sampling state, and to be turned off in the interpolation amplification state; and
a first amplifier arranged such that the common voltage is input to its first input terminal, and its second input terminal is connected to the first terminal of the first capacitor array,
and wherein the second amplifier circuit comprises a second capacitor array, a second switch circuit, a second switch, and a second amplifier, and is configured in the same manner as that of the first amplifier circuit.

7. An A/D converter according to claim 5, wherein the third amplifier circuit and the fourth amplifier circuit are respectively configured to generate the fifth voltage and the sixth voltage by interpolating from the third voltage and the fourth voltage.

8. An A/D converter according to claim 7, wherein the third amplifier circuit comprises:
a third capacitor array comprising a plurality of third capacitors arranged such that their first terminals are connected together;
a fourth capacitor array arranged such that their first terminals are connected together to the first terminals of the third capacitor array;
a third switch circuit configured to apply the third voltage to the second terminals of the third capacitor array in a sampling state, and to apply, in an interpolation amplification state, a fixed voltage to the second terminals of certain third capacitors from among the third capacitor array, the number of which is determined according to the judgment result obtained by the second sub-A/D converter;
a fourth switch circuit configured to apply the fourth voltage to the second terminals of the fourth capacitor array in the sampling state, and to apply, in the interpolation amplification state, a fixed voltage to the second terminals of the certain fourth capacitors from among the fourth capacitor array, the number of which is determined according to the judgment result obtained by the second sub-A/D converter;
a third switch arranged between the fixed voltage terminal and the connected-together first terminals of the third capacitor array and the fourth capacitor array, and configured to be turned on in the sampling state, and to be turned off in the interpolation amplification state; and
a third amplifier arranged such that the common voltage is input to its first input terminal, and its second input terminal is connected to the first terminals of the third capacitor array and the fourth capacitor array to which they are connected together,
and wherein the fourth amplifier circuit comprises a fifth capacitor array, a sixth capacitor array, a fifth switch circuit, a sixth switch circuit, a fourth switch, and a fourth amplifier, and is configured in the same manner as that of the aforementioned third amplifier circuit.

9. An A/D converter according to claim 8, wherein the third switch circuit is configured to apply the third voltage received from its upstream stage as the fixed voltage when the fixed voltage is to be applied to the third capacitor array in the interpolation amplification state, and the fourth switch circuit is configured to apply the fourth voltage received from its upstream stage as the fixed voltage when the fixed voltage is to be applied to the fourth capacitor array in the interpolation amplification state, thereby canceling the offset voltage of the amplifier of the converter circuit of the upstream stage.

10. An A/D converter according to claim 8, wherein the first amplifier circuit through the fourth amplifier circuit are each configured as a differential amplifier.

11. An A/D converter according to claim 10, wherein the third amplifier circuit and the fourth amplifier circuit are respectively configured to generate the fifth voltage and the sixth voltage by means of interpolation from, or otherwise extrapolation from, the third voltage and the fourth voltage using a combination of the non-inverted signal of, or otherwise the inverted signal of, the third voltage and the non-inverted signal of, or otherwise the inverted signal of, the fourth voltage.

12. An A/D converter according to claim 11, wherein the third switch circuit is configured to apply the non-inverted signal of, or otherwise the inverted signal of, the third voltage to the second terminal of the third capacitor array in the sampling state,
and wherein the fourth switch circuit is configured to apply the non-inverted signal of, or otherwise the inverted signal of, the fourth voltage to the second terminal of the fourth capacitor array in the sampling state.

13. An A/D converter according to claim 8, wherein the B-type converter circuit further comprises a gain adjustment unit which is capable of digitally controlling the gains of the third amplifier and the fourth amplifier.

14. An A/D converter according to claim 5, further comprising:
an input switch arranged upstream of the B-type converter circuit, and configured to supply the third voltage and the fourth voltage to the B-type converter circuit while performing swapping between them; and
an output switch arranged downstream of the B-type converter circuit, and configured to output the seventh voltage and the eighth voltage to its downstream B-type converter circuit while performing swapping between them.

15. An A/D converter according to claim 6, wherein the first amplifier and the second amplifier each comprise a dynamic differential amplifier,
and wherein the dynamic differential amplifier comprises:
a first input terminal and a second input terminal;
a first output terminal and a second output terminal;
a first load capacitor arranged between the first output terminal and a fixed voltage terminal;
a second load capacitor arranged between the second output terminal and the fixed voltage terminal;
an initializing circuit configured to initialize the charge stored in each of the first load capacitor and the second load capacitor;
an input differential pair comprising a first input transistor and a second input transistor arranged such that the first load capacitor and the second load capacitor respectively function as their load, and their control terminals are respectively connected to the first input terminal and the second input terminal; and
a control circuit configured to disconnect a charging/discharging path for the first load capacitor and the second load capacitor when the midpoint voltage between the electric potentials at the first output terminal and the second output terminal reaches a predetermined threshold voltage.

16. An A/D converter according to claim 8, wherein the third amplifier and the fourth amplifier each comprise a dynamic differential amplifier,
and wherein the dynamic differential amplifier comprises:
a first input terminal and a second input terminal;
a first output terminal and a second output terminal;
a first load capacitor arranged between the first output terminal and a fixed voltage terminal;
a second load capacitor arranged between the second output terminal and the fixed voltage terminal;
an initializing circuit configured to initialize the charge stored in each of the first load capacitor and the second load capacitor;
an input differential pair comprising a first input transistor and a second input transistor arranged such that the first load capacitor and the second load capacitor respectively function as their load, and their control terminals are respectively connected to the first input terminal and the second input terminal; and
a control circuit configured to disconnect a charging/discharging path for the first load capacitor and the second load capacitor when the midpoint voltage between the electric potentials at the first output terminal and the second output terminal reaches a predetermined threshold voltage.

17. An A/D converter according to claim 15, further comprising:
a first switch arranged between the first load capacitor and the first input transistor; and
a second switch arranged between the second load capacitor and the second input transistor,
wherein the control circuit is configured to disconnect the charging/discharging paths for the first load capacitor and the second load capacitor by turning off the first switch and the second switch.

18. An A/D converter according to claim 15, wherein the dynamic differential amplifier further comprises a tail current source configured to supply a tail current to the input differential pair,
wherein the control circuit is configured to disconnect the charging/discharging path for the first load capacitor and the second load capacitor by turning off the tail current source.

19. An A/D converter according to claim 15, wherein the control circuit comprises:
a first dividing capacitor and a second dividing capacitor arranged in series between the first output terminal and the second output terminal; and
a comparator configured to compare an electric potential at a connection node that connects the first dividing capacitor and the second dividing capacitor with a predetermined threshold voltage.

20. An A/D converter according to claim 19, wherein the comparator comprises an inverter configured to receive a power supply voltage and a ground voltage as a power supply.

21. An A/D converter according to claim 19, wherein the initializing circuit is configured to initialize the electric potential at the connection node that connects the first dividing capacitor and the second dividing capacitor to the same electric potentials as those at the first output terminal and the second output terminal.

22. An A/D converter according to claim 21, wherein the control circuit comprises a NAND gate configured to receive the respective electric potentials at the first load capacitor and the second load capacitor, and configured to disconnect the charging/discharging path for the first load capacitor and the second load capacitor according to the output of the NAND gate,
and wherein the NAND gate comprises a first P-channel transistor, a first N-channel transistor, a second N-channel transistor sequentially stacked between the power supply terminal and the ground terminal so as to form a first path, and a second P-channel transistor, a third N-channel transistor, and a fourth N-channel transistor sequentially stacked between the power supply terminal and the ground terminal so as to form a second path arranged in parallel with the first path,
and wherein a first input signal is applied to the gates of the first P-channel transistor, the first N-channel transistor, and the fourth N-channel transistor,
and wherein a second input signal is applied to the gates of the second P-channel transistor, the second N-channel transistor, and the third N-channel transistor,
and wherein the output terminal of the NAND gate is connected to the drains of the first P-channel transistor and the second P-channel transistor.

23. A dynamic differential amplifier comprising:
a first input terminal and a second input terminal;
a first output terminal and a second output terminal;
a first load capacitor arranged between the first output terminal and a fixed voltage terminal;
a second load capacitor arranged between the second output terminal and the fixed voltage terminal;
an initializing circuit configured to initialize the charge stored in each of the first load capacitor and the second load capacitor;
an input differential pair comprising a first input transistor and a second input transistor arranged such that the first load capacitor and the second load capacitor respectively function as their load, and their control terminals are respectively connected to the first input terminal and the second input terminal; and
a control circuit configured to disconnect a charging/discharging path for the first load capacitor and the second load capacitor when the midpoint voltage of the electric potentials at the first output terminal and the second output terminal reaches a predetermined threshold voltage.

24. A dynamic differential amplifier according to claim 23, further comprising:
a first switch arranged between the first load capacitor and the first input transistor; and
a second switch arranged between the second load capacitor and the second input transistor,
wherein the control circuit is configured to disconnect the charging/discharging path for the first load capacitor and the second load capacitor by turning off the first switch and the second switch.