1 

IN THE UNITED STATES DISTRICT COURT 

FOR THE WESTERN DISTRICT OF TEXAS 

WACO DIVISION 

PARKERVISION, INC., 

Plaintiff, 

vs. 

INTEL CORPORATION, 

Defendant. 

 Civil Action No. 6:20-cv-00562-ADA 

 JURY TRIAL DEMANDED 

JOINT CLAIM CONSTRUCTION STATEMENT 

 

Case 6:20-cv-00562-ADA Document 45 Filed 05/17/21 Page 1 of 16
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Pursuant to the Court’s March 1, 2021 Order entered in this case, see Dkt. 40 at 1, Plaintiff 

ParkerVision, Inc. (“ParkerVision”) and Defendant Intel Corporation (“Intel”) submit this Joint 

Claim Construction Statement. The claim terms identified in Exhibit 1 below are found in U.S. 

Patent Nos. 6,049,706 (“’706 patent”); 7,050,508 (“’508 patent”); and 8,190,108 (“’108 patent”). 

Case 6:20-cv-00562-ADA Document 45 Filed 05/17/21 Page 2 of 16
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Exhibit 1 

Case 6:20-cv-00562-ADA Document 45 Filed 05/17/21 Page 3 of 16
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I. AGREED CONSTRUCTIONS 

Claim Term Agreed Construction Patent(s) 

Claim(s) 

“energy transfer signal 

comprising a train of pulses” 

“a signal comprising a train of pulses 

having non-negligible apertures that tend away from zero”

’706 patent, claims 106, 176 

II. DISPUTED CLAIM TERMS 

Claim Term Intel’s Proposal ParkerVision’s Proposal Pa

Cl

“under-sample” / “undersamples” / “under-sampling” 1 “sample[s/ing] at less than or equal to twice the 

frequency of the input signal using negligible apertures (i.e., pulse widths) that tend towards zero time in duration”

“sampling at an aliasing rate” or “sampling at less than or equal to twice the frequency of the input signal” 

’707, 

“storage module”2 “a module that stores 

a non-negligible amount of energy from an input electromagnetic (EM) 

“a module of an energy transfer system that stores non-negligible amounts of energy 

’701119

1 The parties agreed to rely on their briefing in ParkerVision, Inc. v. Intel Corp., No. 6:20-cv-108 (W.D. Te

terms that are also in dispute in this case: “under-sampling,” “storage module,” and “switch.” The parties’ prior 

these three terms are reflected here. Intel reserves its right to appeal should the Court adopt, in this case, the sam

adopted previously.

2 See fn. 1 above

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Claim Term Intel’s Proposal ParkerVision’s Proposal Pa

Cl

signal” from an input 

electromagnetic signal for driving a low impedance load” 

“switch”3 “an electronic device 

for opening and closing a circuit”

“an electronic device for opening and closing a circuit as dictated by an independent control input” 

’7016pat

“a down-convert and delay 

module to under-sample an input signal to produce an input sample of a down-converted image of said input signal, and to delay said input sample”4

Function: under-sample an input 

signal according to a control signal to produce an input sample of a down-converted image of said input signal, and to delay said input sample 

Structure: the down convert and 

delay module 2624 in Fig. 26 and described at 26:1-27:21 and 28:20-41, that includes the switches 2650 and 2654, and the capacitors 2652 and 2656; and equivalents thereof 

Plain and ordinary meaning ’70

“a frequency translator to 

produce a sample of a downFunction: produce a sample of a down-converted image of an input Plain and ordinary meaning ’70

3 See fn. 1 above 4 Intel addresses this term (“a down-convert and delay module ...”) and the immediately following term (“

...”) together in its briefing, and refers to these two terms as the “Down-Convert and Delay” terms.

Case 6:20-cv-00562-ADA Document 45 Filed 05/17/21 Page 5 of 16
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Claim Term Intel’s Proposal ParkerVision’s Proposal Pa

Cl

converted image of an input signal, and to delay said sample” 

signal according to a control signal, and to delay said sample 

Structure: the down convert and 

delay module 2624 in Fig. 26 and described at 26:1-27:21 and 28:20-41, that includes the switches 2650 and 2654, and the capacitors 2652 and 2656; and equivalents thereof. 

“said input sample”, “said sample” 

“the sample of the image that has been down-converted” 

Plain and ordinary meaning ’70

7, 

“delay module to delay instances of an output signal”, “delay modules to further delay one or more of said delayed and down-converted input samples” 

Function: delay instances of an 

output signal / further delay one or more of said delayed and downconverted input samples Structure: structure including “first 

delay module 2628,” “second delay module 2630” shown in Fig 26, “delay module 3204” shown in Fig. 32 and described at 35:1-18; the sample and hold circuit 4501 and 4503 in Fig. 45 and described at 32:44-33:19; or an analog delay line having a combination of capacitors, inductors and/or resistors described at 35:19-27; or equivalents thereof. 

Plain and ordinary meaning ’70

34

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Claim Term Intel’s Proposal ParkerVision’s Proposal Pa

Cl

“harmonic”, “harmonics” Harmonic: “A sinusoidal 

component of a periodic wave that has a frequency that is an integer multiple of the fundamental frequency of the periodic wave” Harmonics: “Sinusoidal components of a periodic wave each of which have a frequency that is an integer multiple of the fundamental frequency of the periodic wave” 

Harmonic: “A sinusoidal component of a periodic wave that has a frequency that is an integer multiple of the fundamental frequency of the periodic waveform and including the fundamental frequency as the first harmonic” Harmonics: “A frequency or tone that, when compared to its fundamental or reference frequency or tone, is an integer multiple of it and including the fundamental frequency as the first harmonic” 

’707, cla

“pulse widths that are established to improve energy transfer” 

Indefinite Plain and ordinary meaning, or 

Pulse widths that use non-negligible apertures for energy transfer 

’70

“means for under-sampling an input signal to produce an input sample of a down-converted image of said input signal” 

Function: under-sampling an input 

signal to produce an input sample of a down-converted image of said input signal and under-sampling the input signal according to a control signal Structure: the switch 2650 and the capacitor 2652 in Fig. 26 and described at 26:1-27:21, 28:20-28, and 39:25-28; the switch 5308 and capacitor 5310 in Fig. 53A and described at 28:46-47; the switch 

Function: under-sampling an input 

signal to produce an input sample of a down-converted image of the input signal and under-sampling the input signal according to a control signal Structure: switch 2650 in Fig. 26; switch 5308 in Figs. 53A/53A-1; and equivalents thereof 

’70

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Claim Term Intel’s Proposal ParkerVision’s Proposal Pa

Cl

5308 and capacitor 5310 in Fig. 53A-1 and described at 28:52-56 and equivalents thereof. 

“first delaying means for delaying said input sample” 

Function: delaying said input 

sample Structure: the switch 2654 and 

capacitor 2656 shown in Fig. 26 and described at 25:57-27:21 and 28:20-28; and equivalents thereof. 

Function: delaying the input sample 

of a down-converted image of said input signal Structure: capacitor 2656 in Fig. 26 

or capacitor 5310 in Figs. 53A/53A1; and equivalents thereof 

’70

“second delaying means for delaying instances of an output signal” 

Function: delaying instances of an 

output signal Structure: structure including “first 

delay module 2628,” “second delay module 2630” shown in Fig 26 and described at 32:27-55, “delay module 3204” shown in Fig. 32 and described at 35:1-18; the sample and hold circuits 4501 and 4503 in Fig. 45 and described at 32:44-64; or an analog delay line having a combination of capacitors, inductors and/or resistors described at 35:19-27; and equivalents thereof. 

Function: delaying instances of an 

output signal Structure: delay modules 1722A, 1722B, 1722C, etc. in FIG. 17; delay modules 1912, 1914 in Fig. 19; delay modules 2316, 2318 in Fig. 23; first delay module 2628, second delay module 2630 in Fig. 26; delay module 3204 shown in Fig. 32; sample and hold circuits 4501, 4503 shown in Fig. 45; analog delay line 3404 shown in Fig. 34 having a combination of capacitors, inductors, and/or resistors; and equivalents thereof 

’70

“integral filter/frequency translator to filter and downconvert an input signal” 

Function: to filter and downconvert an input signal and to undersample said input signal according 

to a control signal 

“a circuit having a unified input filter and frequency translator” 

’70

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Claim Term Intel’s Proposal ParkerVision’s Proposal Pa

Cl

Structure: the Unified 

Downconvert and Filter (UDF) Module 2622 that includes: 

(1) the frequency translator 1108 

having the down convert and delay module 2624; 

(2) a first delay module, including 

the delay module 2628 shown in Fig. 26, the delay module 3204 shown in Fig. 32 and described at 35:1-18, the sample and hold circuit 4501 or 4503 shown in Fig. 45 and described at 32:44-64, or the analog delay line having a combination of capacitors, inductors and/or resistors described at 35:19-27; 

(3) a second delay module including 

the delay module 2630 shown in Fig. 26, the delay module 3204 shown in Fig. 32 and described at 35:1-18, the sample and hold circuit 4501 or 4503 shown in Fig. 45 and described at 32:44-64, or the analog delay line having a combination of capacitors, inductors and/or resistors described at 35:19-27; 

(4) a first scaling module, including 

the first scaling module 2632 shown in Fig. 26, the resistor attenuator 

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Claim Term Intel’s Proposal ParkerVision’s Proposal Pa

Cl

3602 shown in Fig. 36 and described at 35:44-55, or the amplifier/attenuator 3704 implemented using operational amplifiers, transistors, or FETs shown in Fig. 37 and described at 35:60-67; 

(5) a second scaling module, 

including the second scaling module 2634 shown in Fig. 26, the resistor attenuator 3602 shown in Fig. 36 and described at 35:44-55, or the amplifier/attenuator 3704 implemented using the operational amplifiers, transistors, or FETs shown in Fig. 37 and described at 35:60-67; 

(6) a first adder including, the adder 

2625 in Fig. 26, adder 1720 in Fig. 17, the adder 2522 in Fig. 25, the summer 3902 in Fig. 39, or the summer 4102 in Fig. 41; and 

(7) a second adder, including the 

adder 2626 in Fig. 26, adder 1720 in Fig. 17, the adder 2522 in Fig. 25, the summer 3902 in Fig. 39, and the summer 4102 in Fig. 41; 

and equivalents thereof. 

Case 6:20-cv-00562-ADA Document 45 Filed 05/17/21 Page 10 of 16
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Claim Term Intel’s Proposal ParkerVision’s Proposal Pa

Cl

“modulated signal” “a signal with physical 

characteristics varied to represent the transmitted information” 

“an electromagnetic signal at a transmission frequency having at least one characteristic that has been modulated by a baseband signal” 

’70

“filter tuning means for tuning one or more filter parameters” 

Function: tuning one or more filter 

parameters Structure: scaling modules 

including the resistor attenuator 3602 (shown in Fig. 36 and described at 35:44-55) or the amplifier/attenuator 3704 implemented using operational amplifiers, transistors, or FETS (shown in Fig. 37 and described at 35:60-67), each of the resistor attenuator 3602 and the amplifier/attenuator 3704 having tunable resistors, capacitors, or inductors (as described at 42:33-36); and equivalents thereof; OR the 

control signal generator 4202 (shown in Fig. 42 and described at 36:44-62 and 42:27-32) implemented with a tunable oscillator 4204 and an aperture optimizing module 4210 using tunable components (such as tunable resistors, capacitors, inductors, etc.) 

Function: tuning one or more filter 

parameters Structure: scaling modules 1716A, 1716B, 1716C, 1724A, 1724B, 1724C in Fig. 17; control signal generator 1790 in Fig. 17; input scaling module 1909 in Fig. 19; scaling modules 1916, 1918 in Fig. 19; scaling modules 2312, 2320, 2322 in Fig. 23; scaling module 2632, 2634 in Fig. 26; scaling module 3502 including resistor attenuator 3504, 3602 in Figs. 35, 36; scaling module 3702 including amplifier/attenuator 3704 in Fig. 37; control signal generator 4202 in Fig. 42; and equivalents thereof 

’70

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Claim Term Intel’s Proposal ParkerVision’s Proposal Pa

Cl

(described at 36:63-37:5 and 42:27-32) and equivalents thereof. 

“pulse shaping means for shaping a string of pulses from a reference signal” 

Function: shaping a string of pulses 

from a reference signal Structure: the pulse shaping circuit 

3900 shown in Fig. 39A and described at 48:8-39, the pulse shaping circuit 4000 shown in Fig. 40A and described at 48:40-49:5, and the pulse shaping circuit 4100 shown in Fig. 41 and described at 49:6-26, which incorporates circuit element 4104 shown in Fig. 43 and described at 49:6-26; and equivalents thereof. 

Function: shaping a string of pulses 

from a reference signal

Structure: pulse shaper 3900 in Fig. 39A; pulse shaping circuit/pulse shaper 4000 in Fig. 40A; pulse shaping circuit 4100 in Fig. 41; harmonic enhancement module 4602 in Fig. 46; signal shaper 5010 in Fig. 50; harmonic enhancement module 5124 in Fig. 51B-C; pulse shaper 5310 in Fig. 53; pulse shaper 5438 in Fig. 54A; pulse shaper 5438 in Fig. 55; pulse shaper 5632 in Fig. 56; pulse shaping circuit 5722 in Fig. 57A-C, pulse shaper 6216 in Fig. 62; pulse shaper 7812 in Fig. 78; and equivalents thereof 

’50

“aperture generation means ... for generating a string of multiple pulses from said string of pulses” 

Function: generating a string of 

multiple pulses from said string of pulses Structure: the aperture generation 

module 7806 shown in Fig. 79 and described at 49:54-50:5; and equivalents thereof. 

Function: generating a string of multiple pulses from said string of pulses Structure: aperture generation module 7806 in Fig. 78 having gate(s) and delay(s) such as the aperture generation module shown in Fig. 79; and equivalents thereof 

’50

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Claim Term Intel’s Proposal ParkerVision’s Proposal Pa

Cl

“generating a string of multiple pulses from said string of pulses” 

“generating a signal with multiple the number of pulses as said string of pulses” 

Plain and ordinary meaning ’50

“gating means for gating a bias signal under the control of said string of multiple pulses to generate a periodic signal having a plurality of harmonics at least one of which is at a desired frequency” 

Function: gating a bias signal under 

the control of said string of multiple pulses to generate a periodic signal having a plurality of harmonics at least one of which is at a desired frequency Structure: switch 2816 shown in 

Fig. 28A and described at 35:14-36:24 and 45:47-46:37; GaAsFET 2901 shown in Fig. 29A and described at 36:25-50; GaAsFETs 3002 and 3004 shown in Fig. 30A and described at 36:25-50; switch 5312 shown in Fig. 53 and described at 58:63-59:13, switch 5636 shown in Fig. 56 and described at 60:66-61:10; switch 5420 shown in Fig. 54A and described at 60:1-22; switch 5724 shown in Figs. 57A-B and described at 65:49-55; and equivalents thereof. 

Function: gating a bias signal under the control of said string of multiple pulses to generate a periodic signal having a plurality of harmonics at least one of which is at a desired frequencyStructure: the switches shown in Fig. 28A, 29A, 30A, 31A, 32A, 33A, 53, 54A, 55, 56, 57A-C; and equivalents thereof 

’50

“gating” “opening and closing a device to 

selectively output a signal” 

“changing between the open and closed states of a switch, as dictated by an independent control input” 

’50

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Claim Term Intel’s Proposal ParkerVision’s Proposal Pa

Cl

“bias signal” “a signal having a fixed voltage or 

fixed current” 

“1) a signal having a steady, predetermined level; or 2) the modulating baseband signal” 

’50’10

“control signal” “an oscillating signal that controls 

the first switch with a frequency that is a sub-harmonic of and lower than the desired output frequency” 

Plain and ordinary meaning ’10

“third switch” “a switch controlling whether the 

antenna transmits said signal” 

Plain and ordinary meaning, or “switch” as construed by the Court in Case No. 6:20-cv-108 

’10

“pulse shaper” “a circuit configured to enhance a 

desired harmonic by shaping an oscillating signal” 

“circuitry that shapes an oscillating signal to generate a string of pulses” 

’10

Case 6:20-cv-00562-ADA Document 45 Filed 05/17/21 Page 14 of 16
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Dated: May 17, 2021 

/s/ Raymond W. Mort, III 

Respectfully submitted, 

/s/ J. Stephen Ravel 

Raymond W. Mort, III 

Texas State Bar No. 00791308 

THE MORT LAW FIRM, PLLC 

100 Congress Ave. Suite 2000 

Austin, Texas 78701 

Tel/Fax: 512-865-7950 

Of Counsel: 

Ronald M. Daignault (pro hac vice)* 

Chandran B. Iyer (pro hac vice) 

Jason S. Charkow (pro hac vice)* 

Stephanie R. Mandir (pro hac vice) 

rdaignault@daignaultiyer.com 

cbiyer@daignaultiyer.com 

jcharkow@daignaultiyer.com 

smandir@daignaultiyer.com 

DAIGNAULT IYER LLP 

8200 Greensboro Drive, Suite 900 

Mclean, VA 22102 

*Not admitted in Virginia

ATTORNEYS FOR PARKERVISION, 

INC. 

J. Stephen Ravel 

KELLY HART & HALLMAN LLP 

Texas State Bar No. 16584975 

303 Colorado, Suite 2000 

Austin, Texas 78701 

T (512) 495-6429 

steve.ravel@kellyhart.com 

James E. Wren 

Texas State Bar No. 22018200 

1 Bear Place, Unit 97288 

Waco, Texas 76798 

T (254) 710-7670 

james.wren@baylor.edu 

Michael J. Summersgill (pro hac Vice) 

Sarah B. Petty (pro hac vice) 

Marissa A. Lalli (pro hac vice) 

Wilmer Cutler Pickering Hale and Dorr LLP 

60 State Street 

Boston, Massachusetts 02109 

T (617) 526-6000 

michael.summersgill@wilmerhale.com 

sarah.petty@wilmerhale.com 

marissa.lalli@wilmerhale.com 

Todd Zubler (pro hac vice) 

Wilmer Cutler Pickering Hale and Dorr LLP 

1875 Pennsylvania Avenue NW 

Washington, DC 20006 

T (617) 526-6000 

todd.zubler@wilmerhale.com 

Jason F. Choy (pro hac vice) 

Wilmer Cutler Pickering Hale and Dorr LLP 

350 S. Grand Avenue, Suite 2400 

Los Angeles, California 90071 

T (213) 443-5300 

jason.choy@wilmerhale.com 

ATTORNEYS FOR DEFENDANT 

INTEL CORPORATION 

Case 6:20-cv-00562-ADA Document 45 Filed 05/17/21 Page 15 of 16
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CERTIFICATE OF SERVICE 

I hereby certify that all counsel of record are being served with a copy of the foregoing 

document via the Court’s CM/ECF system per Local Civil Rule CV-5(b)(1) on May 17, 2021. 

/s/ J. Stephen Ravel 

J. Stephen Ravel 

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