# Patent

## Title
Networking methods and systems

## Abstract

A network system includes integrated radio transceivers and digitizers, integrated baseband processors and device controllers, digital interfaces there between, and architectures and partitions for same. Licensing methodologies are provided for implementing the features described herein, and for other products and services.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to wireless networking devices and, more particularly, to wireless networking devices in compliance with Institute of Electrical and Electronics Engineers (IEEE) 802.11 standards.
2. Related Art
There is a need for greater integration of functions in networking methods and systems. There is also a need for digital interfaces between components in networking systems. There is also a need for improved licensing methodologies to transfer technology between entities in order to increase integration and implement digital interfaces.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to integrated radio transceivers and digitizers, integrated baseband processors and device controllers, digital interfaces there between, and to licensing methodologies for same.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.



BRIEF DESCRIPTION OF THE FIGURES
The present invention will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.
FIG. 1 is a block diagram of a wireless networking system 100 including an antenna system 128, a radio transceiver 102, an interface module 106, and a controller 104.
FIG. 2 is a block diagram of a network system 200, wherein the digitizer 108 is integrated with the transceiver 102 in an integrated transceiver/digitizer 202.
FIG. 3A is a block diagram of a network system 300, wherein the baseband processor 110 and MAC 112 are integrated with the controller 104 in an integrated BBP/MAC/Controller 304.
FIG. 3B is a block diagram of a network system 320, wherein the baseband processor 110 is integrated with the transceiver 102 and the digitizer 108, in an integrated transceiver/digitizer/BBP 322.
FIGS. 4A illustrates a licensing methodology according to an embodiment of the present invention.
FIGS. 4B illustrates an example licensing scenario according to an embodiment of the present invention.
FIG. 5 is an example detailed block diagram of the transceiver 102.
FIG. 6 is an example block diagram of the interface module 106.
FIG. 7 is an example pin-layout representation of the interface module 106.
FIG. 8 is an example block diagram of the controller 104.
FIG. 9 is a block diagram of the integrated transceiver/digitizer 202.
FIG. 10 is a block diagram of the integrated BBP/MAC/controller 304
FIG. 11 is an example detailed block diagram of the integrated BBP/MAC/controller 304.
FIG. 12 illustrates another licensing methodology according to an embodiment of the present invention.
FIG. 13 illustrates another licensing methodology according to an embodiment of the present invention.
FIG. 14 illustrates another example licensing scenario according to an embodiment of the present invention.
FIGS. 15 illustrates example products generated in the course of performance of the licensing methodologies of FIGS. 4A, 12, and/or 13.
FIG. 16 also illustrates example products generated in the course of performance of the licensing methodologies of FIGS. 4A, 12, and/or 13.
FIG. 17 is an example block diagram of a bi-directional implementation of a digital interface in accordance with an aspect of the invention.
FIG. 18 is another example block diagram of a bi-directional implementation of a digital interface in accordance with an aspect of the invention.



DETAILED DESCRIPTION OF THE INVENTION










Table of Contents


















I.
Introduction




A. Wireless Networking Systems




B. Technology Licensing Methodologies



II.
Wireless Networking Systems




A. Radio Transceiver and Analog Interface




B. Interface Module




  1. Digitizer




  2. Baseband Processor




  3. MAC




C. Controller



III.
Integrated Radio Transceivers and Digitizers



IV.
Integrated Baseband Processors, MACs, and Controllers



V.
Digital Interfaces and Digital Interface Circuitry



VI.
Additional Applications



VII.
Technology Licensing Methodologies



VIII.
Conclusion










I. Introduction

The present invention is directed to integrated radio transceivers and digitizers, integrated baseband processors and device controllers, digital interfaces there between, architectures and partitions for same, to licensing methodologies for same, and for other products and services.
A. Wireless Networking Systems
FIG. 1 is a block diagram of a wireless networking system 100, including an antenna system 128, a radio transceiver (“transceiver”) 102, an interface module 106, and a controller 104. The transceiver 102 alternatively represents a combination of receiver(s) and transmitter(s). The wireless networking system 100 interfaces between a shared medium, illustrated here as a radio frequency (“RF”) medium, and a device 140. The device 140 can be one or more of a variety of devices, including, without limitation, a computer, a printer, or other electronic devices. The wireless networking system 100 includes a receive path and a transmit path, as described below.
A high level operational description of the networking system 100 is now provided. On the receive side, the transceiver 102 receives an RF signal 132 through the antenna system 128. The RF signal 132 originates from a remote transceiver or other source. The transceiver 102 down-converts the RF signal 132 to baseband analog signals 122, which are provided to the interface module 106. The interface module 106 digitizes and decodes the analog baseband signals 122, and formats the resultant information for the controller 104. The interface module 106 provides the formatted information to the controller 104 through an interface 120. The controller 104 controls and/or enables the device 140 to take appropriate action. On the transmit side, the device 140 communicates to the remote transceiver or other destination through the controller 104, the interface module 106, and the direct-conversion radio transceiver 102, in a similar fashion.
The wireless network system 100 is now described in detail. The transceiver 102 is preferably a direct-conversion radio transceiver. Throughout the remainder of this disclosure, therefore, the transceiver 102 is interchangeably referred to as a direct-conversion radio transceiver 102. The direct-conversion radio transceiver 102 can be any of a variety of direct-conversion radio transceivers, existing now or developed in the future. For example, and without limitation, the direct-conversion radio transceiver 102 can be implemented as a direct-conversion radio transceiver disclosed in one or more of the following:
U.S. Pat. No. 6,061,551, titled, “Method and System for Down-Converting Electromagnetic Signals;”
U.S. Pat. No. 6,091,940, titled, “Method and System for Frequency Up-Conversion;” and
U.S. application Ser. No. 09/550,642, titled, “Method and System for Down-Converting an Electromagnetic Signal, and Transforms for Same,” filed Apr. 16, 1999.
All of which are incorporated herein by reference in their entireties. Alternatively the radio transceiver 102 is implemented with other direct conversion technology and/or combinations thereof.
The direct-conversion radio transceiver 102 frequency down-converts RF signals 132 from an RF frequency to an intermediate or baseband frequency in essentially a single step or process. The direct-conversion radio transceiver 102 preferably up-converts baseband signals for transmission in essentially a single step or process as well. The direct-conversion radio transceiver 102 optionally demodulates and/or modulates as part of the frequency conversion process. The direct-conversion radio transceiver 102 differs from conventional heterodyne transceivers in that heterodyne transceivers perform frequency conversion incrementally over multiple intermediate frequency (“IF”) stages, where each IF stage includes associated filtering and/or amplification.
The transceiver 102 interfaces with the interface module 106 through a combination analog/digital interface 114. More specifically, the transceiver 102 provides analog signals 122 to the interface module 106, and receives analog signals 124 from the interface module 106. The analog signals 122 include down-converted in-phase (“I”) and quadrature-phase (“Q”) baseband receive signals. Similarly, the analog signals 124 include I and Q baseband transmit signals, which are to be up-converted for transmission through the antenna system 128. The analog signals 122 and/or 124 optionally include one or more analog control signals. The transceiver 102 also sends and/or receives digital signals 126 to/from the interface module 106. The digital signals 126 can include, for example, timing and/or control signals.
The interface module 106 converts between the analog signals 122 and 124 on the transceiver 102 side, and digital packetized data on the controller 104 side. The interface module 106 includes a digitizer 108, a baseband processor 110, and a medium access controller (“MAC”) 112. The digitizer 108 receives the analog signals 122, from the radio transceiver 102, and digitizes them. The digitizer provides digitized I and Q receive signals 116 to the baseband processor 110. The digitizer 108 also receives digital I and Q baseband transmit signals 130 from the baseband processor, converts them to the I and Q analog transmit signals 124, and provides them to the transceiver 102.
The baseband processor 110 performs one or more of a variety of processes on the digitized I and Q receive signals 116. The processes can include, without limitation, timing recovery, carrier recovery, filtering, signal conditioning, equalization, gain adjustments, error correction, decoding, demodulation, and the like. Resultant data is provided to the MAC 112 through an interface 118.
The baseband processor 110 receives transmit data from the MAC 112 through the interface 118. The baseband processor 110 performs one or more of a variety of processes on the transmit signals. The processes can include, without limitation, encoding, filtering, and modulation. The baseband processor 110 provides the resultant digital I and Q transmit data 130 to the digitizer 108 for conversion to the I and Q analog transmit signals 124.
The MAC 112 arbitrates access between the shared RF medium and the device 140. The MAC 112 preferably includes one or more devices and/or functions (e.g.; software) in accordance with IEEE 802.11 standards, incorporated herein by reference in their entirety. IEEE 802.11 is described in a number of publicly available documents, such as, for example, O'Hara and Petrick, “802.11 Handbook—A Designer's Companion,” Standards Information Network, IEEE Press, 1999, incorporated herein by reference in its entirety. The MAC 112 is commonly known as a link layer device. Functions performed by the MAC 112 can include, without limitation, network management, authentication, queing, data transmission and reception, error detection, and re-transmission.
The MAC 112 receives data from the baseband processor 110 through the interface 118 and formats (e.g., packetizes) the received data in accordance with requirements of the controller 104. The MAC provides the packetized digital data to the controller 104 via the interface 120. Similarly, the MAC 112 receives packetized data from the controller 104, decodes it, and provides the resultant data to the baseband processor 110 through the interface 118.
The analog I and Q signals 122 and 124 communicated between the transceiver 102 and the digitizer 108 tend to be noisy, and tend to have relatively low amplitudes and power levels. As a result, the transceiver 102 and the interface module 106 must typically be located relatively close to one another. This limits design options. It would be useful if the transceiver 102 and the interface module 106 communicated with one another through an all-digital digital interface, or substantially all-digital interface, because it would allow the direct-conversion radio transceiver 102 and the interface module 106 to be located remote to one another (i.e., positioning can be determined independently of one another). Accordingly, the present invention provides a digital interface between the transceiver 102 and the interface module 106.
FIG. 2 is a block diagram of a network system 200, wherein the digitizer 108 is partitioned or integrated with the transceiver 102 in an integrated transceiver/digitizer 202. The integrated transceiver/digitizer 202 is preferably implemented in a monolithic package such as a multi-chip module (“MCM”) or integrated circuit (“IC”). All, or substantially all of the analog signals 122 and 124 are thus contained within the integrated transceiver/digitizer 202. This allows the integrated transceiver/digitizer 202 to interface with the interface module 206 through a digital interface 208. The digital interface 208 can be a serial bus, a multiplexed bus, a parallel bus, a direct connection, and/or combinations thereof. Example implementations of the digital interface 208 are described below with respect to FIGS. 18 and 19, for example.
The digital interface 208 allows the integrated transceiver/digitizer 202 to be positioned remote (independently) from interface module 206. For example, the integrated transceiver/digitizer 202 can be located near the antenna system 128 and the interface module 206 can be located near the controller 104, and/or in any other convenient location. Additional details of this aspect of the invention are described below
It would also be useful to reduce the number of pin inter-connections in network systems. Referring back to FIG. 1, the interface module 106 typically includes approximately 300 pins for interfacing between the transceiver 102 and the controller 104. FIG. 7 is an example pin-layout representation of the interface module 106, including approximately 257 pins. A first set of pins 702 interface with the radio transceiver 102. The first set of pins 702 corresponds to the interface 114. A second set of pins 704 interface with the controller 104. The second set of pins 704 corresponds to the interface 120. It would be useful to reduce the number of pins. Accordingly, the present invention provides integration designs that reduce the number of pins. This is described below with respect to FIGS. 3A and 3B.
FIG. 3A is a block diagram of a network system 300, wherein the baseband processor 110 and MAC 112 are partitioned with and/or integrated with the controller 104 in an integrated BBP/MAC/Controller 304. As a result of the integration, the second set of pins 704 that were previously required to couple the interface module 106 to the controller 104 are essentially eliminated. The reduces system-integration effort and thus integration costs, as well as providing other advantages that will be apparent to persons skilled in the art. The integrated BBP/MAC/Controller 304 is preferably implemented within a monolithic package, preferably, but not limited to, a single IC.
In the example of FIG. 3A, the digitizer 108 is integrated with the radio transceiver 102, as described above with respect to FIG. 2. Alternatively, the digitizer 108 is not integrated with the radio transceiver 102.
Another advantage provided by the network system 300 relates to quantity discount pricing. For market-based reasons, controller designers/manufactures typically fabricate, or order the fabrication of relatively large numbers of controllers integrated circuits (“ICs”). The cost per IC typically decreases with increasing order size. Interface module designers/manufactures, on the other hand, typically fabricate, or order the fabrication of relatively small numbers of interface module ICs. Fabrication costs per IC typically decrease with increasing order sizes. As a result, when the baseband processor 110 and the MAC 112 are integrated with the controller 104, quantity pricing associated with the controller 104 can be extended to the baseband processor 110 and the MAC 112.
The present invention includes other partition/integration configurations as well. For example, FIG. 3B is a block diagram of a network system 320, wherein the transceiver 102, the digitizer 108, and the baseband processor 110 are integrated in a transceiver/digitizer/BBP 322. The integrated transceiver/digitizer/BBP 322 is preferably implemented as a multi-chip module or an integrated circuit. The integrated transceiver/digitizer/BBP 322 interfaces with the MAC 112 through a digital interface 324. Other particular options are possible, depending on a number of factors, such as available fabrication technologies, available bill of material cost, allocation, customer preference, etc.
B. Technology Licensing Methodologies
The present invention also relates to methods for licensing technology between designers/manufactures of transceivers, interface modules, and controllers. In practice, transceivers, interface modules, and device controllers are typically designed and/or manufactured by different entities. As a result, there is an inherent inertia that inhibits the type of cooperation needed to identify the problems and implement the technology transfers needed to implement the inventions described herein. The inventors of the present invention are skilled in a number of technology fields. These skills have enabled them to identify and solve technology issues described herein. In order to facilitate technology transfers described herein, the inventors have also devised licensing methodologies as described below with respect to FIGS. 4, and 12-17.
II. Wireless Networking Systems
Details of the networking system 100, illustrated in FIG. 1, are now described.
A. Radio Transceiver and Analog Interface
FIG. 5 is an example detailed block diagram of the transceiver 102. The transceiver 102 includes a Tx/Rx switch 502 that selectively operates the transceiver 102 in a receive mode or a transmit mode. The Tx/Rx switch 502 is controlled by a digital transmit/receive control signal 126e. The Tx/Rx switch 502 is illustrated in the receive mode. In the receive mode, the RF signal 132 (FIG. 1) is received by the antenna system 128, filtered in a bandpass filter 504, and down-converted in a receive signal path 510. In the example of FIG. 5, the receive signal path 510 includes a low noise amplifier (“LNA”) 506, an automatic gain control (“AGC”) module 508, I/Q direct down-converters 512, and receive analog circuitry 514. The LNA 506 is controlled by a LNA gain control signal 126b, which is typically a digital signal. The AGC module 508 is controlled by a Rx-AGC signal 124c, which is typically an analog signal. The receive analog circuitry 514 can include, for example, and without limitation, filters, amplifiers, AGCs, D.C. offset controls, and the like. The receive, signal path 510 outputs baseband analog I and Q signals I-Rx 122a and Q-Rx 122b, respectively, which are provided to the digitizer 108.
In a transmit mode, analog I and Q transmit signals I-Tx 124a and Q-Tx 124b, respectively, are received from the digitizer 108. The I and Q transmit signals I-Tx 124a and Q-Tx 124b are up-converted in a transmit signal path 516, filtered in the bandpass filter 504, and provided to the antenna system 128. In the example of FIG. 5, the transmit signal path 516 includes transmit analog circuitry 518, I/Q direct up-converters 520, one or more filters 522, 524, and a programmable amplifier 526. The transmit analog circuitry 518 receives a transmit level control signal 124d, which, in the example of FIG. 5, is an analog signal. Alternatively, the transmit level control signal 124d is a digital signal.
The transceiver 102 optionally includes a diversity switch 528 controlled by a digital diversity antenna selection signal 126a. The diversity switch selectively activates/deactivates portions of the antenna system 128.
The transceiver 102 further includes one or more frequency synthesizers 532 that receive a reference clock 534 from an oscillator 530, and a programming interface signal 126c. The oscillator 530 also provides one or more reference clocks 126d to the baseband processor 110. Based on the description herein, construction and operation of the components within the transceiver 102 will be understood by those skilled in the relevant art(s).
In summary, in the example of FIG. 5, the interface 114 includes at least the following analog signals:

    
    
        baseband analog I and Q signals I-Rx 122a and Q-Rx 122b, respectively;
        baseband analog I and Q transmit signals I-Tx 124a and Q-Tx 124b; 
        Rx-AGC signal 124c; and
        transmit level control signal 124d. 
    
    


In addition, one or more of tie following nominally digital signals may instead be analog signals:

    
    
        diversity antenna selection signal 126a; 
        LNA gain control signal 126b; 
        programming interface signal 126c; 
        reference clock 126d; and
        transmit/receive control signal 126e. 
    
    


Because of the relatively low signal strength, noise, and other factors associated with analog signals, the transceiver 102 and the interface module 106 must typically be physically positioned relatively close to one another. In practice, transceivers, interface modules, and/or communication networks are typically designed, manufactured, and/or integrated by different entities. The physical positioning requirement between the transceiver 102 and the interface module 106, therefore, requires that the different entities coordinate with one another during design, manufacturing, and/or integration of the network system 100. This is cumbersome and adds additional costs to the network system 100. Accordingly, the present invention provides methods and systems for digitally interfacing between transceivers and interface modules. This reduces the level of coordination required between the different entities and thus, reduces costs associated with network systems.
B. Interface Module
1. Digitizer
FIG. 6 is an example block diagram of the interface module 106, wherein the digitizer 108 receives the baseband analog I and Q signals I-Rx 122a and Q-Rx 122b, respectively, and outputs the baseband analog I and Q transmit signals I-Tx 124a and Q-Tx 124b, respectively, the Rx AGC signal 124c, and the transmit level control signal 124d. The digitizer 108 is illustrated with analog-to-digital converters (“ADCs”) 602 and digital-to-analog converters (“DACs”) 604. The ADCs 602 and the DACs 604 can be implemented with any of a variety of designs including, without limitation, comparators.
The remaining digital signals, including diversity antenna selection signal 126a, LNA gain control signal 126b, programming interface signal 126c, and reference clock 126d, and transmit/receive control signal 126e, are communicated between the transceiver 102 and the baseband processor 110 without passing through the digitizer 108.
2. Baseband Processor
The baseband processor 110 includes a receive path 606 and a transmit path 608. The receive path 606 receives digitized baseband I and Q signals 610 and 612, respectively, which are filtered by I and Q receive filters 614 and 616, respectively. Filtered I and Q signals 618 and 620 are demodulated and optionally equalized in a demodulator/equalizer 622. A demodulated baseband signal 624 is decoded by a decoder 626, the output of which is provided to a descrambler 628. The output of the descrambler 620 is provided to a receive MAC interface 630, which outputs receive data 632 to the MAC 112.
In the transmit path 608, a transmit MAC interface 636 receives transmit data 634 from the MAC 112. The transmit MAC interface 636 outputs transmit data 638 to a PLCP interface 640, which outputs transmit data 642 to a scrambler 644. The scrambler 644 outputs transmit data 646 to an encoder 648, which outputs I and Q transmit data 650 and 652, respectively, to I and Q transmit filters 654 and 656, respectively. The I and Q transmit filters 654 and 656 output I and Q transmit data 658 and 660, respectively, to DACs 604b and 604c, which convert the I and Q transmit data 658 and 660 to analog I and Q transmit signals 124a and 124b, respectively.
3. MAC
The MAC 112 receives the receive data 632 from the baseband processor 110 and reformats the receive data 632 according to requirements of the controller 104. The MAC 112 typically reformats the receive data 632 into packet-based data for transmission to the controller 104. The MAC 112 provides the reformatted receive data to the controller 104 through a host interface 662 and through the interface 120. An example of the interface 120 is represented by the second set of pins 704 in FIG. 7, as described above.
The MAC 112 receives transmit data from the controller 104 through the host interface 662, and reformats the transmit data according to requirements of the baseband processor 110. The MAC 112 typically de-packetizes the transmit data, and provides the de-packetized data to the baseband processor 110 as the transmit data 634.
C. Controller
The controller 104 can be any of a variety of controllers, including, without limitation, printer controllers and the like, or other electronic/data processing devices. FIG. 8 is an example block diagram of the controller 104.
The controller 104 communicates with the interface module 106 through the interface 120, using a packet-based format.
III. Integrated Radio Receivers and Digitizers
Integration of the transceiver 102 and the digitizer 108 is now described. FIG. 9 is a block diagram of the integrated transceiver/digitizer 202, wherein the digitizer 108, including the ADCs 602 and the DACs 604, are integrated with the transceiver 102. The transceiver 102 and the digitizer 108, as illustrated in FIG. 9, operate substantially as described above with respect to FIGS. 5 and 6. The integrated transceiver/digitizer 202 interfaces with the baseband processor 108 through the digital interface 208. In the example of FIG. 9, integrated transceiver/digitizer 202 further includes transceiver-side digital interface circuitry 902, which is described below with respect to FIG. 18. The transceiver-side digital interface circuitry 902 can be considered part of the digital interface 208. It is noted that, in embodiments, the digital interface 208 and the transceiver-side digital interface circuitry 902 are substantially all-digital, but not necessarily all digital.
IV. Integrated Baseband Processors, MACs, and Controllers
Integration of the baseband processor 108, the MAC 112, and the controller 104 is now described. FIG. 10 is a block diagram of the integrated BBP/MAC/controller 304 (FIG. 3A). In FIG. 10, the baseband processor 108 and the MAC 112 interface with the controller 104 via an internal system bus 1002.
FIG. 11 is an example detailed block diagram of the integrated BBP/MAC/controller 304. In FIG. 11, the BBP/MAC/controller 304 of FIG. 8 is modified to include an internal cell 1102, which includes the baseband processor 110, the MAC 112, and internal I/O circuitry. The internal I/O circuitry can include, for example, controller-side digital interface circuitry associated with the digital interface 208, as described below with respect to FIG. 18. The internal bus 1002 interfaces the cell 1102, and other interface cells, with a central processing unit 1104. The integrated BBP/MAC/controller 304 interfaces with the digitizer 108, which is preferably, but not necessarily, integrated with the transceiver 102, through the digital interface 208.
V. Digital Interfaces and Digital Interface Circuitry
The digital interface 208 (FIGS. 2, 3A, 9, 10, and 11), can include one or more of a serial bus, a multiplexed bus, a parallel bus, a direct connection, and/or combinations thereof. A multiplexed bus digital interface 208 can be synchronous or non-synchronous. The digital interface 208 can also include digital interface circuitry, as now described.
FIGS. 17 and 18 are example block diagrams of a bi-directional implementation of digital interface 208. More specifically, FIG. 17 is an example block diagram of a bi-directional implementation of digital interface 208, including the transceiver-side digital circuitry 902 from FIG. 9. FIG. 18 is an example block diagram of a bi-directional implementation of the digital interface 208, including controller-side digital interface circuitry 1802 within the internal cell 1102 of FIG. 11.
In FIG. 17, the transceiver-side digital interface circuitry 902 includes a plurality of latches 1702, a bi-directional bus driver 1704, and an address control and timing circuit 1706. The transceiver-side digital interface circuitry 902 can be considered as part of the digital interface 208. The digital interface 208 further includes a bus 1708. The bus 1708 can be designed with a bandwidth that is suitable for a sample rate and/or symbol rate associated with the transceiver 102.
In operation, in the transmit path, digital data from the baseband processor 110 is presented to the bi-directional bus driver 1704 from the bus 1708. At an appropriate time, the address control and timing circuits 1706 control the bi-directional bus driver 1704 to present the digital data to an essentially parallel bus 1710, which presents the digital data to each of the latches 1702. The address control and timing circuits 1706 then control a selected one of the latches 1702 to pass the digital data through the selected latch.
Similarly, in the receive path, digital receive data is presented to the latches 1702d and 1702e from the analog-to-digital converters 602a and 602b, respectively. The address control and timing circuits 1706 control a selected one of the latches 1702d and 1702e to pass the digital data through the selected latch and onto the parallel bus 1710. The address control and timing circuits 1806 then control the bidirectional bus driver 1704 to pass the digital receive data through to the bus 1708.
In FIG. 18, the controller-side digital interface circuitry 1802 operates in a fashion similar to that of the digital interface circuitry 902, as will be apparent to one skilled in the relevant art(s), based on the description herein.
In an embodiment, the controller-side digital interface circuitry 1802 includes similar components as digital interface circuitry 902, including a plurality of latches, a bi-directional bus driver, and an address control and timing circuit. In an embodiment, a plurality of latches are coupled between the bi-directional bus driver and the baseband processor (BBP) and medium access controller (MAC).
VI. Additional Applications
Based on the description herein, one skilled in the relevant art(s) will understand that the present invention can be implemented in a variety of radio applications. For example, and without limitation, the present invention can be implemented with telephones, telephone base stations, positioning units, communication networks, pagers, security systems, repeaters, mobile radios, cellular telephones, satellite communications, computer, computer peripherals, home devices, automobiles, such as automobile radio receivers and/or transceivers, aircraft, boats, radio controlled devices, and the like.
The present invention can be implemented in applications described in U.S. patent application Ser. No. 10,086,250, titled, “Applications of Universal Frequency Translation,” filed Mar. 4, 2002, incorporated herein by reference in its entirety.
The controller 104 can represent digital circuitry other than packet-based circuitry. For example, and without limitation, the controller 104 can represent a digital controller for an automobile radio, or the like.
VII. Technology Licensing Methodologies
Flowchart 402 of FIG. 4A depicts a licensing methodology in accordance with an embodiment of the present invention. Flowchart 402 shall be described with reference to an example licensing scenario 420 shown in FIG. 4B. Flowchart 402 begins with step 404, where control immediately passes to step 406.
In step 406, a licensor 422 develops and/or obtains the rights to a primary technology 434. The primary technology 434 can represent any intangible or tangible technology-related object, including but not limited to any know-how, trade secret, product, apparatus, component, system, schematic, layout, plan, architecture, mathematical model, data, formulae, algorithm, method, guideline, practice, prototype, cell library, core, semiconductor topography, report as well as any tool, software, firmware and/or hardware, and/or any portion(s) or combinations portions thereof, and/or any intellectual property right relating thereto. The primary technology 434 may or may not be subject to one or more patents and/or patent applications. The licensor 422 has rights to license and/or otherwise grant access to the primary technology 434 to third parties, although the licensor 422 may or may not own the primary technology 434, and may or may not have developed the primary technology 434.
In step 408, the licensor 422 develops and/or obtains rights to secondary technology 424. The secondary technology 424 can represent any intangible or tangible object, including but not limited to any know-how, trade secret, product, apparatus, component, system, schematic, layout, plan, architecture, mathematical model, data, formulae, algorithm, method, guideline, practice, prototype, cell library, semiconductor topography, report as well as any tool, software, firmware and/or hardware, and/or any portion(s) or combinations portions thereof, and/or any intellectual property right relating thereto. The secondary technology 424 may or may not be subject to one or more patents and/or patent applications. The licensor 422 has rights to license and/or otherwise grant access to the secondary technology 424 to third parties, although the licensor 422 may or may not own the secondary technology 424, and may or may not have developed the secondary technology 424. In the example FIG. 4B, the secondary technology 424 is operable with the primary technology 434.
With reference to FIG. 4B, consider an example scenario where the licensor 422 is trying to introduce the primary technology 434 (and possibly the secondary technology 424) into a market where competing technologies exist. (It is noted that reference is made to this example for illustrative purposes only, and is not limiting.) Such competing technologies may have already been adopted by customers to some extent. Some of these customers may have incorporated these competing technologies into their products, or may be in the process of doing so. Accordingly, there is inertia with such customers to continue to use the competing technologies. Such inertia makes it difficult for the licensor 422 to convince customers to use the primary technology 434, because doing so would involve some expense on the part of customers to transition to the primary technology.
In the licensing methodology of FIG. 4A, according to an embodiment of the invention, the licensor 422 uses the secondary technology 424 to help overcome such inertia.
In particular, in step 410, the licensor 422 uses the secondary technology 424 to help enhance and promote the market for the primary technology 434. In an embodiment, in step 410, the licensor 422 provides the secondary technology 424 to licensee 426 via a license agreement 425 containing terms favorable to the licensee 426. By doing so, the licensee 426 is more likely to use secondary technology 424 in its applications. Once the licensee 426 has adopted secondary technology 424 for its applications, licensee 426 is also more likely to use primary technology 434 for its applications, since primary technology 434 is operable with secondary technology 424. Also, once licensee 426 begins using the secondary technology 424, there may be a number of additional advantages for also using primary technology 434. Thus, in step 410, by encouraging the licensee 426 to use the secondary technology 424 in its applications, licensor 422 is also able to encourage the licensee 426 to use the primary technology 434 for the licensee 426's applications.
There are any number of ways for the licensor 422 to provide favorable terms in the license agreement 425 to the licensee 426 in step 410. For example, the licensor 422 may license the secondary technology 424 to the licensee 426 in accordance with a payment structure favorable to the licensee 426. In the example of FIG. 4B, the licensee 426 is shown as paying a first licensee fee 446 to the licensor 422 in exchange for access to secondary technology 424. In an embodiment, the first license fee 446 could be relatively low (given the market). For example, the first license fee 446 may comprise an access fee coupled with periodic royalty payments. In an embodiment, the access fee is set at a relatively low level (relative to the market for comparable intellectual property), and may be payable over time, and the periodic royalty payments are also set at a low level, or are waived altogether. Other favorable payment structures will be apparent to persons skilled in the relevant art(s).
There are other ways for the licensor 422 to provide favorable terms in the license agreement 425 to the licensee 426 in step 410. For example, the licensor 422 can structure the license agreement 425 so that options to access other fields of use, or options to access other geographical areas, or volume discounts, may vest at relatively low thresholds. Other ways that favorable license terms can be provided to licensee 426 in step 410 will be apparent to persons skilled in the relevant art(s).
As described above, the license agreement 425 includes a first license fee 446 that is paid by the licensee 426 to enable the licensee 426 to access and have rights to the secondary technology 424. In an embodiment, the licensee agreement 425 also provides for other license fees that are a function of the manner in which the licensee 426 bundles the secondary technology 424 with other technology, or are a function of the manner in which the licensee 426 enables access to the secondary technology 424 by third parties 442. The licensor 422 can further encourage the licensee 426 to purchase and utilize the primary technology 434 by structuring the license agreement 425 so that such additional licensee fees are lower if the licensor 422 uses the primary technology 434, as opposed to other competing technologies 436. This is represented by steps 412, 414, and 416 in flowchart 402.
Accordingly, in step 412, if licensee 426 uses the licensor 422's primary technology 434 with the secondary technology 424, then the licensee 426 pays to the licensor 422 a second license fee 448. For example, the licensee 426 may use the secondary technology 424 to produce a product 438. Prior to selling the product 438, the licensee 426 may bundle, integrate, or otherwise couple the product 438 with the licensor 422's primary technology 434, such that the primary technology 434 operates with the secondary technology 434. In this case, the licensee 426 pays to the licensor 422 a second license fee 448 in step 412.
If, instead, the licensee 426 uses other technology 436 with the secondary technology 424 in the product 438, then the licensee pays a third license fee 450 to the licensor 422. The third license fee 450 is greater than the second license fee 448. For example, the licensee 426 may use the secondary technology 424 to produce a product 438. Prior to selling the product 438, the licensee 426 may bundle, integrate, or otherwise couple the product 438 with other technology 436, such that the primary technology 434 operates with the other technology 436. In this case, the licensee 426 pays to the licensor 422 the third license fee 450 in step 414.
There may be cases where the licensee 426 chooses not to couple either the primary technology 434 or other technology 436 to the secondary technology 424 in the product 438. However, the licensee 426 may enable access to the secondary technology 424 (via an access point 440, for example), such that a third party 442 can bundle, connect, integrate, or otherwise couple some technology 444 with the secondary technology 424. The technology 444 could include any technology, including the primary technology 434 and/or other technology 436. If the licensee 426 enables such access to the secondary technology 424 in the product 438, then the licensee 426 is obligated in step 416 to pay a fourth license fee 432 to the licensor 422. The fourth license fee 432 is greater than the second license fee 448. The relationship of the third license fee 450 to the fourth license fee 432 (i.e., which is greater) is implementation dependent.
Accordingly, the licensee 426 pays the lowest license fee (i.e., the second license fee 448) by using the licensor 422's primary technology 434 with the secondary product 424. Through structuring the license agreement 425 in the manner just described, the licensor 422 can provide additional motivation and incentive for the licensee 426 to adopt the licensor 422's primary technology 434 and secondary technology 424.
As discussed above, the licensee 426 uses the secondary technology 424 to produce a product 438. FIG. 15 illustrates an example product 438. The product 438 includes secondary technology 424 and application technology 1502. The product 438 may also include an access point 440, as discussed above.
The application technology 1502 represents any intangible or tangible technology-related object (as defined above). The application technology 1502 includes functionality that is specific to the particular application of the product 438. For example, in the case where the product 438 is a printer (or component thereof), the application technology 1502 is a printer component, such as but not limited to a printer controller. In the case where the product 438 is a computer, the application technology 1502 is a computer component, such as but not limited to a computer controller (such as a microprocessor).
In an embodiment, in step 410 of FIG. 4A, the secondary technology 424 licensed by the licensor 422 to the licensee 426 comprises a synthesizable or compilable core software product representing one or more integrated circuit functions in one or more descriptor languages (such as, but not limited to, Verilog, VHDL, C, etc.). The secondary technology 424 can be synthesized or compiled using design tools, and can be instantiated in an integrated circuit design, in whole or in part, or used as machine instructions to a processor (hardware or software). The secondary technology 424 may also include other components, such as for example, associated design files and/or know-how.
Also, in an embodiment, the application technology 1502 similarly comprises a synthesizable or compilable core software product.
In an embodiment, the licensee 426 instantiates the application technology 1502 and the secondary technology 424 in an integrated circuit design, such that the application technology 1502 and the secondary technology 424 are embedded in one or more integrated circuits. This embodiment is referred to as an integrated solution, and is applicable in any integrated circuit operation or initiative. This embodiment is advantageous because it enables the licensee 426 to more efficiently and economically achieve high volumes of products 438, particularly when compared to non-integrated solutions. Accordingly, this integrated embodiment of the invention provides further incentive and motivation for the adoption of the licensor 422's primary technology 434 and the secondary technology 424, particularly in the context of the licensing methodology 402 of FIG. 4A.
The licensing methodology of the invention shall now be further described with reference to an example embodiment involving wireless products. The operation of this wireless licensing embodiment is illustrated in flowchart 1202 of FIG. 12. Reference in flowchart 1202 to wireless technology is for illustrative purposes only, and is not limiting. The invention is applicable to any technology, as will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.
Flowchart 1202 shall be described with reference to the example licensing scenario 420 shown in FIG. 4B, wherein primary technology 434 represents a wireless transceiver module, and the secondary technology 424 represents a baseband processor (BBP) and/or a media access controller (MAC). The transceiver module, baseband processor, and media access controller may be those described elsewhere herein, or may be others that are commercially available now or in the future.
In step 1206, the licensor 422 obtains rights to a transceiver module 434 (step 1206 corresponds to step 406 in FIG. 4A). In an embodiment, the transceiver module 434 is based on heterodyne communication technology. In an alternative embodiment, the transceiver module 434 is based on direct conversion technology. In an embodiment, the transceiver module 434 is implemented using D2D direct conversion technology from ParkerVision, Inc., of Jacksonville, Fla. D2D receivers, transmitters, and transceivers are described, for example, in the patents and patent applications referenced above, which are herein incorporated by reference in their entireties.
In step 1208, the licensor 422 obtains rights to BBP and/or MAC IP 424 (step 1208 is similar to step 408 in FIG. 4A). The BBP/MAC IP 424 is operable with the transceiver module 434.
In step 1210, to enhance the market of the licensor 422's transceiver module 434, the licensor 422 provides the BBP/MAC IP 424 to the licensee 426 at favorable-terms. Step 1210 corresponds to step 410 in FIG. 4A.
The licensee 426 uses the BBP/MAC IP 424 to produce a product 438. For example, the licensee 426 may instantiate the BBP/MAC IP 424 into a BBP/MAC module(s) in the product 438, in a manner that the BBP/MAC module(s) operates with other components in the product 438 (see, for example, FIG. 15 and the associated discussion above). Such design, development, and fabrication of the product 438 will be apparent to persons skilled in the relevant arts.
In step 1212, if the licensee 426 uses the licensor 422's transceiver module 434 with the BBP/MAC module 424 in the product 438, then the licensee 426 pays a second license fee 448 to the licensor 422. For example, if the licensee 426 integrates, combines, connects, couples, or otherwise provides the licensor 422's transceiver module 434 with the BBP/MAC module 424 in the product 438, then the licensee 426 pays a second license fee 448 to the licensor 422. Step 1212 corresponds to step 412 in FIG. 4A.
In step 1214, if the licensee 426 uses some other transceiver module 436 with the BBP/MAC module 424 in the product 438, then the licensee 426 pays a third license fee 450 to the licensor 422. For example, if the licensee 426 integrates, combines, connects, couples, or otherwise provides some other transceiver module 436 with the BBP/MAC module 424 in the product 438, then the licensee 426 pays a third license fee 450 to the licensor 422. Preferably, the third license fee 450 is lower than the second license fee 448. Step 1214 corresponds to step 414 in FIG. 4A.
If the licensee 426 does not couple any transceiver technology to the BBP/MAC module 424 in the product 438, but enables access to the BBP/MAC module 424 in the product 438 such that a third party 442 could couple a transceiver 444 or other device to the BBP/MAC module 424, perhaps via an access point 440, then in step 1216 the licensee 426 pays a fourth license fee 432 to the licensor 422. Preferably, the fourth license fee 432 is lower than the second license fee 448. Step 1216 corresponds to step 416 in FIG. 4A.
The wireless technology licensing example of the invention shall now be further described with reference to flowchart 1302 shown in FIG. 13. Flowchart 1302-shall be described with reference to the example licensing scenario 1402 shown in FIG. 14.
In step 1306, to enhance the market of the licensor 422's transceiver module 434, the licensor 422 licenses the BBP/MAC IP 424 to the licensee 426 at favorable terms. Step 1306 is similar to step 410 in FIG. 4A. In the example scenario 1402 of FIG. 14, the transceiver module 434 includes a second digital interface 1452A, an example of which is described elsewhere herein. It is noted that the interfaces 1450, 1452 are preferably digital interfaces, but may also comprise analog or hybrid (combinations of digital and analog) interfaces.
In step 1308, the licensee 426 uses the BBP/MAC IP 424 to produce a product 438. For example, the licensee 426 may instantiate, embed, integrate, install, couple, etc., the BBP/MAC IP 424 into a BBP/MAC module 1458 in the product 438, in a manner that the BBP/MAC module 1458 operates with other components in the product 438. FIG. 16 illustrates an example product 438 (reference is also made to FIG. 15 and the associated discussion above). Such design, development, and fabrication of the product 438 will be apparent to persons skilled in the relevant arts. The product 438 includes a first digital interface 1450 for enabling access to the BBP/MAC module 1458 from outside the product 438. An example of first digital interface 1450 is described elsewhere herein.
In step 1310, it is determined whether the licensee 426 has coupled a transceiver to the BBP/MAC module 1458 in the product 438 via the first digital interface 1450. More generally, it is determined whether the licensee 426 has coupled a second interface 1452 to the first digital interface 1450 in the product 438. If the licensee 426 has coupled some device to the BBP/MAC module 1458 in the product 438 via the first digital interface 1450, then step 1312 is performed.
In step 1312, it is determined whether the licensee 426 has coupled the licensor 422's transceiver module 434 to the BBP/MAC module 1458 in the product 438. Such coupling would have been achieved by coupling the second digital interface 1452A of the transceiver module 434 to the first digital interface 1450 of the BBP/MAC module 1458. If the licensee 426 has coupled the licensor 422's transceiver module 434 to the BBP/MAC module 1458 in the product 438, then step 1314 is performed. In step 1314, the licensee 426 pays a second license fee 448 to the licensor 422.
If, in step 1312, it is determined that the licensee 426 has coupled some other transceiver module 436 to the BBP/MAC module 1458 in the product 438, then step 1316 is performed. Such coupling would have been achieved by coupling the second digital interface 1452B of the transceiver module 436 to the first digital interface 1450 of the BBP/MAC module 1458. In step 1316, the licensee 426 pays a third license fee 450 to the licensor 422.
If, in step 1310, it is determined that the licensee 426 has not coupled a transceiver to the BBP/MAC module 1458 in the product 438 (or, more generally, has not coupled a second digital interface 1452 to the first digital interface 1450), then step 1318 is performed. In step 1318, it is determined whether the licensee 426 has enabled access to the BBP/MAC module 1458. Such access may be enabled, for example, by including and activating the first digital interface 1450 in the product 438. If the licensee 426 has enabled access to the BBP/MAC module 1458, then step 1320 is performed. In step 1320, the licensee 426 pays a fourth license fee 432 to the licensor 422.
Preferably, both the third license fee 450 and the fourth license fee 432 are greater than the second license fee 448. There are embodiments, however, when the second license fee 448 is equal to or greater than the third license fee 450 and/or the fourth license fee 432. For example, this may be the case where the licensor 422's transceiver module 434 is superior to other technologies, and/or has gained commercial success.
The discussion so far has focused on the license fees paid by the licensee 426 to the licensor 422. In some embodiments, however, the licensor 422 receives licensing revenue from other sources. For example, the licensor 422 may receive a fifth license fee 1456 and/or a sixth license fee 1454 from the parties who produce the other transceiver modules 436, 444 having the second digital interfaces 1452B, 1452C. This may be the case, for example, where the licensor 422 exerts control over the intellectual property related to the pertinent transceiver, BBP/MAC, and/or interface technologies through the use of patents, trade secrets, trademarks, or other vehicles or combinations thereof.
The use of the first digital interface 1450 and the second digital interface 1452 provides the present invention with additional advantages. For example, by using a digital interface, the transceiver 434, 436, or 444 can be positioned independent of the position of the BBP/MAC module 1458. This is described elsewhere herein in greater detail. Because of this advantage, there is additional incentive and motivation for the adoption of the licensor 422's BBP/MAC 424 and transceiver module 434.
In the example scenarios described above, the licensor 422 has access to at least two technologies, the primary technology 434 and the secondary technology 424 (see FIG. 4B). For example, with reference to FIG. 14, the licensor 422 has access to the transceiver module 434 and the BBP/MAC 424.
This illustrates another advantage of the invention. It is often the case that customers must interact with multiple suppliers to gain access to the technologies needed to design and implement a given product. Such suppliers may not cooperate with one another, and/or may not design their respective technologies for use with the technologies of others. Accordingly, customers are faced with the sometimes difficult tasks of acquiring the technologies, and then integrating the technologies for use with each other.
In contrast, according to the invention, the licensor 422 is a single source for the primary technology 434 and the secondary technology 424. Accordingly, it is much easier for customers to gain access to the primary technology 434 and the secondary technology 424, since they need only interface with the licensor 422. Also, in embodiments, the primary technology 434 is designed for easy and/or enhanced operation with the secondary technology 424. Thus, integration of the primary technology 434 with the secondary technology 424 is simplified. Also, performance advantages are gained by using the primary technology 434 with the secondary technology 424.
Thus, embodiments of the invention exhibit additional advantages to further encourage adoption of the licensor 422's primary technology 434 and secondary technology 424.
VIII. Conclusion
The present invention has been described above with the aid of functional building blocks illustrating the performance of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Any such alternate boundaries are thus within the scope and spirit of the claimed invention. One skilled in the art will recognize that these functional building blocks can be implemented by discrete components, application specific integrated circuits, processors executing appropriate software, and the like, and/or combinations thereof.
When used herein, the terms “connected” and/or “coupled” are generally used to refer to electrical connections. Such electrical connections can be direct electrical connections with no intervening components, and/or indirect electrical connections through one or more components.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

## Claims

1. A network system, comprising:
a direct conversion radio transceiver coupled to a digitizer, integrated within a first integrated device;
a medium access controller coupled between a baseband processor and digital control circuitry, integrated within a second integrated device; and
a digital interface that couples said first integrated device to said second integrated device;
wherein said digitizer comprises:
a in-phase receive path analog-to-digital converter;
a quadrature-phase receive path analog-to-digital converter;
a in-phase transmit path digital-to-analog converter; and
a quadrature-phase transmit path digital-to-analog converter;

wherein said digital interface comprises transceiver-side digital interface circuitry, including:
a plurality of latches coupled to said digital-to-analog converters and to said analog-to-digital converters;
a bi-directional bus driver coupled between said plurality of latches and a bi-directional bus; and
address control and timing circuitry coupled to said latches; and

wherein said digital interface further comprises controller-side digital interface circuitry, including:
a second bi-directional bus driver coupled to said bi-directional bus;
a second plurality of latches coupled between said second bi-directional bus driver and said baseband processor; and
second address control and timing circuitry coupled to said second plurality of latches.

2. The network system according to claim 1, wherein said first integrated device comprises a multi-chip module.

3. The network system according to claim 1, wherein said first integrated device comprises an integrated circuit.

4. The network system according to claim 1, wherein said second integrated device comprises an integrated circuit.

5. The network system according to claim 1, wherein said digital interface comprises a serial bus.

6. The network system according to claim 1, wherein said digital interface comprises a parallel bus.

7. The network system according to claim 1, wherein said digital interface comprises a hybrid serial/parallel bus.

8. The network system according to claim 1, wherein said digital interface comprises a multiplexed bus.

9. The network system according to claim 1, wherein said digital interface comprises a direct connection between said first and second integrated devices.

10. The network system according to claim 1, wherein said digital interface is an all-digital interface.

11. The network system according to claim 1, wherein said direct conversion radio transceiver comprises a receive path coupled between said digitizer and an antenna system, said receive path including:
a low noise amplifier coupled to said antenna system;
an automatic gain control module coupled to said low noise amplifier;
in-phase and quadrature-phase direct down-converters coupled to said automatic gain control module; and
receive analog circuitry coupled between said in-phase and quadrature-phase direct down-converters and said digitizer.

12. The network system according to claim 1, wherein said direct conversion radio transceiver comprises a transmit path coupled between said digitizer and an antenna system, said transmit path including:
transmit analog circuitry coupled to said digitizer;
in-phase and quadrature-phase direct up-converters coupled to said transmit analog circuitry; and
power amplifier circuitry coupled between outputs of said in-phase and quadrature-phase direct up-converters and said antenna system.

13. The network system according to claim 11, wherein said direct conversion radio transceiver further comprises a transmit path coupled between said digitizer and said antenna system, said transmit path including:
transmit analog circuitry coupled to said digitizer;
in-phase and quadrature-phase direct up-converters coupled to said transmit analog circuitry; and
power amplifier circuitry coupled between outputs of said in-phase and quadrature-phase direct up-converters and said antenna system.

14. The network system according to claim 13, wherein said direct conversion radio transceiver further comprises:
a clock generator coupled to said in-phase and quadrature-phase direct down-converters and to said in-phase and quadrature-phase direct up-converters; and
a frequency synthesizer coupled to said clock generator.

15. The network system according to claim 1, wherein said digitizer further comprises an automatic gain control digital-to-analog converter.

16. The network system according to claim 1, wherein said second integrated device comprises an internal system bus coupled between said medium access controller and said controller.

17. A network system, comprising:
a direct conversion radio transceiver;
a baseband processor;
a digitizer coupled between said direct conversion radio transceiver and said baseband processor; and
a digital interface coupled to said baseband processor, said digital interface configured to couple to a medium access controller;
wherein said direct conversion radio transceiver, said baseband processor, and said digitizer are integrated in an integrated device;
wherein said digitizer comprises:
a in-phase receive path analog-to-digital converter;
a quadrature-phase receive path analog-to-digital converter;
a in-phase transmit path digital-to-analog converter; and
a quadrature-phase transmit path digital-to-analog converter;

wherein said digital interface comprises transceiver-side digital interface circuitry, including:
a plurality of latches coupled to said baseband processor;
a bi-directional bus driver coupled between said plurality of latches and a bi-directional bus; and
address control and timing circuitry coupled to said latches; and

wherein said digital interface further comprises controller-side digital interface circuitry, including:
a second bi-directional bus driver coupled to said bi-directional bus;
a second plurality of latches coupled between said second bi-directional bus driver and said medium access controller; and
second address control and timing circuitry coupled to said second plurality of latches.

18. The network system according to claim 17, wherein said integrated device comprises a multi-chip module.

19. The network system according to claim 17, wherein said integrated device comprises an integrated circuit.

20. The network system according to claim 17, wherein said digital interface comprises a serial bus.

21. The network system according to claim 17, wherein said digital interface comprises a parallel bus.

22. The network system according to claim 17, wherein said digital interface comprises a hybrid serial/parallel bus.

23. The network system according to claim 17, wherein said digital interface comprises a multiplexed bus.

24. The network system according to claim 17, wherein said digital interface comprises a direct connection between said baseband processor and said medium access controller.

25. The network system according to claim 17, wherein said digital interface is an all-digital interface.

26. The network system according to claim 17, wherein said direct conversion radio transceiver comprises a receive path coupled between said digitizer and an antenna system, said receive path including:
a low noise amplifier coupled to said antenna system;
an automatic gain control module coupled to said low noise amplifier;
in-phase and quadrature-phase direct down-converters coupled to said automatic gain control module; and
receive analog circuitry coupled between said in-phase and quadrature-phase direct down-converters and said digitizer.

27. The network system according to claim 17, wherein said direct conversion radio transceiver comprises a transmit path coupled between said digitizer and an antenna system, said transmit path including:
transmit analog circuitry coupled to said digitizer;
in-phase and quadrature-phase direct up-converters coupled to said transmit analog circuitry; and
power amplifier circuitry coupled between outputs of said in-phase and quadrature- phase direct up-converters and said antenna system.

28. The network system according to claim 26, wherein said direct conversion radio transceiver further comprises a transmit path coupled between said digitizer and said antenna system, said transmit path including:
transmit analog circuitry coupled to said digitizer;
in-phase and quadrature-phase direct up-converters coupled to said transmit analog circuitry; and
power amplifier circuitry coupled between outputs of said in-phase and quadrature-phase direct up-converters and said antenna system.

29. The network system according to claim 28, wherein said direct conversion radio transceiver further comprises:
a clock generator coupled to said in-phase and quadrature-phase direct down-converters and to said in-phase and quadrature-phase direct up-converters; and
a frequency synthesizer coupled to said clock generator.

30. The network system according to claim 17, wherein said digitizer further comprises an automatic gain control digital-to-analog converter.

31. The network system according to claim 17, wherein said second integrated device comprises an internal system bus coupled between said medium access controller and said controller.

32. The network system according to claim 1, wherein said first integrated device is positioned independently from said second integrated device.

33. The network system according to claim 1, wherein said first integrated device is implemented within a single integrated circuit.

34. The network system according to claim 1, wherein said second integrated device is implemented within a single integrated circuit.

35. The network system according to claim 1, wherein said digital control circuitry communicates with said medium access controller using a packet-based format.

36. The network system according to claim 17, wherein said integrated device is implemented within a single integrated circuit.