EXHIBIT 11

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 1 of 182
U.S. Patent No. 10,474,595

SK hynix HMA42GR7AFR4N-UHTD

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 2 of 182
U.S. Patent No. 10,474,595: Claim 1

“1. A memory module operable with a memory controller of a host system, comprising:”

Page 2 of 181

1. A memory module 

operable with a memory 

controller of a host system, 

comprising:

The SK hynix Products are memory modules operable with a memory controller of a host system.

For example, the SK hynix Products are DDR4 registered dual in-line memory modules (“RDIMM”).

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 3 of 182
U.S. Patent No. 10,474,595: Claim 1

“1. A memory module operable with a memory controller of a host system, comprising:”

Page 3 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet, at 1.

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 3

(annotation added).

JEDEC RDIMM Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 4 of 182
U.S. Patent No. 10,474,595: Claim 1

“1. A memory module operable with a memory controller of a host system, comprising:”

Page 4 of 181

JEDEC RDIMM Specification (annotation added).

The SK hynix HMA42GR7AFR4N-UHTD is manufactured according to JEDEC specifications:

See SKH DDR4 Module Label Info at 3.

See SKH DDR4 Module Label Info at 3.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 5 of 182
U.S. Patent No. 10,474,595: Claim 1

“1. A memory module operable with a memory controller of a host system, comprising:”

Page 5 of 181

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

The SK hynix Products are intended for use as main memory in systems such as servers and workstations. 

JEDEC RDIMM Standard (annotation added).

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 3 

(annotations added).

The SK hynix Products are operable with a memory controller of a host system. For example, the SK hynix Products 

include a printed circuit board (PCB) for communicating signals between (e.g., to/from) the memory module and the 

memory controller of a host system.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 6 of 182
U.S. Patent No. 10,474,595: Claim 1

“1. A memory module operable with a memory controller of a host system, comprising:”

Page 6 of 181

JEDEC RDIMM Specification.

For example, the SK hynix Products contain contacts for connecting to a memory controller of a computer system.

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 7 of 182
U.S. Patent No. 10,474,595: Claim 1

“1. A memory module operable with a memory controller of a host system, comprising:”

Page 7 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 81 

(annotations added).

For example, the SK hynix include a JEDEC RCD01 compliant register clock driver (“RCD”) that is operable with a 

memory controller of a host system. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 8 of 182
U.S. Patent No. 10,474,595: Claim 1

“1. A memory module operable with a memory controller of a host system, comprising:”

Page 8 of 181

See, e.g., JEDEC RDIMM Standard (annotation added).

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 81 

(annotations added).

Specifically, the SK hynix Products contain an IDT 4RCD0124KC0 RCD.

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 9 of 182
U.S. Patent No. 10,474,595: Claim 1

“1. A memory module operable with a memory controller of a host system, comprising:”

Page 9 of 181

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

The IDT 4RCD0124KC0 RCD is JEDEC Compliant.

See 4RCD0124K DDR4 Register Clock Driver Webpage at 1.

IDT Leader in Server Memory Chipsets at 1.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 10 of 182
U.S. Patent No. 10,474,595: Claim 1

“1. A memory module operable with a memory controller of a host system, comprising:”

Page 10 of 181

The SK hynix Products further comply with the JEDEC SDRAM Standard, JESD79-4.

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 1.

The RCD is operatively coupled to the memory controller of the host system.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 11 of 182
U.S. Patent No. 10,474,595: Claim 1

“1. A memory module operable with a memory controller of a host system, comprising:”

Page 11 of 181

JEDEC RDIMM Standard (annotation added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 12 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 12 of 181

a printed circuit board 

having edge connections that 

fit into a corresponding slot 

of the host system so as to be 

in electrical communication 

with the memory controller, 

the edge connections 

including first edge 

connections via which the 

memory module receives or 

outputs data signals, second 

edge connections via which 

the memory module receives 

address and control signals, 

and an error edge connection 

in addition to the first edge 

connections and the second 

edge connections;

The SK hynix Products include a printed circuit board having edge connections that fit into a corresponding slot of the 

host system so as to be in electrical communication with the memory controller, the edge connections including via which 

the memory module receives or outputs data signals, second edge connections via which the memory module receives 

address and control signals, and an error edge connection in addition to the first edge connections and the second edge 

connections.

The SK hynix Products include a printed circuit board (PCB) having edge connections that fit into a corresponding slot of 

the host system so as to be in electrical communication with the memory controller.

For example, the PCB of the SK hynix Products is configured to fit into a corresponding slot of the host system.

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 3 

(annotation added).

JEDEC RDIMM Standard (annotation added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 13 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 13 of 181

For example, as illustrated in the figures below, the SK hynix Products include a printed circuit board (PCB) having edge 

connections for communicating signals between (e.g., to/from) the memory module and the memory controller of the host 

system, e.g., electrical communication between the memory module and the memory controller.

JEDEC RDIMM Standard.

JEDEC RDIMM Standard (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 14 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 14 of 181

For example, the SK hynix Products contain contacts (e.g., edge connections) for connecting to a memory controller of a 

computer system.

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 15 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 15 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 81 

(annotations added).

The edge connections of the SK hynix Products include a first edge connections, second edge connections, and an error 

edge connection in addition to the first edge connections and the second edge connections.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 16 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 16 of 181

JEDEC RDIMM Standard (showing, for example, WE_n, A0, DQ4).

JEDEC RDIMM Standard (showing, for example, ALERT_n).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 17 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 17 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 10 (showing 

separate pin connections for data, address, control, and ALERT_n).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 18 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 18 of 181

For example, the SK hynix Products include first edge connections for communicating data signals between the memory 

module and the memory controller of the host system. For example, the SK hynix Products include the following 

input/output pins:

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 19 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 19 of 181

JEDEC RDIMM Standard.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 5, 

7. 

The DQ and DQS signals are used to communicate data signals between the memory module and the memory controller 

of the host system.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 20 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 20 of 181

JEDEC RDIMM Standard (annotations added).

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 7.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 21 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 21 of 181

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 7.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 22 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 22 of 181

See, e.g.,JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 97.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 23 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 23 of 181

See, e.g., JEDEC DDR4 SDRAM Specification.

See also JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 126, 94-144.

The SK hynix Products also include second edge connections for communicating address and control signals from the 

memory controller of the host system. For example, the SK hynix Products include the following input pins:

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 24 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 24 of 181

JEDEC RDIMM Standard.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 6. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 25 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 25 of 181

See JEDEC RCD01 Specification.

The PCB further includes an error edge connection in addition to the first set of edge connections and the second set of 

edge connections. For example, the SK hynix Products include the ALERT_n pin.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 26 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 26 of 181

JEDEC RDIMM Standard (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 27 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 27 of 181

JEDEC RDIMM Standard (annotations added).

JEDEC RDIMM Standard.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 28 of 182
U.S. Patent No. 10,474,595: Claim 1

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 28 of 181

JEDEC RDIMM Standard (annotations added) (showing Alert_n at pin 208, separate and distinct from control, address, 

and data pins / edge connections).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 29 of 182
U.S. Patent No. 10,474,595: Claim 1

“dynamic random access memory elements on the printed circuit board;”

Page 29 of 181

dynamic random access 

memory elements on the 

printed circuit board;

The SK hynix Products include dynamic random access memory elements on the printed circuit board.

For example, the SK hynix Product includes a plurality of JEDEC-compliant synchronous dynamic random access 

memories (“SDRAMs”). 

JEDEC RDIMM Standard (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 30 of 182
U.S. Patent No. 10,474,595: Claim 1

“dynamic random access memory elements on the printed circuit board;”

Page 30 of 181

See SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 20 

(showing SDRAM device D9, D27, D0, D18, D10, D28, D1, and D19).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 31 of 182
U.S. Patent No. 10,474,595: Claim 1

“dynamic random access memory elements on the printed circuit board;”

Page 31 of 181

See SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 55.

Specifically, the SK hynix HMA42GR7AFR4N-UHTD comprises 36 SDRAM components.

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD) (front side).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 32 of 182
U.S. Patent No. 10,474,595: Claim 1

“dynamic random access memory elements on the printed circuit board;”

Page 32 of 181

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD) (back side).

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD) (SDRAM).

The SDRAM devices are JEDEC complaint.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 33 of 182
U.S. Patent No. 10,474,595: Claim 1

“dynamic random access memory elements on the printed circuit board;”

Page 33 of 181

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 1.

The SDRAM devices are outlined in red in the figure below.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 34 of 182
U.S. Patent No. 10,474,595: Claim 1

“dynamic random access memory elements on the printed circuit board;”

Page 34 of 181

JEDEC RDIMM Standard (annotations added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 65. 

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD) (front side).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 35 of 182
U.S. Patent No. 10,474,595: Claim 1

“dynamic random access memory elements on the printed circuit board;”

Page 35 of 181

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD) (back side).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 36 of 182
U.S. Patent No. 10,474,595: Claim 1

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection; and”

Page 36 of 181

a module controller on the 

printed circuit board and 

coupled to the dynamic 

random access memory 

elements, the module 

controller having an open 

drain output coupled to the 

error edge connection; and

The SK hynix Products include a module controller on the printed circuit board and coupled to the dynamic random 

access memory elements, the module controller having an open drain output coupled to the error edge connection.

The SK hynix Products comprise a module controller on the printed circuit board. For example, the SK hynix Products 

contain a JEDEC-compliant IDT 4RCD0124KC0 RCD on the printed circuit board.

See, e.g., JEDEC RDIMM Standard (annotation added).

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 81 

(annotations added).

Specifically, the SK hynix Products contain an IDT 4RCD0124KC0 RCD.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 37 of 182
U.S. Patent No. 10,474,595: Claim 1

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection; and”

Page 37 of 181

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

The IDT 4RCD0124KC0 RCD is JEDEC Compliant.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 38 of 182
U.S. Patent No. 10,474,595: Claim 1

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection; and”

Page 38 of 181

See 4RCD0124K DDR4 Register Clock Driver Webpage at 1.

IDT Leader in Server Memory Chipsets at 1.

The SK hynix Products comprise a module controller coupled to the dynamic random access memory elements. For 

example, the IDT 4RCD0124KC0 RCD is coupled to the plurality of dynamic random access memory elements on the 

PCB.

JEDEC RDIMM Standard.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 39 of 182
U.S. Patent No. 10,474,595: Claim 1

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection; and”

Page 39 of 181

JEDEC RDIMM Standard.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 40 of 182
U.S. Patent No. 10,474,595: Claim 1

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection; and”

Page 40 of 181

See JEDEC RCD01 Specification.

See JEDEC RCD01 Specification (annotations added).

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 41 of 182
U.S. Patent No. 10,474,595: Claim 1

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection; and”

Page 41 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 42 of 182
U.S. Patent No. 10,474,595: Claim 1

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection; and”

Page 42 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 22.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 43 of 182
U.S. Patent No. 10,474,595: Claim 1

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection; and”

Page 43 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 20.

The SK hynix Products comprise a module controller having an open drain output coupled to the error edge connection. 

For example, the JEDEC-complaint IDT 4RCD0124KC0 RCD contains an ALERT_n pin, which is an open drain output 

coupled to the error edge connection of the PCB.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 44 of 182
U.S. Patent No. 10,474,595: Claim 1

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection; and”

Page 44 of 181

See JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 45 of 182
U.S. Patent No. 10,474,595: Claim 1

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection; and”

Page 45 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 46 of 182
U.S. Patent No. 10,474,595: Claim 1

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection; and”

Page 46 of 181

JEDEC RDIMM Standard (annotation added).

JEDEC RDIMM Standard (annotation added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 5, 

7.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 47 of 182
U.S. Patent No. 10,474,595: Claim 1

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection; and”

Page 47 of 181

JEDEC RDIMM Standard (annotations added).

JEDEC Annex B- Raw Card B for RDIMM, at 20.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 48 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module is configurable to operate in any of at least a first mode and a second mode;"

Page 48 of 181

wherein the memory module 

is configurable to operate in 

any of at least a first mode 

and a second mode;

The SK hynix Products are memory modules configurable to operate in at least a first mode and a second mode.

For example, the IDT 4RCD0124KC0 RCD is configured to operate in a first mode, e.g., a normal operating mode (e.g., 

when RC0C control word = x000).

See JEDEC RCD01 Specification (annotations added).

For example, the IDT 4RCD0124KC0 RCD is further configured to operate in a second mode, e.g., Clock-to-CA training 

mode (e.g., when RC0C control word = x001).

See JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 49 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module is configurable to operate in any of at least a first mode and a second mode;"

Page 49 of 181

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 50 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 50 of 181

wherein the memory module 

in the first mode is 

configurable to perform one 

or more normal memory 

read or write operations by 

communicating data signals 

via the first edge connections 

in response to address and 

control signals received via 

the second edge connections, 

wherein the memory module 

in the second mode is not 

accessed by the memory 

controller for normal 

memory read or write 

operations, and wherein the 

memory module in the 

second mode is configurable 

to perform operations related 

to one or more training 

sequences;

In the first mode, the SK hynix Products are configurable to perform one or more normal memory read or write operations 

by communicating data signals via the first edge connections in response to address and control signals received via the 

second edge connections.

For example, the SK hynix Products are configured to operate in a normal operating mode, e.g., a first mode.

See JEDEC RCD01 Specification (annotations added).

The SK hynix Products are configured to perform one or more memory read or write operations by communicating data 

signals via the first edge connections in response to address and command signals received via the second edge 

connections. 

For example, during the first mode (e.g., a normal mode of operation), the RCD receives address and control signals 

corresponding to read and write commands from the memory controller via the second edge connections. The RCD 

outputs corresponding address and control signals to the SDRAM devices, which cause the SDRAM devices to execute 

read and write operations.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 51 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 51 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 52 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 52 of 181

See JEDEC RCD01 Specification (annotations added).

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 53 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 53 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 54 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 54 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 22.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 55 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 55 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 20.

The SDRAM components receive these signals as inputs from the RCD.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 56 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 56 of 181

JEDEC DDR4 SDRAM Specification.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 6.

JEDEC DDR4 SDRAM Specification.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 6.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 57 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 57 of 181

JEDEC DDR4 SDRAM Specification.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 6.

These signals are used during reads and writes that occur during operational mode, e.g., the first mode.

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 7.

JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 94.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 58 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 58 of 181

Additionally, the RCD outputs chips select commands QACS0_n, QACS1_N, and/or QACS3_n, and QBCS0_n, 

QBCS1_N, and/or QBCS3_n, which activate the relevant SDRAM chip depending on the mode of operation.

See JEDEC RCD01 Specification.

In response to the address and command information received via the second edge connections, the SK hynix Products 

communicate data signals via the first edge connections while performing memory read or write operations. For example 

the DQ and DQS signals (first edge connections) are used to communicate data signals between the memory module and 

host in response to read/write commands and addressing information received from the second edge connections:

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 59 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 59 of 181

JEDEC RDIMM Standard.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 5, 

7. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 60 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 60 of 181

JEDEC RDIMM Standard (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 61 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 61 of 181

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 7.

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 7.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 62 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 62 of 181

See, e.g.,JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 97.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 63 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 63 of 181

See, e.g., JEDEC DDR4 SDRAM Specification.

See also JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 126, 94-144.

In the second mode, the SK hynix Products are not accessed by the memory controller for normal memory read or write 

operations, and are configurable to perform operations related to one or more training sequences.

For example, while the SK hynix Product is in Clock-to-CA training mode (e.g., a second mode), the dynamic random 

access memory devices (DRAMs) of the memory module are isolated from normal use, and normal operational read/write 

commands are not decoded.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 64 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 64 of 181

See JEDEC RCD01 Specification.

Further, while in the second mode, the SK hynix Products are configurable to perform operations related to one or more 

training sequences.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 65 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 65 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 66 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the memory module in the first mode is configurable to perform one or more normal memory read or write operations by communicating data 

signals via the first edge connections in response to address and control signals received via the second edge connections, wherein the memory module in 

the second mode is not accessed by the memory controller for normal memory read or write operations, and wherein the memory module in the second 

mode is configurable to perform operations related to one or more training sequences;”

Page 66 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 67 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 67 of 181

wherein the module 

controller is configurable to 

receive via the second edge 

connections the address and 

control signals associated 

with the one or more normal 

memory read or write 

operations, wherein the 

dynamic random access 

memory elements are 

configurable to communicate 

data signals with the 

memory controller via the 

first edge connections in 

accordance with the address 

and control signals, and 

wherein the module 

controller is further 

configurable to output via 

the open drain output and the 

error edge connection a 

signal indicating a parity 

error having occurred while 

the memory module is in the 

first mode;

The module controller of the SK hynix Products is configurable to receive via the second edge connections the address 

and control signals associated with the one or more normal memory read or write operations, wherein the dynamic random 

access memory elements of the SK hynix Products are configurable to communicate data signals with the memory 

controller via the first edge connections in accordance with the address and control signals, and wherein the module 

controller of the SK hynix Products is further configurable to output via the open drain output and the error edge 

connection a signal indicating a parity error having occurred while the SK hynix Products are in the first mode.

While the SK hynix Products are in the first mode, the module controller of the SK hynix Products is configurable to 

receive via the second edge connections the address and control signals associated with the one or more normal memory 

read or write operations. For example, during the first mode (e.g., a normal mode of operation), the RCD receives address 

and control signals corresponding to read and write commands from the memory controller via the second edge 

connections. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 68 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 68 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 69 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 69 of 181

See JEDEC RCD01 Specification (annotations added).

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 70 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 70 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 71 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 71 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 22.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 72 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 72 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 20.

Further, in the first mode, the dynamic random access memory elements are configurable to communicate data signals 

with the memory controller via the first edge connections in accordance with the address and control signals. For example,

the RCD outputs the address and control signals to the SDRAM devices, which cause the SDRAM devices to execute read 

and write operations. The SDRAM components receive these signals as inputs from the RCD.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 73 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 73 of 181

JEDEC DDR4 SDRAM Specification.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 6.

JEDEC DDR4 SDRAM Specification.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 6.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 74 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 74 of 181

JEDEC DDR4 SDRAM Specification.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 6.

These signals are used during reads and writes that occur during the normal operational mode, e.g., the first mode.

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 7.

JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 94.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 75 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 75 of 181

Additionally, the RCD outputs chips select commands QACS0_n, QACS1_N, and/or QACS3_n, and QBCS0_n, 

QBCS1_N, and/or QBCS3_n, which activate the relevant SDRAM chip depending on the mode of operation.

See JEDEC RCD01 Specification.

In accordance with those address and control signals, the SDRAM communicate data signals with the memory controller 

via the first edge connections. For example the DQ and DQS signals (first edge connections) are used to communicate 

data signals between the memory module and host in response to read/write commands and addressing information 

received from the second edge connections:

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 76 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 76 of 181

JEDEC RDIMM Standard.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 77 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 77 of 181

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 5, 

7. 

JEDEC RDIMM Standard (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 78 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 78 of 181

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 7.

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 7.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 79 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 79 of 181

See, e.g.,JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 97.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 80 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 80 of 181

See, e.g., JEDEC DDR4 SDRAM Specification.

See also JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 126, 94-144.

The module controller is further configurable to output via the open drain output and the error edge connection a signal 

indicating a parity error having occurred while the SK hynix Products are in the first mode. For example, the ALERT_n 

pin of the SK hynix Products is used to indicate a parity error while the memory module operates in the first mode (e.g., a 

normal mode of operation). 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 81 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 81 of 181

JEDEC RDIMM Standard (annotation added).

JEDEC RDIMM Standard (annotation added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 5, 

7.

During the first mode (e.g., a normal mode of operation), the RCD uses the ALERT_n signal to indicate a parity error 

having occurred.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 82 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 82 of 181

See, e.g.,JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 83 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller is configurable to receive via the second edge connections the address and control signals associated with the one or more 

normal memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with the 

memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller is further 

configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred while the memory module 

is in the first mode;”

Page 83 of 181

See JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 84 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller in the second mode is further configurable to provide information related to the one or more training sequences by driving 

the open drain output and the error edge connection to a first state or to a second state, one of the first state and the second state being a low logic level and 

the other one of the first state and the second state being a high impedance state.”

Page 84 of 181

wherein the module 

controller in the second 

mode is further configurable 

to provide information 

related to the one or more 

training sequences by 

driving the open drain output 

and the error edge 

connection to a first state or 

to a second state, one of the 

first state and the second 

state being a low logic level 

and the other one of the first 

state and the second state 

being a high impedance 

state.

The module controller of the SK hynix Products in the second mode is further configurable to provide information related 

to the one or more training sequences by driving the open drain output and the error edge connection to a first state or to a

second state, one of the first state and the second state being a low logic level and the other one of the first state and the 

second state being a high impedance state.

For example, the SK hynix products are configured to drive the Alert_n signal, in either a HIGH or LOW state, to the 

error edge connection via the open drain output while the memory module is in Clock-to-CA training mode, e.g., the 

second mode. The Alert_n signal constitutes information related to the Clock-to-CA training sequences.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 85 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller in the second mode is further configurable to provide information related to the one or more training sequences by driving 

the open drain output and the error edge connection to a first state or to a second state, one of the first state and the second state being a low logic level and 

the other one of the first state and the second state being a high impedance state.”

Page 85 of 181

See JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 86 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller in the second mode is further configurable to provide information related to the one or more training sequences by driving 

the open drain output and the error edge connection to a first state or to a second state, one of the first state and the second state being a low logic level and 

the other one of the first state and the second state being a high impedance state.”

Page 86 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 87 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller in the second mode is further configurable to provide information related to the one or more training sequences by driving 

the open drain output and the error edge connection to a first state or to a second state, one of the first state and the second state being a low logic level and 

the other one of the first state and the second state being a high impedance state.”

Page 87 of 181

See JEDEC RCD01 Specification (annotation added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 88 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller in the second mode is further configurable to provide information related to the one or more training sequences by driving 

the open drain output and the error edge connection to a first state or to a second state, one of the first state and the second state being a low logic level and 

the other one of the first state and the second state being a high impedance state.”

Page 88 of 181

JEDEC RDIMM Standard (annotations added).

The Alert_n signal provides information related to the one or more training sequences. For example, while in Clock-toCA training mode, the IDT 4RCD0124KC0 RCD ORs all enabled Dn inputs from the memory controller and then outputs 

the result of that OR operation to the memory controller via the Alert_n pin. The module controller of the SK hynix

Products drives the open drain output and the error edge connection to one of two states. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 89 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller in the second mode is further configurable to provide information related to the one or more training sequences by driving 

the open drain output and the error edge connection to a first state or to a second state, one of the first state and the second state being a low logic level and 

the other one of the first state and the second state being a high impedance state.”

Page 89 of 181

See JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 90 of 182
U.S. Patent No. 10,474,595: Claim 1

“wherein the module controller in the second mode is further configurable to provide information related to the one or more training sequences by driving 

the open drain output and the error edge connection to a first state or to a second state, one of the first state and the second state being a low logic level and 

the other one of the first state and the second state being a high impedance state.”

Page 90 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 91 of 182
U.S. Patent No. 10,474,595: Claim 10

“10. A memory module operable with a memory controller of a host system, comprising:”

Page 91 of 181

10. A memory module 

operable with a memory 

controller of a host system, 

comprising:

The SK hynix Products are memory modules operable with a memory controller of a host system.

For example, the SK hynix Products are DDR4 registered dual in-line memory modules (“RDIMM”).

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 92 of 182
U.S. Patent No. 10,474,595: Claim 10

“10. A memory module operable with a memory controller of a host system, comprising:”

Page 92 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet, at 1.

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 3

(annotation added).

JEDEC RDIMM Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 93 of 182
U.S. Patent No. 10,474,595: Claim 10

“10. A memory module operable with a memory controller of a host system, comprising:”

Page 93 of 181

JEDEC RDIMM Specification (annotation added).

The SK hynix HMA42GR7AFR4N-UHTD is manufactured according to JEDEC specifications:

See SKH DDR4 Module Label Info at 3.

See SKH DDR4 Module Label Info at 3.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 94 of 182
U.S. Patent No. 10,474,595: Claim 10

“10. A memory module operable with a memory controller of a host system, comprising:”

Page 94 of 181

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

The SK hynix Products are intended for use as main memory in systems such as servers and workstations. 

JEDEC RDIMM Standard (annotation added).

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 3 

(annotations added).

The SK hynix Products are operable with a memory controller of a host system. For example, the SK hynix Products 

include a printed circuit board (PCB) for communicating signals between (e.g., to/from) the memory module and the 

memory controller of a host system.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 95 of 182
U.S. Patent No. 10,474,595: Claim 10

“10. A memory module operable with a memory controller of a host system, comprising:”

Page 95 of 181

JEDEC RDIMM Specification.

For example, the SK hynix Products contain contacts for connecting to a memory controller of a computer system.

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 96 of 182
U.S. Patent No. 10,474,595: Claim 10

“10. A memory module operable with a memory controller of a host system, comprising:”

Page 96 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 81 

(annotations added).

For example, the SK hynix include a JEDEC RCD01 compliant register clock driver (“RCD”) that is operable with a 

memory controller of a host system. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 97 of 182
U.S. Patent No. 10,474,595: Claim 10

“10. A memory module operable with a memory controller of a host system, comprising:”

Page 97 of 181

See, e.g., JEDEC RDIMM Standard (annotation added).

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 81 

(annotations added).

Specifically, the SK hynix Products contain a IDT 4RCD0124KC0 RCD.

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 98 of 182
U.S. Patent No. 10,474,595: Claim 10

“10. A memory module operable with a memory controller of a host system, comprising:”

Page 98 of 181

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

The IDT 4RCD0124KC0 RCD is JEDEC Compliant.

See 4RCD0124K DDR4 Register Clock Driver Webpage at 1.

IDT Leader in Server Memory Chipsets at 1.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 99 of 182
U.S. Patent No. 10,474,595: Claim 10

“10. A memory module operable with a memory controller of a host system, comprising:”

Page 99 of 181

The SK hynix Products further comply with the JEDEC SDRAM Standard, JESD79-4.

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 1.

The RCD is operatively coupled to the memory controller of the host system.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 100 of 182
U.S. Patent No. 10,474,595: Claim 10

“10. A memory module operable with a memory controller of a host system, comprising:”

Page 100 of 181

JEDEC RDIMM Standard (annotation added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 101 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 101 of 181

a printed circuit board 

having edge connections that 

fit into a corresponding slot 

of the host system so as to be 

in electrical communication 

with the memory controller, 

the edge connections 

including first edge 

connections via which the 

memory module receives or 

outputs data signals, second 

edge connections via which 

the memory module receives 

address and control signals, 

and an error edge connection 

in addition to the first edge 

connections and the second 

edge connections;

The SK hynix Products include a printed circuit board having edge connections that fit into a corresponding slot of the 

host system so as to be in electrical communication with the memory controller, the edge connections including via which 

the memory module receives or outputs data signals, second edge connections via which the memory module receives 

address and control signals, and an error edge connection in addition to the first edge connections and the second edge 

connections.

The SK hynix Products include a printed circuit board (PCB) having edge connections that fit into a corresponding slot of 

the host system so as to be in electrical communication with the memory controller.

For example, the PCB of the SK hynix Products is configured to fit into a corresponding slot of the host system.

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 3 

(annotation added).

JEDEC RDIMM Standard (annotation added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 102 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 102 of 181

For example, as illustrated in the figures below, the SK hynix Products include a printed circuit board (PCB) having edge 

connections for communicating signals between (e.g., to/from) the memory module and the memory controller of the host 

system, e.g., electrical communication between the memory module and the memory controller.

JEDEC RDIMM Standard.

JEDEC RDIMM Standard (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 103 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 103 of 181

For example, the SK hynix Products contain contacts (e.g., edge connections) for connecting to a memory controller of a 

computer system.

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 104 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 104 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 81 

(annotations added).

The edge connections of the SK hynix Products include a first edge connections, second edge connections, and an error 

edge connection in addition to the first edge connections and the second edge connections.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 105 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 105 of 181

JEDEC RDIMM Standard (showing, for example, WE_n, A0, DQ4).

JEDEC RDIMM Standard (showing, for example, ALERT_n).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 106 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 106 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 10 (showing 

separate pin connections for data, address, control, and ALERT_n).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 107 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 107 of 181

For example, the SK hynix Products include first edge connections for communicating data signals between the memory 

module and the memory controller of the host system. For example, the SK hynix Products include the following 

input/output pins:

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 108 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 108 of 181

JEDEC RDIMM Standard.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 5, 

7. 

The DQ and DQS signals are used to communicate data signals between the memory module and the memory controller 

of the host system.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 109 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 109 of 181

JEDEC RDIMM Standard (annotations added).

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 7.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 110 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 110 of 181

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 7.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 111 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 111 of 181

See, e.g.,JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 97.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 112 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 112 of 181

See, e.g., JEDEC DDR4 SDRAM Specification.

See also JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 126, 94-144.

The SK hynix Products also include second edge connections for communicating address and control signals from the 

memory controller of the host system. For example, the SK hynix Products include the following input pins:

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 113 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 113 of 181

JEDEC RDIMM Standard.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 6. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 114 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 114 of 181

See JEDEC RCD01 Specification.

The PCB further includes an error edge connection in addition to the first set of edge connections and the second set of 

edge connections. For example, the SK hynix Products include the ALERT_n pin.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 115 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 115 of 181

JEDEC RDIMM Standard (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 116 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 116 of 181

JEDEC RDIMM Standard (annotations added).

JEDEC RDIMM Standard.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 117 of 182
U.S. Patent No. 10,474,595: Claim 10

“a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the 

memory controller, the edge connections including first edge connections via which the memory module receives or outputs data signals, second edge 

connections via which the memory module receives address and control signals, and an error edge connection in addition to the first edge connections and 

the second edge connections;”

Page 117 of 181

JEDEC RDIMM Standard (annotations added) (showing Alert_n at pin 208, separate and distinct from control, address, 

and data pins / edge connections).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 118 of 182
U.S. Patent No. 10,474,595: Claim 10

“dynamic random access memory elements on the printed circuit board;”

Page 118 of 181

dynamic random access 

memory elements on the 

printed circuit board;

The SK hynix Products include dynamic random access memory elements on the printed circuit board.

For example, the SK hynix Product includes a plurality of JEDEC-compliant synchronous dynamic random access 

memories (“SDRAMs”). 

JEDEC RDIMM Standard (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 119 of 182
U.S. Patent No. 10,474,595: Claim 10

“dynamic random access memory elements on the printed circuit board;”

Page 119 of 181

See SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 20 

(showing SDRAM device D9, D27, D0, D18, D10, D28, D1, and D19).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 120 of 182
U.S. Patent No. 10,474,595: Claim 10

“dynamic random access memory elements on the printed circuit board;”

Page 120 of 181

See SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 55.

Specifically, the SK hynix HMA42GR7AFR4N-UHTD comprises 36 SDRAM components.

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD) (front side).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 121 of 182
U.S. Patent No. 10,474,595: Claim 10

“dynamic random access memory elements on the printed circuit board;”

Page 121 of 181

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD) (back side).

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD) (SDRAM).

The SDRAM devices are JEDEC complaint.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 122 of 182
U.S. Patent No. 10,474,595: Claim 10

“dynamic random access memory elements on the printed circuit board;”

Page 122 of 181

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 1.

The SDRAM devices are outlined in red in the figure below.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 123 of 182
U.S. Patent No. 10,474,595: Claim 10

“dynamic random access memory elements on the printed circuit board;”

Page 123 of 181

JEDEC RDIMM Standard (annotations added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 65. 

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD) (front side).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 124 of 182
U.S. Patent No. 10,474,595: Claim 10

“dynamic random access memory elements on the printed circuit board;”

Page 124 of 181

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD) (back side).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 125 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 125 of 181

a module controller on the 

printed circuit board and 

coupled to the dynamic 

random access memory 

elements, the module 

controller having an open 

drain output coupled to the 

error edge connection and 

configurable to drive the 

open drain output from a 

first state to a second state 

and from the second state to 

the first state, one of the first 

state and the second state 

being a low logic level, and 

the other one of the first state 

and the second state being a 

high impedance state; and

The SK hynix Products include a module controller on the printed circuit board and coupled to the dynamic random 

access memory elements, the module controller having an open drain output coupled to the error edge connection. The 

module controller of the SK hynix Products is configurable to drive the open drain output from a first state to a second 

state and from the second state to the first state, one of the first state and the second state being a low logic level, and the 

other one of the first state and the second state being a high impedance state

The SK hynix Products comprise a module controller on the printed circuit board. For example, the SK hynix Products 

contain a JEDEC-compliant IDT 4RCD0124KC0 RCD on the printed circuit board.

See, e.g., JEDEC RDIMM Standard (annotation added).

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 81 

(annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 126 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 126 of 181

Specifically, the SK hynix Products contain a IDT 4RCD0124KC0 RCD.

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

(Exemplary Photo of SK Hynix HMA42GR7AFR4N-UHTD).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 127 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 127 of 181

The IDT 4RCD0124KC0 RCD is JEDEC Compliant.

See 4RCD0124K DDR4 Register Clock Driver Webpage at 1.

IDT Leader in Server Memory Chipsets at 1.

The SK hynix Products comprise a module controller coupled to the dynamic random access memory elements. For 

example, the IDT 4RCD0124KC0 RCD is coupled to the plurality of dynamic random access memory elements on the 

PCB.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 128 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 128 of 181

JEDEC RDIMM Standard.

JEDEC RDIMM Standard.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 129 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 129 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 130 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 130 of 181

See JEDEC RCD01 Specification (annotations added).

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 131 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 131 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 132 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 132 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 22.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 133 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 133 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 20.

The SK hynix Products comprise a module controller having an open drain output coupled to the error edge connection. 

For example, the JEDEC-complaint IDT 4RCD0124KC0 RCD contains an ALERT_n pin, which is an open drain output 

coupled to the error edge connection of the PCB.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 134 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 134 of 181

See JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 135 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 135 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 136 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 136 of 181

JEDEC RDIMM Standard (annotation added).

JEDEC RDIMM Standard (annotation added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 5, 

7.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 137 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 137 of 181

JEDEC RDIMM Standard (annotations added).

JEDEC Annex B- Raw Card B for RDIMM, at 20.

The module controller of the SK hynix Products is configurable to drive the open drain output from a first state to a 

second state and from the second state to the first state, one of the first state and the second state being a low logic leve l, 

and the other one of the first state and the second state being a high impedance state. For example, the SK hynix products 

are configured to drive the Alert_n signal, from a HIGH state to a LOW state and from a LOW state to a HIGH state, 

while the memory module operates in the first mode (e.g., a normal mode of operation). 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 138 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 138 of 181

JEDEC RDIMM Standard (annotation added).

JEDEC RDIMM Standard (annotation added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 5, 

7.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 139 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 139 of 181

See, e.g.,JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 140 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 140 of 181

See JEDEC RCD01 Specification (annotations added).

Additionally, for example, the SK hynix Products are configured to drive the Alert_n signal, from a HIGH state to a LOW 

state and from a LOW state to a HIGH state, while the memory module is in Clock-to-CA training mode, e.g., the second 

mode. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 141 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 141 of 181

See JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 142 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 142 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 143 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 143 of 181

See JEDEC RCD01 Specification (annotation added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 144 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 144 of 181

JEDEC RDIMM Standard (annotations added).

The Alert_n signal provides information related to the one or more training sequences. For example, while in Clock-toCA training mode, the IDT 4RCD0124KC0 RCD ORs all enabled Dn inputs from the memory controller and then outputs 

the result of that OR operation to the memory controller via the Alert_n pin. The module controller of the SK hynix

Products drives the open drain output and the error edge connection to one of two states. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 145 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 145 of 181

See JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 146 of 182
U.S. Patent No. 10,474,595: Claim 10

“a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain 

output coupled to the error edge connection and configurable to drive the open drain output from a first state to a second state and from the second state to 

the first state, one of the first state and the second state being a low logic level, and the other one of the first state and the second state being a high 

impedance state; and”

Page 146 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 147 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the memory module is operable in at least a first mode in which the memory module is configurable to perform one or more memory read or write 

operations by communicating data signals via the first edge connections in response to address and control signals received via the second edge 

connections, and a second mode in which the memory module is not accessed by the memory controller for memory read or write operations, and wherein 

the memory module in the second mode is configurable to perform operations related to one or more training sequences without communicating data signals 

via the first edge connections”

Page 147 of 181

wherein the memory module 

is operable in at least a first 

mode in which the memory 

module is configurable to 

perform one or more 

memory read or write 

operations by 

communicating data signals 

via the first edge connections 

in response to address and 

control signals received via 

the second edge connections, 

and a second mode in which 

the memory module is not 

accessed by the memory 

controller for memory read 

or write operations, and 

wherein the memory module 

in the second mode is 

configurable to perform 

operations related to one or 

more training sequences 

without communicating data 

signals via the first edge 

connections

The SK hynix Products are operable in at least a first mode in which the memory module is configurable to perform one

or more memory read or write operations by communicating data signals via the first edge connections in response to 

address and control signals received via the second edge connections, and a second mode in which the memory module is 

not accessed by the memory controller for memory read or write operations, and wherein the memory module in the 

second mode is configurable to perform operations related to one or more training sequences without communicating data 

signals via the first edge connections.

For example, the SK hynix Product is configured to operate in a first mode, e.g., a normal operating mode (e.g., when the 

IDT 4RCD0124KC0 RCD’s RC0C control word = x000), and in a second mode, e.g., Clock-to-CA training mode (e.g., 

when the IDT 4RCD0124KC0 RCD’s RC0C control word = x001).

See JEDEC RCD01 Specification (annotations added).

For example, the IDT 4RCD0124KC0 RCD is further configured to operate in a second mode, e.g., Clock-to-CA training 

mode (e.g., when RC0C control word = x001).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 148 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the memory module is operable in at least a first mode in which the memory module is configurable to perform one or more memory read or write 

operations by communicating data signals via the first edge connections in response to address and control signals received via the second edge 

connections, and a second mode in which the memory module is not accessed by the memory controller for memory read or write operations, and wherein 

the memory module in the second mode is configurable to perform operations related to one or more training sequences without communicating data signals 

via the first edge connections”

Page 148 of 181

See JEDEC RCD01 Specification (annotations added).

The SK hynix Products are operable in a first mode (e.g., a normal operation mode) in which the memory module is 

configurable to perform one or more memory read or write operations by communicating data signals via the first edge 

connections in response to address and control signals received via the second edge connections.

See JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 149 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the memory module is operable in at least a first mode in which the memory module is configurable to perform one or more memory read or write 

operations by communicating data signals via the first edge connections in response to address and control signals received via the second edge 

connections, and a second mode in which the memory module is not accessed by the memory controller for memory read or write operations, and wherein 

the memory module in the second mode is configurable to perform operations related to one or more training sequences without communicating data signals 

via the first edge connections”

Page 149 of 181

The SK hynix Products are configured to perform one or more memory read or write operations by communicating data 

signals via the first edge connections in response to address and command signals received via the second edge 

connections.

For example, during the first mode (e.g., a normal mode of operation), the RCD receives address and control signals 

corresponding to read and write commands from the memory controller via the second edge connections. The RCD 

outputs corresponding address and control signals to the SDRAM devices, which cause the SDRAM devices to execute 

read and write operations.

Additionally, the RCD outputs chips select commands QACS0_n, QACS1_N, and/or QACS3_n, and QBCS0_n, 

QBCS1_N, and/or QBCS3_n, which activate the relevant SDRAM chip depending on the mode of operation.

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 150 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the memory module is operable in at least a first mode in which the memory module is configurable to perform one or more memory read or write 

operations by communicating data signals via the first edge connections in response to address and control signals received via the second edge 

connections, and a second mode in which the memory module is not accessed by the memory controller for memory read or write operations, and wherein 

the memory module in the second mode is configurable to perform operations related to one or more training sequences without communicating data signals 

via the first edge connections”

Page 150 of 181

In response to the address and command information received via the second edge connections, the SK hynix Products 

perform one or more memory read or write operations by communicating data signals via the first edge connections. For 

example the DQ and DQS signals (first edge connections) are used to communicate data signals between the memory 

module and host in response to read/write commands and addressing information received from the second edge 

connections:

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 151 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the memory module is operable in at least a first mode in which the memory module is configurable to perform one or more memory read or write 

operations by communicating data signals via the first edge connections in response to address and control signals received via the second edge 

connections, and a second mode in which the memory module is not accessed by the memory controller for memory read or write operations, and wherein 

the memory module in the second mode is configurable to perform operations related to one or more training sequences without communicating data signals 

via the first edge connections”

Page 151 of 181

JEDEC RDIMM Standard.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 5, 

7. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 152 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the memory module is operable in at least a first mode in which the memory module is configurable to perform one or more memory read or write 

operations by communicating data signals via the first edge connections in response to address and control signals received via the second edge 

connections, and a second mode in which the memory module is not accessed by the memory controller for memory read or write operations, and wherein 

the memory module in the second mode is configurable to perform operations related to one or more training sequences without communicating data signals 

via the first edge connections”

Page 152 of 181

JEDEC RDIMM Standard (annotations added).

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 7.

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 7.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 153 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the memory module is operable in at least a first mode in which the memory module is configurable to perform one or more memory read or write 

operations by communicating data signals via the first edge connections in response to address and control signals received via the second edge 

connections, and a second mode in which the memory module is not accessed by the memory controller for memory read or write operations, and wherein 

the memory module in the second mode is configurable to perform operations related to one or more training sequences without communicating data signals 

via the first edge connections”

Page 153 of 181

See, e.g.,JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 97.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 154 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the memory module is operable in at least a first mode in which the memory module is configurable to perform one or more memory read or write 

operations by communicating data signals via the first edge connections in response to address and control signals received via the second edge 

connections, and a second mode in which the memory module is not accessed by the memory controller for memory read or write operations, and wherein 

the memory module in the second mode is configurable to perform operations related to one or more training sequences without communicating data signals 

via the first edge connections”

Page 154 of 181

See, e.g., JEDEC DDR4 SDRAM Specification.

See also JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 126, 94-144.

In the second mode, the SK hynix Products are not accessed by the memory controller for normal memory read or write 

operations, and are configurable to perform operations related to one or more training sequences.

For example, while the SK hynix Product is in Clock-to-CA training mode (e.g., a second mode), the dynamic random 

access memory devices (DRAMs) of the memory module are isolated from normal use, and normal operational read/write 

commands are not decoded.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 155 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the memory module is operable in at least a first mode in which the memory module is configurable to perform one or more memory read or write 

operations by communicating data signals via the first edge connections in response to address and control signals received via the second edge 

connections, and a second mode in which the memory module is not accessed by the memory controller for memory read or write operations, and wherein 

the memory module in the second mode is configurable to perform operations related to one or more training sequences without communicating data signals 

via the first edge connections”

Page 155 of 181

See JEDEC RCD01 Specification.

Further, while in the second mode, the SK hynix Products are configurable to perform operations related to one or more 

training sequences.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 156 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the memory module is operable in at least a first mode in which the memory module is configurable to perform one or more memory read or write 

operations by communicating data signals via the first edge connections in response to address and control signals received via the second edge 

connections, and a second mode in which the memory module is not accessed by the memory controller for memory read or write operations, and wherein 

the memory module in the second mode is configurable to perform operations related to one or more training sequences without communicating data signals 

via the first edge connections”

Page 156 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 157 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the memory module is operable in at least a first mode in which the memory module is configurable to perform one or more memory read or write 

operations by communicating data signals via the first edge connections in response to address and control signals received via the second edge 

connections, and a second mode in which the memory module is not accessed by the memory controller for memory read or write operations, and wherein 

the memory module in the second mode is configurable to perform operations related to one or more training sequences without communicating data signals 

via the first edge connections”

Page 157 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 158 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 158 of 181

wherein the module 

controller in the first mode is 

configurable to receive via 

the second edge connections 

the address and control 

signals associated with the 

one or more memory read or 

write operations, wherein the 

dynamic random access 

memory elements are 

configurable to communicate 

data signals with the 

memory controller via the 

first edge connections in 

accordance with the address 

and control signals, and 

wherein the module 

controller in the first mode is 

further configurable to 

output via the open drain 

output and the error edge 

connection a signal 

indicating a parity error 

having occurred in the 

memory module while the 

memory module is in the 

first mode;

The module controller of the SK hynix Products is, in the first mode, configurable to receive via the second edge 

connections the address and control signals associated with the one or more memory read or write operations, wherein the 

dynamic random access memory elements are configurable to communicate data signals with the memory controller via 

the first edge connections in accordance with the address and control signals. The module controller of the SK hynix

Products is further configurable, in the first mode, to output via the open drain output and the error edge connection a 

signal indicating a parity error having occurred in the memory module.

While the SK hynix Products are in the first mode, the module controller of the SK hynix Products is configurable to 

receive via the second edge connections the address and control signals associated with the one or more normal memory 

read or write operations. For example, during the first mode (e.g., a normal mode of operation), the RCD receives address 

and control signals corresponding to read and write commands from the memory controller via the second edge 

connections. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 159 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 159 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 160 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 160 of 181

See JEDEC RCD01 Specification (annotations added).

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 161 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 161 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 162 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 162 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 22.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 163 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 163 of 181

SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 20.

Further, in the first mode, the dynamic random access memory elements are configurable to communicate data signals 

with the memory controller via the first edge connections in accordance with the address and control signals. For example, 

the RCD outputs the address and control signals to the SDRAM devices, which cause the SDRAM devices to execute read 

and write operations. The SDRAM components receive these signals as inputs from the RCD.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 164 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 164 of 181

JEDEC DDR4 SDRAM Specification.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 6.

JEDEC DDR4 SDRAM Specification.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 6.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 165 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 165 of 181

JEDEC DDR4 SDRAM Specification.

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 6.

These signals are used during reads and writes that occur during the normal operational mode, e.g., the first mode.

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 7.

JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 94.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 166 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 166 of 181

Additionally, the RCD outputs chips select commands QACS0_n, QACS1_N, and/or QACS3_n, and QBCS0_n, 

QBCS1_N, and/or QBCS3_n, which activate the relevant SDRAM chip depending on the mode of operation.

See JEDEC RCD01 Specification.

In accordance with those address and control signals, the SDRAM communicate data signals with the memory controller 

via the first edge connections. For example the DQ and DQS signals (first edge connections) are used to communicate 

data signals between the memory module and host in response to read/write commands and addressing information 

received from the second edge connections:

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 167 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 167 of 181

JEDEC RDIMM Standard.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 168 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 168 of 181

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 5, 

7. 

JEDEC RDIMM Standard (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 169 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 169 of 181

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH DDR4 Device Operation at 7.

JEDEC DDR4 SDRAM Specification (annotations added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 7.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 170 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 170 of 181

See, e.g.,JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 97.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 171 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 171 of 181

See, e.g., JEDEC DDR4 SDRAM Specification.

See also JEDEC DDR4 SDRAM Specification.

See also SKH DDR4 Device Operation at 126, 94-144.

The module controller is further configurable to output via the open drain output and the error edge connection a signal 

indicating a parity error having occurred while the SK hynix Products are in the first mode. For example, the ALERT_n 

pin of the SK hynix Products is used to indicate a parity error while the memory module operates in the first mode (e.g., a 

normal mode of operation). 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 172 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 172 of 181

JEDEC RDIMM Standard (annotation added).

JEDEC RDIMM Standard (annotation added).

See also SKH HHMA451R7AFR8N / HMA41GR7AFR8N / HMA41GR7AFR4N / HMA42GR7AFR4N Datasheet at 5, 

7.

During the first mode (e.g., a normal mode of operation), the RCD uses the ALERT_n signal to indicate a parity error 

having occurred.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 173 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 173 of 181

See, e.g.,JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 174 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the first mode is configurable to receive via the second edge connections the address and control signals associated with 

the one or more memory read or write operations, wherein the dynamic random access memory elements are configurable to communicate data signals with 

the memory controller via the first edge connections in accordance with the address and control signals, and wherein the module controller in the first mode 

is further configurable to output via the open drain output and the error edge connection a signal indicating a parity error having occurred in the memory 

module while the memory module is in the first mode;”

Page 174 of 181

See JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 175 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the second mode is further configurable to output to the memory controller open-drain signals related to the one or more 

training sequences via the open drain output and the error edge connection while the memory module is in the second mode.”

Page 175 of 181

wherein the module 

controller in the second 

mode is further configurable 

to output to the memory 

controller open-drain signals 

related to the one or more 

training sequences via the 

open drain output and the 

error edge connection while 

the memory module is in the 

second mode.

The module controller of the SK hynix Products is, in the second mode, further configurable to output to the memory 

controller open-drain signals related to the one or more training sequences via the open drain output and the error edge 

connection while the memory module is in the second mode.

For example, the SK hynix products are configured to drive the Alert_n signal to the error edge connection via the open 

drain output while the memory module is in Clock-to-CA training mode, e.g., the second mode. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 176 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the second mode is further configurable to output to the memory controller open-drain signals related to the one or more 

training sequences via the open drain output and the error edge connection while the memory module is in the second mode.”

Page 176 of 181

See JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 177 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the second mode is further configurable to output to the memory controller open-drain signals related to the one or more 

training sequences via the open drain output and the error edge connection while the memory module is in the second mode.”

Page 177 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 178 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the second mode is further configurable to output to the memory controller open-drain signals related to the one or more 

training sequences via the open drain output and the error edge connection while the memory module is in the second mode.”

Page 178 of 181

See JEDEC RCD01 Specification (annotation added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 179 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the second mode is further configurable to output to the memory controller open-drain signals related to the one or more 

training sequences via the open drain output and the error edge connection while the memory module is in the second mode.”

Page 179 of 181

JEDEC RDIMM Standard (annotations added).

The Alert_n signals relate to the one or more training sequences. For example, while in Clock-to-CA training mode, the 

IDT 4RCD0124KC0 RCD ORs all enabled Dn inputs from the memory controller and then outputs the result of that OR 

operation to the memory controller via the Alert_n pin. The module controller of the SK hynix Products drives the open 

drain output and the error edge connection to one of two states. 

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 180 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the second mode is further configurable to output to the memory controller open-drain signals related to the one or more 

training sequences via the open drain output and the error edge connection while the memory module is in the second mode.”

Page 180 of 181

See JEDEC RCD01 Specification (annotations added).

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 181 of 182
U.S. Patent No. 10,474,595: Claim 10

“wherein the module controller in the second mode is further configurable to output to the memory controller open-drain signals related to the one or more 

training sequences via the open drain output and the error edge connection while the memory module is in the second mode.”

Page 181 of 181

See JEDEC RCD01 Specification.

Case 6:20-cv-00194-ADA Document 1-11 Filed 03/17/20 Page 182 of 182