EXHIBIT A 

Case 6:20-cv-00160-ADA Document 1-1 Filed 02/28/20 Page 1 of 27
c12) United States Patent 

Tsividis 

(54) POWER DISSIPATION REDUCTION IN 

WIRELESS TRANSCEIVERS 

(71) Applicant: Theta IP, LLC, Coppell, TX (US) 

(72) Inventor: Yannis Tsividis, New York, NY (US) 

(73) Assignee: Theta IP, LLC, Coppell, TX (US) 

( *) Notice: Subject to any disclaimer, the term of this 

patent is extended or adjusted under 35 

U.S.C. 154(b) by 0 days. 

(21) Appl. No.: 15/080,421 

(22) Filed: Mar. 24, 2016 

(65) Prior Publication Data 

US 2016/0212700 Al Jul. 21, 2016 

Related U.S. Application Data 

(63) Continuation of application No. 11/318,646, filed on 

Dec. 27, 2005, now Pat. No. 9,331,728, which is a 

(Continued) 

(51) Int. Cl. 

H04B 1138 

H04M 1100 

(52) U.S. Cl. 

(2015.01) 

(2006.01) 

(Continued) 

CPC ........ H04W 5210209 (2013.01); H04B 11109 

(2013.01); Y02B 60/50 (2013.01) 

(58) Field of Classification Search 

CPC ... H04B 1/04; H04B 1/16; H04B 1/40; H04B 

1/109; H04B 1/0475; H04B 1/1607; 

(Continued) 

111111 1111111111111111111111111111111111111111111111111111111111111 

US00983 8962B2 

(10) Patent No.: 

(45) Date of Patent: 

US 9,838,962 B2 

Dec. 5, 2017 

(56) References Cited 

U.S. PATENT DOCUMENTS 

3,408,587 A * 10/1968 Lancaster 

4,270,222 A 5/1981 Menant 

(Continued) 

H03G 1/0052 

330/129 

FOREIGN PATENT DOCUMENTS 

DE 

EP 

10026152 

0795967 

212001 

9/1997 

(Continued) 

OTHER PUBLICATIONS 

US 6,529,069, 03/2003, Krishnapura et a!. (withdrawn) 

(Continued) 

Primary Examiner- Quochien B Vuong 

(74) Attorney, Agent, or Firm- Blakely Sokoloff Taylor 

& Zafman LLP 

(57) ABSTRACT 

Processes, methods and circuits for improving battery life by 

reducing the battery power-drain ofbattery-powered devices 

with wireless receivers is disclosed. Embodiments provide 

for variably changing the bias current, impedance, and gain 

through a plurality of values, either separately or in combination, during receiver circuit operation to optimize power 

dissipation. The dynamic changes to gain, bias and impedance characteristics of the receiver circuit may occur in any 

of an amplifier, a filter, and a mixer, and are responsive to the 

components of an input signal comprising a desired signal 

and interferer signal. Dynamic changes may also be made to 

a dynamic range and noise floor of the receiver circuit. 

6 Claims, 15 Drawing Sheets 

Case 6:20-cv-00160-ADA Document 1-1 Filed 02/28/20 Page 2 of 27
(60) 

(51) 

(58) 

(56) 

US 9,838,962 B2 

Page 2 

Related U.S. Application Data 6,668,028 B1 12/2003 Wieck 

continuation of application No. 10/784,613, filed on 6,670,901 B2 12/2003 Brueske et a!. 

6,683,492 B2 112004 Krishnapura et al. 

Feb. 23, 2004, now Pat. No. 7,010,330. 6,687,491 B2 2/2004 Wieck 

6,694,129 B2 2/2004 Peterzell et a!. 

Provisional application No. 60/451,230, filed on Mar. 6,697,611 B1 2/2004 Franca-Neto 

6,710,651 B2 3/2004 Forrester 

1, 2003, provisional application No. 60/451,230, filed 6,714,557 B1 3/2004 Smith et al. 

on Mar. 1, 2003. 6,724,251 B1 4/2004 Ziazadeh et a!. 

6,735,424 B1 5/2004 Larson eta!. 

Int. Cl. 6,784,738 B1 8/2004 Jin eta!. 

H04W52102 (2009.01) 6,801,760 B2 10/2004 Hutchinson et a!. 

6,807,406 B1 10/2004 Razavi eta!. 

H04B 1110 (2006.01) 6,819,938 B2 1112004 Sahota 

Field of Classification Search 6,819,939 B2 1112004 Masarnura 

CPC .. H04B 17/309; H04B 17/318; H04B 17/336; 6,826,418 B2 1112004 Adachi eta!. 

H04B 17/345; H04B 2001/045; H04B 6,870,425 B2 * 3/2005 Leifso ................. H03F 3/45085 

2001/0416; H04W 52/52; H04W 52/0261; 

330/254 

6,933,779 B2 8/2005 Lee eta!. 

H04W 88/02; H03G 3/004; H03G 3/20 6,944,427 B2 9/2005 Haub eta!. 

USPC ........... 455/63.1, 67.13, 127.1, 127.2, 127.5, 6,963,755 B2 1112005 Chen eta!. 

455/226.1, 226.2, 232.1, 234.1, 250.1, 6,965,655 B1 1112005 Mostov eta!. 

455/251.1, 295, 296, 311, 343.1, 572, 6,993,297 B2 112006 Smith, Jr. 

7,016,654 B1 3/2006 Bugeja 455/574; 370/442; 330/127, 134, 144 7,054,605 B1 5/2006 Groe 

See application file for complete search history. 7,079,825 B2 7/2006 Wieck 

7,095,994 B1 8/2006 Aytur et al. 

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6,157,668 A 12/2000 Gilhousen et a!. GB 2362523 1112001 

6,175,279 B1 112001 Ciccarelli et al. wo W0-02/35756 5/2002 

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6,298,221 B1 10/2001 Nguyen wo W0-2004/0 17 589 2/2004 

6,339,711 B1 112002 Otaka et al. 

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6,370,187 B1 4/2002 Agah 

6,370,210 B1 4/2002 Yamamoto Aparin, Vladimir , et a!., "A Highly-Integrated Tri-Band!Quad6,388,525 B1 5/2002 Bien Mode SiGe BiCMOS RF-to-Baseband Receiver for Wireless 

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6,633,550 B1 10/2003 Gardenfors et a!. Behbahani, Farbod , et a!., "Adaptive Analog IF Signal Processor 

6,639,447 B2 10/2003 Manku eta!. for a Wide-Band CMOS Wireless Receiver", IEEE Journal of 

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Case 6:20-cv-00160-ADA Document 1-1 Filed 02/28/20 Page 3 of 27
US 9,838,962 B2 

Page 3 

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Hollman, Tuomas, eta!., "A 2.7-V CMOS Dual-Mode Baseband 

Filter for PDC and WCDMA", IEEE Journal of Solid-State Circuits, vol. 36, No.7, (Jul. 2001), pp. 1148-1153. 

Lee, Kang-Yoon , et a!., "Full-CMOS 2-GHz WCDMA Direct 

Conversion Transmitter and Receiver", IEEE Journal of Solid-State 

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Leung, Vincent , et al., "Digital-IF WCDMA Handset Transmitter 

IC in 0.25um SiGe BiCMOS", 2004 IEEE International Solid-State 

Circuits Conference, (2004), pp. 182-183. 

Orsatti, Paolo, eta!., "AlO-mA-Receive, 55-rnA-Transmit, SingleChip GSM Transceiver in 0.25-m CMOS", IEEE Journal of SolidState Circuits, vol. 34, No. 12, (Dec. 1999), pp. 1869-1880. 

Parssinen, Aarno, et a!., "A 2-GHz Wide-Band Direct Conversion 

Receiver for WCDMA Applications", IEEE Journal of Solid-State 

Circuits, vol. 34, No. 12, (Dec. 1999), pp. 1893-1903. 

Reynolds, S , eta!., "A Direct-Conversion Receiver IC for WCDMA 

Mobile Systems", Proceedings of the 2002 Bipolar/BiCMOS Circuits and Technology,(2002), pp. 61-64. 

Ryynanen, Jussi , et a!., "RF Gain Control in Direct Conversion 

Receivers", IEEE, (2002), pp. IV-117-IV-120. 

Sanielevici, Sergio A., eta!., "A 900-MHz Transceiver Chipset for 

Two-Way Paging Applications", IEEE Journal of Solid-State Circuits, vol. 33, No. 12, (Dec. 1998), pp. 2160-2168. 

Tadjpour, Shahrzad, "A900 MHz Dual Conversion, Low-IF CMOS 

GSM Receiver", A dissertation submitted in partial satisfaction of 

the requirements for the degree Doctor of Philosophy in Electrical 

Engineering, University of California, Los Angeles, (200 1 ). 

Tasic, Aleksandar, eta!., "Concept of Frequency-Transconductance 

Tuning of Bipolar Voltage-Controlled Oscillators", IEEE, (2002), 

pp. III-555-III-558. 

Tasic, Aleksandar, et al., "Concept of Phase-Noise Tuning of 

Bipolar Voltage-Controlled Oscillators", IEEE, (2002), pp. V-161-

V-164. 

Tsividis, Y ., et a!., "Internally Varying Analog Circuits Minimize 

Power Dissipation", IEEE Circuits& Devices Magazine, (Jan. 

2003), pp. 63-72. 

Tsividis, Y , "Minimising power dissipation in analogue signal 

processors through syllabic companding", Electronic Letters, vol. 

35, No. 21, (Oct. 14, 1999), pp. 1805-1807. 

Van Den Bos, Chris, et al., "Architecture of a reconfigurable radio 

receiver front-end using overall feedback", Electronics Research 

Laboratory, Delft University of Technology, (2001). 

Xiong, Wei , et a!., "An S-hand Low-Noise Amplifier with SelfAdjusting Bias for Improved Power Consumption and Dynamic 

Range in a Mobile Environment", 1999 IEEE Radio Frequency 

Integrated Circuits Symposium, TUE5-4, (1999), pp. 193-196. 

Yoshizawa, Atsushi, et al., "An Anti-Blocker Structure MOSFET-C 

Filter for a Direct Conversion Receiver", IEEE 2001 Custom 

Integrated Circuits Conference, (2001), pp. 5-8. 

Zargari, Masoud , et al., "A Single-Chip Dual-Band Tri-Mode 

CMOS Transceiver for IEEE 802.11a/b/g WLAN", 2004 IEEE 

International Solid-State Circuits Conference, (2004), pp. 96-97. 

"Office Action dated Nov. 1, 2016; U.S. Appl. No. 15/080,432", 

(dated Nov. 1, 2016). 

Christensen, Craig L., "A Low Power, Low Datarate Integrated 

433MHz Wireless Transceiver in CMOS", Proceedings of the 15th 

Biennial University/Government/Industry Microelectronics Symposium, (2003), pp. 70-73. 

Rudell, Jacques C., et a!., "Recent Developments in High Integration Multi-Standard CMOS Transceivers for Personal Communication Systems", Proceedings of the 1998 International Symposium on 

Low Power Electronics and Design, (Aug. 10-12, 1998), pp. 149-

154. 

Schuchter, Walter, et a!., "A Single Chip FSK/ASK 900MHz 

Transceiver in a Standard 0.25um CMOS Technology", 2001 IEEE 

Radio Frequency Integrated Circuits(RFIC) Symposium, (200 1 ), 

pp. 183-186. 

* cited by examiner 

Case 6:20-cv-00160-ADA Document 1-1 Filed 02/28/20 Page 4 of 27
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US 9,838,962 B2 

1 

POWER DISSIPATION REDUCTION IN 

WIRELESS TRANSCEIVERS 

CROSS-REFERENCES TO RELATED 

APPLICATIONS 

This application is a continuation of U.S. patent application Ser. No. 11/318,646, filed Dec. 27, 2005, which is a 

continuation of U.S. patent application Ser. No. 10/784,613, 

filed Feb. 23, 2004, which claims the benefit of U.S. 

provisional application No. 60/451,229, filed Mar. 1, 2003, 

which is incorporated by reference. 

This application claims the benefit of U.S. provisional 

application No. 60/451,230, filed Mar. 1, 2003, which is 

incorporated by reference. 

BACKGROUND 

The present invention relates to power dissipation reduction techniques for electronic circuits, for example wireless 

transceiver integrated circuits. 

Wireless networking is quickly becoming ubiquitous, as 

desktop, notebook, and handheld computers are connected 

to share Internet access and files. Wireless networking cards 

compatible with PCMCIA and compact flash form factors 

are popular for laptops and handhelds respectively, particularly as mobile users connect to the Internet on the road at 

coffee shops, hotels, and airports. 

A downside of this connectivity is a corresponding drain 

on battery life, especially for these portable devices. The 

power consumed by a wireless transmitter and receiver 

reduces the usefulness of a device and sends a user on a hunt 

for an electrical outlet for recharging. 

One reason why this power drain is high is that electronic 

circuits are typically designed to function properly under 

worst-case operating conditions. For a wireless transceiver, 

the worst case condition is when a desired signal reception 

strength is low, while other transceivers or nearby electronic 

equipment generate interfering signals and other spurious 

nmse. 

But a wireless transceiver does not always operate in 

these worst-case conditions. For example, a base station, 

router or access point may be nearby such that the received 

signal is strong. Also, there may be no interfering signals, or 

they may be relatively weak. In these situations, receiver 

circuit currents can be reduced below what is necessary for 

the worst case condition. If this is done, power dissipation is 

reduced, and battery life is increased. 

Thus, what is needed are circuits and methods that can 

adapt to a better-than-worst-case condition and reduce circuit currents and therefore power dissipation accordingly. 

SUMMARY 

Accordingly, embodiments of the present invention provide methods and circuits for reducing power dissipation in 

wireless transceivers and other electronic circuits and systems. Embodiments of the present invention use bias current 

reduction, impedance scaling, gain, and other dynamic 

changes either separately or in combination to reduce power 

dissipation in response to better-than-worst case conditions. 

For example, bias currents are reduced in response to a need 

for reduced signal handling capability, impedances are 

scaled thus reducing required drive and other bias currents 

in response to a strong received signal, or gain is varied and 

impedances are scaled in response to a low received signal 

in the presence of no or weak interfering signals. Alternately, 

2 

currents may start low and be increased in response to 

worse-than-best-case conditions, or they may start at a point 

in between and vary up or down. These variations may be 

made to electronic systems generally, and are particularly 

suited and discussed below in the context of a wireless 

transceiver that may be used in networking devices, cellular 

telephones, and other wireless systems. 

An exemplary embodiment of the present invention provides a method of receiving a signal using an integrated 

10 circuit. The integrated circuit includes a signal path having 

a low-noise amplifier configured to receive the signal, a 

mixer having an input coupled to an output of the low-noise 

amplifier, and a low-pass filter having an input coupled to an 

output of the mixer. The method itself includes determining 

15 a first signal strength at a first node in the signal path in the 

integrated circuit and dynamically changing an impedance 

of a component in the signal path based on the first signal 

strength. 

A further exemplary embodiment of the present invention 

20 provides a method of receiving a signal using an integrated 

circuit. The integrated circuit includes a signal path having 

a low-noise amplifier configured to receive the signal, a 

mixer having an input coupled to an output of the low-noise 

amplifier, and a low-pass filter having an input coupled to an 

25 output of the mixer. The method itself includes determining 

a first signal strength at a first node in the signal path in the 

integrated circuit and dynamically changing a bias current in 

the signal path based on the first signal strength. 

Another exemplary embodiment of the present invention 

30 provides a method of receiving a signal using an integrated 

circuit. The integrated circuit includes a signal path having 

a first circuit and a second circuit having an input coupled to 

an output of the first circuit. The method itself includes 

determining a first signal strength at a first node in the signal 

35 path in the integrated circuit. The first node is before the first 

circuit in the signal path. The method further includes 

dynamically changing a gain of the first circuit based on the 

first signal strength and dynamically changing an impedance 

of a component in the second circuit based on the first signal 

40 strength. 

Still a further exemplary embodiment of the present 

invention provides a wireless transceiver integrated circuit 

including a receiver having a signal path, the signal path 

including a low-noise amplifier, a mixer having an input 

45 coupled to an output of the low-noise amplifier, and a 

low-pass filter having an input coupled to an output of the 

mixer, as well as a first signal strength indicator circuit 

coupled to the signal path and configured to determine a first 

signal strength. An impedance in the signal path is config50 ured to be dynamically adjusted in response to the first signal 

strength. 

Yet a further exemplary embodiment of the present invention provides a wireless transceiver integrated circuit. This 

integrated circuit includes a receiver comprising a signal 

55 path, the signal path having a low-noise amplifier, a mixer 

having an input coupled to an output of the low-noise 

amplifier, and a low-pass filter having an input coupled to an 

output of the mixer, as well as a first signal strength indicator 

circuit coupled to the signal path, and configured to deter60 mine a first signal strength. A bias current in the signal path 

is configured to be dynamically adjusted in response to the 

first signal strength. 

Another exemplary embodiment of the present invention 

provides a wireless transceiver integrated circuit. This cir65 cuit includes a receiver comprising a signal path, the signal 

path having a first circuit; and a second circuit having an 

input coupled to an output of the first circuit; as well as a first 

Case 6:20-cv-00160-ADA Document 1-1 Filed 02/28/20 Page 20 of 27
US 9,838,962 B2 

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signal strength indicator circuit coupled to the signal path, 

and configured to determine a first signal strength. A gain of 

the first circuit is configured to be dynamically adjusted in 

response to the first signal strength, and an impedance in the 

second circuit is configured to be dynamically adjusted in 

response to the first signal strength. 

A better understanding of the nature and advantages of the 

present invention may be gained with reference to the 

following detailed description and the accompanying drawings. 

BRIEF DESCRIPTION OF THE DRAWINGS 

10 

FIG. 1 is a block diagram of a wireless transceiver that 15 may benefit by incorporation of embodiments of the present 

invention; 

4 

is shown for illustrative purposes only and does not to limit 

either the possible embodiments of the present invention or 

the claims. 

There are three main portions of this transceiver circuit, a 

receiver, transmitter, and synthesizer. This transceiver may 

be completely or partially integrated on a semiconductor 

chip, or it may be integrated onto multiple integrated circuits. In a specific embodiment, the circuitry bounded by 

dashed line 100 is integrated on a single chip coupled to one 

or more external components or circuits. The integrated 

circuit or circuits forming this wireless transceiver may 

incorporate various integrated circuit devices such as a 

bipolar, CMOS, or BiCMOS devices made using a silicon, 

silicon-germanium (SiGe), gallium arsenide or other III-V 

process, or other manufacturing process. Embodiments of 

the present invention may also be applicable to circuits 

manufactured using nanotechnology processing. 

The receiver includes a signal path formed by low-noise 

amplifier 102, I and Q mixers 104 and 106, low pass filters 

FIGS. 2A and 2B illustrate examples of desired and 

interfering signals and noise that may be received by a 

circuit in a wireless receiver; 

FIG. 3 illustrates what can occur as a maximum signal 

handling capability is reduced in the worst-case signal 

condition; 

FIG. 4 illustrates a portion of a receiver consistent with an 

embodiment of the present invention; 

20 108 and 110, and baseband amplifiers 114 and 116. Other 

circuitry in the receiver includes received strength indicator 

122, automatic gain control circuit 166, baseband gain 

control circuit 120, tuning circuit 112, and offset cancellation circuit 118. 

FIG. 5 illustrates the relationship between a required bias 

current and a given output signal for a representative circuit; 

FIG. 6 is an example of how a circuit's impedances may 

25 

be scaled to reduce drive currents, and depending on the 

circuit configuration used, to reduce associated bias currents 30 

as well; 

FIG. 7 illustrates how gain may be inserted in a signal 

path to improve a circuit's signal to noise ratio; 

FIGS. 8A-8D illustrate some of the possible power saving 

techniques that may be used when received desired and 35 

interferer signals are all at a low power level; 

FIGS. 9A-9C illustrate one of the possible power saving 

techniques that may be used when a received desired signal 

The transmitter includes input up-converter mixers 124 

and 126, summing node 176, which may be conceptual 

rather than an actual circuit, transmit variable gain amplifier 

128, and power amplifier 130. 

The synthesizer includes a voltage-controlled oscillator 

148, which drives I and Q buffers 154 and 152, prescaler 

156, reference clock buffer 142 and divider 158, phasefrequency detector 160, charge pump 162, and loop filter 

146, which in a specific embodiment is formed by external 

components. 

Signals are received on an antenna, not shown, and 

typically pass through an RF switch and bandpass filter 

before being received by the low-noise amplifier 102 on line 

101. The low noise amplifier gains the received signal and 

is strong while all interfering signals are at a low power provides it to quadrature mixers 104 and 106. I and Q mixers 

level; 

FIGS. 10A-10C illustrate one of the possible power 

saving techniques that may be used when received desired 

and interferer signals are all at a high power level; 

40 104 and 106 down-convert the received signal to baseband 

by multiplying them with quadrature versions of the oscillator signal provided by buffers 152 and 154. This down 

conversion also produces a high frequency component at a 

FIGS. 11A-11D illustrate one of the possible power 

saving techniques that may be used when a received desired 45 

signal is weak while one or more interfering signals are 

strong; 

FIG. 12 is a summary illustrating four different input 

conditions and some of the appropriate power-saving 

changes that may be made in response to those conditions; 50 

FIG. 13 shows how power may be saved as a function of 

time by employing one or more of the power saving methods 

consistent with embodiments of the present invention; 

FIG. 14 is a block diagram of a portion of a receiver 

consistent with an embodiment of the present invention; and 55 

FIG. 15 is a block diagram of a portion of a transmitter 

consistent with an embodiment of the present invention. 

frequency that is equal to the sum of the frequencies of the 

received signal and the VCO. This unwanted signal is 

filtered by low pass filters 108 and 110, which in turn drive 

baseband amplifiers 114 and 116. The outputs of baseband 

amplifiers 114 and 116 are typically converted to digital 

signals by analog-to-digital converters at the front end of a 

digital signal processing block. 

In the transmit mode, I and Q versions of the signal to be 

transmitted are provided on lines 121 and 123 to up-convert 

mixers 124 and 126. These up-convert mixers multiply the 

I and Q portions of the transmit signal by quadrature 

versions of the VCO signal provided by buffers 152 and 154. 

The outputs of the up-convert mixers 124 and 126 are 

sUlllilled, and amplified by transmit VGA 128, which in tum 

drives power amplifier 130. The output of power amplifier 

DESCRIPTION OF EXEMPLARY 130 is typically filtered, and passes through the RF switch to 

EMBODIMENTS 60 the antenna for transmission. 

FIG. 1 is a block diagram of a wireless transceiver that 

may benefit by incorporation of embodiments of the present 

invention. This wireless transceiver may be designed to send 

and receive signals consistent with the IEEE 802.11a, 

802.11b, 802.11g, or other signaling standard or combination of standards. This figure, as with all the included figures, 

A reference clock is received and buffered by the reference buffer 142. The VCO generates quadrature oscillatory 

signals that are divided by prescaler 156. The reference 

clock is typically generated by a crystal or other stable 

65 periodic clock source. The phase-frequency detector 116 

compares the phase or frequency (depending on whether the 

synthesizer is tracking or acquiring the correct frequency) of 

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US 9,838,962 B2 

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the divided VCO signal and the reference clock, or a divided 

version of the reference clock, and generates an error signal, 

which drives the charge pump 162. The output signal of the 

charge pump 162 is filtered by the loop filter 146, which is 

commonly a lead-lag filter, and which provides a tuning or 

correction signal to the VCO 148. 

6 

density integrated over the bandwidth of interest. For simplicity and comparison, this level is shown as a horizontal 

line, and is not meant to imply noise density. 

Often in wireless receivers, a circuit at different times will 

receive an input spectrum similar to those shown in FIGS. 

2A and 2B. The input spectrum of FIG. 2B is generally 

considered the worst-case input signal, and typical design 

methodology involves designing a receiver for this condition, specifically the weakest desired signal accompanied by 

Embodiments of the present invention may be used to 

reduce the power dissipation of one or more of these 

included circuits. For example, the power dissipation in the 

low-noise amplifier 102, down-convert mixers 104 and 106, 

low pass filters 108 and 110, or baseband amplifiers 114 and 

116 may be optimized. Also, power dissipation in up-convert 

mixers 124 126, variable gain amplifier 128, and power 

amplifier 130 may also be optimized. Similarly, VCO 148 

and prescaler 156 currents may be adjusted. Embodiments 

of the present invention may also be applied in other circuits 

which may be included in other integrated circuit receivers, 

transmitters, transceivers, or other electronic circuits or 

systems. 

10 largest interference level. Circuit impedances and currents 

are set such that the noise floor 264 is sufficiently low for an 

acceptable bit-error rate, while bias currents are set sufficiently high for the required Smax 262. 

Conversely, the input spectrum in FIG. 2A is that of the 

15 best-case input signal, specifically, a robust desired signal 

accompanied by no or low-level interferers. In this case, the 

noise floor 214 may be allowed to rise, while the maximum 

signal handling capability Smax 212 may be reduced. When 

this is done, the receiver circuit may save significant power. 

When a receiver is actively receiving a desired signal, 

each block in the signal path has at its input the desired 

signal as well as noise and possibly interfering signals. The 

desired signal is the useful, information-carrying portion of 

20 For example, the circuit's impedances may be increased, 

thus reducing required drive currents. Similarly, bias currents may be lowered, thus reducing the maximum signal in 

handling capability. 

a received signal. The noise may be thermal, shot, or other 

noise generated on the integrated circuit, in addition to 

received noise generated by sources external to the chip. The 

noise at the input of a block may be referred to as the 

equivalent input noise. The interfering signal or signals, or 

interferers, may be generated by similar transceivers, or 

other electrical equipment, circuits, or systems. 

The minimum power dissipation for a circuit is propor25 tiona! to the required maximum signal-to-noise ratio, which 

is the ratio between Smax 212 or 262 and N 214 or 264. 

Thus, a circuit receiving an input similar to the one shown 

in FIG. 2A can dissipate less power than one receiving the 

input as shown in FIG. 2B, while still achieving an accept30 able bit-error rate. 

FIGS. 2A and 2B illustrate examples of desired signals, 

interferers, and noise that may be received by one of the 

various circuits in a wireless receiver. In each of these 

figures, the signal strength is plotted along a Y-axis 204 or 

254 as a function of frequency along an X-axis 202 or 252. 35 

In the example of FIG. 2A, a received desired signal 206 is 

large in comparison to interfering signals 208 and 210. In 

these examples, two interfering signals are shown for illustrative purposes, though there may be no such signals, one 

such signal, or more than two such signals in the frequency 40 

range of interest. Also, while for these examples the interferers are shown as being at a higher frequency than the 

desired signal, there may be one or more interferers at higher 

or lower frequencies as the desired signal. In this specific 

example, the acceptable noise floor 214 is relatively high, 45 

while maximum signal handling capability Smax 212 (that 

is the maximum signal power that can be handled with an 

acceptably low distortion) needs only to be high enough to 

accommodate the desired signal. For this specific example, 

the circuit receiving this input spectrum only requires a 50 

relatively small dynamic range for proper operation, that is 

the range between Smax 212 and the noise floor 214 is 

relatively small. 

FIG. 3 illustrates what can occur when the maximum 

signal handling capability Smax 314 is reduced in the 

worst-case condition, that is when a weak desired signal 306 

is accompanied by large interferers 310 and 312. Again, 

signal strength is plotted along a Y-axis 304 as a function of 

frequency along X-axis 302. In this specific example, Smax 

314 is reduced below the peak levels of the interferers 310 

and 312. Since Smax is low, the circuit cannot handle the 

interferers linearly. The resulting nonlinearities lead to a 

mixing of the interferers and the creation of intermodulation 

products 308 (for example, a third-order intermodulation 

distortion, IM3), one of which in this example occurs at the 

same frequency as the desired signal 306. As can be seen, if 

the intermodulation products 308 become excessive, the 

received signal bit error rate may become excessive, and the 

desired signal 306 may be lost. Accordingly, while Smax 

may be lowered even under some unfavorable conditions in 

order to reduce power, care should be taken to avoid 

corruption of the received desired signal. 

FIG. 4 illustrates a portion of a receiver consistent with an 

embodiment of the present invention. Included is a filter 

430. An optional gain element 420 is placed in front of the 

filter 430 in order to increase signal levels. Signal strength 

indicator circuits 440 and 450 are connected to input line 

410 and output line 460. In this specific example, the input 

signal spectrum on line 410 is shown as desired signal 412 

and interferers 414 and 416. The signal spectrum at the 

output line 460 is shown as desired signal 462 and interferers 

464 and 466. The signal strength indicators 440 and 450 do 

not provide information as to the relative sizes of the desired 

and interfering signals. Rather, a cumulative signal level is 

provided at their outputs. For example, the first signal 

strength indicator 440 outputs a level corresponding to the 

sum of desired signal 412 and interfering signals 414 and 

Conversely, in the example shown in FIG. 2B, the desired 

signal 256 is relatively weak compared to the large inter- 55 

ferers 258 and 260. In this example, the noise floor 264 

should be relatively low so as to prevent an unacceptable 

level of error in the recovery the desired signal 256. The 

maximum signal handling capability Smax 262 should be 

relatively high to accommodate the large interferers in order 60 

to avoid the creation of intermodulation products as 

described below. Accordingly, in this specific example, the 

circuit receiving this input spectrum should have a large 

dynamic range, particularly in comparison to the example of 

FIG. 2A. 65 416, while the second signal strength indicator 450 provides 

a signal level corresponding to the sum of desired signal 462 

and interfering signals 464 and 466. In this specific example, 

It should be noted that the noise level or noise floors 

shown in these and the other included figures is the noise 

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US 9,838,962 B2 

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the gain of the gain and filter circuit combinations is shown 

as approximately one, while the interfering signals 414 and 

416 signal levels are reduced. 

8 

source can be reduced. Many other examples where drive 

currents and possibly bias currents may be reduced will be 

appreciated by one skilled in the art. 

FIG. 7 illustrates another degree of freedom that made be 

employed to reduce current levels in a transceiver. Specifically, a gain element 720 may be inserted in front of a circuit 

block 730 in order to improve the combined circuit's signalto-noise ratio by a factor equal to the gain of the inserted 

gain block. This is particularly useful when large interferers 

A comparison of the signal levels provided by the signal 

strength indicators 440 and 450 indicates that much of the 

combined received signal on line 410 has been filtered. 

Accordingly, it may be deduced that large interfering signals 

present at the input are being filtered by the filter 430. From 

this information, as will be shown in greater detail below, the 

bias, impedance, and gain of the gain stage 420 and filter 430 

combination may be optimized to reduce power dissipation. 

10 are absent and the desired received signal is moderate or low. 

There are several real world situations where the received 

signal is better than the worst-case condition such that power 

can be saved. For example, large interferers may be present 

only part of the time, that is, on a temporary or transient 15 

basis. The interfering equipment may be some distance from 

the transceiver, or it may be operating in the low power 

mode. Also, the desired signal may be very strong as 

compared to the noise and interferers, for example a hub, 

router, or access point may be nearby. 20 

Specifically, gain is added to the signal while impedances 

are increased, which raise the noise floor. In this way, a given 

signal-to-noise ratio may be maintained while the power is 

decreased. 

The gain of such an element may be varied by increasing 

a current in a differential pair or increasing a load resistance 

using switches. Many other examples where the gain of this 

element may be varied will be appreciated by one skilled in 

the art. 

These variables, or degrees of freedom, specifically 

reducing bias currents, increasing impedances, and increasing gain may be used as in the following examples. 

FIG. SA is a block diagram of a functional block S20 and 

optional gain element S10 in accordance with an embodiSome transceivers consistent with embodiments of the 

present invention are designed to work with more than one 

data transfer specification or standard. In this case, when a 

transceiver is operating in a mode having a lower data rate, 

the power saving techniques described here may be 

employed. 

FIG. 5 illustrates the relationship between a required 

biased current 516 for a given output signal 514 for a 

representative circuit 510. If the output signal current level 

is relatively low, such as the output current shown as 526, 

the corresponding bias current 52S may be low. Conversely, 

if the output signal current level is larger as with the example 

536, the corresponding bias current level 53S should also be 

high. Accordingly, if a bias current is initially set high to 

handle large a large input signal, for example a large 

interferer, this current may be reduced if the input signal is 

smaller. 

25 ment of the present invention. Functional block S20, like the 

functional blocks in the following diagrams, may be a filter, 

mixer, amplifier, or other circuit or circuits in a wireless 

transceiver or other electronic circuits or system. An input 

signal is received on line S12 by the optional gain element 

30 S14. When the optional gain block S10 is not used, the input 

signal may be received directly by the function block S20. 

The gain of the optional gain element S12 is controlled by 

a gain control signal on line S14. The functional block 

receives an output signal from the optional gain element S10 

There are many ways by which these bias currents can be 

reduced. For example, the current may be generated by 

placing a voltage across a resistor by applying a bias voltage 

35 and provides an output VOUT on line S22. The lines in this 

and the other included figures may be one or more lines, 

depending on whether single-ended, differential, or other 

type of signaling is employed. 

One or more impedances are under control of signals on 

40 impedance control lines S24. Similarly, one or more bias 

to the base of a device whose emitter is connected to ground currents in the function block are under control of one or 

through a resistance. In this case, the resistor may be 

increased by opening switches across portions of the resistance, or lowering the bias voltage applied at the base. 

Several ways in which this may be done will be readily 45 

understood by one skilled in the art. 

FIG. 6 is an example of how a circuit's impedances may 

be scaled to reduce drive currents, and, depending on the 

circuit configuration used, associated bias currents as well. 

A driver 612 has a load R 614 and C 616. The frequency 50 

response of this circuit is the same as that seen by driver 622, 

which drives an impedance of 2R 624 and C/2 626. But the 

impedance of the load seen by driver 622 is double that seen 

more signals on bias control lines S26. These various control 

lines may be logic signals, analog signals, voltage or currents lines, or other signal or bias lines. In other embodiments of the present invention, the gain control element S10 

may be included in the function block S20. Also, various 

embodiments may not incorporate either or both the impedance control and bias control. 

FIG. SB is an example input that may be present on line 

YIN S12. In this example, a desired signal S36 is relatively 

weak, as are interfering signals S37 and S3S. The initial bias 

and circuit configuration is such that the noise floor S33 and 

maximum signal handling capability Smax S31 are adjusted 

by 612, thus the output current required by the driver 622 is for worst case conditions. The circuit of FIG. SA, as with all 

reduced by one-half. 55 the circuits described here, receives noise at its input which 

may be referred to as input equivalent noise or input referred 

noise. Additionally, the circuit of FIG. SA generates noise 

which is added to the input referred noise. Depending on the 

As an example, the output stage of each of these drivers 

may be a Class A emitter follower formed by an emitter 

follower connected to a current source. When the outputs are 

driven high, the emitter of driver 622 need supply only 

one-half the drive current as driver 612. In this way, an 60 

impedance can be scaled in order to decrease a circuit's 

required drive current. 

Also, the discharge current for driver 622 is only one half 

that of driver 612 for a given negative-going slew rate. Thus, 

the current source of 622 may be reduced by the same factor 65 

of one-half as compared to driver 612. In this example, the 

bias current, that is the current in the pull-down current 

gain characteristics of the circuitry, the output noise at 

various frequencies may be greater than, equal to, or less 

than the input referred noise. For simplicity, the noise floor 

and maximum signal handling capability Smax, in this and 

the other figures, are shown as straight lines, though the 

noise and Smax are typically curved as a function of 

frequency. 

That the input spectrum is as shown in FIG. SB can be 

determined, for example, by low signal strength indications 

Case 6:20-cv-00160-ADA Document 1-1 Filed 02/28/20 Page 23 of 27
US 9,838,962 B2 

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on line YIN 812 and YOUT 822. That is, a low level signal 

strength indication on line YIN 812 indicates that no portion 

of the input signal is particularly large. 

For this exemplary input, there are at least two methods 

by which the power dissipation for this circuitry may be 

reduced. Depending on the exact circuits and structures 

used, one of these methods may be preferred. 

10 

control the gain of gain control element 1010, while one or 

more impedance and bias control signals are received by the 

function block 1020 on line to 1024 and 1026. 

FIG. lOB illustrates a received signal that may be received 

on line YIN 1012. In this example, the desired signall036 

and interferers 1037 and 1038 are each relatively large. This 

may be determined, for example, by detecting a large signal 

level at the input line YIN 812 and a smaller signal level 

after a filter, since these readings would indicate that a large 

signal is received, but that interferers are being reduced. 

As before, in this example, the noise floor 1033 and 

maximum signal handling capability 1031 are initially set 

for the worst case conditions. Since the desired signal is 

relatively large in this case, the noise floor may be allowed 

In FIG. 8C, the bias current is decreased, thereby lowering 

the maximum signal handling capability 841 as compared to 

831, closer to the desired and interfering signal levels. 10 

Again, the bias currents in the function block 820 may be 

reduced by switching impedances that appear across a 

voltage thereby changing a resulting bias current, by reducing a voltage at the gate of a MOS or base of a bipolar 

transistor, or by other methods. 

In FIG. 8D, a second method of reducing power dissipation in the function block 820 is employed. Specifically, 

Smax 851 is held constant as compared Smax 831. The 

desired and interfering signals are amplified such that they 

are closer to the available signaling handling capability 851. 20 

Also, the noise floor 853 is raised as compared to noise floor 

833 in FIG. 8B. Specifically, the noise contributed by the 

function block 820 is increased, such that the noise at its 

output is increased to noise floor 853. This is done by 

increasing one or more impedance in function block 810, 25 

such that drive currents inside that block are reduced. 

15 to rise, a shown by noise floor 1043 in FIG. lOC. Since the 

desired signal 1046 and interferers 1047 are large, the 

maximum signal handling capability Smax 1041 remains 

constant. Again, the noise floor is increased by increasing 

Depending on the exact configuration, this may also allow 

some biasing currents to be reduced, while maintaining the 

maximum signal handling capability 851 at a sufficient level. 

Alternately, these two methods of reducing power dissipa- 30 

tion in function block 820 may be done in combination. 

The included examples are explained for the exemplary 

situation where biasing and other parameters are set for 

worst-case conditions, and then changed to save power 

when it is discovered that the conditions are better-than- 35 

worst case. Alternately, the bias currents and other parameters may be set for maximum power savings, or an intermediate point, and the power can be adjusted from there. 

FIG. 9A illustrates a block diagram including an optional 

gain element 910 and function block 920. Again, an input 40 

signal is received on line 912 by optional gain element 910 

which in turn drives function block 920. The function block 

provides an output YOUT on line 922, and receives impedance and bias control signals on lines 924 and 926. 

impedances in the function block 1020. This reduces the 

required drive current, and may also allow for a reduction in 

bias currents. 

FIG. 11A illustrates a block diagram including an optional 

gain element 1110 and function block 1120 in accordance 

with an embodiment of the present convention. An input 

signal is received on line 1112 by the optional gain control 

element 1110, while an output signal is provided by the 

function block 1120 on line YOUT 1122. Gain, impedance, 

and bias control signals are received on lines 1114, 1124, and 

1126. 

FIG. 11B is an exemplary input signal that may be 

received by the gain control element 1110 on line YIN 1112. 

In this specific example, the desired signal1136 is relatively 

low or weak while the interfering signals 1137 and 1138 are 

large. This may be determined, for example, by detecting a 

large signal level at the input line YIN 812 and a much 

smaller signal level after a filter, since these readings would 

indicate that a large signal is received and that large interferers are being reduced such that the resulting signal, the 

desired signal, is relatively weak. 

Again, the maximum signal handling capability 1131 and 

noise floor 1133 are initially set for worst case conditions. If 

the desired signal is sufficiently low, while the interferers are 

sufficiently high, power savings may not be achievable over 

the worst case settings, since this is in fact the worst case 

FIG. 9B shows the spectrum for what may be considered 

a best-case received signal. Specifically, the desired signal 

936 is strong, while the interfering signals 937 and 938 are 

relatively weak. This may be determined, for example, by 

detecting a large signal level at the input line YIN 812 and 

a large signal level after a filter, since these readings would 

indicate that a large signal is received, but that it is at the 

desired signal frequency. 

45 condition. But, if the desired signal is somewhat larger than 

the worst case condition, then power may be saved in at least 

two different ways. 

For example, FIG. 11C shows the maximum signal handling capability 1141 being lowered. In this case, the inter50 fering signals 1147 in 1148 began to clip and distort, thereby 

creating intermodulation products 1145, which distort the 

desired signal 1146. So long as care is taken to not corrupt 

The maximum signaling capability 931 and noise floor the desired signal1146 beyond an acceptable limit, typically 

933 are shown as being set for the worst case conditions. In 

this case, the noise floor 933 is lower than the maximum 55 

allowed for proper signal reception. Accordingly, one or 

more impedance in the function block 920 may be increased, 

such that the noise floor 943 rises as shown in FIG. 9C. In 

this way one or more of the driving currents in the function 

block 920 may be reduced. Similarly, since the drive current 60 

is reduced, one or more bias current may also be reduced, 

depending on the exact circuit configuration. 

measured by a bit-error rate, power may be reduced in this 

way. 

Similarly, in FIG. 11D, the noise floor 1153 is raised 

somewhat, thereby saving power. Again, this may be done so 

long as the noise floor is not sufficiently high that the system 

bit-error rate becomes unacceptable. 

FIG. 12 is a summary of the above four examples. The 

received signal strengths are shown in column 1210, while 

appropriate power saving responses are listed in column 

1220. Specifically, in row 1230, the desired signal and 

interferer signal strengths are both weak or small. In this 

FIG. lOA illustrates a block diagram showing an optional 

gain element 1010 driving a function block 1020. An input 

signal is received by the gain element 1010 on line 1012, and 

an output is provided by function block 1020 on line YOUT 

1022. One or more gain control signals present on lines 1014 

65 case, proper responses include decreasing Smax, or increasing one or more circuit impedances while increasing the 

circuit gain. Depending on the exact circuit configuration, 

Case 6:20-cv-00160-ADA Document 1-1 Filed 02/28/20 Page 24 of 27
US 9,838,962 B2 

11 

one of these options may be preferred over the other. 

Alternately, they may be done in combination, or done in 

combination with other power saving techniques. Also, in 

some specific embodiments, when both desired signal and 

interferer signal strengths are small, the gain may need to be 

increased while the impedance is maintained or not 

increased in order to keep the noise floor low. 

In row 1240, the desired signal strength is strong or large, 

while the interfering signals are small. In this case, an 

appropriate response is to increase one or more of the circuit 10 

impedances. Again, depending on the exact circuit in question, one or more of the bias currents may also be reduced. 

In row 1250, both the desired signals and interfering 

signal strengths are large. Again, in this case an appropriate 

response is to increase one or more of the circuit imped- 15 

ances. 

In row 1260, the received desired signal strength is weak 

or small, while the interfering signals are large. Since this is 

the worst case situation for which the circuit is designed, 

substantial power savings are difficult to achieve. However, 20 

again, if the received signal is above a minimum level 

necessary for proper operation, some distortion of the interferers or raising of the noise floor may be acceptable. 

It should be noted that not all possible signal conditions 

are listed here. For example, either the signal or interferer 25 

may be of a relatively medium strength, or the interferer may 

be absent. Also, these terms are for exemplary purposes and 

are not meant to convey specific signal conditions, but rather 

are only qualitative. The proper response to a specific 

condition depends on the embodiment of the present inven- 30 

tion, the particular circuit topology, the requirements of the 

signaling standard used, as well as other constraints. 

FIG. 13 is an example shown how power may be saved as 

a function of time by employing one or more of these 

methods consistent with embodiments of the present inven- 35 

tion. Power is plotted along a Y-axis 1304 as a function of 

time along X-axis 1302. Conventional worst case design 

would fix power dissipation at line 1310. As can be seen, 

dynamic power dissipation 1320 under the control of variable gains, impedances, biasing, or combination thereof, 40 

allows for a lower average power 1330 as compared to the 

power dissipated 1310 by the conventional design. 

FIG. 14 is a block diagram of a portion of a receiver 

consistent with an embodiment of the present invention. 

Included are low-noise amplifier 1410, mixer 1420, gain 45 

stage 1430, filter 1440, AGC amplifier 1450, and VCO 1460. 

Signal strength detection is done at the output of the lownoise amplifier by signal strength indicator 1470, at the 

output of the mixer by signal strength indicator 1472, and at 

the output of the filter by signal strength indicator 1474. The 50 

outputs of the signal strength indicator circuits are received 

by the computational circuit 1470, which in tum controls 

gain and power control circuits 1480 and 1485. Power and 

gain control circuits 1480 and 1485 control the gain, biasing, 

and impedance levels of the circuits in the receiver signal 55 

path. Also, the gain and power control circuits may control 

the same parameters in the VCO 1460. This figure is greatly 

simplified for purposes of explanation. For example, the 

quadrature nature of the mixers and following circuits are 

not shown. Also, power-down and start-up circuits are not 60 

included. 

The current level in the low-noise amplifier determines a 

multitude of parameters including voltage gain, linearity, 

input impedance matching, and noise figure. When conditions are better than worst-case, some of these parameters 65 

may be relaxed while maintaining an acceptable bit-error 

rate, thus saving power. 

12 

The bias current in the mixers effect that block's noise 

figure and linearity. Care is taken in reducing power in this 

block so as not to increase nonlinearities, particularly the 

third-order nonlinearity as measured by IP3, the third-order 

intercept point, beyond an acceptable limit. 

A key parameter of the VCO is phase noise, an increase 

in which increases the sidebands on either side of the 

oscillation signal. During transmission, the phase noise 

should be kept low to avoid interference with adjacent 

channels and for preserving modulation information. 

During reception however, if the conditions are better 

than worst case, the phase noise requirement for the VCO is 

relaxed, and power can be saved consistent with embodiments of the present invention. The achievable phase noise 

power spectral density is approximately inversely proportional to the bias current used. Thus, when low phase noise 

is not required during reception, bias current in the VCO can 

be reduced. 

Most of the power savings in a transceiver in accordance 

with embodiments of the present invention is achieved in the 

receiver portion. Additional power may be saved in the 

transmitter section. 

FIG. 15 is a block diagram of a transmitter portion 

consistent with an embodiment of the present invention. 

Included is a signal path formed by gain stage 1510 and 

power amplifier 1520. The output power level is sensed by 

output level sensing circuit 1550, which in turn adjusts the 

biasing of the power amplifier 1520 through the power 

control circuit 1540. Additionally, a transmitter level control 

signal is received by power control circuits 1530 and 1540, 

which in tum control the biasing of gain stage 1510 and 

power amplifier 1520. Gain control circuit 1560 also adjusts 

the gain of gain stage 1510 and power amplifier 1520. 

Additional circuitry that varies impedances in each of these 

circuits may also be included. 

Since the gain, impedance and biasing of these blocks are 

being dynamically varied, care must be taken to not negatively affect the signal being processed. For example, specific embodiments of the present invention perform some or 

all of these variations during preamble. Also, as changes 

occur, the circuits in some embodiments are limited such 

that they may only adapt to an improvement in conditions 

after frames are completed. If conditions worsen, the circuits 

may be allowed to change in order to save the data. 

Alternately, a system may be manually calibrated, for 

example at set up, and when the network configuration is 

changed. 

The above description of specific embodiments of the 

invention has been presented for the purposes of illustration 

and description. It is not intended to be exhaustive or to limit 

the invention to the precise form described, and many 

modifications and variations are possible in light of the 

teaching above. The embodiments were chosen and 

described in order to best explain the principles of the 

invention and its practical applications to thereby enable 

others skilled in the art to best utilize the invention in various 

embodiments and with various modifications as are suited to 

the particular use contemplated. 

What is claimed is: 

1. A method for power dissipation reduction in a receiver 

of a wireless transceiver of a battery powered portable 

wireless device, and a corresponding improvement in a drain 

on battery life of the battery powered portable wireless 

device, the method comprising: 

receiving a wireless signal having a desired signal and an 

interferer signal, by the wireless transceiver of the 

battery powered portable wireless device, the wireless 

Case 6:20-cv-00160-ADA Document 1-1 Filed 02/28/20 Page 25 of 27
US 9,838,962 B2 

13 

transceiver having a receiver signal path comprising a 

plurality of circuits, wherein the plurality of circuits 

includes an amplifier, a filter, and a mixer, and wherein 

the wireless transceiver comprises a circuit for determining a signal strength of the interferer signal and a 

signal strength of the desired signal at a first node in the 

receiver signal path; and 

varying an impedance and a bias current of one or more 

of the plurality of circuits in the receiver signal path of 

the wireless transceiver as the signal strength of the 10 

interferer signal and the signal strength of the desired 

signal vary; 

14 

the wireless transceiver is reduced and the impedance 

of the circuit in the receiver signal path of the wireless 

transceiver is reduced resulting in reduced current drain 

when compared to the first current drain; and 

(iv) when the signal strength of the interferer signal is low 

and the signal strength of the desired signal is high, the 

bias current of the circuit in the receiver signal path of 

the wireless transceiver is increased and the impedance 

of the circuit in the receiver signal path of the wireless 

transceiver is increased, resulting in a reduction in 

current drain compared to the first current drain. 

2. The method of claim 1, wherein the circuit in the wherein the bias current and the impedance of the circuit 

in the receiver signal path of the wireless transceiver 

are varied according to the following: 

receiver signal path of the wireless transceiver whose 

15 impedance is varied is the amplifier. 

3. The method of claim 1, wherein the circuit in the 

receiver signal path of the wireless transceiver whose 

impedance is varied is the mixer. 

(i) when the signal strength of the interferer signal is high 

and the signal strength of the desired signal is low, the 

bias current of the circuit in the receiver signal path of 

the wireless transceiver is increased and the impedance 

of the circuit in the receiver signal path of the wireless 20 

transceiver is reduced, resulting in a first current drain; 

(ii) when the signal strength of the interferer signal is high 

and the signal strength of the desired signal is high, the 

bias current of the circuit in the receiver signal path of 

the wireless transceiver is increased while the imped- 25 

ance of the circuit in the receiver signal path of the 

wireless transceiver is increased, resulting in a reduction in current drain when compared to the first current 

drain; 

(iii) when the signal strength of the interferer signal is low 30 

and the signal strength of the desired signal is low, the 

bias current of the circuit in the receiver signal path of 

4. The method of claim 1, wherein the circuit in the 

receiver signal path of the receiver transceiver whose impedance is varied is the filter. 

5. The method of claim 1, wherein varying the impedance 

of the circuit in the receiver signal path of the wireless 

transceiver is affected by switching in and out an impedance 

in series with a load of the circuit in the receiver signal path 

of the wireless transceiver. 

6. The method of claim 1, wherein varying the bias 

current of the circuit in the receiver signal path of the 

wireless transceiver is affected by varying an impedance in 

a bias current path of the circuit in the receiver signal path 

of the wireless transceiver. 

* * * * * 

Case 6:20-cv-00160-ADA Document 1-1 Filed 02/28/20 Page 26 of 27
PATENT NO. 

APPLICATION NO. 

DATED 

INVENTOR(S) 

UNITED STATES PATENT AND TRADEMARK OFFICE 

CERTIFICATE OF CORRECTION 

: 9,838,962 B2 

: 15/080421 

:December 5, 2017 

: Yannis Tsividis 

Page 1 of 1 

It is certified that error appears in the above-identified patent and that said Letters Patent is hereby corrected as shown below: 

In the Claims 

In Claim 1, at Column 14, Line 8, "increased" should be replaced with --decreased--. 

Signed and Sealed this 

Thirty-first Day of December, 2019 

An"--"-..........-

Andrei Iancu 

Director of the United States Patent and Trademark Office 

Case 6:20-cv-00160-ADA Document 1-1 Filed 02/28/20 Page 27 of 27