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                                 EXHIBIT 10.18
                                                                        [ LOGO ]


                                    Quotation

COMPANY:                 NSC

COMPANY CONTACT:         Graham Clark

NMRC REF NO.             718/2001

QUOTATION DATE:          30/05/01


Proposal of Work as described in document "Proposal for National Scientific
Corporation revision B 30th May 2001.

5 sections: Simulation, Process Short Loops, Device Fabrication, Design and
Testing

<TABLE>
<S>      <C>                                <C>
1.       Simulation                         Total Cost IRL 9,000
2.       Process Short Loops                Total Cost IRL 19,200
3.       Device Fabrication                 Total Cost IRL 36,000
4.       Design                             Total Cost IRL 7,000
5.       Testing                            Total Cost IRL 9,000
</TABLE>

The proposal of work is given with the clear recognition that making tunnel
diodes is a high risk process and while every effort will be made to make tunnel
diodes this can not be guaranteed.



Quotation valid for three months from above date and subject to [  ] terms and
conditions at contract stage.

Credit terms: Payment due strictly within 30 days from date of invoice.

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Name:
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Title:
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                  Proposal for National Scientific Corporation
                           Prepared by Julie Donnelly
                            Revision B 30th May 2001.


         The following proposal is broken own in to 5 sections: Simulation,
Process short loops, Device Fabrication, Design and Testing. There is a brief
summary of the work involved in each section and then a cost for the work
involved. The various sections will operate in parallel so that an integrated
approach is taken to the overall work. It should be noted that making tunnel
diodes is a high risk process and while every effort will be made to make the
diodes successfully, there are no published results on working silicon substrate
diodes.

1.       SIMULATION

The simulation will concentrate on obtaining "best" process parameters for the
devices and will cover three areas of interest:

a) Simulation of depletion mode device in the NMRC 1.5um process. There is a
target specification of - 0.4V for the Vt of the depletion mode device. The
effect of the blanket NMRC Vt adjust will be investigated and there may be a
recommendation for the masked Vt.

b) Simulation of substrate N+/P+ tunnel diode (hereafter referred to as
"substrate diode") using existing NMRC implants or recommending unique implants.
The impact of any additional anneals on the 1.5um process will also be assessed.

c) Simulation of P+ doping in polysilicon (hereafter referred to as "poly
diode") with the objective being to try and locate the peak doping concentration
as close to the lower interface as possible. The impact of any additional
anneals on the 1.5um process will also be assessed.

Simulation Cost:  IRL 9,000.  Projected time:  3 - 4 weeks.

2.       PROCESS SHORT LOOPS

1.       Depletion mode Vt

                 There are no short loop processes being proposed for this
device, as it would require too many process steps to check out.

2.       Substrate diode + poly diode

                  9 mask process [zero, active, nwell, N+ S/D, P+ S/D, contact,
                  metal 1]. 1 run of 16 wafers with a matrix of various implants
                  using the standard NMRC anneal.

                  Cost: 16 wafers at L 1,200 each. Total cost = IRL 19,200.
                  Project Time: 8 weeks.
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3.       FULL DEVICE RUN

A full device run (17 masks) will be run in parallel with the process
short-loops but held at key stages if short loop wafer results are required.
This cost is based on an initial estimate of the process and may change if there
are additional steps added (eg: additional Vt mask or additional substrate diode
mask and implant).

Cost: 20 wafers at L 1,800 each. Total cost = IRL 36,000. Projected Time: 15
weeks.

4.       DESIGN

CHIP FINISHING COST                 IRL 1,000

RETICLES:         Currently require 14 layers (NMRC zero will be used).

COST: 5 reticles at L 1,200 each + chip finishing. Total cost = IRL 7,000.
Projected Time: 3 weeks.


Current layers:


Nwell

Pwell

Active

Gate

Nplus

Pplus

Contact

Metal 1

Via

Metal 2

Passivation

  * Depletion Device Vt

  * Tunnel Poly contact

  * Tunnel poly definition


Possible layers:

CMOS Vt mask

Tunnel N+ mask

Tunnel P+ mask


5.       TESTING

The testing will involve device testing of the short loop wafers and full
process wafers. The short loop wafer testing characteristic device
characteristics that will be used to give good guidelines for the implant/anneal
matrix for the main device batch.
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Estimated cost of testing:  IRL 9,000.  Projected Time:  3 - 4 weeks.


PAYMENT SCHEDULE:

<TABLE>
<CAPTION>
PAYMENT             SECTION           MILESTONE                                     COST               PROJECTED
                                                                                                       TIMESCALE
-------             -------           ---------                                     ----               ---------
<S>                 <C>               <C>                                        <C>                   <C>
Payment 1           Design            Design approved at Compugraphics.          IRL  7,000              Week 1
Payment 2           Simulation        Simulation Report delivered.               IRL  9,000              Week 4
Payment 3           Fabrication       All processing complete.                   IRL 55,200             Week 15
Payment 4           Testing           Testing Report delivered.                  IRL  9,000             Week 17
</TABLE>


SUMMARY

This project will use process short loops to characterise substrate and
polysilicon tunnel diodes. Using the feedback from test results a full batch of
device wafers will be fabricated which will incorporate the tunnel diodes in to
a well-characterised CMOS process.