# Patent

## Title
Performing statistical timing analysis with non-separable statistical and deterministic variations

## Abstract

In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and stews at the corresponding corner.

## Background
BACKGROUND OF THE INVENTION
The present invention relates generally to design automation, and relates more particularly to the timing analysis of integrated circuit (IC) chips.
Manufacturing and environmental variations are unavoidable in integrated circuit (IC) chips. Delays and slews of signals propagated through logic gates and wires depend on these variations. Statistical timing is commonly used to analyze IC chips for timing violations in the range of these variations. Statistical timing assumes that manufacturing and environmental variations are random and therefore behave statistically. Applying this assumption, statistical timing analysis models chip timing statistically. It approximates timing accurately in the regions of highly probable values of variations while allowing higher error in the regions of less probable values of variations.
Conventionally, the delays of gates and wires in the chip are modeled in the linear canonical form of variational parameters, which is simple and efficient to propagate through the circuit. FIG. 1, for example, illustrates the conventional linear approach to modeling timing quantities in statistical timing. Specifically, FIG. 1 illustrates the delay D for an exemplary logic gate as a function of two sources of variation X and V. X and V in this case are linear, separable parameters. X and V may be set to any value within a range of values (i.e., X1-X2 and V1-V2, respectively). The delay is modeled in linear canonical form as D(V,X)=d0+dvΔV+dxΔX. The delay sensitivities dx and dv are computed by finite differencing, as illustrated. The delay sensitivities can also be computed by differentiating the delays of gates and wires with respect to variational variables. In some cases, the sensitivities of delays and slews can be assigned (asserted) assuming a known percentage of variability, without requiring explicit finite differencing or computing of derivatives. A process “corner” occurs where a boundary (i.e., highest or lowest possible) value of X meets a boundary value of Y. As illustrated, the linear canonical form is an exact model of the delay for all process corners when dealing with linear separable parameters.
Some variables, however, are not separable and thus do not interact linearly. For example, chips are designed to operate correctly in a range of supply voltages (Vdd); a circuit using a chip can set the supply voltage to any value in this range. At different supply voltages, the sensitivities of delays and slews to some parameters will be different, because the variations due to these parameters and the supply voltage are not separable. FIG. 2 illustrates the application of the linear approach illustrated in FIG. 1 to modeling timing quantities with non-separable parameters X and V. As illustrated, the linear form cannot model the delay exactly when the delay is a function of non-separable parameters.
Moreover, variables like supply voltage are not statistical, but deterministic. Chips must work at any voltage within the required range of voltage values. All voltage values in this range are equally important, even the lowest and highest (“corner”) values. The statistical approximation used by statistical timing analysis is not accurate enough to model variations of supply voltage or similar deterministic parameters. The statistical approximation cannot achieve sufficient accuracy near the corner values of the deterministic parameters, especially if some statistical parameters are not separable with the deterministic parameters.
Conventional statistical timing methodology therefore uses two timing runs at each voltage “corner” to account for these non-separable, non-statistical (deterministic) variations: a first timing run at a low supply voltage (V1) and a second timing run at a high supply voltage (V2). The use of multiple timing runs, however, is inefficient and inconvenient. For instance, timing closure will take longer and will require more computational resources. Additionally, a circuit optimized at one supply voltage will often fail at another supply voltage. This leads to multiple iterations in circuit design and optimization.
The deterministic variables requiring equally high accuracy of timing analysis across the entire range of variations including their corners are called “corner-based variables” due to the necessity of using corner analysis in their modeling.
SUMMARY OF THE INVENTION
In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and slews at the corresponding corner.



BRIEF DESCRIPTION OF THE DRAWINGS
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
FIG. 1 illustrates the conventional linear approach to modeling timing quantities in statistical timing;
FIG. 2 illustrates the application of the linear approach illustrated in FIG. 1 to modeling timing quantities with non-separable parameters;
FIG. 3 is a flow diagram illustrating one embodiment of a method for performing statistical timing analysis for a circuit in which the timing quantities are dependent on deterministic, corner-based variables and non-separable statistical process variables, according to the present invention;
FIG. 4 illustrates the delay for an exemplary chip as a function of two sources of variation that are non-separable;
FIG. 5 illustrates the application of finite differencing to computing the extended linear canonical form of EQN. 2;
FIG. 6 illustrates propagation of signal arrival times through a portion of an exemplary timing graph;
FIG. 7 is a flow diagram illustrating one embodiment of a method for computing a maximum of two extended canonical forms, according to the present invention; and
FIG. 8 is a high-level block diagram of timing analysis method that is implemented using a general purpose computing device.



DETAILED DESCRIPTION
In one embodiment, the present invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. Embodiments of the invention extend the linear canonical forms of process parameters (variables) by including cross-terms that model the interaction of the non-separable statistical variables with deterministic corner-based variables. The extended canonical form models timing quantities as a function of separable and non-separable variations with a hyperbolic surface. The cross-terms for delays and slews of logic gates and wires can be computed by finite differencing to the corners involving variations of the deterministic corner-based and corresponding non-separable variables simultaneously. The variability of delays and slews can also be assigned to logic gates and wires without their explicit computation by applying known information about the amount of variability. Arrival times and required arrival times are propagated through a timing graph using extended versions of statistical operations: addition, subtraction, minimum, and maximum. The extended versions of the statistical operations are applied to extended canonical forms, and the result is also computed in extended canonical form. This approach is able to time circuits in a single timing run for both corners of a deterministic (corner-based) variable, and is thus faster and requires less memory than conventional techniques for performing statistical timing with non-separable variables. Moreover, this approach can be applied to substantially any design automation process that utilizes statistical timing, including sign-off timing, circuit optimization, and selective voltage binning.
FIG. 3 is a flow diagram illustrating one embodiment of a method 300 for performing statistical timing analysis for a circuit in which the timing quantities are dependent on deterministic, corner-based variables and non-separable statistical process variables, according to the present invention.
The method 300 is initialized in step 302 and proceeds to step 304, where the timing quantities of the circuit are acquired. The timing quantities include the delays of the gates and wires and the arrival times at the circuit inputs. In one embodiment, these timing quantities depend on deterministic, corner-based process variables such as supply voltage, temperature, or the like and statistical process variables, some of which are non-separable with the deterministic, corner-based variables. In one embodiment, the interaction of a corner-based parameter with non-separable parameters is modeled using cross-products. In particular, the linear canonical form discussed above is extended by adding: (1) a term for the linear part of the deterministic, corner-based parameter's variation; and (2) a cross-term for each parameter that has a non-separable interaction with the corner-based parameter. Thus,

t=t0+axΔX+ayΔY+aRΔR  (EQN. 1)

becomes

t=t0+aVΔV+axΔX+axVΔVΔX+ayΔY+aRVΔRΔY+aRΔR  (EQN. 2)

where aVΔV is the term for the linear part of the corner-based parameter V's variation, X is a statistical parameter that interacts in a non-separable manner with the corner-based parameter V, axVΔVΔX is the cross-term for the non-separable interaction of the corner-based parameter V and the statistical parameter X, Y is a parameter that is separable from the corner-based parameter V, R is an uncorrelated parameter representing random uncertainty, and aRVΔRΔY is the cross-term for the non-separable interaction of the corner-based parameter V with the uncorrelated parameter R. Although the letter “V” is commonly used to denote voltage, in the above example V represents a generic deterministic, corner-based parameter. That is, the disclosed invention is applicable to any deterministic, corner-based parameter. As discussed in further detail below, EQN. 2 contains the informational equivalent of two timing runs.

FIG. 4 illustrates the delay D for an exemplary chip as a function of two sources of variation X and V, where X and V are non-separable. As illustrated, the extended canonical form embodied in EQN. 2 produces a hyperboloid that fits all four process corners exactly. This makes the approximation with the extended canonical form exact at all corners of the deterministic, corner-based variables. Moreover, projecting the value for the corner-based variable V to one of its corners (e.g., LV or HV) turns the extended canonical form into a linear form. Projection to a given corner involves substituting the given corner's value for the corner-based parameter in the extended canonical form. For instance, D(V,X)=d0+dVΔV+dxΔX+dVXΔVΔX becomes DLV(T)=d0,LV+dX,LVT when projected to the low V (L e., LV) corner and DHV(T)=d0,HV+dX,HVX when projected to the high V (i.e., HV) corner. The corner-based variable can also be projected to any arbitrary value within its corners. The projection turns the extended canonical form into a linear canonical form that is the interpolation of the linear canonical forms corresponding to the high V and low V corners of the projected variable. Linear interpolation between the high and low corners is useful for voltage binning when the corner-based variable is supply voltage. The linear canonical form obtained by projection models statistical variability at the corner of projection. In addition, the mean, uncorrelated random term, and sigma are also computed.
Projection can also be performed to the worst corner (i.e., the corner where the extended canonical form takes its minimum or maximum value). For example, for variables that are separable with the corner-based parameter, the values for substitution are selected according to the signs (i.e., positive or negative) of their sensitivities. For variables that are not separable with the corner-based parameter, the worst corner is selected in two steps. First, the corner-based parameter is set to its lowest value (e.g., V=V1) and the sensitivities to the non-separable variables are computed (e.g., ax,1=ax+axVΔV1). This includes computing the worst corners for the variables that are not separable with the corner-based parameter V and computing the worst contribution of the corner-based parameter V and the variables that are non-separable with V at the lowest value (e.g., V=V1), taking into account all root square summation settings. Second, the corner-based parameter is set to its highest value (e.g., V=V2) and the sensitivities to the non-separable variables are computed (e.g., ax,2=ax+axVΔV2). This includes computing the worst corners for the variables that are not separable with the corner-based parameter V and computing the worst contribution of the corner-based parameter V and the variables that are non-separable with V at the highest value (e.g., V=V2), taking into account all root square summation settings. If the linear terms have a greater effect than all of the cross-terms together, then the worst corner can be computed from the signs of the linear sensitivities.
Once the delay is expressed in extended linear canonical form as in EQN. 2, the delay can be computed. In one embodiment, where the delay of a logic gate or wire is known as a function of process and environmental parameters, the extended canonical form of the delay can be computed using finite differencing. Specifically, the cross-terms for delays and slews are computed by finite differencing to the process corners involving variations of the deterministic, corner-based and corresponding non-separable variables simultaneously.
FIG. 5 illustrates the application of finite differencing to computing the extended linear canonical form of EQN. 2. As illustrated, the linear sensitivities to the parameter X can be computed using finite differencing from the base corner (V1, X1) to the other corner (V1, X2) for the parameter X. Thus, dx:(V1,X1)→(V1,X2). Likewise, the linear sensitivity to the parameter V can be computed using finite differencing from the base corner (V1, X1) to the other corner (V2, X1) for the parameter V. Thus, dV:(V1,X1)→(V2,X1). Finally, sensitivity dVX to the cross term ΔVΔX can be computed using finite differencing from the base corner (V1, X1) to the cross-corner (V2, X2). Thus, dVX: (V1,X1)→(V2,X2).
Based on the above, one can compute dVX as:




  
    
      
        
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where ΔX=X2−X1 and ΔV=V2−V1.

Referring back to FIG. 3, once the timing quantities are acquired, the method 300 proceeds to step 306, where the circuit is modeled as a timing graph. In one embodiment, the timing graph is a directed acyclic timing graph. The nodes of the timing graph represent the inputs and outputs of the gates, while the edges (timing arcs) of the graph represent the propagation of signals from a gate's input to its output or from a first gate's output to a second gate's input. FIG. 6, for example, illustrates propagation of signal arrival times through a portion of an exemplary timing graph 600 having three nodes 605, 615, and 620 and two edges 610 and 625. The nodes 605 and 620 have arrival times TI,1 and TI,2, respectively. Timing edges 610 and 625 have delays D1 and D2, respectively. The latest arrival time T at node 615 is computed as the maximum of the arrival time T1=TI,1+D1 propagated through edge 610 and the arrival time T2−TI,2+D2 propagated through the edge 625.
In step 308, a single timing run is performed using the acquired timing quantities and the timing graph. In one embodiment, a timing run involves two main operations: (1) propagation of the arrival times through the timing edges of the timing graph; and (2) computation of the latest (or earliest) arrival time at the nodes of the timing graph (e.g., MIN or MAX arrival time). The first step (propagation of the arrival times) requires addition of the extended canonical forms of the delays to the extended canonical forms of the arrival times at the nodes of the timing graph. The second step (computation of the arrival time) requires computation of a statistical and deterministic maximum or minimum among a plurality of the extended canonical forms of the arrival times propagated through the timing edges of the timing graph to its nodes.
The addition and subtraction of the extended canonical forms is relatively simple. In general, all sensitivities and all cross-terms, except for the cross-term of the uncorrelated variation, are summed for addition or subtracted for subtraction. Uncorrelated variations are projected to the corners of the corner-based parameter and then root square summed at each corner of the corner-based parameter. In one embodiment, the root sum square is computed at the corners V1 and V2, respectively, as follows:

tR(V1)=√{square root over ((tR,1+tR,V,1ΔV1)2+(dR,1+dR,V,1ΔV1)2)}{square root over ((tR,1+tR,V,1ΔV1)2+(dR,1+dR,V,1ΔV1)2)}

tR(V2)=√{square root over ((tR,1+tR,V,1ΔV2)2+(dR,1+dR,V,1ΔV2)2)}{square root over ((tR,1+tR,V,1ΔV2)2+(dR,1+dR,V,1ΔV2)2)}  (EQN. 4)

where tR,1 and dR,1 are the sensitivities to uncorrelated variations of the arrival time and the delay, respectively; tR,V,1 and dR,V,1 are the cross-term sensitivities to variation of the variable V and uncorrelated variations of the arrival time and the delay, respectively. Them the cross-term of the uncorrelated random variation, tR,V, of the resultant extended canonical form is computed as:





  
    
      
        
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The computation of the arrival time at the circuit output, as discussed above, typically involves a statistical MIN or MAX operation. For example, referring again to FIG. 6, the latest arrival time T to the node 615 is calculated as:

T=max(T1,T2)  (EQN. 6)

where T1 and T2 are the arrival times of the signals propagated through the edges 610 and 625 to the node 615.

In one embodiment, EQN. 6 is computed by a method illustrated in greater detail with respect to FIG. 7. First, the arrival times T1 and T2 that are propagated through the edges 610 and 625 are projected at each corner of the corner-based parameter V. This produces the linear canonical forms T1(V1), T2(V1), and T1(V2), T2(V2). Next, the statistical maximum is computed at each corner of the corner-based parameter V as:

T(V1)=max(T1(V1),T2(V1))

T(V2)=max(T1(V2),T2(V2))  (EQN. 7)

Finally, the Resultant Simple Linear Canonical Forms T(V1) and T(V2) are combined into an extended canonical form as discussed above.
Referring back to FIG. 3, once the timing run has been performed, the arrival times, required arrival times, and timing slacks of the circuit nodes latches, and outputs are output in step 310. The method 300 then terminates in step 312.
FIG. 7 is a flow diagram illustrating one embodiment of a method 700 for computing a maximum of two extended canonical forms, according to the present invention. For the purposes of illustration the method 700 is described as computing the maximum T of the extended canonical forms T1 and T2.
The method is initialized in step 705 and proceeds to step 710, where the first extended canonical form T1 is projected to the first corner V1 of the corner-based variable V. In step 715, the second extended canonical form T2 is projected to the first corner V1 of the corner-based variable V. The projected canonical forms T1(V1) and T2(V1) are linear canonical forms.
In step 720, the statistical maximum T(V1) is computed from the projected linear canonical forms T1(V1) and T2(V1). In one embodiment, this computation applies the conventional statistical maximum operation. The resultant linear canonical form T(V1) is the projection of the required extended canonical form T to the first corner V1.
In step 725, the first extended canonical form T1 is projected to the second corner V2 of the corner-based variable V. In step 730, the second extended canonical form T2 is projected to the first corner V2 of the corner-based variable V. The projected canonical forms T1(V2) and T2(V2) are linear canonical forms.
In step 735, the statistical maximum T(V2) is computed from the projected linear canonical forms T1(V2) and T2(V2). In one embodiment, this computation applies the conventional statistical maximum operation. The resultant linear canonical form T(V2) is the projection of the required extended canonical form T to the first corner V2.
In step 740, the two linear canonical forms of the statistical maximums T(V1) and T(V2) are combined to compute the extended canonical form T. In this step, T(V1) and T(V2) are projections of T to the first and second corners. V1 and V2, respectively. This computation is performed using:




  
    
      
        
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t0=t0,1+dVV1  (EQN. 9)





  
    
      
        
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where t0,1, t0,2, and t0 are the mean values of the linear canonical forms T(V1) and T(V2) and the extended canonical form T, respectively; tV is the sensitivity of the extended canonical form T to the corner-based variable V; tX,1 and tX,2 are the sensitivities of the linear canonical forms T(V1) and T(V2) to the non-separable variable X; and tX,V is the sensitivity of the extended canonical form T to the corner-based variable V and the non-separable variable X.

The method 700 terminates in step 745. The computation of the minimum of two extended canonical forms is performed in a similar manner.
The method 300 (for performing statistical timing with non-separable statistical and deterministic, corner-based variations) improves the accuracy of statistical timing. The method 300 also saves processing time and reduces turn-around time for timing analysis by obtaining the timing information for each corner of a corner-based parameter via projection of the extended canonical forms of the delays, slews, arrival times, required arrival times, timing slacks, and other timing quantities. This approach is convenient for circuit optimization because it provides a single metric to guide optimization. This approach can also compute the worst timing slack for both the corner-based parameter and all statistical parameter variations.
Further applications of the disclosed approach include selective voltage binning. For example, the timing slacks for all voltage bins can be obtained by projection as discussed above. This allows circuit optimization and achieves timing closure for circuits with selective voltage binning.
Moreover, although the invention is discussed within the context of a single corner-based parameter, it may be extended to timing analysis involving multiple corner-based variables. In this case, any deterministic variables (e.g., supply voltage, temperature, or the like) are declared as deterministic, corner-based parameters. Cross-terms are then introduced between all non-separable statistical and deterministic, corner-based variables (memory requirements in this step can be reduced by neglecting high-order cross-terms involving the products of three or more quantities). Operations on the extended canonical forms can also be extended to multiple corner-based variables.
Further embodiments of the invention can be extended to account for the nonlinearity of deterministic, corner-based variables. In this case, quadratic or higher-order terms are introduced into the computation, and a middle range corner for the corner-based parameter is considered in computing the sensitivities to the quadratic or higher-order term.
It is noted that the extended canonical form for the delays and arrival times that is discussed above is related to the corner canonical forms for the corner-based parameters. The corner canonical forms are projections of the extended canonical form to the corners of the deterministic, corner-based parameter. For example, in the equation t=t0+aVΔV+axΔX+axVΔVΔX+ayΔY+ayVΔVΔY+azΔZ+aRΔR, the corner canonical forms for the corner-based parameter V can be computed as:

tΔV1=t0,1+ax,1ΔX+ay,1ΔY+az,1ΔZ+aR,1ΔR =t0+aVΔV1+(ax+axVΔV1)ΔX+(ay+ayVΔV1)ΔY+azΔZ+aRΔR  (EQN. 12)

and

tΔV2=t0,2+ax,2ΔX+ay,2ΔY+az,2ΔZ+aR,2ΔR =t0+aVΔV2+(ax+axVΔV2)ΔX+(ay+ayVΔV2)ΔY+azΔZ+aRΔR  (EQN. 13)

Similarly, the Extended Canonical Form can be Projected to any Other Value of the corner-based parameter.

The extended canonical form uniquely represents the canonical forms at the corners of the corner-based parameter V. That is, the canonical forms for the corners V=V1 and V=V2 are computed from the extended canonical form. Conversely, the extended canonical form of the delay, arrival time, required arrival time, timing slack, or other timing quantity can be computed from the canonical forms at the corners V=V1 and V=V2.
Since a corner-based parameter is a deterministic rather than statistical variable, the corner-based parameter may not be statistically correlated with any variables. For example, supply voltage Vdd is not correlated with any variables and is not a statistical variable. Thus, a correlation matrix will not depend on Vdd. Therefore, the correlated variables are de-correlated by linear transformation. Thus, one has:




  
    
      
        
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                          2
                        
                        ·
                        Δ
                      
                      ⁢
                      
                        
                      
                      ⁢
                      Y
                    
                  
                
              
            
          
        
      
    
    
      
        (
        
          EQN
          .
          
            
          
          ⁢
          14
        
        )
      
    
  




The external extended canonical form, t=t0+aVΔV+axΔX+axVΔVΔX+ayΔY+ayVΔVΔY+azΔZ+aRΔR, is thus transformed into internal extended canonical form as:

t=t0+aVΔV+aint,1Δuint,1+aint,V,1ΔVΔuint,1+ayΔuint,2+aint,V,2ΔVΔuint,2+azΔZ+aRΔR  (EQN. 15)

The sensitivities to cross terms in EQN. 15 are computed by the same linear transformation as the linear sensitivities to the corresponding variables. This follows from the fact that the variables X and Y are transformed linearly.
FIG. 8 is a high-level block diagram of timing analysis method that is implemented using a general purpose computing device 800. In one embodiment, a general purpose computing device 800 comprises a processor 802, a memory 804, a timing analysis module 805 and various input/output (I/O) devices 806 such as a display, a keyboard, a mouse, a stylus, a wireless network access card, and the like. In one embodiment, at least one I/O device is a storage device (e.g., a disk drive, an optical disk drive, a floppy disk drive, a path selection tool, and/or a test pattern generation tool). It should be understood that the timing analysis module 805 can be implemented as a physical device or subsystem that is coupled to a processor through a communication channel.
Alternatively, the timing analysis module 805 can be represented by one or more software applications (or even a combination of software and hardware, e.g., using Application Specific Integrated Circuits (ASIC)), where the software is loaded from a storage medium (e.g., I/O devices 806) and operated by the processor 802 in the memory 804 of the general purpose computing device 800. Thus, in one embodiment, the timing analysis module 805 for performing statistical timing analysis with non-separable statistical and deterministic variations, as described herein with reference to the preceding Figures, can be stored on a non-transitory computer readable storage medium (e.g., RAM, magnetic or optical drive or diskette, and the like).
It should be noted that although not explicitly specified, one or more steps of the methods described herein may include a storing, displaying and/or outputting step as required for a particular application. In other words, any data, records, fields, and/or intermediate results discussed in the methods can be stored, displayed, and/or outputted to another device as required for a particular application. Furthermore, steps or blocks in the accompanying Figures that recite a determining operation or involve a decision, do not necessarily require that both branches of the determining operation be practiced. In other words, one of the branches of the determining operation can be deemed as an optional step.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. Various embodiments presented herein, or portions thereof, may be combined to create further embodiments. Furthermore, terms such as top, side, bottom, front, back, and the like are relative or positional terms and are used with respect to the exemplary embodiments illustrated in the figures, and as such these terms may be interchangeable.

## Claims

1. A method for performing timing analysis of an integrated circuit chip, the method comprising:
computing a timing quantity of the integrated circuit chip, wherein the timing quantity depends on at least a first process parameter that is deterministic and corner-based and a second process parameter that is non-separable with the first process parameter, wherein the computing comprises:
extending a linear canonical form of the timing quantity to account for an interaction of the first process parameter with the second process parameter, wherein the linear canonical form contains an informational equivalent of multiple timing runs; and
projecting a value for the first process parameter to a corner associated with the first process parameter; and
calculating the timing quantity in accordance with the linear canonical form, after the projecting; and

performing a single timing run using the timing quantity, wherein the single timing run produces an arrival time, a required arrival time, or a timing slack at a node of the integrated circuit chip.

2. The method of claim 1, wherein the extending comprises:
modeling a linear portion of a variation of the first processing parameter; and
modeling the interaction of the first process parameter with the second process parameter as a cross-product.

3. The method of claim 2, wherein the calculating comprises:
computing a sensitivity to the cross-product using finite differencing.

4. The method of claim 3, wherein the finite differencing is performed for each process corner that involves a variation of the first process parameter and the second process parameter simultaneously.

5. The method of claim 3, wherein the computing the sensitivity comprises:
modeling the interaction of the first process parameter with the second process parameter as a quadratic or higher-order term, where the first process parameter is non-linear; and
computing a sensitivity to the quadratic or higher-order term in accordance with a middle range corner for the first process parameter.

6. The method of claim 2, wherein the calculating comprises:
assigning the sensitivity assuming a known percentage of variability.

7. The method of claim 1, wherein the projecting comprises:
substituting a value associated with the corner for the first process parameter in the linear canonical form that is extended.

8. The method of claim 1, wherein the projecting comprises:
substituting a value associated with a first corner for the first process parameter in a first version the linear canonical form that is extended, wherein the first corner is associated with a lowest value for the first process parameter; and
substituting a value associated with a second corner for the first process parameter in a second version the linear canonical form that is extended, wherein the second corner is associated with a highest value for the first process parameter.

9. The method of claim 8, further comprising:
performing linear interpolation between the first version the linear canonical form that is extended and the second version the linear canonical form that is extended.

10. The method of claim 1, wherein the method further comprises:
modeling the integrated circuit chip as a timing graph, wherein each node in the timing graph represents an input or an output of a gate in the integrated circuit chip and each edge in the timing graph represents a propagation of a signal in the integrated circuit chip.

11. The method of claim 10, wherein the performing comprises:
propagating the timing quantity through the timing graph; and
computing an arrival time at the node of the integrated circuit chip, in accordance with the timing quantity as propagated.

12. The method of claim 11, wherein the propagating comprises:
adding the linear canonical form of the timing quantity, as extended, and an extended linear canonical form of at least one more timing quantity.

13. The method of claim 12, wherein the adding comprises:
summing all sensitivities and cross-products in the linear canonical form of the timing quantity, as extended, and the extended linear canonical form of the at least one more timing quantity.

14. The method of claim 11, wherein the arrival time is a statistical minimum or a statistical maximum among all arrival times at the node of the integrated circuit chip.

15. The method of claim 11, wherein the computing comprises:
projecting an arrival time on an input edge of the node of the integrated circuit chip at each corner associated with the first process parameter, to produce a plurality of quantities;
computing a statistical maximum or a statistical minimum among the plurality of quantities at each corner associated with the first process parameter, to produce a simple canonical form at each corner associated with the first process parameter; and
combining the simple canonical form for each corner associated with the first process parameter to produce an extended canonical form.

16. The method of claim 1, wherein the arrival time is used in a circuit optimization process.

17. The method of claim 1, wherein the arrival time is used in a sign-off timing process.

18. The method of claim 1, wherein the arrival time is used in a selective voltage binning process.

19. The method of claim 1, wherein the first process parameter is supply voltage.

20. The method of claim 1, wherein the first process parameter is temperature.

21. The method of claim 1, wherein the timing quantity is a delay or a signal slew of a gate or wire in the integrated circuit chip.

22. The method of claim 1, wherein the timing quantity is an arrival time at the input of the integrated circuit chip or a required arrival time at an output of the integrated circuit chip.

23. A computer readable storage device containing an executable program for performing timing analysis of an integrated circuit chip, where the program performs steps of:
computing a timing quantity of the integrated circuit chip, wherein the timing quantity depends on at least a first process parameter that is deterministic and corner-based and a second process parameter that is non-separable with the first process parameter, wherein the computing comprises:
extending a linear canonical form of the timing quantity to account for an interaction of the first process parameter with the second process parameter,

wherein the linear canonical form contains an informational equivalent of multiple timing runs; and
projecting a value for the first process parameter to a corner associated with the first process parameter; and
calculating the timing quantity in accordance with the linear canonical form, after the projecting; and

performing a single timing run using the timing quantity, wherein the single timing run produces an arrival time, a required arrival time, or a timing slack at a node of the integrated circuit chip.

24. Apparatus for performing timing analysis of an integrated circuit chip, the apparatus comprising:
means for computing a timing quantity of the integrated circuit chip, wherein the timing quantity depends on at least a first process parameter that is deterministic and corner-based and a second process parameter that is non-separable with the first process parameter, wherein the means for computing comprises:
means for extending a linear canonical form of the timing quantity to account for an interaction of the first process parameter with the second process parameter, wherein the linear canonical form contains an informational equivalent of multiple timing runs; and
means for projecting a value for the first process parameter to a corner associated with the first process parameter; and
means for calculating the timing quantity in accordance with the linear canonical form, after the projecting; and

means for performing a single timing run using the timing quantity, wherein the single timing run produces an arrival time, a required arrival time, or a timing slack at a node of the integrated circuit chip.