# Patent

## Title
Multi-operand floating point operations in a programmable integrated circuit device

## Abstract

A programmable logic device is programmed to add a plurality N of unnormalized numbers at once. Because the inputs are not normalized, they could all have different exponents. The largest exponent of the N exponents is found, and for each of the inputs, its mantissa is right-shifted at by the difference between the largest exponent and the exponent of that particular input. The N shifted mantissas are combined, optionally with sign data, in an (N+1):2 compressor to provide carry and save vectors which may be combined in a carry-propagate adder. Numbers may converted back to normalized form at the end of the operation. If necessary to avoid data loss, a number may be normalized after an intermediate step.

## Background
BACKGROUND OF THE INVENTION
This invention relates to performing floating point arithmetic operations in programmable integrated circuit devices, such as programmable logic devices (PLDs).
As applications for which programmable devices are used increase in complexity, it has become more common to design programmable devices to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a programmable device that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of specialized processing block that has been provided on programmable devices is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.
For example, PLDs sold by Altera Corporation, of San Jose, Calif., under the family name STRATIX® include DSP blocks, each of which includes a plurality of multipliers (e.g., 18-by-18 multipliers). Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as individual multipliers, but also as smaller multipliers (by leaving some inputs unused or zeroed), or as one larger multiplier. In addition, complex multiplication (which decomposes into two multiplication operations for each of the real and imaginary parts) can be performed.
The arithmetic operations to be performed by a PLD frequently are floating point operations. The IEEE754-1985 standard requires that in floating point operations, values be normalized at all times because it implies a leading “1”.
SUMMARY OF THE INVENTION
The present invention relates to circuitry that carries out floating point operations on multiple operands without normalization, although the results may be normalized if IEEE754-1985 compliance is required. In addition, normalization may be performed in intermediate steps if loss of data might otherwise result. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD).
In accordance with the present invention, there is provided a method of configuring a programmable integrated circuit device to perform floating point addition operations on a plurality of numbers, where each of the numbers is represented by a respective mantissa and a respective exponent. The method includes configuring logic of the programmable integrated circuit device to determine a largest exponent of the respective exponent of the plurality of numbers, and to subtract each respective exponent from the largest exponent to determine a respective shifting amount, and to select the largest exponent as a resultant exponent. Logic of the programmable integrated circuit device also is configured to shift each respective mantissa of the plurality of numbers by the respective shifting amount. A compressor is configured in the programmable integrated circuit device to simultaneously combine the plurality of shifted mantissas into a carry vector and a save vector. A carry-propagate adder is configured in the programmable integrated circuit device to combine the carry vector and the save vector.
A programmable logic device so configured, a machine-readable data storage medium encoded with software for performing the method, and logic circuitry to perform floating point addition operations on a plurality of numbers, are also provided.



BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:
FIG. 1 shows logical architecture for an embodiment of a multi-input floating point adder according to the present invention;
FIG. 2 is a schematic representation of a portion of binary sort logic used in an embodiment of the invention;
FIG. 3 is a schematic representation of normalization as performed in accordance with an embodiment of the invention;
FIG. 4 is a schematic representation of an alternate arrangement of a portion of the normalization operation represented by FIG. 3;
FIG. 5 is a cross-sectional view of a magnetic data storage medium encoded with a set of machine-executable instructions for performing the method according to the present invention;
FIG. 6 is a cross-sectional view of an optically readable data storage medium encoded with a set of machine-executable instructions for performing the method according to the present invention; and
FIG. 7 is a simplified block diagram of an illustrative system employing a programmable logic device incorporating the present invention.



DETAILED DESCRIPTION OF THE INVENTION
Floating point numbers are commonplace for representing real numbers in scientific notation in computing systems. Examples of real numbers in scientific notation are:

    
    
        3.1415926510×10° (π)
        2.71828182810×10° (e)
        0.00000000110 or 1.010×10−9 (seconds in a nanosecond)
        315576000010 or 3.1557610×109 (seconds in a century)
    
    


The first two examples are real numbers in the range of the lower integers, the third example represents a very small fraction, and the fourth example represents a very large integer. Floating point numbers in computing systems are designed to cover the large numeric range and diverse precision requirements shown in these examples. Fixed point number systems have a very limited window of representation which prevents them from representing very large or very small numbers simultaneously. The position of the notional binary-point in fixed point numbers addresses this numeric range problem to a certain extent but does so at the expense of precision. With a floating point number the window of representation can move, which allows the appropriate amount of precision for the scale of the number.
Floating point representation is generally preferred over fixed point representation in computing systems because it permits an ideal balance of numeric range and precision. However, floating point representation requires more complex implementation compared to fixed point representation.
The IEEE754-1985 standard is commonly used for floating point numbers. A floating point number includes three different parts: the sign of the number, its mantissa and its exponent. Each of these parts may be represented by a binary number and, in the IEEE754-1985 format, have the following bit sizes:















Sign
Exponent
Bias
Mantissa







Single
1 bit
 8 bits
 −127
23 bits


Precision
[31]
[30 . . . 23]

[22 . . . 00]


32-Bit






Double
1 bit
11 bits
−1023
52 bits


Precision
[63]
[62 . . . 52]

[51 . . . 0] 


64-Bit









The exponent preferably is an unsigned binary number which, for the single precision format, ranges from 0 to 255. In order to represent a very small number, it is necessary to use negative exponents. To achieve this the exponent preferably has a negative bias associated with it. For single-precision numbers, the bias preferably is −127. For example a value of 140 for the exponent actually represents (140−127)=13, and a value of 100 represents (100−127)=−27. For double precision numbers, the exponent bias preferably is −1023.
As discussed above, according to the standard, the mantissa is a normalized number—i.e., it has no leading zeroes and represents the precision component of a floating point number. Because the mantissa is stored in binary format, the leading bit can either be a 0 or a 1, but for a normalized number it will always be a 1. Therefore, in a system where numbers are always normalized, the leading bit need not be stored and can be implied, effectively giving the mantissa one extra bit of precision. Therefore, in single precision format, the mantissa typically includes 24 bits of precision.
However, the IEEE754-1985 standard requires continuous normalization—i.e., normalization after every step of a multistep computation—to maintain the leading “1” to preserve accuracy. This is expensive in terms of programmable resources, as each normalization operation requires two steps—(1) finding the position of the “1”, and (2) shifting the fractional part to get a leading “1” (which is then eliminated, because it is implied).
In accordance with copending, commonly-assigned U.S. patent application Ser. No. 11/625,655, filed Jan. 22, 2007, which is hereby incorporated by reference herein in its entirety, there is no implied leading “1”, so that normalization is not required. Although this requires that one bit of precision be given up, because all bits must be kept, rather than implied, this greatly reduces the required logic, particularly shifting logic, and therefore the latency of the floating point operations. Moreover, in a programmable device that already has dedicated arithmetic circuits, such as multipliers and/or adders, that are capable of handling the extra bits, there is no additional cost in terms of logic resources to handle those extra bits.
Specifically, according to above-incorporated application Ser. No. 11/625,655, to configure a programmable device to perform floating point operations, the programmable device preferably is configured so that floating point values in accordance with a first format, such as the IEEE754-1985 standard format, preferably are converted to an internal format for calculation purposes, and are reconverted to the standard format upon completion of the operations.
Whereas the IEEE754-1985 standard format includes a 24-bit unsigned mantissa (23 bits plus the implied “1”) and an 8-bit exponent, the internal format preferably includes a 32-bit signed mantissa and a 10-bit exponent. When converting from the standard 24-bit format to the 32-bit format of the invention, the implied leading “1” of the mantissa is made explicit and preferably is initially positioned at the 28th bit location. This leaves the four most significant bits of the 32-bit number available for overflows as operations progress. For example, 16 additions could be performed before any overflow would consume all four bits. Similarly, because the original standard representation is only 24 bits wide, the four least significant bits also are available for any underflows that may occur.
As stated above, preferably, and ordinarily, during floating point operations the operands remain in the internal format, and are converted back to their original format only upon completion of operations. Because of the initial presence of the leading and trailing bits, as well as the larger exponent size, during operations it is possible to continue beyond conditions that might have led to overflows or underflows in the original format, because of the possibility that the accumulation of further results may reverse the overflow or underflow condition.
However, if during operation the accumulation of underflows or overflows reaches the point that information may be lost—e.g., there would be an overflow if the data were converted back to the standard format, or an underflow would be approached such that fewer than three significant bits beyond the required mantissa precision (i.e., in this example, fewer than 1+23+3=27 bits) would remain—it may be desirable to normalize the data at an intermediate step to prevent lost of precision. In such a case, subsequent operations preferably would not include further normalization until the final result is achieved (unless a condition again arises in which data may be lost).
Although the arrangement described in above-incorporated application Ser. No. 11/625,655 achieves savings in device area, as well as number of operations performed, it nevertheless operates on only two operands at a time. For example, to add four numbers a, b, c, d, together, a and b might be added in one operation, with c and d being added in a separate operation, and then the two intermediate sums are added. To add eight numbers, the tree would have a third level, with four individual additions of two addends each in the first level, two additions of two addends each in the second level, and a final addition of two addends in the third level. This is expensive in terms of both resources and latency.
Therefore, in accordance with the present invention, a plurality N of unnormalized numbers can be added at once, as shown in FIG. 1. Because the inputs are not normalized, they could all have different exponents. The largest exponent of the N exponents 101 is found by module 200 as described in connection with FIG. 2, and for each of the inputs, its mantissa 102 is right-shifted by one of shifters 103 by the difference 104 between the largest exponent 105 and the exponent 101 of that particular input (note that this holds even for the input with the largest exponent, except that the shift will be zero bits). The N shifted mantissas are combined, optionally with sign data, in an (N+1):2 compressor 106 to provide carry and save vectors 107, 108 which may be added in a carry-propagate adder 109 to provide output mantissa 110.
The (N+1)th input 111 to compressor 106 represents the sign. If the addends are being represented in IEEE754-1985 format (except for not being normalized), then each will have a separate sign bit. In that case, the (N+1)th input 111 is a number representing how many of the inputs have a sign bit indicating a negative number. This may be thought of as a unary (1°) to binary (2°) conversion, but also may be considered to be a “count-leading-ones” module. In addition, each of the mantissas would be XORed at 112 with its sign bit to create a one's-complement equivalent representation. If any subtractions are involved, then the sign bit associated with any minuend is inverted before the unary-to-binary conversion and before the one's-complement conversion.
If signed numbers (where the most significant bit indicates the sign) are used instead of unsigned numbers with separate sign bits, and all of the operations are additions, then the mantissas are used directly, and the (N+1)th input 111, as well as XOR-gates 112, can be omitted. If some of the operations may be subtractions, the signed number inputs 111, 112 would be used but would be determined by the subtraction controls. But if the presence of subtractions is fixed for a particular user logic design, then the necessary inversions can be fixed when the user logic design is compiled, and inputs 111, 112 again could be omitted.
One embodiment of exponent sorting module 200 may use a binary sorting tree to find the largest exponent. The exponents 101 may be paired off arbitrarily. For each pair, the larger of the two exponents 201, 202 may be found as shown in FIG. 2. As seen there, exponents 201, 202 are input as signed numbers to subtractor 203, as well as to the 0th and 1th inputs, respectively, of multiplexer 204. Exponent 202 is subtracted from exponent 201. The most significant bit (MSB) of the difference 205 controls multiplexer 204. Thus, if exponent 201 is larger, difference 205 is positive, so its MSB is a 0 and multiplexer 204 selects exponent 201. If exponent 202 is larger, difference 205 is negative, so its MSB is a 1 and multiplexer 204 selects exponent 202. The results are passed to the next level of tree 200. If any level has an odd number of inputs, one input simply gets a bye to the following level. The number of levels required to sort N exponents 101 is ceil(log 2(N)).
As compared to a tree of carry-propagate adders, the structure 100 of FIG. 1 is about the same size, in terms of device area. Although compressor 106 may be larger than the equivalent number of adders, the absence of pipeline registers between adder levels makes the difference negligible. However, even though it does not present an advantage in device area, structure 100 presents a latency advantage. For example, in the case of eight inputs, the latency would be about one-half of the latency using the technique of above-incorporated application Ser. No. 11/625,655.
Normalization may be required at the end of a calculation, if an IEEE754-1985-compliant output is required. In addition, if data will be lost because an overflow or underflow will occur, then intermediate normalization may take place. Whether at the end of the calculation, or at an intermediate step, normalization may be performed, for example, by circuitry 300 such as that shown in FIG. 3.
The absolute value of denormalized mantissa 301 is determined at 302. A count-leading-zeroes module 303 may determine, by counting leading zeroes, how many bits of shifting are required to renormalize output 301. The number so determined may be used in left shifter 305 to adjust pipelined mantissa 301 and at subtractor 306 to adjust pipelined exponent 304. The normalized mantissa 310 and exponent 311 are adjusted as necessary by rounding stage 307 as is well known (e.g., from the IEEE754-1985 specification), to provide a resultant mantissa 320 and a resultant exponent 321.
If signed numbers are being used, then for normalization, arrangement 400 of FIG. 4 may be substituted in FIG. 3 for count-leading-zeroes module 303. Arrangement 400 includes a count-leading-zeroes module 403, as well as a count-leading-ones module 401. If a number is positive, then it will have some number of leading zeroes, the first of which is the sign bit. Count-leading-zeroes module 403 will determine how many leading zeroes there are, and that number, output at 405, will be used in left shifter 305 to normalize the number. If a number is negative, then it will have some number of leading ones, the first of which is the sign bit. Count-leading-ones module 401 will determine how many leading ones there are, and that number, output at 405, will be used in left shifter 305 to normalize the number. Whether the output of count-leading-ones module 401 or count-leading-zeroes module 403 is used is determined by a multiplexer 402 whose control input is the most significant bit of the input number 404. Whichever of count-leading-ones module 401 or count-leading-zeroes module 403 is not selected by multiplexer 402 may have a completely erroneous output, but it will be ignored.
One potential use for the present invention may be in programmable integrated circuit devices such as programmable logic devices, where programming software can be provided to allow users to configure a programmable device to perform multi-input floating point addition and subtraction (subtraction is the same as addition, with an adjustment the sign of the minuend). The result would be that fewer logic resources of the programmable device would be consumed. And where the programmable device is provided with a certain number of dedicated blocks for arithmetic functions (to spare the user from having to configure arithmetic functions from general-purpose logic), the number of dedicated blocks needed to be provided (which may be provided at the expense of additional general-purpose logic) can be reduced (or sufficient dedicated blocks for more operations, without further reducing the amount of general-purpose logic, can be provided).
Instructions for carrying out the method according to this invention may be encoded on a machine-readable medium, to be executed by a suitable computer or similar device to implement the method of the invention for programming or configuring PLDs to perform arithmetic operations in accordance with the format describe above. For example, a personal computer may be equipped with an interface to which a PLD can be connected, and the personal computer can be used by a user to program the PLD using a suitable software tool, such as the QUARTUS® II software available from Altera Corporation, of San Jose, Calif.
FIG. 5 presents a cross section of a magnetic data storage medium 600 which can be encoded with a machine-executable program that can be carried out by systems such as the aforementioned personal computer, or other computer or similar device. Medium 600 can be a floppy diskette or hard disk, or magnetic tape, having a suitable substrate 601, which may be conventional, and a suitable coating 602, which may be conventional, on one or both sides, containing magnetic domains (not visible) whose polarity or orientation can be altered magnetically. Except in the case where it is magnetic tape, medium 600 may also have an opening (not shown) for receiving the spindle of a disk drive or other data storage device.
The magnetic domains of coating 602 of medium 600 are polarized or oriented so as to encode, in manner which may be conventional, a machine-executable program, for execution by a programming system such as a personal computer or other computer or similar system, having a socket or peripheral attachment into which the PLD to be programmed may be inserted, to configure appropriate portions of the PLD, including its specialized processing blocks, if any, in accordance with the invention.
FIG. 6 shows a cross section of an optically-readable data storage medium 700 which also can be encoded with such a machine-executable program, which can be carried out by systems such as the aforementioned personal computer, or other computer or similar device. Medium 700 can be a conventional compact disk read only memory (CD-ROM) or digital video disk read only memory (DVD-ROM) or a rewriteable medium such as a CD-R, CD-RW, DVD-R, DVD-RW, DVD+R, DVD+RW, or DVD-RAM or a magneto-optical disk which is optically readable and magneto-optically rewriteable. Medium 700 preferably has a suitable substrate 701, which may be conventional, and a suitable coating 702, which may be conventional, usually on one or both sides of substrate 701.
In the case of a CD-based or DVD-based medium, as is well known, coating 702 is reflective and is impressed with a plurality of pits 703, arranged on one or more layers, to encode the machine-executable program. The arrangement of pits is read by reflecting laser light off the surface of coating 702. A protective coating 704, which preferably is substantially transparent, is provided on top of coating 702.
In the case of magneto-optical disk, as is well known, coating 702 has no pits 703, but has a plurality of magnetic domains whose polarity or orientation can be changed magnetically when heated above a certain temperature, as by a laser (not shown). The orientation of the domains can be read by measuring the polarization of laser light reflected from coating 702. The arrangement of the domains encodes the program as described above.
Thus it is seen that a method for carrying out floating point operations, a PLD programmed to perform the method, and software for carrying out the programming, have been provided.
A PLD 90 programmed according to the present invention may be used in many kinds of electronic devices. One possible use is in a data processing system 900 shown in FIG. 7. Data processing system 900 may include one or more of the following components: a processor 901; memory 902; I/O circuitry 903; and peripheral devices 904. These components are coupled together by a system bus 905 and are populated on a circuit board 906 which is contained in an end-user system 907.
System 900 can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD 90 can be used to perform a variety of different logic functions. For example, PLD 90 can be configured as a processor or controller that works in cooperation with processor 901. PLD 90 may also be used as an arbiter for arbitrating access to a shared resources in system 900. In yet another example, PLD 90 can be configured as an interface between processor 901 and one of the other components in system 900. It should be noted that system 900 is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims.
Various technologies can be used to implement PLDs 90 as described above and incorporating this invention.
It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the various elements of this invention can be provided on a PLD in any desired number and/or arrangement. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow.

## Claims

1. A method of configuring a programmable integrated circuit device to perform floating point addition operations on more than two numbers, each of said numbers being represented by a respective mantissa and a respective exponent, said method comprising:
configuring logic of said programmable integrated circuit device to determine a largest exponent of said respective exponent of said more than two numbers, and to subtract each respective said exponent from said largest exponent to determine a respective shifting amount, and to select said largest exponent as a resultant exponent;
configuring logic of said programmable integrated circuit device to shift each respective mantissa of said more than two numbers by said respective shifting amount;
configuring a compressor in said programmable integrated circuit device to simultaneously combine said more than two shifted mantissas into a carry vector and a save vector; and
configuring a carry-propagate adder in said programmable integrated circuit device to combine said carry vector and said save vector.

2. The method of claim 1 wherein:
said configuring logic of said programmable integrated circuit device to determine a largest exponent comprises configuring logic of said programmable integrated circuit device to perform a binary sort.

3. The method of claim 1 further comprising:
configuring logic of said programmable integrated circuit device to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount.

4. The method of claim 3 wherein:
configuring logic of said programmable integrated circuit device to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount comprises configuring logic of said programmable integrated circuit device to determine said left-shift amount by counting leading zeroes in said resultant mantissa when said resultant mantissa represents an unsigned number or a positive signed number, and by counting leading ones in said resultant mantissa when said resultant mantissa represents a negative signed number.

5. The method of claim 3 further comprising configuring logic of said programmable integrated circuit device to round said normalized resultant mantissa and said reduced resultant exponent to produce a final mantissa and a final exponent.

6. The method of claim 1 wherein:
said floating-point addition operations include one or both of negative addends and subtraction operations; and
said numbers are unsigned numbers having mantissas and separate sign bits; said method further comprising:
configuring logic of said programmable integrated circuit device to count each of said numbers having a sign bit equal to 1, representing a negative addend or a subtraction, for input to said compressor;
configuring logic of said programmable integrated circuit device to invert said mantissas of any negative addend, and any minuend in any subtraction operation, for input to said compressor.

7. The method of claim 1 wherein:
said floating-point addition operations include one or both of negative addends and subtraction operations; and
said numbers are signed numbers having sign bits as part of their mantissas; said method further comprising:
configuring logic of said programmable integrated circuit device to count subtraction control bits associated with said numbers for input to said compressor.

8. A programmable integrated circuit device configurable to perform floating point addition operations on more than two numbers, each of said numbers being represented by a respective mantissa and a respective exponent, said programmable integrated circuit device comprising:
programmable logic configurable to determine a largest exponent of said respective exponent of said more than two numbers, and to subtract each respective said exponent from said largest exponent to determine a respective shifting amount, and to select said largest exponent as a resultant exponent;
programmable logic configurable to shift each respective mantissa of said plurality of numbers by said respective shifting amount;
programmable logic configurable as a compressor to simultaneously combine said plurality of shifted mantissas into a carry vector and a save vector; and
programmable logic configurable to combine said carry vector and said save vector.

9. The device of claim 8 wherein said programmable logic configurable to combine said carry vector and said save vector comprises a fixed carry-propagate adder.

10. The device of claim 8 wherein said programmable logic configurable to combine said carry vector and said save vector comprises logic configurable as a carry-propagate adder.

11. The device of claim 8 wherein said programmable logic configurable to determine a largest exponent comprises programmable logic configurable to perform a binary sort.

12. The device of claim 8 further comprising programmable logic configurable to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount.

13. The device of claim 12 wherein said logic configurable to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount comprises logic configurable to determine said left-shift amount by counting leading zeroes in said resultant mantissa when said resultant mantissa represents an unsigned number or a positive signed number, and by counting leading ones in said resultant mantissa when said resultant mantissa represents a negative signed number.

14. The device of claim 12 further comprising logic configurable to round said normalized resultant mantissa and said reduced resultant exponent to produce a final mantissa and a final exponent.

15. The device of claim 8 wherein:
said floating-point addition operations include one or both of negative addends and subtraction operations; and
said numbers are unsigned numbers having mantissas and separate sign bits; said device further comprising:
logic configured to count each of said numbers having a sign bit equal to 1, representing a negative addend or a subtraction, for input to said compressor;
logic configured to invert said mantissas of any negative addend, and any minuend in any subtraction operation, for input to said compressor.

16. The device of claim 8 wherein:
said floating-point addition operations include one or both of negative addends and subtraction operations; and
said numbers are signed numbers having sign bits as part of their mantissas; said device further comprising:
logic configured to count subtraction control bits associated with said numbers for input to said compressor.

17. A non-transitory machine-readable data storage medium encoded with machine-executable instructions for configuring a programmable integrated circuit device to perform floating point addition operations on a more than two numbers, each of said numbers being represented by a respective mantissa and a respective exponent, said instructions comprising:
instructions to configure logic of said programmable integrated circuit device to determine a largest exponent of said respective exponent of said more than two numbers, and to subtract each respective said exponent from said largest exponent to determine a respective shifting amount, and to select said largest exponent as a resultant exponent;
instructions to configure logic of said programmable integrated circuit device to shift each respective mantissa of said more than two numbers by said respective shifting amount;
instructions to configure a compressor in said programmable integrated circuit device to simultaneously combine said more than two shifted mantissas into a carry vector and a save vector; and
instructions to configure a carry-propagate adder in said programmable integrated circuit device to combine said carry vector and said save vector.

18. The non-transitory machine-readable data storage medium of claim 17 wherein said instructions to configure logic of said programmable integrated circuit device to determine a largest exponent comprise instructions to configure logic of said programmable integrated circuit device to perform a binary sort.

19. The non-transitory machine-readable data storage medium of claim 17 wherein said instructions further comprise instructions to configure logic of said programmable integrated circuit device to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount.

20. The non-transitory machine-readable data storage medium of claim 19 wherein said instructions to configure logic of said programmable integrated circuit device to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount comprise instructions to configure logic of said programmable integrated circuit device to determine said left-shift amount by counting leading zeroes in said resultant mantissa when said resultant mantissa represents an unsigned number or a positive signed number, and by counting leading ones in said resultant mantissa when said resultant mantissa represents a negative signed number.

21. The non-transitory machine-readable data storage medium of claim 19 wherein said instructions further comprise instructions to configure logic of said programmable integrated circuit device to round said normalized resultant mantissa and said reduced resultant exponent to produce a final mantissa and a final exponent.

22. Circuitry for performing floating point addition operations on more than two numbers, each of said numbers being represented by a respective mantissa and a respective exponent, said circuitry comprising:
logic to determine a largest exponent of said respective exponent of said more than two numbers, and to subtract each respective said exponent from said largest exponent to determine a respective shifting amount, and to select said largest exponent as a resultant exponent;
logic to shift each respective mantissa of said more than two numbers by said respective shifting amount;
a compressor to simultaneously combine said more than two shifted mantissas into a carry vector and a save vector; and
logic to combine said carry vector and said save vector.

23. The circuitry of claim 22 wherein said logic to combine said carry vector and said save vector comprises a carry-propagate adder.

24. The circuitry of claim 22 wherein said logic to determine a largest exponent comprises binary sort logic.

25. The circuitry of claim 22 further comprising logic to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount.

26. The circuitry of claim 25 wherein said logic to normalize said resultant mantissa by a left-shift amount and to reduce said resultant exponent by said left-shift amount comprises count-leading-zeroes logic to count leading zeroes in said resultant mantissa to determine said left-shift amount when said resultant mantissa represents an unsigned number or a positive signed number, and count-leading-ones logic to count leading ones in said resultant mantissa to determine said left-shift amount when said resultant mantissa represents a negative signed number.

27. The circuitry of claim 25 further comprising logic to round said normalized resultant mantissa and said reduced resultant exponent to produce a final mantissa and a final exponent.

28. The circuitry of claim 22 wherein:
said floating-point addition operations include one or both of negative addends and subtraction operations; and
said numbers are unsigned numbers having mantissas and separate sign bits; said circuitry further comprising:
logic to count each of said numbers having a sign bit equal to 1, representing a negative addend or a subtraction, for input to said compressor; and
logic to invert said mantissas of any negative addend, and any minuend in any subtraction operation, for input to said compressor.

29. The circuitry of claim 22 wherein:
said floating-point addition operations include one or both of negative addends and subtraction operations; and
said numbers are signed numbers having sign bits as part of their mantissas; said circuitry further comprising:
logic to count subtraction control bits associated with said numbers for input to said compressor.