# Patent

## Title
Doubled balanced mixer with improved component matching

## Abstract

An improved passive double balanced mixer with reduced capacitor voltage mismatch is described. A passive double balanced mixer includes two sets of mixer circuits, each comprised of switches. Each switch is separately divided into a first portion and a second portion of unequal number of fingers. A first and second LO AC coupling capacitors associated with a given switch are coupled at one end to an LO signal. The outputs of the first LO AC coupling capacitors are coupled to the first portion of the first switch and the second portion of the second switch, respectively, while the outputs of the second LO AC coupling capacitors are coupled to the second portion of the first switch and the first portion of the second switch, respectively. In one embodiment, the unequal number of fingers is defined by an n−1 and an n+1 number of fingers, respectively. In an alternate embodiment, the mixer is an ADB mixer with a transconductance amplifier and two sets of mixer circuits as above.

## Background
TECHNICAL FIELD
The present disclosure relates to mixer circuits, and in particular, to double balanced mixer circuits with improved component matching.
BACKGROUND
Mixer circuits are used in a variety of applications. For example, they are often used in radio frequency (RF) applications for up-converting or down-converting. In this context up-converting is the process of mixing a baseband signal such as a differential baseband signal, with an RF signal that is generated by a local oscillator circuit that operates in the RF range. This process generates a mixed RF signal with the baseband information included within the RF signal generated by the local oscillator. Down converting is the process of separating the baseband signal from the mixed RF signal generated by the local oscillator. When the radio frequency (RF) spectrum is directly translated to the baseband in the first down-conversion, the receiver is called a “homodyne,” “direct-conversion,” or “Zero-IF” architecture.
FIG. 1 shows a conventional double balanced mixer 100. Double balanced mixer (DBM) 100 includes two mixer circuits the outputs of which are coupled to common load. DBM 100 is comprised generally of two sets of differential transistor pairs M1/M2 110/112 and M3/M4 114/116, each of which receives a first differential input signal RF_P, RF_M, respectively. The two sets of differential transistor pairs M1/M2 110/112 and M3/M4 114/116 receive a second differential signal LO_P, LO_M that drives the gates of transistor pairs M1/M3 110/114 and M2/M4 112/116, respectively. This second differential signal typically arrives from a local oscillator (LO). The biasing of the gate, drain and source terminals of transistors M1 110, M2 112, M3 114 and M4 116 is well known in the art and shall not be described.
While M1 110, M2 112, M3 114 and M4 116 are shown as transistor devices, it is known to substitute any equivalent amplifying or switching device in the configuration shown. The term passive is generally used to indicate that a mixer configuration performs no amplification. The term active is generally used to indicate that a mixer configuration performs amplification. Complementary-metal-oxide (CMOS) semiconductor technology is a common fabrication process technology.
It is desirable to match M1 110, M2 112, M3 114 and M4 116. However manufacturing variations may cause components of the circuit to be mismatched. Such mismatches may cause the output of the circuit to include a variety of unwanted frequencies. For example mismatch in the differential devices M1 110 and M2 112 or M3 114 and M4 116 may cause even harmonics. In some cases, harmonic impurities resulting from manufacturing variances may be very small and effectively negligible. When the variances are sufficiently large, harmonic impurities may impact system performance. For example, in a DBM for a direct conversion receiver, second order inter-modulation (IM2) products in particular may especially degrade the signal-to-noise ratio (SNR) at the baseband. Large manufacturing variations may even cause the system to be completely inoperable. Thus, some portions of the circuits produced by the manufacturing process may have to be discarded, thereby affecting the “yield” of the process. As manufacturing is moving to smaller process nodes, controlling the manufacturing process variances is increasingly difficult, thus methods to improve the spectral purity of mixer circuits have been presented.
FIG. 2 shows the double balanced mixer of FIG. 1 with IM2 product mismatch correction.
To address the effects of mismatch, one or more bias voltages of transistors M1 210, M2 212, M3 214 and M4 216 may be adjusted. In the specific example of FIG. 2, the gate terminals of transistors M2 212 and M4 216 are connected to a gate voltage Vg through resistors R2 214 and R4 218, respectively. Vg may not be configurable, as when tied to an on-chip voltage reference.
A digital-to-analog converter (DAC) 222 configures the gates of transistors M1 210 and M3 214 through resistors R1 212 and R3 216, respectively. Resistors R1 212, R2 214, R3 216 and R4 218 nominally have the same value. More specifically, when the differential signals IF_P and IF_M are not matched, DAC 222 introduces an appropriate DC voltage at the gate of the two devices M1 210 and M3 214, to cause the signals IF_P and IF_M to closely match. Capacitors C1P 202, C1M 206, C2P 204 and C2M 208 serve to couple only the AC components of the signals LO_P and LO_M to the mixer, while isolating the DC voltage of the local oscillator circuit from the bias voltage at the gate of devices M1 210, M2212, M3 214 and M4216, respectively. Capacitors C1P 202, C1M 206, C2P 204 and C2M 208 nominally have the same capacitance value.
In the configuration shown in FIG. 2, device mismatches are corrected without regard to spectral purity at the output caused by possible mismatch between AC coupling capacitors C1P 202, C1M 206, C2P 204 and C2M 208. Mismatch between AC coupling capacitors C1P 202, C1M 206, C2P 204 and C2M 208 is not generally a main source of IM2 products when large capacitors are used to couple the local oscillator signal to the mixer.
However, as devices get smaller and smaller, driven particularly by the demand for smaller and smaller multi-mode, multi-protocol radio transceiver architectures, a need arises for reducing the die area and power consumed by mixers incorporated therein.
As technologies scale down, active devices (such as diodes and transistors) incorporated therein also scale down in size. Passive devices (i.e., resistors, capacitors and inductors) by comparison do not scale down proportionately. The end result is that passive components become a significant stumbling block to miniaturization and power efficiency. This is particularly the case with AC coupling capacitors used in mixers.
The optimum size of an AC-coupling capacitor size is directly related to a desired frequency of operation of the mixer. As the desired frequency of operation increases, the value and hence the size of the AC coupling capacitor value may also be reduced.
Any reduction, however, in local oscillator AC-coupling capacitance motivated by a desire to reduce capacitor size results in greater mismatch. This mismatch will cause a coupling signal strength difference between the LO_P and LO_M signals. This in turn can impact IM2 performance of the mixer requiring calibration and correction, which may not be possible without additional circuitry contributing to additional area, circuit complexity and power inefficiency.
Minimizing this additional source of impact without any additional calibration circuitry is beneficial in double balanced mixers where one or more local oscillator (LO) capacitors for a same polarity are split for IM2 calibration purposes.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a double balanced mixer.
FIG. 2 shows a double balanced mixer of FIG. 1 with IM2 product mismatch correction.
FIG. 3 shows a double balanced mixer with mismatched LO coupling capacitors.
FIG. 4 shows a passive double balanced mixer in accordance with an exemplary embodiment.
FIG. 5 shows an active double balanced mixer in accordance with an alternate exemplary embodiment.



DETAILED DESCRIPTION
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.
The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention can be practiced. The term “exemplary” used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other exemplary embodiments. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary embodiments of the invention. It will be apparent to those skilled in the art that the exemplary embodiments of the invention may be practiced without these specific details. In some instances, well known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary embodiments presented herein.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The present disclosure is directed to double balanced mixers where one or more local oscillator (LO) capacitors for a same polarity are split for IM2 calibration purposes.
FIG. 3 shows a passive double balanced mixer 300 with mismatched LO coupling capacitors 302, 304, 306, 308. As shown, a positive local oscillator signal (LOP) is coupled to a first terminal of capacitors 302 and 306. A second terminal of capacitor 302 is coupled to a gate terminal of transistor 310. A drain terminal of transistor 310 is coupled to the positive baseband output terminal (BBP). A second terminal of capacitor 306 is coupled to a gate terminal of transistor 314. A drain terminal of transistor 314 is coupled to the negative baseband output terminal (BBM).
A negative local oscillator signal (LOM) is coupled to a first terminal of capacitors 304 and 308. A second terminal of capacitor 304 is coupled to a gate terminal of transistor 312. A source terminal of transistor 312 is coupled to the negative baseband output terminal (BBM). A second terminal of capacitor 308 is coupled to a gate terminal of transistor 316. The source terminal of transistor 316 is coupled to the positive baseband output terminal (BBp). A source terminal of transistor 310 is coupled to a drain terminal of transistor 312 and positive RF input signal (RFP). A source terminal of transistor 314 is coupled to a drain terminal of transistor 316 and negative RF input signal (RFM).
The signal present at the gate terminal of transistor 310 may be expressed as:

LOP+δ  Eq. 1

    
    
        where δ is the amplitude or phase variation to the positive local oscillator signal as a result of passing through capacitor 302.
    
    


Similarly, the signal present at the gate terminal of transistor 312 may be expressed as:

LOM+σ  Eq. 2

    
    
        where σ is the amplitude or phase variation to the negative local oscillator signal as a result of passing through capacitor 304.
    
    


The signal present at the gate terminal of transistor 314 may be expressed as:

LOP−δ  Eq. 3

where δ is the amplitude or phase variation to the positive local oscillator signal as a result of passing through capacitor 306.
The signal present at the gate terminal of transistor 316 may be expressed as:

LOM−σ  Eq. 4

where σ is the amplitude or phase variation to the negative local oscillator signal as a result of passing through capacitor 308.
The resulting signal present at the positive baseband output terminal may be expressed as:

BBP=(LOP+δ)RFP+(LOM−σ)RFM  Eq. 5

The resulting signal present at the negative baseband output terminal may be expressed as:

BBM=(LOP−δ)RFM+(LOM+σ)RFP  Eq. 6

From equations 5 and 6, the resulting signal present across the baseband output terminals may be expressed as:

BBOUT=BBP−BBM=(LOP−δ)RFM+(LOM+σ)RFP  Eq. 7

As can be seen, capacitor voltage mismatch significantly contributes to the overall baseband voltage level at the output of mixer 300.
An improved passive double balance mixer with reduced capacitor voltage mismatch is described below. A passive double balance mixer includes two sets of mixer circuits, each comprised of switches. Each switch is separately divided into a first portion and a second portion of unequal number of fingers. A first and second LO AC coupling capacitors associated with a given switch are coupled at one end to a first LO signal. The outputs of the first and second LO AC coupling capacitors are coupled to the first and second portions of the two switches, respectively. In one embodiment, the unequal number of fingers is defined by an n+1 and an n−1 number of fingers, respectively.
FIG. 4 shows a passive double balanced mixer 400 in accordance with an exemplary embodiment. Here, each switch 430, 432, 434, 436 has 2N fingers divided into two portions of unequal number of fingers, N−x and N+x, each constituting a separate and distinct transistor. In an exemplary embodiment, the first portion comprises N−1 fingers and the second portion comprises N+1 fingers. A positive local oscillator signal (LOP) is coupled to a first terminal of capacitors 402 and 406. A second terminal of capacitor 402 is coupled to a gate terminal of transistors 410 (having N−1 fingers) and 415 (having N+1 fingers). A drain terminal of transistor 410 is coupled to the positive baseband output terminal (BBP). A drain terminal of transistor 415 is coupled to the negative baseband output terminal (BBM). A second terminal of capacitor 406 is coupled to a gate terminal of transistors 414 (having N−1 fingers) and 411 (having N+1 fingers). A drain terminal of transistor 414 is coupled to the negative baseband output terminal (BBM). A drain terminal of transistor 411 is coupled to the positive baseband output terminal (BBP).
A negative local oscillator signal (LOM) is coupled to a first terminal of capacitors 404 and 408. A second terminal of capacitor 404 is coupled to a gate terminal of transistors 412 (having N−1 fingers) and 417 (having N+1 fingers). A source terminal of transistor 412 is coupled to the negative baseband output terminal (BBM). A source terminal of transistor 417 is coupled to the positive baseband output terminal (BBP). A second terminal of capacitor 408 is coupled to a gate terminal of transistors 416 (having N−1 fingers) and 413 (having N+1 fingers). A source terminal of transistor 416 is coupled to the positive baseband output terminal (BBP). A source terminal of transistor 413 is coupled to the negative baseband output terminal (BBM).
A source terminal of transistor 410 is coupled to a drain terminal of transistor 412, a drain terminal of transistor 413, a source terminal of transistor 411 and a positive RF input signal (RFP). A source terminal of transistor 414 is coupled to a drain terminal of transistor 416, a drain terminal of transistor 417, a source terminal of transistor 415 and a negative RF input signal (RFM).
For simplicity reasons the number of fingers in FIG. 4 is considered normalized (instead of N−1, we have (N−1)/2N and instead of N+1, we have (N+1)/2N)
In the configuration of passive double balance mixer 400, the signal present at the gate terminal of transistors 410 and 415 may be expressed as:




  
    
      
        
          LO
          P
        
        +
        
          δ
          2
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        8
      
    
  




where δ is the amplitude or phase variation to the positive local oscillator signal as a result of passing through capacitor 402.

The signal present at the gate terminal of transistors 412 and 417 may be expressed as:




  
    
      
        
          LO
          M
        
        +
        
          σ
          2
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        9
      
    
  




where σ is the amplitude or phase variation to the negative local oscillator signal as a result of passing through capacitor 404.

The signal present at the gate terminal of transistors 414 and 411 may be expressed as:




  
    
      
        
          LO
          P
        
        -
        
          δ
          2
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        10
      
    
  




where δ is the amplitude or phase variation to the positive local oscillator signal as a result of passing through capacitor 406.

The signal present at the gate terminal of transistors 416 and 413 may be expressed as:




  
    
      
        
          LO
          M
        
        -
        
          σ
          2
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        11
      
    
  




where σ is the amplitude or phase variation to the negative local oscillator signal as a result of passing through capacitor 408.

The resulting signal present at the positive baseband output terminal may be expressed as:




  
    
      
        
          BB
          P
        
        =
        
          
            
              (
              
                
                  LO
                  P
                
                +
                
                  δ
                  2
                
              
              )
            
            ⁢
            
              RF
              P
            
            ⁢
            
              
                (
                
                  N
                  -
                  1
                
                )
              
              
                2
                ⁢
                N
              
            
          
          +
          
            
              (
              
                
                  LO
                  P
                
                -
                
                  δ
                  2
                
              
              )
            
            ⁢
            
              RF
              P
            
            ⁢
            
              
                (
                
                  N
                  +
                  1
                
                )
              
              
                2
                ⁢
                N
              
            
          
          +
          
            
              (
              
                
                  LO
                  M
                
                -
                
                  σ
                  2
                
              
              )
            
            ⁢
            
              RF
              M
            
            ⁢
            
              
                (
                
                  N
                  -
                  1
                
                )
              
              
                2
                ⁢
                N
              
            
          
          +
          
            
              (
              
                
                  LO
                  M
                
                +
                
                  σ
                  2
                
              
              )
            
            ⁢
            
              RF
              M
            
            ⁢
            
              
                (
                
                  N
                  +
                  1
                
                )
              
              
                2
                ⁢
                N
              
            
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        12
      
    
  




The resulting signal present at the negative baseband output terminal may be expressed as:





  
    
      
        
          BB
          M
        
        =
        
          
            
              (
              
                
                  LO
                  M
                
                +
                
                  σ
                  2
                
              
              )
            
            ⁢
            
              RF
              P
            
            ⁢
            
              
                (
                
                  N
                  -
                  1
                
                )
              
              
                2
                ⁢
                N
              
            
          
          +
          
            
              (
              
                
                  LO
                  M
                
                +
                
                  σ
                  2
                
              
              )
            
            ⁢
            
              RF
              P
            
            ⁢
            
              
                (
                
                  N
                  +
                  1
                
                )
              
              
                2
                ⁢
                N
              
            
          
          +
          
            
              (
              
                
                  LO
                  P
                
                -
                
                  δ
                  2
                
              
              )
            
            ⁢
            
              RF
              M
            
            ⁢
            
              
                (
                
                  N
                  -
                  1
                
                )
              
              
                2
                ⁢
                N
              
            
          
          +
          
            
              (
              
                
                  LO
                  P
                
                +
                
                  δ
                  2
                
              
              )
            
            ⁢
            
              RF
              M
            
            ⁢
            
              
                (
                
                  N
                  +
                  1
                
                )
              
              
                2
                ⁢
                N
              
            
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        13
      
    
  




Therefore, the resulting signal present across the baseband output terminals may be expressed as:




  
    
      
        
          
            
              
                BB
                OUT
              
              =
              
              ⁢
              
                
                  BB
                  P
                
                -
                
                  BB
                  M
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    RF
                    P
                  
                  ⁡
                  
                    (
                    
                      
                        LO
                        P
                      
                      -
                      
                        LO
                        M
                      
                      +
                      
                        δ
                        N
                      
                      -
                      
                        σ
                        N
                      
                    
                    )
                  
                
                +
              
            
          
        
        
          
            
              
              ⁢
              
                
                  RF
                  M
                
                ⁡
                
                  (
                  
                    
                      LO
                      M
                    
                    -
                    
                      LO
                      P
                    
                    -
                    
                      σ
                      N
                    
                    +
                    
                      δ
                      N
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        14
      
    
  




As can be seen in the resulting baseband output signal described in equation 14 above, the LO mismatch resulting from the AC coupling capacitors is reduced by a factor of 1/N when switch splitting is implemented within the passive mixer circuit.
Those of skill would further appreciate that a passive double mixer can be configured as an active mixer comprising a transconductance amplifier. It should also be appreciated that active mixer configurations may also generally benefit from dividing switches into separate portions.
FIG. 5 shows an active double balanced (ADB) mixer 500 in accordance with an alternate exemplary embodiment. Here, an RF signal is coupled to ADB mixer 500 through transconductance amplifier 522 which provides the desired amplification to the mixer. Here, as in the embodiment of FIG. 4, each switch 530, 532, 534, 536 has 2N fingers divided into two portions of unequal number of fingers, N−x and N+x, each constituting a separate and distinct transistor. In an exemplary embodiment, the first portion comprises N−1 fingers and the second portion comprises N+1 fingers. In the exemplary embodiment of FIG. 5, a positive local oscillator signal (LOP) is coupled to a first terminal of capacitors 502 and 506. A second terminal of capacitor 502 is coupled to a gate terminal of transistors 510 (having N−1 fingers) and 515 (having N+1 fingers). A drain terminal of transistor 510 is coupled to the positive baseband output terminal (BBP). A drain terminal of transistor 515 is coupled to the negative baseband output terminal (BBM). A second terminal of capacitor 506 is coupled to a gate terminal of transistors 514 (having N−1 fingers) and 511 (having N+1 fingers). A drain terminal of transistor 514 is coupled to the negative baseband output terminal (BBM). A drain terminal of transistor 511 is coupled to the positive baseband output terminal (BBP).
A negative local oscillator signal (LOM) is coupled to a first terminal of capacitors 504 and 508. A second terminal of capacitor 504 is coupled to a gate terminal of transistors 512 (having N−1 fingers) and 517 (having N+1 fingers). A drain terminal of transistor 512 is coupled to the negative baseband output terminal (BBM). A drain terminal of transistor 517 is coupled to the positive baseband output terminal (BBP). A second terminal of capacitor 508 is coupled to a gate terminal of transistors 516 (having N−1 fingers) and 513 (having N+1 fingers). A drain terminal of transistor 516 is coupled to the positive baseband output terminal (BBP). A drain terminal of transistor 513 is coupled to the negative baseband output terminal (BBM).
A source terminal of transistor 510 is coupled to a source terminal of transistor 512, a source terminal of transistor 513, a source terminal of transistor 511 and to a transconductance amplifier 522. A source terminal of transistor 514 is coupled to a source terminal of transistor 516, a source terminal of transistor 517, a source terminal of transistor 515 and to a transconductance amplifier 522.
While an ADB mixer has been shown with a specific configuration of a transconductance amplifier, this is only for illustrative purposes, as those skilled in the art of mixer design will readily appreciate that such transconductance amplifier maybe implemented in various embodiments.
In addition, it should be appreciated that while the above exemplary embodiments have been described with switched split into two portions, it may be possible or necessary to split a switch into more than two portions; or if two switches, to split one but not the other.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the exemplary embodiments of the invention.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The previous description of the disclosed exemplary embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these exemplary embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

## Claims

1. A double balanced mixer comprising:
two switches, each switch divided into a first portion comprising a first transistor and a second portion comprising a second transistor, the first and second transistors having an unequal number of fingers; and
first and second local oscillator (LO) AC coupling capacitors each having an input coupled to a first LO signal, with outputs of the first and second LO AC coupling capacitors being coupled to the first portion and second portion of the two switches, respectively.

2. The double balanced mixer of claim 1, wherein for each of the two switches, one of the first and second transistors has n−1 fingers, and the other one of the first and second transistors has n+1 fingers.

3. The double balanced mixer of claim 2, wherein the double balanced mixer is a passive double balanced mixer.

4. The double balanced mixer of claim 1, wherein the two switches define a first set of switches, the double balanced mixer further comprising a second set of two switches, where each switch of the second set of two switches is divided into a first portion comprising a third transistor and a second portion comprising a fourth transistor, the third and fourth transistors in each switch having an unequal number of fingers, respectively.

5. The double balanced mixer of claim 4, wherein the double balanced mixer is a passive double balanced mixer.

6. The double balanced mixer of claim 4, further comprising third and fourth LO AC coupling capacitors, each having an input coupled to a second LO signal of opposite polarity relative to the first LO signal, with outputs of the third and fourth LO AC coupling capacitors being coupled to the first and second portions of each switch of the second set of switches, respectively.

7. The double balanced mixer of claim 6, wherein the first and second set of switches are in a bridge configuration.

8. The double balanced mixer of claim 7, wherein the double balanced mixer is a passive double balanced mixer.

9. The double balanced mixer of claim 6, wherein the first, second, third and fourth transistors are each MOS transistors.

10. The double balanced mixer of claim 9, wherein the double balanced mixer is a passive double balanced mixer.

11. The double balanced mixer of claim 6, wherein the double balanced mixer is a passive double balanced mixer.

12. The double balanced mixer of claim 1, wherein the double balanced mixer is adapted for coupling to a digital to analog converter (DAC) to calibrate for IM2 mismatch in the double balanced mixer.

13. The double balanced mixer of claim 12, wherein the double balanced mixer is a passive double balanced mixer.

14. The double balanced mixer of claim 1, wherein the double balanced mixer is a passive double balanced mixer.

15. The double balanced mixer of claim 1, wherein the double balanced mixer is an active double balanced mixer.

16. A wireless communication device including a double balanced mixer comprising:
two switches, each switch divided into a first portion comprising a first transistor and a second portion comprising a second transistor, the first and second transistors having an unequal number of fingers; and
first and second local oscillator (LO) AC coupling capacitors each having an input coupled to a first LO signal, with outputs of the first and second LO AC coupling capacitors being coupled to the first and second portions of the two switches, respectively.

17. The wireless communication device of claim 16, wherein for each of the two switches, one of the first and second transistors has n−1 fingers, and the other one of the first and second transistors has n+1 fingers.

18. The wireless communication device of claim 16, wherein the two switches define a first set of switches, the double balanced mixer further comprising a second set of two switches, where each switch of the second set of two switches is divided into a first portion comprising a third transistor and a second portion comprising a fourth transistor, the third and fourth transistors in each switch having an unequal number of fingers, respectively.

19. The wireless communication device of claim 18, further comprising third and fourth LO AC coupling capacitors, each having an input coupled to a second LO signal of opposite polarity relative to the first LO signal, outputs of the third and fourth LO AC coupling capacitors being coupled to the first and second portions of each switch of the second set of switches, respectively.

20. The wireless communication device of claim 16, wherein the double balanced mixer is a passive double balanced mixer.

21. The wireless communication device of claim 16, wherein the double balanced mixer is an active double balanced mixer.

22. An integrated circuit having a double balanced mixer comprising:
two switches, each switch divided into a first portion comprising a first transistor and a second portion comprising a second transistor, the first and second transistors having an unequal number of fingers; and
first and second local oscillator (LO) AC coupling capacitors each having an input coupled to a first LO signal, with outputs of the first and second LO AC coupling capacitors being coupled to the first portion and second portion of the two switches, respectively.

23. A device including a double balanced mixer comprising:
a plurality of switches, each switch including a number of portions comprising a transistor defined from parallel transistor fingers, the number of fingers in at least a first portion of each switch being of unequal number relative to the number of fingers of at least a second portion in that same switch; and
a plurality of LO AC coupling capacitors each coupled at one end to an LO signal and at the other end to a corresponding portion of each of the plurality of switches to reduce LO capacitance mismatch.