# Patent

## Title
Down conversion filter and communication receiving apparatus

## Abstract

A down-conversion filter is provided, using first and second input terminals to receive signals that are differentially outputted by a preceding circuit, and using an output terminal to output a down-converted and filtered signal. An output capacitor is coupled to the output terminal. A first switched-capacitor network is arranged between the first input terminal and the output terminal. A second switched-capacitor network is arranged between the second input terminal and the output terminal. Each switched-capacitor network has capacitors, charging switches and charge-summing switches. The charging switches are designed to alternatively couple the capacitors to the first (or second) input terminal. The charge-summing switches are designed to couple the capacitors to the output terminal.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This Application claims priority of Taiwan Patent Application No 097145668. filed on Nov. 26, 2008, the entirety of which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to down conversion filters.
2. Description of the Related Art
Conventional down conversion filters are designed to filter noise in a stop band. However, because conventional down conversion filters provide the received signal and noise with the same frequency response, noise in the pass band usually remains with the transmitted signals. Thus, conventional down conversion filters have a difficult time filtering noise in the pass band.
BRIEF SUMMARY OF THE INVENTION
The invention discloses down conversion filters comprising a first and a second input terminal, an output terminal, output capacitor, and a first and a second switched-capacitor network. The first and second input terminals are coupled to differential output terminals of a preceding circuit. The output capacitor is coupled to the output terminal of the down conversion filter. The first switched-capacitor network is coupled between the first input terminal and the output terminal. The second switched-capacitor network is coupled between the second input terminal and the output terminal. Each of the aforementioned switched-capacitor networks comprises a plurality of capacitors, a plurality of charging switches, and a plurality of charge-summing switches. The charging switches control the charging of the capacitors by coupling the capacitors to the first (or second) input terminal. To transfer the charges from the capacitors to the output capacitor, the charge-summing switches are designed to couple the capacitors to the output terminal.
The down conversion filter may further comprise a plurality of discharging switches for discharging the capacitors of the switched-capacitor networks.
The down conversion filters may be applied in communication receivers to receive differential output signals from a mixer of the communication receiver. With the down conversion filters of the invention, the communication receiver decreases common-mode noise.
A detailed description is given in the following embodiments with reference to the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 depicts an exemplary embodiment of down conversion filters of the invention;
FIG. 2 depicts an exemplary embodiment of the clock signals clkN1 ̃clkN(N+1) and the ResetN;
FIG. 3 depicts the exemplary embodiment of frequency responses HIIR,diff(z1, z2) and HIIR,com(z1, z2);
FIG. 4 depicts a down conversion filter with controllable bandwidth;
FIGS. 5A and 5B show frequency responses of the down conversion filter of FIG. 4, wherein the variable capacitor 402 is set to several capacitances;
FIG. 6A shows an exemplary embodiment of FIR filters;
FIG. 6B shows exemplary embodiments of the clock signals for FIG. 6A;
FIG. 7 shows frequency responses of an FIR filter by waveforms;
FIG. 8 shows a down conversion filter with more than two switched-capacitor networks; and
FIG. 9 depicts an exemplary embodiment of communication receivers of the invention.



DETAILED DESCRIPTION OF THE INVENTION
The following description shows exemplary embodiments carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 1 depicts an exemplary embodiment of down conversion filters of the invention. The down conversion filter 100 has two input terminals receiving a first input signal In− and a second input signal In+, respectively, and has an output terminal OUT.
The down conversion filter 100 comprises a first switched-capacitor network 102, a second switched-capacitor network 104 and an output capacitor Co. The output capacitor Co is coupled to the output terminal OUT.
The first and second switched-capacitor networks 102 and 104 are each controlled by a set of clock signals. The first switched-capacitor network 102 is controlled by clock signals clkN1 ̃clkN(N+1) and the ResetN. The second switched-capacitor network 104 is controlled by clock signals clkP1 ̃clkP(P+1) and the ResetP. FIG. 2 depicts an exemplary embodiment of the clock signals clkN1 ̃clkN(N+1) and the ResetN. The pulse width of the clock signals clkN1 ̃clkN(N+1) may be dependent on a sampling frequency fs. In this case, the clock signal clkN2 lags the clock signal clkN1 by one sampling period 1/fs, the clock signal clkN3 lags the clock signal clkN2 by one sampling period 1/fs thus, on. Furthermore, the clock signal ResetN lags the clock signal clkN(N+1) by one sampling period 1/fs. Similarly, the clock signals clkP1 ̃clkP(P+1) and the ResetP may be generated in the same manner.
The first switched-capacitor network 102 comprises a plurality of capacitors CN1 ̃CNN, a plurality of charging switches MNS1 ̃MNSN, a plurality of discharging switches MNR1 ̃MNRN and a plurality of charge-summing switches MNSS1 ̃MNSSN. The first set of clock signals clkN1 ̃clkN(N+1) and the ResetN control the switches MNS1 ̃MNSN, MNR1 ̃MNRN and MNSS1 ̃MNSSN. According to the clock signals clkN1 ̃clkNN, the charging switches MNS1 ̃MNSN are alternatively turned on to alternatively couple the capacitors CN1 ̃CNN to the first input terminal In−. According to the clock signal clkN(N+1), the charge-summing switches MNSS1 ̃MNSSN are turned on to couple the capacitors CN1 ̃CNN with the output capacitor Co, thus, the charges in the capacitors CN1 ̃CNN and Co are rearranged. According to the clock signal ResetN, the discharging switches MNR1 ̃MNRN are turned on to discharge the capacitors CN1 ̃CNN. The capacitor discharging controlled by the discharging switches MNR1 ̃MNRN can dramatically improve noise filtering. The discharging switches MNR1 ̃MNRN are optional.
The second switched-capacitor network 104 comprises a plurality of capacitors CP1 ̃CPP, a plurality of charging switches MPS1 ̃MPSP, a plurality of discharging switches MPR1 ̃MPRP and a plurality of charge-summing switches MPSS1 ̃MPSSP. The second set of clock signals clkP1 ̃clkP(P+1) and the ResetP control the switches MPS1 ̃MPSP, MPR1 ̃MPRP and MPSS1 ̃MPSSP. According to the clock signals clkP1 ̃clkPP, the charging switches MPS1 ̃MPSP are alternatively turned on to couple the capacitors CP1 ̃CPP to the second input terminal In+. According to the clock signal clkP(P+1), the charge-summing switches MPSS1 ̃MPSSP are turned on to couple the capacitors CP1 ̃CPP with the output capacitor Co, thus, the charges in the capacitors CP1 ̃CPP and Co are rearranged. According to the ResetP, the discharging switches MPR1 ̃MPRP are turned on to discharge the capacitors CP1 ̃CPP. The capacitor discharging controlled by the discharging switches MPR1 ̃MPRP can dramatically improve noise filtering. The discharging switches MPR1 ̃MPRP are optional.
The first input signal In− may include a common-mode portion Xcom and a negative differential portion −Xdiff. For example, In−=Xcom−Xdiff . . . . The second input signal In+ may include the common-mode portion Xcom and a positive differential portion +Xdiff. For example, In+=Xcom+Xdiff . . . . The down conversion filter 100 provides the common-mode and differential portions Xcom and Xdiff with distinct frequency responses. The details of the frequency responses are illustrated as follows:



  
    
      
        
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HIIR,diff(z1, z2) represents frequency response for the differential portion Xdiff. HIIR,com(z1, z2) represents frequency response for the common-mode portion Xcom. By properly designing the value of the capacitors CN1 ̃CNN, CP1 ̃CPP and Co, distinct frequency responses for the common-mode portion Xcom and the differential portion Xdiff are available.

FIG. 3 depicts the exemplary embodiments of the frequency responses. Waveform 302 shows the frequency response HIIR,diff(z1, z2) that is for the differential portion Xdiff. Waveform 304 shows the frequency response HIIR,com(z1, z2) that is for the common-mode portion Xcom. In a specific band (such as the pass band), the down conversion filter 100 passes the differential portion Xdiff and depresses the common-mode portion Xcom. Thus, the down conversion filter 100 has good common-mode noise filtering in the pass band.
The two sets of clock signals controlling the first and second switched-capacitor networks have several designs. However, the two sets of clock signals are not limited to having the same frequency; they may comply with distinct frequencies in other cases.
The clock signals clkN(N+1) and clkP(P+1) may be the same signal or distinct signals. When the clock signal clkN(N+1) equals to the clock signal clkP(P+1), the capacitors CN1 ̃CNN and CP1 ̃CPP are simultaneously coupled to the output terminal OUT.
The exemplary embodiment of the FIG. 1 does not introduce output capacitor Co resetting. FIG. 1 is an infinite impulse response filter, as known as IIR filter. The band width thereof is limited. The invention further discloses down conversion filters with controllable bandwidth, as shown in FIG. 4. Symbol clk_chainN represent clock signals clkN1 ̃clkN(N+1) and the ResetN controlling the first switched-capacitor network 102. Symbol clk_chainP represent clock signals clkP1 ̃clkP(P+1) and the ResetP controlling the second switched-capacitor network 104. Compared with FIG. 1, the down conversion filter of FIG. 4 further comprises a variable capacitor 402 coupled to the output terminal OUT. The variable capacitor 402 may be coupled in parallel or in series with the output capacitor Co to change the capacitance at the output terminal OUT. The capacitance of the variable capacitor 402 is dependent on the voltage value VIIR. In other embodiments, the variable capacitor 402 may be replaced by any other variable capacitors well known by a person skilled in the art.
FIGS. 5A and 5B show frequency responses of the down conversion filter of FIG. 4, wherein the variable capacitor 402 is set to several capacitances. FIG. 5A depicts the frequency responses HIIR,diff(z1, z2) for the differential portion Xdiff. The increasing capacitance of the variable capacitor 402 results in the frequency responses 502, 504 and 506. FIG. 5B depicts the frequency responses HIIR,com(z1, z2) for the common-mode portion Xcom. The increasing capacitance of the variable capacitor 402 results in the frequency responses 508, 510 and 512.
The invention further discloses down conversion filters with finite impulse response (FIR). FIG. 6A shows one of the FIR filters. Compared with FIG. 1, the down conversion filter of FIG. 6A further comprises a discharging circuit 602. The discharging circuit 602 is enabled by a signal EN. When the signal EN is high, the clock signal Reset, controls the discharging of the output capacitor Co. FIG. 6B shows an exemplary embodiment of the clock signal Reseto. The enabling of the clock signal Reseto (discharging of the output capacitor Co) is prior to the connection between the switched-capacitor networks 102 and 104 and the output terminal OUT (for example, prior to the duty period of clock clkN(N+1)). The frequency responses for the common-mode portion Xcom and differential portion Xdiff of the signals In− and In+ are illustrated as follows:



  
    
      
        
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HFIR,diff(z1, z2) represents frequency response for the differential portion Xdiff. HFIR, com(z1,z2) represents frequency response for the common-mode portion Xcom.

FIG. 7 shows frequency responses of an FIR filter by waveforms. Waveform 702 shows the frequency response HFIR,diff(z1, z2) that is for the differential portion Xdiff. Waveform 704 shows the frequency response HFIR, com(z1,z2) that is for the common-mode portion Xcom.
The invention further discloses down conversion filters with more than two switched-capacitor networks, as shown in FIG. 8. Signals In− and In+ are differential signals from a preceding circuit. Switched-capacitor networks 802 and 804 form the first unit. Switched-capacitor networks 806 and 808 form the second unit. Switched-capacitor networks 810 and 812 form the third unit. A set of clock signals clk_chain are sent to the switched-capacitor networks as control signals. However, different units may have different use on the clock signals clock_chain. For example, different units may connect their switched-capacitor networks to the output terminal OUT according to different clock signals. Thus, different units may be coupled to the output terminal OUT asynchronously. By this technique shown in FIG. 8, a large number of the switched-capacitor networks may be supported without reducing the tap length of the down conversion filter. Thus, flexibility of the down conversion filter is dramatically improved. It should be noted that the switched-capacitor networks shown in FIG. 8 are not all limited to the use the set of clock signals clk_chain. Different clock signal sets may be used in controlling different switched-capacitor networks.
The invention further discloses a communication receiver, as shown in FIG. 9. An antenna 902 receives signals. The received signal is sent to a mixer 906, via a low-noise transconductance amplifier (LNTA) 904, to be down converted to an intermediate frequency. The mixer 906 differentially outputs an in-phase signal IF_I by a first output terminal and a second output terminal, and differentially outputs an orthogonal signal IF_Q by a third output terminal and a fourth output terminal. The down conversion filters 908 and 910 may be realized by any of the aforementioned down-conversion filters. The down conversion filter 908 converts the in-phase signal IF_I to a base-band in-phase signal BB_I. The down conversion filter 910 converts the orthogonal signal IF_Q to a base-band orthogonal signal BB_Q. The down conversion filters 908 and 910 efficiently eliminate the pass band common-mode signals of IF_I and IF_Q. The control signals of the down conversion filters 908 and 910 are generated by a clock signal generator 914. The local oscillator 912 outputs local oscillating signals LO for the clock signal generator 914 and the mixer 906.
In another exemplary embodiment of the communication receivers of the invention, the mixer 906 does not separate the phase of the intermediate frequency signal. The mixer 906 outputs the same signal IF to both down conversion filters 908 and 910. With properly designed capacitors in the down conversion filters 908 and 910, a base-band in-phase signal BB_I is outputted by the down conversion filter 908 and a base-band orthogonal signal BB_Q is outputted by the down conversion filter 910.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

## Claims

1. A down conversion filter, comprising:
a first input terminal, receiving a first input signal;
a second input terminal, receiving a second input signal;
an output terminal;
an output capacitor, coupled to the output terminal;
a first switched-capacitor network, comprising a plurality of first capacitors, a plurality of first charging switches and a plurality of first charge-summing switches, wherein the first charging switches are designed to alternatively couple the first capacitors to the first input terminal, and the first charge-summing switches are designed to couple the first capacitors to the output terminal; and
a second switched capacitor network, comprising a plurality of second capacitors, a plurality of second charging switches and a plurality of second charge-summing switches, wherein the second charging switches are designed to alternatively couple the second capacitors to the second input terminal, and the second charge-summing switches are designed to couple the second capacitors to the output terminal and are switched on at the exact same time as the first charge-summing switches,
wherein:
the first and second input signals are a pair of differential signals from a preceding circuit; and
the first capacitors and the second capacitors are directly connected to the output capacitor when the first charge-summing switches and the second charge-summing switched are turned on.

2. The down conversion filter as claimed in claim 1, further comprising a plurality of first discharging switches, designed to discharge the first capacitors.

3. The down conversion filter as claimed in claim 1, further comprising a plurality of second discharging switches, designed to discharge the second capacitors.

4. The down conversion filter as claimed in claim 1, wherein the first input signal includes a common-mode portion and a negative differential portion, and the second input signal includes the common-mode portion and a positive differential portion.

5. The down conversion filter as claimed in claim 1, further comprising a variable capacitor coupled to the output terminal.

6. The down conversion filter as claimed in claim 1, further comprising a discharging circuit coupled to the output terminal, designed to discharge the output capacitor according to a clock signal for output capacitor discharging.

7. A communication receiver, comprising:
a mixer, down-converting a received signal, outputting a pair of differential signals at a first and a second output terminal to form an in-phase signal, and outputting another pair of differential signals at by a third and a fourth output terminal to form an orthogonal signal;
a first down conversion filter, comprising:
an output terminal for a base band in-phase signal;
a first output capacitor, coupled to the output terminal for the base band in-phase signal;
a first switched-capacitor network, comprising a plurality of first capacitors, a plurality of first charging switches and a plurality of first charge-summing switches, wherein the first charging switches are designed to alternatively couple the first capacitors to the first output terminal of the mixer, and the first charge-summing switches are designed to couple the first capacitors to the output terminal for the base band in-phase signal; and
a second switched-capacitor network, comprising a plurality of second capacitors, a plurality of second charging switches and a plurality of second charge-summing switches, wherein the second charging switches are designed to alternatively couple the second capacitors to the second output terminal of the mixer, and the second charge-summing switches are designed to couple the second capacitors to the output terminal for the base band in-phase signal and are switched on at the exact same time as the first charge-summing switches,
wherein the first capacitors and the second capacitors are directly connected to the first output capacitor when the first charge-summing switches and the second charge-summing switches are turned on; and

a second down conversion filter, comprising:
an output terminal for a base band orthogonal signal;
a second output capacitor, coupled to the output terminal for the base band orthogonal signal;
a third switched-capacitor network, comprising a plurality of third capacitors, a plurality of third charging switches and a plurality of third charge-summing switches, wherein the third charging switches are designed to alternatively couple the third capacitors to the third output terminal of the mixer, and the third charge-summing switches are designed to couple the third capacitors to the output terminal for the base band orthogonal signal; and
a fourth switched-capacitor network, comprising a plurality of fourth capacitors, a plurality of fourth charging switches and a plurality of fourth charge-summing switches, wherein the fourth charging switches are designed to alternatively couple the fourth capacitors to the fourth output terminal of the mixer, and the fourth charge-summing switches are designed to couple the fourth capacitors to the output terminal for the base band orthogonal signal and are switched on at the exact same time as the third charge-summing switches,
wherein the third capacitors and the fourth capacitors are directly connected to the second output capacitor when the third charge-summing switches and the fourth charge-summing switches are turned on.

8. The communication receiver as claimed in claim 7, further comprising a plurality of first discharging switches for discharging the first capacitors.

9. The communication receiver as claimed in claim 7, further comprising a plurality of second discharging switches for discharging the second capacitors.

10. The communication receiver as claimed in claim 7, further comprising a plurality of third discharging switches for discharging the third capacitors.

11. The communication receiver as claimed in claim 7, further comprising a plurality of fourth discharging switches for discharging the fourth capacitors.

12. A communication receiver, comprising:
a mixer, down-converting a received signal and outputting a pair of differential signals at a first and a second output terminal to form and intermediate frequency signal;
a first down conversion filter, comprising:
an output terminal for a base band in-phase signal;
a first output capacitor, coupled to the output terminal for the base band in-phase signal;
a first switched-capacitor network, comprising a plurality of first capacitors, a plurality of first charging switches and a plurality of first charge-summing switches, wherein the first charging switches are designed to alternatively couple the first capacitors to the first output terminal of the mixer, and the first charge-summing switches are designed to couple the first capacitors to the output terminal for the base band in-phase signal; and
a second switched-capacitor network, comprising a plurality of second capacitors, a plurality of second charging switches and a plurality of second charge-summing switches, wherein the second charging switches are designed to alternatively couple the second capacitors to the second output terminal of the mixer, and the second charge-summing switches are designed to couple the second capacitors to the output terminal for the base band in-phase signal and are switched on at the exact same time as the first charge-summing switches,
wherein the first capacitors and the second capacitors are directly connected to the first output capacitor when the first charge-summing switches and the second charge-summing switches are turned on and

a second down conversion filter, comprising:
an output terminal for a base band orthogonal signal;
a second output capacitor, coupled to the output terminal for the base band orthogonal signal;
a third switched-capacitor filter, comprising a plurality of third capacitors, a plurality of third charging switches and a plurality of third charge-summing switches, wherein the third charging switches are designed to alternatively couple the third capacitors to the first output terminal of the mixer, and the third charge-summing switches are designed to coupled the third capacitors to the output terminal for the base band orthogonal signal; and
a fourth switched-capacitor network, comprising a plurality of fourth capacitors, a plurality of fourth charging switches and a plurality of fourth charge-summing switches, wherein the fourth charging switches are designed to alternatively couple the fourth capacitors to the second output terminal of the mixer, and the fourth charge-summing switches are designed to couple the fourth capacitors to the output terminal for the base band orthogonal signal and are switched on at the exact same time as the third charge-summing switches,
wherein the third capacitors and the fourth capacitors are directly connected to the second output capacitor when the third charge-summing switches and the fourth charge-summing switches are turned on.

13. The communication receiver as claimed in claim 12, further comprising a plurality of first discharging switches for discharging the first capacitors.

14. The communication receiver as claimed in claim 12, further comprising a plurality of second discharging switches for discharging the second capacitors.

15. The communication receiver as claimed in claim 12, further comprising a plurality of third discharging switches for discharging the third capacitors.

16. The communication receiver as claimed in claim 12, further comprising a plurality of fourth discharging switches for discharging the fourth capacitors.