Exhibit 10.1
 Second Amendment
To
Patent Purchase Agreement
 Amendment Effective Date Purchaser Seller
 Background
 Agreement
  Terms Used in This Amendment
  Amendments to Agreement
  Payment
 Purchase Price
  *
  
 *
    
    Confidential treatment requested pursuant to Rule 24b-2 under the
Securities Exchange Act of 1934. In accordance with Rule 24b-2, these
confidential portions have been omitted from this exhibit and filed separately
with the Securities and Exchange Commission.




---



##### 



ABA: ***
 
  
 Post-Closing Payment Post-Closing Payment  Post-Closing Payment Period Post-Closing Notice
  
 *
    
    Confidential treatment requested pursuant to Rule 24b-2 under the
Securities Exchange Act of 1934. In accordance with Rule 24b-2, these
confidential portions have been omitted from this exhibit and filed separately
with the Securities and Exchange Commission. Page 2




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##### 



*
      No Other Changes
  Governing Law
  Counterparts; Electronic Signature
 
 *
    
    Confidential treatment requested pursuant to Rule 24b-2 under the
Securities Exchange Act of 1934. In accordance with Rule 24b-2, these
confidential portions have been omitted from this exhibit and filed separately
with the Securities and Exchange Commission. Page 3




---



##### 



 Transmitted Copy 
  SELLER:
    
    PURCHASER:IRVINE SENSORS CORPORATION
    
    APROLASE DEVELOPMENT CO., LLCBy:
    
    /s/ John J. Stuart, Jr.
    
    
    
    By:
    
    /s/ Melissa ColemanName: John J. Stuart, Jr.
    
    
    
    
    
    Name: Melissa ColemanTitle:  
Sr. VP & Chief Financial Officer
    
    
    
    
    
    Title:  
Authorized Person
 Page 4




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##### 



Exhibit A, revised
 PATENTS TO BE ASSIGNED
 Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor5,235,672
(07/651,477)
    
    US
    
    8/10/1993
(2/6/1991)
    
    Hardware for electronic neural
network
Carson, John C.6,389,404
(09/223,476)
    
    US
    
    5/14/2002
(12/30/1998)
    
    Neural processing module with
input architectures that make
maximal use of a weighted
synapse array
Carson, John C.; Saunders,
Christ H.6,650,704
(09/427,384)
    
    US
    
    11/18/2003
(10/25/1999)
    
    Method of producing a high
quality, high resolution image
from a sequence of low quality,
low resolution images that are
undersampled and subject to
jitter
Carlson, Randolph S.; Arnold,
Jack L.; Feldmus, Valentine G.6,829,237
(09/973,857)
    
    US
    
    12/7/2004 (10/9/2001)
    
    High speed multi-stage switching
network formed from stacked
switching layers Carson, John C.;
Ozguz, Volkan H.7,082,591
(10/346,363)
    
    US
    
    7/25/2006
(1/17/2003)
    
    Method for effectively embedding
various integrated circuits
within field programmable gate
arrays
Carlson, Randolph S.6,856,167
(10/347,038)
    
    US
    
    2/15/2005
(1/17/2003)
    
    Field programmable gate array
with a variably wide word width
memory
Ozguz, Volkan H.; Carlson,
Randolph S.; Gann, Keith D.;
Leon, John P.7,265,579
(11/037,490)
    
    US
    
    9/4/2007
(1/18/2005)
    
    Field programmable gate array
incorporating dedicated memory
stacks
Carlson, Randolph Stuart; Ozguz,
Volkan; Gann, Keith D.; Leon,
John P.5,508,836
(08/305,066)
    
    US
    
    4/16/1996 (9/13/1994)
    
    Infrared wireless communication
between electronic system
components
DeCaro, Robert; Saunders, Christ
H.; Maeding, Dale




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor5,635,705
(08/526,415)
    
    US
    
    6/3/1997
(9/11/1995)
    
    Sensing and selecting observed
events for signal processing
Saunders, Christ H.6,195,268
(09/031,435)
    
    US
    
    2/27/2001
(2/26/1998)
    
    Stacking layers containing
enclosed IC chips
Eide, Floyd K.5,045,685
(07/534,969)
    
    US
    
    9/3/1991
(6/6/1990)
    
    Analog to digital conversion on
multiple channel IC chips
Wall, Llewellyn E.5,104,820
(07/720,025)
    
    US
    
    4/14/1992
(6/24/1991)
    
    Method of fabricating electronic
circuitry unit containing
stacked IC layers having lead
rerouting
Go, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.5,279,991
(07/996,794)
    
    US
    
    1/18/1994
(12/24/1992)
    
    Method for fabricating stacks of
IC chips by segmenting a larger
stack
Minahan, Joseph A.; Pepe, Angel
A.5,432,318
(08/178,923)
    
    US
    
    7/11/1995
(1/7/1994)
    
    Apparatus for segmenting stacked
IC chips
Minahan, Joseph A.5,304,790
(07/956,914)
    
    US
    
    4/19/1994
(10/5/1992)
    
    Apparatus and system for
controllably varying image
resolution to reduce data output
Arnold, Jack5,347,428
(07/985,837)
    
    US
    
    9/13/1994
(12/3/1992)
    
    Module comprising IC memory
stack dedicated to and
structurally combined with an IC
microprocessor chip
Carson, John C.; Indin, Ronald
J.; Shanken, Stuart N.5,406,701
(08/120,675)
    
    US
    
    4/18/1995
(9/13/1993)
    
    Fabrication of dense parallel
solder bump connections
Pepe, Angel A.; Reinker, David
M.; Minahan, Joseph A.5,424,920
(08/232,739)
    
    US
    
    6/13/1995
(4/25/1994)
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor5,432,729
(08/255,465)
    
    US
    
    7/11/1995
(6/8/1994)
    
    Electronic module comprising a
stack of IC chips each
interacting with an IC chip
secured to the stack
Carson, John C.; Some, Raphael R.5,581,498
(08/326,645)
    
    US
    
    12/3/1996
(10/20/1994)
    
    Stack of IC chips in lieu of
single IC chip
Ludwig, David E.; Saunders,
Christ H.; Some, Raphael R.;
Stuart, John J.5,688,721
(08/62,2671)
    
    US
    
    11/18/1997
(3/26/1996)
    
    3D stack of IC chips having
leads reached by vias through
passivation covering access
plane
Johnson, Tony K.5,953,588
(08/777,747)
    
    US
    
    9/14/1999
(12/21/1996)
    
    Stackable layers containing
encapsulated IC chips
Camien, Andrew N; Yamaguchi,
James S.6,072,234
(09/316,740)
    
    US
    
    6/6/2000
(5/21/1999)
    
    Stack of equal layer neo-chips
containing encapsulated IC chips
of different sizes
Camien, Andrew N.; Yamaguchi,
James S.5,955,668
(09/166,458)
    
    US
    
    9/21/1999
(10/5/1998)
    
    Multi-element micro gyro
Hsu, Ying W.; Reeds, III, John
W.; Saunders, Christ H.6,089,089
(09/301,847)
    
    US
    
    7/18/2000
(4/29/1999)
    
    Multi-element micro gyro
Hsu, Ying W.6,578,420
(09/604,782)
    
    US
    
    6/17/2003
(6/26/2000)
    
    Multi-axis micro gyro structure
Hsu, Ying Wen6,014,316
(09/095,416)
    
    US
    
    1/11/2000
(6/10/1998)
    
    IC stack utilizing BGA contacts
Eide, Floyd K.6,028,352
(09/095,415)
    
    US
    
    2/22/2000
(6/10/1998)
    
    IC stack utilizing secondary
lead frames
Eide, Floyd K.6,117,704
(09/282,704)
    
    US
    
    9/12/2000
(3/31/1999)
    
    Stackable layers containing
encapsulated chips
Yamaguchi, James S.; Ozguz,
Volkan H.; Camien, Andrew N.




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor6,476,392
(09/853,819)
    
    US
    
    11/5/2002
(5/11/2001)
    
    Method and apparatus for
temperature compensation of an
uncooled focal plane array
Kaufman, Charles S.; Carson,
Randolph S.; Hornback, William
B.6,891,160
(10/281,393)
    
    US
    
    5/10/2005
(10/25/2002)
    
    Method and apparatus for
temperature compensation of an
uncooled focal plane array
Kaufman, Charles S.; Carson,
Randolph S.; Hornback, William
B.7,235,785
(11/048,634)
    
    US
    
    6/26/2007
(1/31/2005)
    
    Imaging device with multiple
fields of view incorporating
memory-based temperature
compensation of an uncooled
focal plane array
Hornback, Bert; Harwood, Doug;
Boyd, W. Eric; Carlson, Randy6,596,997
(09/921,525)
    
    US
    
    7/22/2003
(8/3/2001)
    
    Retro-reflector warm stop for
uncooled thermal imaging cameras
and method of using the same
Kaufman, Charles S.6,706,971
(10/142,557)
    
    US
    
    3/16/2004
(5/10/2002)
    
    Stackable microcircuit layer
formed from a plastic
encapsulated microcircuit
Albert, Douglas M.; Gann, Keith
D.7,174,627
(10/338,974)
    
    US
    
    2/13/2007
(1/9/2003)
    
    Method of fabricating known good
dies from packaged integrated
circuits
Gann, Keith D.6,560,109
(09/949,024)
    
    US
    
    5/6/2003
(9/7/2001)
    
    Stack of multilayer modules with
heat-focusing metal layer
Yamaguchi, James Satsuo; Pepe,
Angel Antonio; Ozguz, Volkan H.;
Camien, Andrew Nelson6,717,061
(09/949,512)
    
    US
    
    4/6/2004
(9/7/2001)
    
    Stacking of multilayer modules
Yamaguchi, James Satsuo; Pepe,
Angel Antonio; Ozguz, Volkan H.;
Camien, Andrew Nelson




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor6,734,370
(09/948,950)
    
    US
    
    5/11/2004
(9/7/2001)
    
    Multilayer modules with flexible
substrates
Yamaguchi, James Satsuo; Pepe,
Angel Antonio; Ozguz, Volkan H.;
Camien, Andrew Nelson7,127,807
(10/431,914)
    
    US
    
    10/31/2006
(5/7/2003)
    
    Process of manufacturing
multilayer modules
Yamaguchi, James Satsuo; Pepe,
Angel Antonio; Ozguz, Volkan H.;
Camien, Andrew Nelson6,797,537
(09/938,686)
    
    US
    
    9/28/2004
(10/30/2001)
    
    Method of making stackable
layers containing encapsulated
integrated circuit chips with
one or more overlaying
interconnect layers
Pepe, Angel Antonio; Yamaguchi,
James Satsuo6,784,547
(10/302,680)
    
    US
    
    8/31/2004
(11/21/2002)
    
    Stackable layers containing
encapsulated integrated circuit
chips with one or more overlying
interconnect layers
Pepe, Angel Antonio; Yamaguchi,
James Satsuo7,239,012
(10/951,990)
    
    US
    
    7/3/2007
(9/28/2004)
    
    Three-dimensional module
comprised of layers containing
IC chips with overlying
interconnect layers
Pepe, Angel; Yamaguchi, James6,806,559
(10/128,728)
    
    US
    
    10/19/2004
(4/22/2002)
    
    Method and apparatus for
connecting vertically stacked
integrated circuit chips
Gann, Keith D.; Albert, Douglas
M.6,912,862
(10/615,641)
    
    US
    
    7/5/2005
(7/8/2003)
    
    Cryopump piston position tracking
Sapir, Itzhak6,967,411
(10/360,244)
    
    US
    
    11/22/2005
(2/7/2003)
    
    Stackable layers containing ball
grid array packages
Eide, Floyd K.




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor7,242,082
(11/229,351)
    
    US
    
    6/10/2007
(9/15/2005)
    
    Stackable layer containing ball
grid array package
Eide, Floyd6,993,835
(10/726,888)
    
    US
    
    2/7/2006 (12/4/2003)
    
    Method for electrical
interconnection of angularly
disposed conductive patterns
Albert, Douglas Marice6,998,328
(10/701,783)
    
    US
    
    2/14/2006
(11/5/2003)
    
    Method for creating neo-wafers
from singulated integrated
circuit die and a device made
according to the method
Stern, Jonathan Michael7,417,323
(10/703,177)
    
    US
    
    (11/6/2003)
    
    Neo-wafer device and method
Sambo S. He7,198,965
(11/354,370)
    
    US
    
    4/3/2007
(2/14/2006)
    
    Method for making a neo-layer
comprising embedded discrete
components
He, Sambo7,180,579
(10/806,037)
    
    US
    
    2/20/2007
(3/22/2004)
    
    Three-dimensional imaging
processing module incorporating
stacked layers containing
microelectronic circuits
Ludwig, David E.; Kennedy, John
V.; Kleinhans, William; Liu,
Tina; Krutzik, Christian7,436,494
(11/706,724)
    
    US
    
    10/14/2008
(2/15/2007)
    
    Three-dimensional LADAR module
with alignment reference insert
circuitry
Ludwig, David E.; Kennedy, John
V.; Kleinhans, William; Liu,
Tina; Krutzik, Christian7,335,576
(11/197,828)
    
    US
    
    2/26/2008
(8/5/2005)
    
    Method for precision integrated
circuit die singulation using
differential etch rates
David, Ludwig; Yamaguchi, James;
Clark, Stuart; Boyd, W. Eric7,380,459
(11/654,292)
    
    US
    
    6/3/2008
(1/16/2007)
    
    Absolute pressure sensor
Sapir, Itzhak10/968,572
    
    US
    
    10/19/2004
    
    Vertically stacked pre-packaged
integrated circuit chips
Keith Gann; Douglas N. Albert




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor7,440,449
(10/960,712)
    
    US
    
    10/6/2004
    
    High speed switching module
comprised of stacked layers
incorporating T-connect
structures
John C. Carson; Volkan H. Orguz11/977,447
    
    US
    
    10/24/2007
    
    Wire bond method for angularly
disposed conductive pads and a
device made from the method
Randy Wayne Bindrup11/897,938
    
    US
    
    08/31/2007
    
    Field programmable gate array
utilizing dedicated memory
stacks in a vertical layer
format
Ozguz, Volkan; Carlson, Randolph
Stuart; Gann, Keith D.; Leon,
John P.; Boyd, W Eric11/825,643
    
    US
    
    7/7/2007
    
    Ball grid array package format
layers and structure
Keith Gann; W Eric Boyd11/807,671
    
    US
    
    5/30/2007
    
    Large Format Thermoelectic
Infrared Detector and a Method
of Fabrication
Ying Hsu11/731,154
    
    US
    
    3/31/2007
    
    Ball Grid Array Stack
Frank Mantz11/524,090
    
    US
    
    9/20/2006
    
    Stackable tier structure
comprising high density
feedthrough
Volkan Ozguz; Jonathan Stern11/511,117
    
    US
    
    8/26/2006
    
    MEMS cooling device
Itzhak Sapir11/499,403
    
    US
    
    8/4/2006
    
    High density interconnect
assembly comprising stacked
electronic module
John V. Kennedy11/441,908
    
    US
    
    5/26/2006
    
    Stackable tier structure
comprising prefabricated high
density feedthrough
Volkan Ozguz; Jonathan Stern11/429,468
    
    US
    
    5/5/2006
    
    Global positioning using
planetary constants
Sapir Itzhak




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor11/415,891
    
    US
    
    5/1/2006
    
    Low power electronic circuit
incorporating real time clock
Gary Gottlieb11/350,974
    
    US
    
    2/8/2006
    
    Stacked ball grid array package
module utilizing one or more
interposer layers
William E. Boyd; Daniel Michaels11/301,645
    
    US
    
    12/12/2005
    
    Cornerbond assembly comprising
three-dimensional electronic
modules
Albert Douglas11/259,683
    
    US
    
    10/25/2005
    
    Stacked microelectronic layer
and module with three-axis
channel T-connects
Keith D. Gann; W. Eric Boyd11/248,659
    
    US
    
    10/11/2005
    
    Anti-tamper module
Volkan H. Ozguz; John Leon10/178,390
    
    US
    
    6/24/2002
    
    Video event capture, storage and
processing method and apparatus
Randolph S. Carlson60/993,689
    
    US
    
    
    
    Chip scale vacuum pump
Itzhak Sapir11/150,712
    
    US
    
    6/10/2005
    
    Stackable semiconductor chip
layer comprising prefabricated
trench interconnect vias
W. Eric Boyd; Angel Pepe; James
Yamaguchi; Volkan Ozguz; Andrew
Camien; Douglas Albert11/062,507
    
    US
    
    2/22/2005
    
    BGA-scale stacks comprised of
layers containing integrated
circuit die and a method for
making the same
Gann Keith; William E. Boyd12/008,253
    
    US
    
    1/8/2008
    
    Microcombustion power system
Ying Hsu61/007,497
    
    US
    
    12/12/2007
    
    Forced vibration piezo generator
Itzhak Sapir




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorSE0570479
(SE92905662.0)
    
    SE
    
    10/10/2001
(1/29/1992)
    
    Hardware for electronic neural
network
Carson, John C.NL0570479
(NL92905662.0)
    
    NL
    
    10/10/2001
(1/29/1992)
    
    Hardware for electronic neural
network
Carson, John C.JP2005-507894
    
    JP
    
    1/16/2006
    
    Stackable layers containing ball
grid array packages
Inventorship not availableJP2006-286556
    
    JP
    
    10/20/2006
    
    Stackable tier structure
comprising high density
feedthrough
Volkan Ozguz; Jonathan SternJP2000-591490
    
    JP
    
    12/30/1999
    
    Neural processing module with
input architectures that make
maximal use of a weighted
synapse array
Carson, John C.; Saunders,
Christ H.JP3308265
(JP12-554175)
    
    JP
    
    6/10/1999
    
    IC stack utilizing flexible
circuits with BGA contacts
Eide, Floyd K.JP3511008
(JP12-553982)
    
    JP
    
    6/10/1999
    
    IC stack utilizing secondary
leadframes
Eide, Floyd K.JP3544974
(JP06-0502691)
    
    JP
    
    5/5/1993
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.GB0570479
(GB92905662.0)
    
    GB
    
    10/10/2001
(1/29/1992)
    
    Hardware for electronic neural
network
Carson, John C.GB1097467
(GB9992850.2)
    
    GB
    
    11/2/2006
(6/10/1993)
    
    IC stack utilizing secondary
leadframes
Eide, Floyd K.GB1596433
(GB04394026.1)
    
    GB
    
    1/2/2008 (5/12/2004)
    
    A method for creating neo-wafers
from singulated integrated
circuit die and a device made
according to the method Stern,
Jonathan Michael




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorGB0596075
(GB93911250.4)
    
    GB
    
    8/22/2001
(5/5/1993)
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.GB0683968
(GB94903352.6)
    
    GB
    
    10/24/2002
(12/1/1993)
    
    Module comprising IC memory
stack dedicated to and
structurally combined with an IC
microprocessor chip
Carson, John C.; Indin, Ronald
J.; Shanken, Stuart N.GB0695494
(GB94915397.7)
    
    GB
    
    2/24/2001
(4/19/1994)
    
    Electronic module comprising a
stack of IC chips
Carson, John C.; Some, Raphael R.GB0713609
(GB94925876.8)
    
    GB
    
    5/7/2003
(8/12/1994)
    
    Stack of IC chips as substitute
for single IC chip Ludwig, David
E.; Saunders, Christ H.; Some,
Raphael R.; Stuart, John J.GB067087
(GB94909418.9)
    
    GB
    
    (12/16/1993)
    
    Fabricating stacks of IC chips
by segmenting a larger stack
MINIHAN JOSEPH A; PEPE ANGEL AFR1097467
(FR99928570.2)
    
    FR
    
    11/2/2006
(6/10/1993)
    
    IC stack utilizing secondary
leadframes
Eide, Floyd K.FR1596433
(FR04394026.1)
    
    FR
    
    1/2/2008
(5/12/2004)
    
    A method for creating neo-wafers
from singulated integrated
circuit die and a device made
according to the method
Stern, Jonathan MichaelFR0596075
(FR93911250.4)
    
    FR
    
    8/22/2001
(5/5/1993)
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.FR0683968
(FR94903352.6)
    
    FR
    
    10/24/2002
(12/1/1993)
    
    Module comprising IC memory
stack dedicated to and
structurally combined with an IC
microprocessor chip
Carson, John C.; Indin, Ronald
J.; Shanken, Stuart N.FR0695494
(FR94915397.7)
    
    FR
    
    2/24/2001
(4/19/1994)
    
    Electronic module comprising a
stack of IC chips
Carson, John C.; Some, Raphael R.




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorFR0713609
(FR94925876.8)
    
    FR
    
    5/7/2003
(8/12/1994)
    
    Stack of IC chips as substitute
for single IC chip
Ludwig, David E.; Saunders,
Christ H.; Some, Raphael R.;
Stuart, John J.EP02705988.0
    
    EP
    
    1/25/2002
    
    A stackable microcircuit layer
formed from a plastic
encapsulated microcircuit and
method of making the same
Albert, Douglas M.; Gann, Keith
D.EP06255467.0
    
    EP
    
    10/24/2006
    
    Stackable tier structure
comprising high density
feedthrough
Volkan Ozguz; Jonathan SternEP99967712.3
    
    EP
    
    12/30/1999
    
    Neural processing module with
input architectures that make
maximal use of a weighted
synapse array
Carson, John C.; Saunders,
Christ H.EP99928570.2
    
    EP
    
    6/10/1993
    
    IC stack utilizing flexible
circuits with BGA contacts
Eide, Floyd K.EP02805694.3
    
    EP
    
    7/16/2002
    
    Wearable biomonitor with
flexible thinned integrated
circuit
Ogzuz, Volkhan H; Khashayar,
AbbasEP02789292.6
    
    EP
    
    10/25/2002
    
    Stackable layers containing
encapsulated integrated circuit
chips with one or more overlying
interconnect layers and a method
of making the same
Pepe, Angel Antonio; Yamaguchi,
James SatsuoEP02798173.7
    
    EP
    
    9/9/2002
    
    Stacking of multilayer modules 
Yamaguchi, James Satsuo; Pepe,
Angel Antonio; Ozguz, Volkan H.;
Camien, Andrew Nelson




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorEP95935157.8
    
    EP
    
    9/27/1995
    
    Infrared wireless communication
between electronic system
components
DeCaro, Robert; Saunders, Christ
H.; Maeding, DaleEP03721978.9
    
    EP
    
    4/22/2003
    
    Method and apparatus for
connecting vertically stacked
integrated circuit chips
Gann, Keith D.; Albert, Douglas
M.DE69232116
(DE69232116)
    
    DE
    
    10/10/2001
(1/29/1992)
    
    Hardware for electronic neural
network
Carson, John C.DE69330630
(DE69330630)
    
    DE
    
    8/22/2001
(5/5/1993)
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.DE69426695
(DE6942669.5)
    
    DE
    
    2/24/2001
(4/19/1994)
    
    Electronic module comprising a
stack of IC chips
Carson, John C.; Some, Raphael R.DE602004011025
(DE602004011025)
    
    DE
    
    1/2/2008
(5/12/2004)
    
    A method for creating neo-wafers
from singulated integrated
circuit die and a device made
according to the method
Stern, Jonathan MichaelPCT/US06/039915
    
    WO
    
    8/26/2006
    
    MEMS cooling device
Itzhak Sapir4,814,629
(07/107352)
    
    US
    
    3/21/1989
(10/13/1987)
    
    Pixel displacement by series-parallel analog switching
Arnold, Jack L.11/825,643
    
    US
    
    7/7/2007
    
    Ball grid array package format
layers and structure
Keith GannEP06738029.5
    
    EP
    
    3/10/2006
    
    Method for making a neo-layer
comprising embedded discrete
components
Sambo S. He




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorJP2000-519921
    
    JP
    
    11/10/1998
    
    Method for thinning
semiconductor wafers with
circuits and wafers made by the
same
Inventorship not availableJP2004-72804
    
    JP
    
    3/15/2004
    
    Stackable layer, mini stack, and
laminated electronic module
Volkan OzguzEP06735419.1
    
    EP
    
    2/14/2006
    
    Stacked ball grid array package
module utilizing one or more
interposer layers
William E. Boyd5,635,010
    
    US
    
    4/14/1995
    
    Dry adhesive joining of layers
of electronic devices
Angel A. Pepe6,731,121
    
    US
    
    10/16/2000
    
    Highly configurable capacitive
transducer interface circuit
Christ Ying Hsu6,513,380
    
    US
    
    6/19/2001
    
    Mems sensor with single central
anchor and motion-limiting
connection geometry
John William Reeds III6,715,352
    
    US
    
    6/26/2001
    
    Method of designing a flexure
system for tuning the modal
response of a decoupled
micromachined gyroscope and a
gyroscoped designed according to
the method
Michael J. Tracy6,370,937
    
    US
    
    3/19/2001
    
    Method of canceling quadrature
error in an angular rate sensor
Ying Wen Hsu




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorJP2664754
    
    JP
    
    1/4/1998
    
    High density electronic package
comprising stacked sub-modules
Tiong C. GoJP2001-533437
    
    JP
    
    10/16/2000
    
    Highly configurable capacitive
transducer interface circuit
Christ Ying HsuEP02744453.8
    
    EP
    
    6/18/2002
    
    Mems sensor with single central
anchor and motion-limiting
connection geometry
John William Reeds IIIEP02746710.9
    
    EP
    
    6/18/2002
    
    Method of designing a flexure
system for tuning the modal
response of a decoupled
micromachined gyroscope and a
gyroscoped designed according to
the method
Michael J. TracyJP2002-562134
    
    JP
    
    1/25/2002
    
    A stackable microcircuit layer
formed from a plastic
encapsulated microcircuit and
method of making the same12/287,691
    
    US
    
    10/10/2008
    
    Three dimensional LADAR module
with alignment reference insert
circuitry comprising high
density interconnect structure
John Kennedy; David Ludwig;
Christian KrutzikEP03818224.2
    
    EP
    
    8/8/2003
    
    Stackable layers containing ball
grid array packages
Eide, Floyd K.




---



##### 



Exhibit B, revised
 ASSIGNMENT OF PATENT RIGHTS
  Assignor   Assignee   Patent Rights 
  Patents 
 Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor5,235,672
(07/651,477)
    
    US
    
    8/10/1993
(2/6/1991)
    
    Hardware for electronic neural
network
Carson, John C.6,389,404
(09/223,476)
    
    US
    
    5/14/2002
(12/30/1998)
    
    Neural processing module with
input architectures that make
maximal use of a weighted
synapse array
Carson, John C.; Saunders,
Christ H.6,650,704
(09/427,384)
    
    US
    
    11/18/2003
(10/25/1999)
    
    Method of producing a high
quality, high resolution image
from a sequence of low quality,
low resolution images that are
undersampled and subject to
jitter
Carlson, Randolph S.; Arnold,
Jack L.; Feldmus, Valentine G.6,829,237
(09/973,857)
    
    US
    
    12/7/2004 (10/9/2001)
    
    High speed multi-stage switching
network formed from stacked
switching layers Carson, John C.;
Ozguz, Volkan H.7,082,591
(10/346,363)
    
    US
    
    7/25/2006
(1/17/2003)
    
    Method for effectively embedding
various integrated circuits
within field programmable gate
arrays
Carlson, Randolph S.6,856,167
(10/347,038)
    
    US
    
    2/15/2005
(1/17/2003)
    
    Field programmable gate array
with a variably wide word width
memory
Ozguz, Volkan H.; Carlson,
Randolph S.; Gann, Keith D.;
Leon, John P.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor7,265,579
(11/037,490)
    
    US
    
    9/4/2007
(1/18/2005)
    
    Field programmable gate array
incorporating dedicated memory
stacks
Carlson, Randolph Stuart; Ozguz,
Volkan; Gann, Keith D.; Leon,
John P.5,508,836
(08/305,066)
    
    US
    
    4/16/1996 (9/13/1994)
    
    Infrared wireless communication
between electronic system
components
DeCaro, Robert; Saunders, Christ
H.; Maeding, Dale5,635,705
(08/526,415)
    
    US
    
    6/3/1997
(9/11/1995)
    
    Sensing and selecting observed
events for signal processing
Saunders, Christ H.6,195,268
(09/031,435)
    
    US
    
    2/27/2001
(2/26/1998)
    
    Stacking layers containing
enclosed IC chips
Eide, Floyd K.5,045,685
(07/534,969)
    
    US
    
    9/3/1991
(6/6/1990)
    
    Analog to digital conversion on
multiple channel IC chips
Wall, Llewellyn E.5,104,820
(07/720,025)
    
    US
    
    4/14/1992
(6/24/1991)
    
    Method of fabricating electronic
circuitry unit containing
stacked IC layers having lead
rerouting
Go, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.5,279,991
(07/996,794)
    
    US
    
    1/18/1994
(12/24/1992)
    
    Method for fabricating stacks of
IC chips by segmenting a larger
stack
Minahan, Joseph A.; Pepe, Angel
A.5,432,318
(08/178,923)
    
    US
    
    7/11/1995
(1/7/1994)
    
    Apparatus for segmenting stacked
IC chips
Minahan, Joseph A.5,304,790
(07/956,914)
    
    US
    
    4/19/1994
(10/5/1992)
    
    Apparatus and system for
controllably varying image
resolution to reduce data output
Arnold, Jack5,347,428
(07/985,837)
    
    US
    
    9/13/1994
(12/3/1992)
    
    Module comprising IC memory
stack dedicated to and
structurally combined with an IC
microprocessor chip
Carson, John C.; Indin, Ronald
J.; Shanken, Stuart N.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor5,406,701
(08/120,675)
    
    US
    
    4/18/1995
(9/13/1993)
    
    Fabrication of dense parallel
solder bump connections
Pepe, Angel A.; Reinker, David
M.; Minahan, Joseph A.5,424,920
(08/232,739)
    
    US
    
    6/13/1995
(4/25/1994)
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.5,432,729
(08/255,465)
    
    US
    
    7/11/1995
(6/8/1994)
    
    Electronic module comprising a
stack of IC chips each
interacting with an IC chip
secured to the stack
Carson, John C.; Some, Raphael R.5,581,498
(08/326,645)
    
    US
    
    12/3/1996
(10/20/1994)
    
    Stack of IC chips in lieu of
single IC chip
Ludwig, David E.; Saunders,
Christ H.; Some, Raphael R.;
Stuart, John J.5,688,721
(08/62,2671)
    
    US
    
    11/18/1997
(3/26/1996)
    
    3D stack of IC chips having
leads reached by vias through
passivation covering access
plane
Johnson, Tony K.5,953,588
(08/777,747)
    
    US
    
    9/14/1999
(12/21/1996)
    
    Stackable layers containing
encapsulated IC chips
Camien, Andrew N; Yamaguchi,
James S.6,072,234
(09/316,740)
    
    US
    
    6/6/2000
(5/21/1999)
    
    Stack of equal layer neo-chips
containing encapsulated IC chips
of different sizes
Camien, Andrew N.; Yamaguchi,
James S.5,955,668
(09/166,458)
    
    US
    
    9/21/1999
(10/5/1998)
    
    Multi-element micro gyro
Hsu, Ying W.; Reeds, III, John
W.; Saunders, Christ H.6,089,089
(09/301,847)
    
    US
    
    7/18/2000
(4/29/1999)
    
    Multi-element micro gyro
Hsu, Ying W.6,578,420
(09/604,782)
    
    US
    
    6/17/2003
(6/26/2000)
    
    Multi-axis micro gyro structure
Hsu, Ying Wen6,014,316
(09/095,416)
    
    US
    
    1/11/2000
(6/10/1998)
    
    IC stack utilizing BGA contacts
Eide, Floyd K.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor6,028,352
(09/095,415)
    
    US
    
    2/22/2000
(6/10/1998)
    
    IC stack utilizing secondary
lead frames
Eide, Floyd K.6,117,704
(09/282,704)
    
    US
    
    9/12/2000
(3/31/1999)
    
    Stackable layers containing
encapsulated chips
Yamaguchi, James S.; Ozguz,
Volkan H.; Camien, Andrew N.6,476,392
(09/853,819)
    
    US
    
    11/5/2002
(5/11/2001)
    
    Method and apparatus for
temperature compensation of an
uncooled focal plane array
Kaufman, Charles S.; Carson,
Randolph S.; Hornback, William
B.6,891,160
(10/281,393)
    
    US
    
    5/10/2005
(10/25/2002)
    
    Method and apparatus for
temperature compensation of an
uncooled focal plane array
Kaufman, Charles S.; Carson,
Randolph S.; Hornback, William
B.7,235,785
(11/048,634)
    
    US
    
    6/26/2007
(1/31/2005)
    
    Imaging device with multiple
fields of view incorporating
memory-based temperature
compensation of an uncooled
focal plane array
Hornback, Bert; Harwood, Doug;
Boyd, W. Eric; Carlson, Randy6,596,997
(09/921,525)
    
    US
    
    7/22/2003
(8/3/2001)
    
    Retro-reflector warm stop for
uncooled thermal imaging cameras
and method of using the same
Kaufman, Charles S.6,706,971
(10/142,557)
    
    US
    
    3/16/2004
(5/10/2002)
    
    Stackable microcircuit layer
formed from a plastic
encapsulated microcircuit
Albert, Douglas M.; Gann, Keith
D.7,174,627
(10/338,974)
    
    US
    
    2/13/2007
(1/9/2003)
    
    Method of fabricating known good
dies from packaged integrated
circuits
Gann, Keith D.6,560,109
(09/949,024)
    
    US
    
    5/6/2003
(9/7/2001)
    
    Stack of multilayer modules with
heat-focusing metal layer
Yamaguchi, James Satsuo; Pepe,
Angel Antonio; Ozguz, Volkan H.;
Camien, Andrew Nelson




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor6,717,061
(09/949,512)
    
    US
    
    4/6/2004
(9/7/2001)
    
    Stacking of multilayer modules
Yamaguchi, James Satsuo; Pepe,
Angel Antonio; Ozguz, Volkan H.;
Camien, Andrew Nelson6,734,370
(09/948,950)
    
    US
    
    5/11/2004
(9/7/2001)
    
    Multilayer modules with flexible
substrates
Yamaguchi, James Satsuo; Pepe,
Angel Antonio; Ozguz, Volkan H.;
Camien, Andrew Nelson7,127,807
(10/431,914)
    
    US
    
    10/31/2006
(5/7/2003)
    
    Process of manufacturing
multilayer modules
Yamaguchi, James Satsuo; Pepe,
Angel Antonio; Ozguz, Volkan H.;
Camien, Andrew Nelson6,797,537
(09/938,686)
    
    US
    
    9/28/2004
(10/30/2001)
    
    Method of making stackable
layers containing encapsulated
integrated circuit chips with
one or more overlaying
interconnect layers
Pepe, Angel Antonio; Yamaguchi,
James Satsuo6,784,547
(10/302,680)
    
    US
    
    8/31/2004
(11/21/2002)
    
    Stackable layers containing
encapsulated integrated circuit
chips with one or more overlying
interconnect layers
Pepe, Angel Antonio; Yamaguchi,
James Satsuo7,239,012
(10/951,990)
    
    US
    
    7/3/2007
(9/28/2004)
    
    Three-dimensional module
comprised of layers containing
IC chips with overlying
interconnect layers
Pepe, Angel; Yamaguchi, James6,806,559
(10/128,728)
    
    US
    
    10/19/2004
(4/22/2002)
    
    Method and apparatus for
connecting vertically stacked
integrated circuit chips
Gann, Keith D.; Albert, Douglas
M.6,912,862
(10/615,641)
    
    US
    
    7/5/2005
(7/8/2003)
    
    Cryopump piston position tracking
Sapir, Itzhak6,967,411
(10/360,244)
    
    US
    
    11/22/2005
(2/7/2003)
    
    Stackable layers containing ball
grid array packages
Eide, Floyd K.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor7,242,082
(11/229,351)
    
    US
    
    6/10/2007
(9/15/2005)
    
    Stackable layer containing ball
grid array package
Eide, Floyd6,993,835
(10/726,888)
    
    US
    
    2/7/2006 (12/4/2003)
    
    Method for electrical
interconnection of angularly
disposed conductive patterns
Albert, Douglas Marice6,998,328
(10/701,783)
    
    US
    
    2/14/2006
(11/5/2003)
    
    Method for creating neo-wafers
from singulated integrated
circuit die and a device made
according to the method
Stern, Jonathan Michael7,417,323
(10/703,177)
    
    US
    
    (11/6/2003)
    
    Neo-wafer device and method
Sambo S. He7,198,965
(11/354,370)
    
    US
    
    4/3/2007
(2/14/2006)
    
    Method for making a neo-layer
comprising embedded discrete
components
He, Sambo7,180,579
(10/806,037)
    
    US
    
    2/20/2007
(3/22/2004)
    
    Three-dimensional imaging
processing module incorporating
stacked layers containing
microelectronic circuits
Ludwig, David E.; Kennedy, John
V.; Kleinhans, William; Liu,
Tina; Krutzik, Christian7,436,494
(11/706,724)
    
    US
    
    10/14/2008
(2/15/2007)
    
    Three-dimensional LADAR module
with alignment reference insert
circuitry
Ludwig, David E.; Kennedy, John
V.; Kleinhans, William; Liu,
Tina; Krutzik, Christian7,335,576
(11/197,828)
    
    US
    
    2/26/2008
(8/5/2005)
    
    Method for precision integrated
circuit die singulation using
differential etch rates
David, Ludwig; Yamaguchi, James;
Clark, Stuart; Boyd, W. Eric7,380,459
(11/654,292)
    
    US
    
    6/3/2008
(1/16/2007)
    
    Absolute pressure sensor
Sapir, Itzhak10/968,572
    
    US
    
    10/19/2004
    
    Vertically stacked pre-packaged
integrated circuit chips
Keith Gann; Douglas N. Albert




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor7,440,449
(10/960,712)
    
    US
    
    10/6/2004
    
    High speed switching module
comprised of stacked layers
incorporating T-connect
structures
John C. Carson; Volkan H. Orguz11/977,447
    
    US
    
    10/24/2007
    
    Wire bond method for angularly
disposed conductive pads and a
device made from the method
Randy Wayne Bindrup11/897,938
    
    US
    
    08/31/2007
    
    Field programmable gate array
utilizing dedicated memory
stacks in a vertical layer
format
Ozguz, Volkan; Carlson, Randolph
Stuart; Gann, Keith D.; Leon,
John P.; Boyd, W Eric11/825,643
    
    US
    
    7/7/2007
    
    Ball grid array package format
layers and structure
Keith Gann; W Eric Boyd11/807,671
    
    US
    
    5/30/2007
    
    Large Format Thermoelectic
Infrared Detector and a Method
of Fabrication
Ying Hsu11/731,154
    
    US
    
    3/31/2007
    
    Ball Grid Array Stack
Frank Mantz11/524,090
    
    US
    
    9/20/2006
    
    Stackable tier structure
comprising high density
feedthrough
Volkan Ozguz; Jonathan Stern11/511,117
    
    US
    
    8/26/2006
    
    MEMS cooling device
Itzhak Sapir11/499,403
    
    US
    
    8/4/2006
    
    High density interconnect
assembly comprising stacked
electronic module
John V. Kennedy11/441,908
    
    US
    
    5/26/2006
    
    Stackable tier structure
comprising prefabricated high
density feedthrough
Volkan Ozguz; Jonathan Stern11/429,468
    
    US
    
    5/5/2006
    
    Global positioning using
planetary constants
Sapir Itzhak




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor11/415,891
    
    US
    
    5/1/2006
    
    Low power electronic circuit
incorporating real time clock
Gary Gottlieb11/350,974
    
    US
    
    2/8/2006
    
    Stacked ball grid array package
module utilizing one or more
interposer layers
William E. Boyd; Daniel Michaels11/301,645
    
    US
    
    12/12/2005
    
    Cornerbond assembly comprising
three-dimensional electronic
modules
Albert Douglas11/259,683
    
    US
    
    10/25/2005
    
    Stacked microelectronic layer
and module with three-axis
channel T-connects
Keith D. Gann; W. Eric Boyd11/248,659
    
    US
    
    10/11/2005
    
    Anti-tamper module
Volkan H. Ozguz; John Leon10/178,390
    
    US
    
    6/24/2002
    
    Video event capture, storage and
processing method and apparatus
Randolph S. Carlson60/993,689
    
    US
    
    
    
    Chip scale vacuum pump
Itzhak Sapir11/150,712
    
    US
    
    6/10/2005
    
    Stackable semiconductor chip
layer comprising prefabricated
trench interconnect vias
W. Eric Boyd; Angel Pepe; James
Yamaguchi; Volkan Ozguz; Andrew
Camien; Douglas Albert11/062,507
    
    US
    
    2/22/2005
    
    BGA-scale stacks comprised of
layers containing integrated
circuit die and a method for
making the same
Gann Keith; William E. Boyd12/008,253
    
    US
    
    1/8/2008
    
    Microcombustion power system
Ying Hsu61/007,497
    
    US
    
    12/12/2007
    
    Forced vibration piezo generator
Itzhak SapirSE0570479
(SE92905662.0)
    
    SE
    
    10/10/2001
(1/29/1992)
    
    Hardware for electronic neural
network
Carson, John C.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorNL0570479
(NL92905662.0)
    
    NL
    
    10/10/2001
(1/29/1992)
    
    Hardware for electronic neural
network
Carson, John C.JP2005-507894
    
    JP
    
    1/16/2006
    
    Stackable layers containing ball
grid array packages
Inventorship not availableJP2006-286556
    
    JP
    
    10/20/2006
    
    Stackable tier structure
comprising high density
feedthrough
Volkan Ozguz; Jonathan SternJP2000-591490
    
    JP
    
    12/30/1999
    
    Neural processing module with
input architectures that make
maximal use of a weighted
synapse array
Carson, John C.; Saunders,
Christ H.JP3308265
(JP12-554175)
    
    JP
    
    6/10/1999
    
    IC stack utilizing flexible
circuits with BGA contacts
Eide, Floyd K.JP3511008
(JP12-553982)
    
    JP
    
    6/10/1999
    
    IC stack utilizing secondary
leadframes
Eide, Floyd K.JP3544974
(JP06-0502691)
    
    JP
    
    5/5/1993
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.GB0570479
(GB92905662.0)
    
    GB
    
    10/10/2001
(1/29/1992)
    
    Hardware for electronic neural
network
Carson, John C.GB1097467
(GB9992850.2)
    
    GB
    
    11/2/2006
(6/10/1993)
    
    IC stack utilizing secondary
leadframes
Eide, Floyd K.GB1596433
(GB04394026.1)
    
    GB
    
    1/2/2008 (5/12/2004)
    
    A method for creating neo-wafers
from singulated integrated
circuit die and a device made
according to the method Stern,
Jonathan MichaelGB0596075
(GB93911250.4)
    
    GB
    
    8/22/2001
(5/5/1993)
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorGB0683968
(GB94903352.6)
    
    GB
    
    10/24/2002
(12/1/1993)
    
    Module comprising IC memory
stack dedicated to and
structurally combined with an IC
microprocessor chip
Carson, John C.; Indin, Ronald
J.; Shanken, Stuart N.GB0695494
(GB94915397.7)
    
    GB
    
    2/24/2001
(4/19/1994)
    
    Electronic module comprising a
stack of IC chips
Carson, John C.; Some, Raphael R.GB0713609
(GB94925876.8)
    
    GB
    
    5/7/2003
(8/12/1994)
    
    Stack of IC chips as substitute
for single IC chip Ludwig, David
E.; Saunders, Christ H.; Some,
Raphael R.; Stuart, John J.GB067087
(GB94909418.9)
    
    GB
    
    (12/16/1993)
    
    Fabricating stacks of IC chips
by segmenting a larger stack
MINIHAN JOSEPH A; PEPE ANGEL AFR1097467
(FR99928570.2)
    
    FR
    
    11/2/2006
(6/10/1993)
    
    IC stack utilizing secondary
leadframes
Eide, Floyd K.FR1596433
(FR04394026.1)
    
    FR
    
    1/2/2008
(5/12/2004)
    
    A method for creating neo-wafers
from singulated integrated
circuit die and a device made
according to the method
Stern, Jonathan MichaelFR0596075
(FR93911250.4)
    
    FR
    
    8/22/2001
(5/5/1993)
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.FR0683968
(FR94903352.6)
    
    FR
    
    10/24/2002
(12/1/1993)
    
    Module comprising IC memory
stack dedicated to and
structurally combined with an IC
microprocessor chip
Carson, John C.; Indin, Ronald
J.; Shanken, Stuart N.FR0695494
(FR94915397.7)
    
    FR
    
    2/24/2001
(4/19/1994)
    
    Electronic module comprising a
stack of IC chips
Carson, John C.; Some, Raphael R.FR0713609
(FR94925876.8)
    
    FR
    
    5/7/2003
(8/12/1994)
    
    Stack of IC chips as substitute
for single IC chip
Ludwig, David E.; Saunders,
Christ H.; Some, Raphael R.;
Stuart, John J.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorEP02705988.0
    
    EP
    
    1/25/2002
    
    A stackable microcircuit layer
formed from a plastic
encapsulated microcircuit and
method of making the same
Albert, Douglas M.; Gann, Keith
D.EP06255467.0
    
    EP
    
    10/24/2006
    
    Stackable tier structure
comprising high density
feedthrough
Volkan Ozguz; Jonathan SternEP99967712.3
    
    EP
    
    12/30/1999
    
    Neural processing module with
input architectures that make
maximal use of a weighted
synapse array
Carson, John C.; Saunders,
Christ H.EP99928570.2
    
    EP
    
    6/10/1993
    
    IC stack utilizing flexible
circuits with BGA contacts
Eide, Floyd K.EP02805694.3
    
    EP
    
    7/16/2002
    
    Wearable biomonitor with
flexible thinned integrated
circuit
Ogzuz, Volkhan H; Khashayar,
AbbasEP02789292.6
    
    EP
    
    10/25/2002
    
    Stackable layers containing
encapsulated integrated circuit
chips with one or more overlying
interconnect layers and a method
of making the same
Pepe, Angel Antonio; Yamaguchi,
James SatsuoEP02798173.7
    
    EP
    
    9/9/2002
    
    Stacking of multilayer modules
Yamaguchi, James Satsuo; Pepe,
Angel Antonio; Ozguz, Volkan H.;
Camien, Andrew NelsonEP95935157.8
    
    EP
    
    9/27/1995
    
    Infrared wireless communication
between electronic system
components
DeCaro, Robert; Saunders, Christ
H.; Maeding, DaleEP03721978.9
    
    EP
    
    4/22/2003
    
    Method and apparatus for
connecting vertically stacked
integrated circuit chips
Gann, Keith D.; Albert, Douglas
M.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorDE69232116
(DE69232116)
    
    DE
    
    10/10/2001
(1/29/1992)
    
    Hardware for electronic neural
network
Carson, John C.DE69330630
(DE69330630)
    
    DE
    
    8/22/2001
(5/5/1993)
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.DE69426695
(DE6942669.5)
    
    DE
    
    2/24/2001
(4/19/1994)
    
    Electronic module comprising a
stack of IC chips
Carson, John C.; Some, Raphael R.DE602004011025
(DE602004011025)
    
    DE
    
    1/2/2008
(5/12/2004)
    
    A method for creating neo-wafers
from singulated integrated
circuit die and a device made
according to the method
Stern, Jonathan MichaelPCT/US06/039915
    
    WO
    
    8/26/2006
    
    MEMS cooling device
Itzhak Sapir4,814,629
(07/107352)
    
    US
    
    3/21/1989
(10/13/1987)
    
    Pixel displacement by series-
parallel analog switching
Arnold, Jack L.11/825,643
    
    US
    
    7/7/2007
    
    Ball grid array package format
layers and structure
Keith GannEP06738029.5
    
    EP
    
    3/10/2006
    
    Method for making a neo-layer
comprising embedded discrete
components
Sambo S. HeJP2000-519921
    
    JP
    
    11/10/1998
    
    Method for thinning
semiconductor wafers with
circuits and wafers made by the
same
Inventorship not availableJP2004-72804
    
    JP
    
    3/15/2004
    
    Stackable layer, mini stack, and
laminated electronic module
Volkan OzguzEP06735419.1
    
    EP
    
    2/14/2006
    
    Stacked ball grid array package
module utilizing one or more
interposer layers

William E. Boyd5,635,010
    
    US
    
    4/14/1995
    
    Dry adhesive joining of layers
of electronic devices
Angel A. Pepe6,731,121
    
    US
    
    10/16/2000
    
    Highly configurable capacitive
transducer interface circuit
Christ Ying Hsu




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor6,513,380
    
    US
    
    6/19/2001
    
    Mems sensor with single central
anchor and motion-limiting
connection geometry
John William Reeds III6,715,352
    
    US
    
    6/26/2001
    
    Method of designing a flexure
system for tuning the modal
response of a decoupled
micromachined gyroscope and a
gyroscoped designed according to
the method
Michael J. Tracy6,370,937
    
    US
    
    3/19/2001
    
    Method of canceling quadrature
error in an angular rate sensor

Ying Wen HsuJP2664754
    
    JP
    
    1/4/1998
    
    High density electronic package
comprising stacked sub-modules
Tiong C. GoJP2001-533437
    
    JP
    
    10/16/2000
    
    Highly configurable capacitive
transducer interface circuit

Christ Ying HsuEP02744453.8
    
    EP
    
    6/18/2002
    
    Mems sensor with single central
anchor and motion-limiting
connection geometry
John William Reeds IIIEP02746710.9
    
    EP
    
    6/18/2002
    
    Method of designing a flexure
system for tuning the modal
response of a decoupled
micromachined gyroscope and a
gyroscoped designed according to
the method
Michael J. TracyJP2002-562134
    
    JP
    
    1/25/2002
    
    A stackable microcircuit layer
formed from a plastic
encapsulated microcircuit and
method of making the same12/287,691
    
    US
    
    10/10/2008
    
    Three dimensional LADAR module
with alignment reference insert
circuitry comprising high
density interconnect structure
John Kennedy; David Ludwig;
Christian KrutzikEP03818224.2
    
    EP
    
    8/8/2003
    
    Stackable layers containing ball
grid array packages
Eide, Floyd K.




---



##### 








---



##### 



Costa Mesa,
California March 16, 2009
 ASSIGNOR:

Irvine Sensors CorporationBy:
    /s/ John J. Stuart, Jr.Name:
    John J. Stuart, Jr.Title:
    Sr. VP & Chief Financial Officer(Signature MUST be attested) ATTESTATION OF SIGNATURE PURSUANT TO 28 U.S.C. § 1746
 John J. Stuart, Jr




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##### 



John J. Stuart, Jr
 John J. Stuart, Jr
 EXECUTED on 16 March, 2009 (date)/s/ John C. CarsonPrint name:     John C. Carson




---



##### 



Exhibit C, revised
 ASSIGNMENT OF RIGHTS IN CERTAIN ASSETS
  Assignor   Assignee   Certain
Assets 
 Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorPCT/US00/029448
    
    WO
    
    10/25/2000
    
    SYSTEM AND METHODS FOR PRODUCING HIGH
RESOLUTION IMAGES FROM A VIDEO
SEQUENCE OF LOWER RESOLUTION IMAGES
CARLSON RANDOLPH S; ARNOLD JACK L;
FELDMUS VALENTIN GPCT/US92/005348
    
    WO
    
    6/24/1992
    
    Fabricating electronic circuitry unit
containing stacked IC layers having
lead rerouting
Go, Tiong C.(deceased,); Minahan,
Joseph A.; Shanken, Stuart N.PCT/US03/004462
    
    WO
    
    5/5/1993
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.PCT/US99/013171
    
    WO
    
    6/10/1999
    
    IC stack utilizing flexible circuits
with BGA contacts
Eide, Floyd K.PCT/US06/008920
    
    WO
    
    3/10/2006
    
    Method for making a neo-layer
comprising embedded discrete
components
He, SamboPCT/US01/031583
    
    WO
    
    10/9/2001
    
    High speed switching module comprised
of stacked layers incorporating
T-connect structures
John C. Carson; Volkan H. OrguzPCT/US02/002276
    
    WO
    
    1/25/2002
    
    A stackable microcircuit layer formed
from a plastic encapsulated
microcircuit and method of making the
same
Albert, Douglas M.; Gann, Keith D.PCT/US02/006848
    
    WO
    
    3/4/2002
    
    Retro-reflector warm stop for
uncooled thermal imaging cameras and
method of using the same
Kaufman, Charles S.




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorPCT/US02/022617
    
    WO
    
    7/16/2002
    
    Wearable biomonitor with flexible
thinned integrated circuit
Ogzuz, Volkhan H; Khashayar, AbbasPCT/US02/028628
    
    WO
    
    9/9/2002
    
    Stacking of multilayer modules
Yamaguchi, James Satsuo; Pepe, Angel
Antonio; Ozguz, Volkan H.; Camien,
Andrew NelsonPCT/US02/034339
    
    WO
    
    10/25/2002
    
    Stackable layers containing
encapsulated integrated circuit chips
with one or more overlying
interconnect layers and a method of
making the same
Pepe, Angel Antonio; Yamaguchi, James
SatsuoPCT/US02/19779
    
    WO
    
    6/24/2002
    
    Video event capture, storage and
processing method and apparatus
Randolph S. CarlsonPCT/US03/009190
    
    WO
    
    9/27/1993
    
    Fabrication of dense parallel solder
bump connections
Pepe, Angel A.; Reinker, David M.;
Minahan, Joseph A.PCT/US03/013569
    
    WO
    
    4/22/2003
    
    Method and apparatus for connecting
vertically stacked integrated circuit
chips
Gann, Keith D.; Albert, Douglas M.PCT/US03/024706
    
    WO
    
    08/08/2003
    
    Stackable layers containing ball grid
array packages
Eide, Floyd K.PCT/US83/01142
    
    WO
    
    7/25/1983
    
    Multiplexer circuitry for high
density analog signalsPCT/US88/003084
    
    WO
    
    9/8/1988
    
    Bonding of aligned conductive bumps
on adjacent surfaces
Go, Tiong C.PCT/US92/000780
    
    WO
    
    1/29/1992
    
    Hardware for electronic neural network
Carson, John C.PCT/US92/003705
    
    WO
    
    6/28/1990
    
    Fabricating electronic circuitry unit
containing stacked IC layers having
lead rerouting
Go, Tiong C.(deceased,); Minahan,
Joseph A.; Shanken, Stuart N.




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorPCT/US93/009470
    
    WO
    
    10/5/1993
    
    Apparatus and system for controllably
varying image resolution to reduce
data output
Arnold, JackPCT/US93/011601
    
    WO
    
    12/1/1993
    
    Module comprising IC memory stack
dedicated to and structurally
combined with an IC microprocessor
chip
Carson, John C.; Indin, Ronald J.;
Shanken, Stuart N.PCT/US93/012268
    
    WO
    
    12/16/1993
    
    Fabricating stacks of IC chips by
segmenting a larger stack
MINIHAN JOSEPH A; PEPE ANGEL APCT/US94/004322
    
    WO
    
    4/19/1994
    
    Electronic module comprising a stack
of IC chips
Carson, John C.; Some, Raphael R.PCT/US94/009186
    
    WO
    
    8/12/1994
    
    Stack of IC chips as substitute for
single IC chip
Ludwig, David E.; Saunders, Christ
H.; Some, Raphael R.; Stuart, John J.PCT/US95/002851
    
    WO
    
    3/7/1995
    
    3D stack of IC chips having leads
reached by vias through passivation
covering access plane
Johnson, Tony K.PCT/US95/012378
    
    WO
    
    9/27/1995
    
    Infrared wireless communication
between electronic system components
DeCaro, Robert; Saunders, Christ H.;
Maeding, DalePCT/US96/000746
    
    WO
    
    1/22/1996
    
    Stackable modules and multimodular
assemblies
Carson, John C.; DeCaro, Robert E.;
Hsu, Ying; Miyake, Michael K.PCT/US96/014610
    
    WO
    
    9/11/1996
    
    SENSING AND SELECTING OBSERVED EVENTS
FOR SIGNAL PROCESSING
SAUNDERS CHRIST HPCT/US98/021798
    
    WO
    
    10/14/1998
    
    Multi-element micro gyro
Hsu, Ying WenPCT/US98/023929
    
    WO
    
    11/10/1998
    
    Method for thinning semiconductor
wafers with circuits and wafers made
by the same
Albert, Douglas; Ogzuz Volkhan H




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorPCT/US99/001734
    
    WO
    
    3/23/1990
    
    Analog to digital conversion
incorporated in Z-technology module
Wall, Llewellyn E.PCT/US99/004211
    
    WO
    
    2/25/1999
    
    STACKING LAYERS CONTAINING ENCLOSED
IC CHIPS
EIDE FLOYDPCT/US99/031124
    
    WO
    
    12/30/1999
    
    Neural processing module with input
architectures that make maximal use
of a weighted synapse array
Carson, John C.; Saunders, Christ H.07/329,003
    
    US
    
    3/27/1989
    
    Analog to digital conversion on
multiple channel IC chips
Wall, Llewellyn E.07/377,241
    
    US
    
    7/7/1989
    
    Inventorship not available07/884,719
    
    US
    
    5/15/1992
    
    Method for fabricating stacks of IC
chips by segmenting a larger stack
Minahan, Joseph A.; Pepe, Angel A.07/884660
    
    US
    
    5/15/1992
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.07/955461
    
    US
    
    10/2/1992
    
    Fabrication of dense parallel solder
bump connections
Joseph Minahan08/052,475
    
    US
    
    4/23/1993
    
    Electronic module comprising a stack
of IC chips each interacting with an
IC chip secured to the stack
face Carson, John C.; Some, Raphael R.08/106,909
    
    US
    
    8/13/1993
    
    Inventorship not available08/213,149
    
    US
    
    3/15/1994
    
    3D stack of IC chips having leads
reached by vias through passivation
covering access plane
Johnson, Tony K.08/870,812
    
    US
    
    6/6/1997
    
    Multi-element micro gyro
Hsu, Ying W.; Reeds, III, John W.;
Saunders, Christ H.08/943,305
    
    US
    
    10/14/1997
    
    Multi-element micro gyro
Hsu, Ying W.; Reeds, III, John W.;
Saunders, Christ H.




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor09/190,378
    
    US
    
    11/10/1998
    
    Method for thinning semiconductor
wafers with circuits and wafers made
by the same
Albert, Douglas09/770,864
    
    US
    
    1/26/2001
    
    Method of making a stackable
microcircuit layer from a plastic
encapsulated microcircuit
Douglas M. Albert; Keith D. Gann10/197,006
    
    US
    
    7/16/2002
    
    Wearable biomonitor with flexible
thinned integrated circuit
Ogzuz, Volkhan H; Khashayar, Abbas10/663,371
    
    US
    
    
    
    Stacked microelectronic module with
vertical interconnect vias Ogzuz,
Volkhan H;10/805,849
    
    US
    
    3/22/2004
    
    Three-dimensional imaging device
incorporating stacked layers
containing microelectronic circuits
David E. Ludwig; John V. Kennedy;
Christian Krutzik11/003,429
    
    US
    
    12/6/2004
    
    Wearable biomonitor with flexible
thinned integrated circuit
Ogzuz, Volkhan H; Khashayar, Abbas60/036,759
    
    US
    
    1/28/1997
    
    Multi-element micro gyro
Hsu, Ying W.; Reeds, III, John W.;
Saunders, Christ H.60/049,025
    
    US
    
    6/9/1997
    
    Stacking layers containing enclosed
IC chips
Eide, Floyd K.60/049,026
    
    US
    
    6/9/1997
    
    Stacking layers containing enclosed
IC chips Eide, Floyd K.60/049,582
    
    US
    
    6/13/1997
    
    IC stack utilizing BGA contacts
Eide, Floyd K.60/065,088
    
    US60/238,797
    
    US
    
    10/6/2000
    
    High speed data switch with
traverse-mated stacks containing
superconducting electronics
John Carson60/274,120
    
    US60/305,353
    
    US
    
    
    
    Biomonitor device
Ogzuz, Volkhan H60/346,494
    
    US
    
    1/9/2002
    
    Low cost miniature computer and
methods for making same Gann, Keith




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor60/348,852
    
    US
    
    1/17/2002
    
    Field programmable gate array
structure incorporating high density
support circuitry and method for
making same
Ozguz, Volkan H.;60/354,442
    
    US
    
    2/7/2002
    
    BGA layer and assembly and method for
making same
Eide, Floyd K.60/355,955
    
    US
    
    2/12/2002
    
    Stacked BGA assembly Eide, Floyd K.60/394,167
    
    US
    
    7/8/2002
    
    Cryopump piston position tracking
using an encoder
Sapir, Itzhak60/410,895
    
    US
    
    
    
    Wearable biomonitor with flexible
thinned integrated circuit
Ogzuz, Volkhan H; Khashayar, Abbas60/424,022
    
    US
    
    
    
    NEO-wafers and NEO-chips, device and
method
Sambo S. He60/424,025
    
    US
    
    11/6/2002
    
    Creating wafers from singulated die
Stern, Jonathan Michael60/462,677
    
    US
    
    3/28/2003
    
    High-speed transmitter and receiver
incorporating three-dimensional
readout electronic module
David E. Ludwig;60/546,598
    
    US
    
    2/20/2004
    
    BGA-scale stacks comprised of thin
small outline packages and method for
making the same
Gann Keith; William E. Boyd60/617,356
    
    US
    
    10/8/2004
    
    Anti-tamper module
Volkan H. Ozguz; John Leon60/652,777
    
    US
    
    2/14/2005
    
    Stacked ball grid array package
module utilizing one or more
interposer layers
William E. Boyd; Daniel Michaels60/678,618
    
    US
    
    5/5/2005
    
    GPS incorporating low power real time
clock circuitry
Itzhak Sapir60/684,372
    
    US
    
    5/26/2005
    
    Stackable layers of encapsulated
integrated circuit chips
interconnected with prefabricated via
structures
Volkan Ozguz; Jonathan Stern




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor60/710,717
    
    US
    
    8/24/2005
    
    Surface trenched stackable layers
Keith Gann; Douglas N. Albert60/711,375
    
    US
    
    8/26/2005
    
    High density interconnect scheme for
stacked electronic modules
John V. Kennedy60/711,376
    
    US
    
    8/26/2005
    
    MEMS cooling device
Itzhak Sapir60/758,922
    
    US
    
    1/17/2006
    
    Absolute pressure sensor
Sapir, Itzhak60/628,742
    
    US
    
    11/18/2004
    
    Interface optimization of high
density interconnects
Stewart Clark60/617,426
    
    US
    
    10/8/2004
    
    Interface optimization of high
density interconnects
Stewart ClarkRE33331
(07/336,017)
    
    US
    
    9/11/1990
(4/10/1989)
    
    Multiplexer circuitry for high
density analog signals
Inventorship not available4,490,626
(06/403,004)
    
    US
    
    12/25/1984
(7/29/1982)
    
    Multiplexer circuitry for high
density analog signals
Carlson, Randolph S.4,912,545
(07/097,797)
    
    US
    
    3/27/1990
(9/16/1987)
    
    Bonding of aligned conductive bumps
on adjacent surfaces
Go, Tiong C.4,983,533
(07/114,415)
    
    US
    
    1/8/1991
(10/28/1987)
    
    High-density electronic modules 
process and product
Go, Tiong C.4,290,844
(06/015070)
    
    US
    
    9/22/1981
(2/26/1979)
    
    Focal plane photo-detector mosaic
array fabrication
Rotolante, Ralph A.; Koehler, Toivo4,304,624
(05/855242)
    
    US
    
    12/8/1981
(11/28/1977)
    
    Method of fabricating a multi-layer
structure for detector array module
Carson, John C.; Dahlgren, Paul F.4,352,715
(06/206993)
    
    US
    
    10/5/1982
(11/17/1980)
    
    Detector array module fabrication
Carson, John C.; Dahlgren, Paul F.4,354,107
(06/206994)
    
    US
    
    10/12/1982
(11/14/1980)
    
    Detector array module-structure and
fabrication
Carson, John C.; Dahlgren, Paul F.




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor4,403,238
(06/213933)
    
    US
    
    9/6/1983
(12/8/1980)
    
    Detector array focal plane
configuration
Clark, Stewart A.4,449,044
(06/262296)
    
    US
    
    5/15/1984
(5/11/1981)
    
    Focal plane photo-detector mosaic
array apparatus
Rotolante, Ralph A.; Koehler, Toivo4,525,921
(06/517221)
    
    US
    
    7/2/1985
(7/25/1983)
    
    High-density electronic processing
package-structure and fabrication
Carson, John C.; Clark, Stewart A.4,551,629
(06/572802)
    
    US
    
    11/5/1985
(1/23/1984)
    
    Detector array module-structure and
fabrication
Carson, John C.; Clark, Stewart A.4,555,623
(06/558099)
    
    US
    
    11/26/1985
(12/5/1983)
    
    Pre-amplifier in focal plane detector
array
Bridgewater, Walter F.; De Caro,
Robert E.; Larson, Roger; Wall,
Llewellyn E.4,596,948
(06/661727)
    
    US
    
    6/24/1986
(10/17/1984)
    
    Constant current source for
integrated circuits
Wall, Llewellyn E.4,617,160
(06/674096)
    
    US
    
    10/14/1986
(11/23/1984)
    
    Method for fabricating modules
comprising uniformly stacked, aligned
circuit-carrying layers
Belanger, Robert J.; Bisignano, Alan
G.4,646,128
(06/720902)
    
    US
    
    2/24/1987
(4/8/1985)
    
    High-density electronic processing
packagestructure and fabrication
Carson, John C.; Clark, Stewart A.4,672,737
(06/761889)
    
    US
    
    6/16/1987
(8/2/1985)
    
    Detector array module fabrication
process
Carson, John C.; Clark, Stewart A.4,675,532
(06/795988)
    
    US
    
    6/23/1987
(11/6/1985)
    
    Combined staring and scanning
photodetector sensing system having
both temporal and spatial filter in
Carson, John C.4,704,319
(06/842159)
    
    US
    
    11/3/1987
(3/21/1986)
    
    Apparatus and method for fabricating
modules comprising stacked
circuit-carrying layers
Belanger, Robert J.; Bisignano, Alan
G.




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    Inventor4,706,166
(06/856835)
    
    US
    
    11/10/1987
(4/25/1986)
    
    High-density electronic
modulesprocess and product
Go, Tiong C.4,764,846
(07/000562)
    
    US
    
    8/16/1988
(1/5/1987)
    
    High density electronic package
comprising stacked sub-modules
Go, Tiong C.4,779,005
(07/048551)
    
    US
    
    10/18/1988
(5/11/1987)
    
    Multiple detector viewing of pixels
using parallel time delay and
integration circuitry
Arnold, Jack L.4,791,286
(07/042686)
    
    US
    
    12/13/1988
(4/27/1987)
    
    Pre-amplifier in focal plane detector
array
Wall, Llewellyn E.4,806,761
(07/023644)
    
    US
    
    2/21/1989
(3/9/1987)
    
    Thermal imager incorporating
electronics module having focal plane
sensor mosaic
Carson, John C.; Clark, Stewart A.4,912,545
(07/097797)
    
    US
    
    3/27/1990
(9/16/1987)
    
    Bonding of aligned conductive bumps
on adjacent surfaces
Go, Tiong C.5,701,233
(08/376,799)
    
    US
    
    12/23/1997
(1/23/1995)
    
    Stackable modules and multimodular
assemblies
Carson, John C.; DeCaro, Robert E.;
Hsu, Ying; Miyake, Michael K.5,745,631
(08/592,691)
    
    US
    
    4/28/1998
(1/26/1996)
    
    Self-aligning optical beam system
Reinker, David M.NL0511218
(NL90917886.5)
    
    NL
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic circuitry unit
containing stacked IC layers having
lead rerouting
Go, Tiong C.(deceased,); Minahan,
Joseph A.; Shanken, Stuart N.JP06-0515293
    
    JP
    
    12/16/1993
    
    Inventorship not availableJP97-0513369
    
    JP
    
    9/27/1995
    
    Infrared wireless communication
between electronic system components
DeCaro, Robert; Saunders, Christ H.;
Maeding, DaleJP02-0506137
    
    JP
    
    3/23/1990
    
    Inventorship not availableJP04-0505734
    
    JP
    
    1/29/1992
    
    Hardware for electronic neural network
Carson, John C.




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorJP58-502699
    
    JP
    
    7/25/1983
    
    Inventorship not availablePCT/US98/021798
    
    WO
    
    10/14/1998
    
    Multi-element micro gyro Hsu, Ying WenFR0511218
(FR90917886.5)
    
    FR
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic circuitry unit
containing stacked IC layers having
lead rerouting
Go, Tiong C.(deceased,); Minahan,
Joseph A.; Shanken, Stuart N.EP0116072
(EP83902618.4)
    
    EP
    
    10/11/1989
(7/25/1983)
    
    Multiplexer circuitry for high
density analog signalsEP01979633.3
    
    EP
    
    10/9/2001
    
    High speed multi-stage stacked layer
switch
John C. Carson; Volkan H. OrguzEP02797722.2
    
    EP
    
    3/4/2002
    
    Retro-reflector warm stop for
uncooled thermal imaging cameras and
method of using the same
Kaufman, Charles S.EP0511218
(EP90917886.5)
    
    EP
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic circuitry unit
containing stacked IC layers having
lead rerouting
Go, Tiong C.(deceased,); Minahan,
Joseph A.; Shanken, Stuart N.EP0570479
(EP92905662.0)
    
    EP
    
    10/10/2001
(1/29/1992)
    
    Hardware for electronic neural network
Carson, John C.EP067087 (EP94909418.9)
    
    EP
    
    (12/16/1993)
    
    Fabricating stacks of IC chips by
segmenting a larger stack MINIHAN
JOSEPH A; PEPE ANGEL AEP0683968
(EP94903352.6)
    
    EP
    
    10/24/2002
(12/1/1993)
    
    Module comprising IC memory stack
dedicated to and structurally
combined with an IC microprocessor
chip
Carson, John C.; Indin, Ronald J.;
Shanken, Stuart N.EP0695494
(EP94915397.7)
    
    EP
    
    2/24/2001
(4/19/1994)
    
    Electronic module comprising a stack
of IC chips
Carson, John C.; Some, Raphael R.EP0713609
(EP94925876.8)
    
    EP
    
    5/7/2003
(8/12/1994)
    
    Stack of IC chips as substitute for
single IC chip
Ludwig, David E.; Saunders, Christ
H.; Some, Raphael R.; Stuart, John J.




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorEP90906503.9
    
    EP
    
    3/23/1990
    
    Analog to digital conversion in
Z-technology module
Wall, Llewellyn E.EP92916059.6
    
    EP
    
    6/24/1992
    
    Fabricating electronic circuitry unit
containing stacked IC layers having
lead rerouting
Go, Tiong C.(deceased,); Minahan,
Joseph A.; Shanken, Stuart N.EP93922760.9
    
    EP
    
    9/27/1993
    
    Fabrication of dense parallel solder
bump connections
Pepe, Angel A.; Reinker, David M.;
Minahan, Joseph A.EP96902733.3
    
    EP
    
    1/22/1996
    
    Stackable modules and multimodular
assemblies
Carson, John C.; DeCaro, Robert E.;
Hsu, Ying; Miyake, Michael K.EP98957755.6
    
    EP
    
    11/10/1998
    
    Method for thinning semiconductor
wafers with circuits and wafers made
by the same
Albert, Douglas; Ogzuz Volkhan HEP98964683.1
    
    EP
    
    10/14/1998
    
    Multi-element micro gyro
Hsu, Ying WenDE0683968
(DE94903352.6)
    
    DE
    
    10/24/2002
(12/1/1993)
    
    Module comprising IC memory stack
dedicated to and structurally
combined with an IC microprocessor
chip
Carson, John C.; Indin, Ronald J.;
Shanken, Stuart N.DE69030195
(DE69030195.2)
    
    DE
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic circuitry unit
containing stacked IC layers having
lead rerouting
Go, Tiong C.(deceased,); Minahan,
Joseph A.; Shanken, Stuart N.FR0116072
(FR83902618.4)
    
    FR
    
    7/25/1983
    
    Multiplexer circuitry for high
density analog signals
Inventorship not availableDE0116072
(DE83902618.4)
    
    DE
    
    7/25/1983
    
    Multiplexer circuitry for high
density analog signals
Inventorship not availableGB0116072
(GB83902618.4)
    
    GB
    
    7/25/1983
    
    Multiplexer circuitry for high
density analog signals
Inventorship not available




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorNL0116072
(NL83902618.4)
    
    NL
    
    7/25/1983
    
    Multiplexer circuitry for high
density analog signals
Inventorship not availableSE0116072
(SE83902618.4)
    
    SE
    
    7/25/1983
    
    Multiplexer circuitry for high
density analog signals
Inventorship not availableEP0596075
(EP93911250.4)
    
    EP
    
    8/22/2001 (5/5/1993)
    
    Non-conductive end layer for
integrated stack of IC chips Miyake,
Michael K.EP1097467
(EP99928570.2)
    
    EP
    
    11/2/2006
(6/10/1993)
    
    IC stack utilizing secondary
leadframes
Eide, Floyd K.10/339,023
    
    US
    
    1/9/2003
    
    Method for making stacked integrated
circuits (ICs) using prepackaged
parts Keith D. Gann11/644,438
    
    US
    
    12/22/2006
    
    Method for making stacked integrated
circuits (ICs) using prepackaged
parts
Keith D. Gann09/949,203
    
    US
    
    9/7/2001
    
    Method of manufacturing multilayer
modules
James Satsuo Yamaguchi; Angel Antonio
Pepe; Volkan H. Ozguz; Andrew Nelson
CamienEP1596433
(EP04394026.1)
    
    EP
    
    1/2/2008
(5/12/2004)
    
    A method for creating neo-wafers from
singulated integrated circuit die and
a device made according to the method
Stern, Jonathan MichaelTR1596433
(TR04394026.1)
    
    TR
    
    1/2/2008
(5/12/2004)
    
    A method for creating neo-wafers from
singulated integrated circuit die and
a device made according to the method
Stern, Jonathan Michael




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorIT1596433
(IT04394026.1)
    
    IT
    
    1/2/2008
(5/12/2004)
    
    A method for creating neo-wafers from
singulated integrated circuit die and
a device made according to the method
Stern, Jonathan MichaelIE1596433
(IE04394026.1)
    
    IE
    
    1/2/2008
(5/12/2004)
    
    A method for creating neo-wafers from
singulated integrated circuit die and
a device made according to the method
Stern, Jonathan MichaelEP05111589.7
    
    EP
    
    12/1/2005
    
    BGA-scale stacks comprised of layers
containing integrated circuit die and
a method for making the same
Gann Keith; William E. Boyd11/302,480
    
    US
    
    12/12/2005
    
    Neo-wafer device comprised of
multiple singulated integrated
circuit die
Stern JonathanJP2098125
(JP63-501172)
    
    JP
    
    10/20/1987
    
    High-density electronic modules,
process and product
Go, Tiong C.DE6933329
    
    DE
    
    12/16/1993
    
    Method for fabricating stacks of IC
chips by segmenting a larger stack
Joseph A. MinahanIT0676087
    
    IT
    
    12/16/1993
    
    Method for fabricating stacks of IC
chips by segmenting a larger stack
Joseph A. MinahanNL0676087
    
    NL
    
    12/16/1993
    
    Method for fabricating stacks of IC
chips by segmenting a larger stack
Joseph A. MinahanPCT/US99/023460
    
    WO
    
    10/6/1999
    
    Multi-element micro gyro
Ying W. Hsu




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorEP99951869.9
    
    EP
    
    10/6/1999
    
    Multi-element micro gyro
Ying W. Hsu60/049,580
    
    US
    
    6/13/1997
    
    IC stack utilizing secondary
leadframes
Floyd K. EidePCT/US99/013173
    
    WO
    
    06/10/1999
    
    IC stack utilizing secondary
leadframes
Floyd K. EideDE69933873
    
    DE
    
    6/10/1999
    
    IC stack utilizing secondary
leadframes
Floyd K. EidePCT/US02/006803
    
    WO
    
    3/4/2002
    
    Method and apparatus for temperature
compensation of an uncooled focal
plane array
Randolph S. CarsonEP02721271.1
    
    EP
    
    3/4/2002
    
    Method and apparatus for temperature
compensation of an uncooled focal
plane array
Randolph S. CarsonCY1596433
    
    CY
    
    5/12/2004
    
    Method for creating neo-wafers from
singulated integrated circuit die and
a device made according to the method
Jonathan SternEE1596433
    
    EE
    
    5/12/2004
    
    Method for creating neo-wafers from
singulated integrated circuit die and
a device made according to the method
Jonathan SternGR1596433
    
    GR
    
    5/12/2004
    
    Method for creating neo-wafers from
singulated integrated circuit die and
a device made according to the method
Jonathan Stern




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorHU1596433
    
    HU
    
    5/12/2004
    
    Method for creating neo-wafers from
singulated integrated circuit die and
a device made according to the method
Jonathan SternLU1596433
    
    LU
    
    5/12/2004
    
    Method for creating neo-wafers from
singulated integrated circuit die and
a device made according to the method
Jonathan Stern11/302,480
    
    US
    
    12/12/2005
    
    Neo-wafer device comprised of
multiple singulated integrated
circuit die
Jonathan Stern60/785,135
    
    US
    
    3/24/2006
    
    Method for image jitter reduction in
a multiplayer LADAR device
John Kennedy60/300,449
    
    US
    
    6/25/2001
    
    Video event capture, storage and
processing method and apparatus
Randolph S. CarlsonPCT/US06/005754
    
    WO
    
    2/14/2006
    
    Stacked ball grid array package
module utilizing one or more
interposer layers
William E. BoydPCT/US96/005065
    
    WO
    
    4/11/1996
    
    Dry adhesive joining of layers of
electronic devices
Angel A. PepePCT/US88/000060
    
    WO
    
    1/4/1998
    
    High density electronic package
comprising stacked sub-modules
Tiong C. GoPCT/US00/041207
    
    WO
    
    10/16/2006
    
    Highly configurable capacitive
transducer interface circuit
Christ Ying Hsu




---



##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorPCT/US02/019452
    
    WO
    
    6/18/2002
    
    Mems sensor with single central
anchor and motion-limiting connection
geometry
John William Reeds IIIPCT/US02/020290
    
    WO
    
    6/26/2002
    
    Method of designing a flexure system
for turning the modal response of a
decoupled micromachined gyroscope and
a gyroscope designed according to the
method
Michael J. TracyPCT/US01/08720
    
    WO
    
    3/19/2001
    
    Method of canceling quadrature error
in an angular rate sensor
Ying Wen Hsu06/187,787
    
    US
    
    9/16/1980
    
    Detector array module-structure and
fabrication
John C. Carson06/282,459
    
    US
    
    7/13/1981
    
    Detector array module-structure and
fabrication
John C. Carson60/159,832
    
    US
    
    10/15/1999
    
    Universal capacitive interface circuit
Christ Ying Hsu06/721,040
    
    US
    
    4/8/1985
    
    Thermal imager incorporating
electronics module having focal plane
sensor mosaic
John C. Carson60/190,271
    
    US
    
    3/17/2000
    
    Method for canceling quadrature error
in angular rate sensor
Ying Wen HsuEP0340241
    
    EP
    
    1/4/1998
    
    High density electronic package
comprising stacked sub-modules
Tiong C. Go




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##### 



Title of Patent and First NamedPatent or Application No.
    
    Country
    
    Filing Date
    
    InventorDE3854814
    
    DE
    
    1/4/1998
    
    High density electronic package
comprising stacked sub-modules
Tiong C. GoFR0340241
    
    FR
    
    1/4/1998
    
    High density electronic package
comprising stacked sub-modules
Tiong C. GoGB0340241
    
    GB
    
    1/4/1998
    
    High density electronic package
comprising stacked sub-modules
Tiong C. GoEP00982671.0
    
    EP
    
    10/16/2000
    
    Highly configurable capacitive
transducer interface circuit
Christ Ying HsuPCT/US87/002746
    
    WO
    
    10/20/1987
    
    High-density electronic modules,
process and product
Tiong C. GoEP0385979
    
    EP
    
    10/20/1987
    
    High-density electronic modules,
process and product
Tiong C. GoDE0385979
    
    DE
    
    10/20/1987
    
    High-density electronic modules,
process and product
Tiong C. GoFR0385979
    
    FR
    
    10/20/1987
    
    High-density electronic modules,
process and product
Tiong C. Go60/809,466
    
    US
    
    5/30/2006
    
    Large format thermoelectric infrared
detector and a method of fabrication
Ying HsuGB0385979
    
    GB
    
    10/20/1987
    
    High-density electronic modules,
process and product
Tiong C. Go




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##### 



ASSIGNOR:
Irvine Sensors CorporationBy:
    /s/ John J. Stuart, Jr.Name:
    John J. Stuart, Jr.Title:
    Sr. VP & Chief Financial Officer




---



##### 



Exhibit G revised
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##### 



Cross License Agreement dated ***, and amended on *** between Irvine Sensors Corporation and ***.
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##### 



PATENT PURCHASE AGREEMENT
  Agreement   Seller   Purchaser 
 1. Background
    2. Definitions
  Abandoned Assets  Exhibit C .
  Assigned Patent Rights 
  Assignment Agreements 
  Common Interest Agreement  Exhibit E
  Docket 
  Effective Date 
  Executed Assignments  Exhibit
B , Exhibit C,
  Live Assets  Exhibits A and/or B
  Patents 




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 Primary Warranties 
  Prosecution History Files 
  Transmitted Copy 
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Deliverables   Deliverables  Exhibits A B Exhibit C Exhibit A B Exhibit C
 Closing  Closing 
 Closing Conditions
 Signature by Seller
 Transmittal of Documents
 Page 2




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Compliance With Agreement
 Representations and Warranties True
 Patents Not Abandoned
 Delivery of Executed Assignments
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 Royalty Agreement
 Existing License Agreements Exhibit G
 Delivery of License Agreements
 Payment
  Termination and Survival
 
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    Confidential treatment requested pursuant to Rule 24b-2 under the Securities Exchange Act of 1934. In accordance with Rule 24b-2, these confidential portions have been omitted from this exhibit and filed separately with the
Securities and Exchange Commission. Page 3




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##### 



4. Transfer of Patents and Additional Rights
 Assignment of Patents Exhibit B
 Assignment of Additional Rights
     Assignment of Rights in Certain Assets Exhibit C
 License Back to Seller under Patents Seller License
 5. Additional Obligations
 Further Cooperation
   Page 4




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##### 



Payment of Fees
 Foreign Assignments
 Pre-existing Royalty Agreement
 6. Representations and Warranties of Seller
  Authority
 Title and Contest
 Page 5




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##### 



Existing Licenses and Obligations Exhibit G Exhibit G Exhibit G Exhibit G Exhibit G
 Restrictions on Rights
 Validity and Enforceability
 Conduct
 Enforcement
 Patent Office Proceedings
 Fees
 Abandoned Assets
 Page 6




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##### 



7. Representations and Warranties of Purchaser
    8. Miscellaneous
 Limitation of Liability
 Limitation on Consequential Damages
 Compliance With Laws
 Confidentiality of Terms
 Page 7




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Governing Law; Venue/Jurisdiction
 Notices.
 If to Purchaser
    
    If to SellerAprolase Development Co., LLC
2711 Centerville Road, Suite 400Wilmington,
DE 19808
    
    Irvine Sensors Corporation
3001 Redhill Ave.
Bldg. 4, Suite 108
Costa Mesa, CA 92672Attn: Managing Director
    
    Attn: Eric Boyd
  Relationship of Parties
 Equitable Relief
 Severability
 Waiver
 Miscellaneous
 Page 8




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. Exhibit A Exhibit B Exhibit C Exhibit D Exhibit E Exhibit F Exhibit G
 Counterparts; Electronic Signature; Delivery Mechanics  Transmitted Copy 
 Publicity and SEC Reporting Exhibit F Exhibit F Exhibit F SEC
  SELLER:
    
    
    
    PURCHASER:IRVINE SENSORS CORPORATION
    
    
    
    APROLASE DEVELOPMENT CO., LLCBy:
    
    /s/ John C. Carson
    
    
    
    By:
    
    /s/ Melissa ColemanName: John C. Carson
    
    
    
    
    
    Name: Melissa ColemanTitle:   President and CEO
    
    
    
    
    
    Title:   Authorized Person
 Effective Date: December 11, 2008
 Page 9




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Exhibit A




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Exhibit B




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Exhibit C




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Exhibit D
 LIST OF INITIAL DELIVERABLES
 
 U.S. Patents For each item of the Patents that is an issued United States
patent
        Non-U.S
       Patent Applications
         Common Interest Agreement
 Thorough Search/Declaration
 Exhibit D Exhibit D




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Exhibit E
 COMMON INTEREST AGREEMENT
 Agreement Counsel
 1. Background.
 Purchaser Seller party parties Patent Matters
  2. Common Interest.
  Common Interest Materials
 3. Nondisclosure.
   4. Relationship; Additions; Termination.
    5. General Terms.
    
  Counsel for Aprolase Development Co., LLC
    
    Counsel for Irvine Sensors CorporationBy:
    
    
    
    
    
    By:Date:
    
    
    
    

    
    Date:




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Exhibit F
 FORM OF PRESS RELEASE
 At Closing:




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Exhibit G