FORM OF LIEN
    RELEASE AGREEMENT
  THIS LIEN RELEASE AGREEMENT Agreement Company Investor Party Parties
  RECITALS
  WHEREAS, Note
  WHEREAS, Liens
  WHEREAS Patent Assets Patent Buyer Patent Sale and
    License
  WHEREAS,
  WHEREAS, Escrow Agent Bridge
    Notes Escrow Deposit
  AGREEMENT
  NOW THEREFORE,
  Release of Liens Please
    Initial One
  Exhibit A
  Shares
 1




---



##### 



Exhibit A
  Exhibit A
  Equity Consideration
  Governing Law
  Attorneys Fees
  Waiver of Jury Trial and Setoff; Consent to
    Jurisdiction; Etc.
  Representation by Counsel
 2




---



##### 



Admissibility of this
    Agreement
  Notices
  Amendments and Modification.
  Counterparts/Execution
  Successors and
    Assigns
  Severability
  Entire Agreement
  [SIGNATURE
    PAGE FOLLOWS]
 3




---



##### 



IN WITNESS WHEREOF
  IRVINE
    SENSORS CORPORATION
    a Delaware corporation
  By:John Carson,President and Chief Executive OfficerAddress:
   INVESTOR:
  By:Name:Title:Address:
  4




---



##### 



FORM OF RELEASE OF SECURITY INTEREST
 Secured Party Debtor
   Secured
    
    Execution
    
    
    
    RecordationDebtor
    
    Party
    
    Date
    
    Reel/Frame
    
    DateIrvine Sensors
Corporation
  Patents




---



##### 



Secured Party
 Name:Address:




---



##### 



Exhibit A
 Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor5,235,672
(07/651,477)
    
    US
    
    8/10/1993
(2/6/1991)
    
    Hardware for
electronic neural
networkCarson, John C.6,389,404
(09/223,476)
    
    US
    
    5/14/2002
(12/30/1998)
    
    Neural processing
module with input
architectures that
make maximal use of
a weighted synapse
arrayCarson, John C.;
Saunders, Christ H.6,650,704
(09/427,384)
    
    US
    
    11/18/2003
(10/25/1999)
    
    Method of producing
a high quality,
high resolution
image from a
sequence of low
quality, low
resolution images
that are
undersampled and
subject to jitterCarlson, Randolph
S.; Arnold, Jack
L.; Feldmus,
Valentine G.6,829,237
(09/973,857)
    
    US
    
    12/7/2004
(10/9/2001)
    
    High speed
multi-stage
switching network
formed from stacked
switching
layers Carson, John
C.; Ozguz, Volkan
H.7,082,591
(10/346,363)
    
    US
    
    7/25/2006
(1/17/2003)
    
    Method for
effectively
embedding various
integrated circuits
within field
programmable gate
arraysCarlson, Randolph S.6,856,167
(10/347,038)
    
    US
    
    2/15/2005
(1/17/2003)
    
    Field programmable
gate array with a
variably wide word
width memoryOzguz, Volkan H.; Carlson, Randolph
S.; Gann, Keith D.;
Leon, John P.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor7,265,579
(11/037,490)
    
    US
    
    9/4/2007
(1/18/2005)
    
    Field programmable
gate array
incorporating
dedicated memory
stacksCarlson, Randolph
Stuart; Ozguz,
Volkan; Gann, Keith
D.; Leon, John P.5,508,836(08/305,066)
    
    US
    
    4/16/1996
(9/13/1994)
    
    Infrared wireless
communication
between electronic
system
components DeCaro,
Robert; Saunders,
Christ H.; Maeding,
Dale5,635,705
(08/526,415)
    
    US
    
    6/3/1997
(9/11/1995)
    
    Sensing and
selecting observed
events for signal
processingSaunders, Christ H.6,195,268
(09/031,435)
    
    US
    
    2/27/2001
(2/26/1998)
    
    Stacking layers
containing enclosed
IC chipsEide, Floyd K.5,045,685
(07/534,969)
    
    US
    
    9/3/1991
(6/6/1990)
    
    Analog to digital
conversion on
multiple channel IC
chipsWall, Llewellyn E.5,104,820
(07/720,025)
    
    US
    
    4/14/1992
(6/24/1991)
    
    Method of
fabricating
electronic
circuitry unit
containing stacked
IC layers having
lead reroutingGo, Tiong
C.(deceased,);
Minahan, Joseph A.;
Shanken, Stuart N.5,279,991
(07/996,794)
    
    US
    
    1/18/1994
(12/24/1992)
    
    Method for
fabricating stacks
of IC chips by
segmenting a larger
stackMinahan, Joseph A.;
Pepe, Angel A.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor5,432,318
(08/178,923)
    
    US
    
    7/11/1995
(1/7/1994)
    
    Apparatus for segmenting
stacked IC chipsMinahan, Joseph A.5,304,790
(07/956,914)
    
    US
    
    4/19/1994
(10/5/1992)
    
    Apparatus and system for controllably
varying image resolution to reduce
data outputArnold, Jack5,347,428
(07/985,837)
    
    US
    
    9/13/1994
(12/3/1992)
    
    Module comprising IC memory stack
dedicated to and structurally
combined with an IC microprocessor
chipCarson, John C.; Indin, Ronald J.;
Shanken, Stuart N.5,406,701
(08/120,675)
    
    US
    
    4/18/1995
(9/13/1993)
    
    Fabrication of dense parallel solder
bump connectionsPepe, Angel A.; Reinker, David M.;
Minahan, Joseph A.5,424,920
(08/232,739)
    
    US
    
    6/13/1995
(4/25/1994)
    
    Non-conductive end layer for
integrated stack of IC chipsMiyake, Michael K.5,432,729
(08/255,465)
    
    US
    
    7/11/1995
(6/8/1994)
    
    Electronic module comprising a stack
of IC chips each interacting with an
IC chip secured to the stackCarson, John C.; Some, Raphael R.5,581,498
(08/326,645)
    
    US
    
    12/3/1996
(10/20/1994)
    
    Stack of IC chips in lieu of single
IC chipLudwig, David E.; Saunders, Christ
H.; Some, Raphael R.; Stuart, John J.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor5,688,721
(08/62,2671)
    
    US
    
    11/18/1997
(3/26/1996)
    
    3D stack of IC chips having leads
reached by vias through passivation
covering access planeJohnson, Tony K.5,953,588
(08/777,747)
    
    US
    
    9/14/1999
(12/21/1996)
    
    Stackable layers containing
encapsulated IC chipsCamien, Andrew N; Yamaguchi, James S.6,072,234
(09/316,740)
    
    US
    
    6/6/2000
(5/21/1999)
    
    Stack of equal layer neo-chips
containing encapsulated IC chips of
different sizesCamien, Andrew N.; Yamaguchi, James S.5,955,668
(09/166,458)
    
    US
    
    9/21/1999
(10/5/1998)
    
    Multi-element micro gyroHsu, Ying W.; Reeds, III, John W.; Saunders, Christ H.6,089,089
(09/301,847)
    
    US
    
    7/18/2000
(4/29/1999)
    
    Multi-element micro gyro

Hsu, Ying W.6,578,420
(09/604,782)
    
    US
    
    6/17/2003
(6/26/2000)
    
    Multi-axis micro gyro structureHsu, Ying Wen6,014,316
(09/095,416)
    
    US
    
    1/11/2000
(6/10/1998)
    
    IC stack utilizing BGA contactsEide, Floyd K.6,028,352
(09/095,415)
    
    US
    
    2/22/2000(6/10/1998)
    
    IC stack utilizing secondary
leadframes Eide, Floyd K.6,117,704
(09/282,704)
    
    US
    
    9/12/2000
(3/31/1999)
    
    Stackable layers containing
encapsulated chips




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorYamaguchi, James S.; Ozguz, Volkan
H.; Camien, Andrew N.6,476,392
(09/853,819)
    
    US
    
    11/5/2002
(5/11/2001)
    
    Method and apparatus for temperature
compensation of an uncooled focal
plane arrayKaufman, Charles S.; Carson, Randolph
S.; Hornback, William B.6,891,160
(10/281,393)
    
    US
    
    5/10/2005
(10/25/2002)
    
    Method and apparatus for temperature
compensation of an uncooled focal
plane arrayKaufman, Charles S.; Carson, Randolph
S.; Hornback, William B.7,235,785
(11/048,634)
    
    US
    
    6/26/2007
(1/31/2005)
    
    Imaging device with multiple fields
of view incorporating memory-based
temperature compensation of an
uncooled focal plane arrayHornback, Bert; Harwood, Doug; Boyd,
W. Eric; Carlson, Randy6,596,997
(09/921,525)
    
    US
    
    7/22/2003
(8/3/2001)
    
    Retro-reflector warm stop for
uncooled thermal imaging cameras and
method of using the sameKaufman, Charles S.6,706,971
(10/142,557)
    
    US
    
    3/16/2004
(5/10/2002)
    
    Stackable microcircuit layer formed
from a plastic encapsulated
microcircuitAlbert, Douglas M.; Gann, Keith D.7,174,627
(10/338,974)
    
    US
    
    2/13/2007
(1/9/2003)
    
    Method of fabricating known good dies
from packaged integrated circuits




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorGann, Keith D.6,560,109
(09/949,024)
    
    US
    
    5/6/2003
(9/7/2001)
    
    Stack of multilayer modules with
heat-focusing metal layerYamaguchi, James Satsuo; Pepe, Angel
Antonio; Ozguz, Volkan H.; Camien,
Andrew Nelson6,717,061
(09/949,512)
    
    US
    
    4/6/2004
(9/7/2001)
    
    Stacking of multilayer modulesYamaguchi, James Satsuo; Pepe, Angel
Antonio; Ozguz, Volkan H.; Camien,
Andrew Nelson6,734,370
(09/948,950)
    
    US
    
    5/11/2004
(9/7/2001)
    
    Multilayer modules with flexible
substratesYamaguchi, James Satsuo; Pepe, Angel
Antonio; Ozguz, Volkan H.; Camien,
Andrew Nelson7,127,807
(10/431,914)
    
    US
    
    10/31/2006
(5/7/2003)
    
    Process of manufacturing multilayer
modulesYamaguchi, James Satsuo; Pepe, Angel
Antonio; Ozguz, Volkan H.; Camien,
Andrew Nelson6,797,537
(09/938,686)
    
    US
    
    9/28/2004
(10/30/2001)
    
    Method of making stackable layers
containing encapsulated integrated
circuit chips with one or more
overlaying interconnect layersPepe, Angel Antonio; Yamaguchi, James
Satsuo6,784,547
(10/302,680)
    
    US
    
    8/31/2004
(11/21/2002)
    
    Stackable layers containing
encapsulated integrated circuit chips
with one or more




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventoroverlying interconnect layersPepe, Angel Antonio; Yamaguchi, James
Satsuo7,239,012
(10/951,990)
    
    US
    
    7/3/2007
(9/28/2004)
    
    Three-dimensional module comprised of
layers containing IC chips with
overlying interconnect layersPepe, Angel; Yamaguchi, James6,806,559
(10/128,728)
    
    US
    
    10/19/2004(4/22/2002)
    
    Method and apparatus for connecting
vertically stacked integrated circuit
chips Gann, Keith D.; Albert, Douglas
M.6,912,862
(10/615,641)
    
    US
    
    7/5/2005
(7/8/2003)
    
    Cryopump piston position tracking
Sapir, Itzhak6,967,411
(10/360,244)
    
    US
    
    11/22/2005
(2/7/2003)
    
    Stackable layers containing ball grid
array packages
Eide, Floyd K.7,242,082
(11/229,351)
    
    US
    
    6/10/2007
(9/15/2005)
    
    Stackable layer containing ball grid
array package
Eide, Floyd6,993,835
(10/726,888)
    
    US
    
    2/7/2006 (12/4/2003)
    
    Method for electrical interconnection
of angularly disposed conductive
patterns Albert, Douglas Marice6,998,328
(10/701,783)
    
    US
    
    2/14/2006
(11/5/2003)
    
    Method for creating neo-wafers from
singulated integrated circuit die and
a device made according to the method
Stern, Jonathan Michael




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor7,417,323
(10/703,177)
    
    US
    
    (11/6/2003)
    
    Neo-wafer device and
method

Sambo S. He7,198,965
(11/354,370)
    
    US
    
    4/3/2007
(2/14/2006)
    
    Method for making a neo-layer comprising
embedded discrete componentsHe, Sambo7,180,579
(10/806,037)
    
    US
    
    2/20/2007
(3/22/2004)
    
    Three-dimensional imaging
processing module
incorporating stacked
layers containing
microelectronic circuitsLudwig, David E.; Kennedy,
John V.; Kleinhans,
William; Liu, Tina;
Krutzik, Christian7,436,494
(11/706,724)
    
    US
    
    10/14/2008
(2/15/2007)
    
    Three-dimensional lanar
module with alignment
refernce insert circuitry

Ludwig, David E.; Kennedy,
John V.; Kleinhans,
William; Liu, Tina;
Krutzik, Christian7,335,576
(11/197,828)
    
    US
    
    2/26/2008
(8/5/2005)
    
    Method for precision
integrated circuit die
singulation using
differential etch ratesDavid, Ludwig; Yamaguchi,
James; Clark, Stuart; Boyd,
W. Eric7,380,459
(11/654,292)
    
    US
    
    6/3/2008
(1/16/2007)
    
    Absolute pressure sensorSapir, Itzhak09/949,203
    
    US
    
    9/7/2001
    
    Method of manufacturing
multilayer modulesJames Satsuo Yamaguchi;
Angel Antonio Pepe; Volkan




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorH. Ozguz; Andrew Nelson
Camien10/968,572
    
    US
    
    10/19/2004
    
    Vertically stacked
pre-packaged integrated
circuit chipsKeith Gann; Douglas N.
Albert7,440,449
(10/960,712)
    
    US
    
    10/6/2004
    
    High speed switching module
comprised of stacked layers
incorporating T-connect
structuresJohn C. Carson; Volkan H.
Orguz11/977,447
    
    US
    
    
    
    Inventorship not available11/897,938
    
    US
    
    
    
    Inventorship not available11/825,643
    
    US
    
    7/7/2007
    
    Inventorship not available11/807,671
    
    US
    
    
    
    Inventorship not available11/731,154
    
    US
    
    
    
    Inventorship not available11/644,438
    
    US
    
    12/22/2006
    
    Method for making stacked
integrated circuits (ICs)
using prepackaged partsKeith D. Gann11/524,090
    
    US
    
    9/20/2006
    
    Stackable tier structure
comprising high density
feedthroughVolkan Ozguz; Jonathan Stern




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor11/511117
    
    US
    
    8/26/2006
    
    MEMS cooling deviceItzhak Sapir11/499,403
    
    US
    
    8/4/2006
    
    High density interconnect
assembly comprising stacked
electronic moduleJohn V. Kennedy11/441908
    
    US
    
    5/26/2006
    
    Stackable tier structure
comprising prefabricated
high density feedthroughVolkan Ozguz; Jonathan Stern11/429,468
    
    US
    
    
    
    Inventorship not available11/415,891
    
    US
    
    5/1/2006
    
    Low power electronic
circuit incorporating real
time clockGary Gottlieb10/339,023
    
    US
    
    1/9/2003
    
    Method for making stacked
integrated circuits (ICs)
using prepackaged
parts 
Keith D. Gann11/350,974
    
    US
    
    2/8/2006
    
    Stacked ball grid array
package module utilizing
one or more interposer
layersWilliam E. Boyd; Daniel
Michaels11/302,480
    
    US
    
    12/12/2005
    
    Neo-wafer device comprised
of multiple singulated
integrated circuit dieStern Jonathan11/301645
    
    US
    
    12/12/2005
    
    Cornerbond assembly
comprising
three-dimensional
electronic modules




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorAlbert Douglas11/259,683
    
    US
    
    10/25/2005
    
    Stacked microelectronic
layer and module with
three-axis channel
T-connectsKeith D. Gann; W. Eric Boyd11/248,659
    
    US
    
    10/11/2005
    
    Anti-tamper moduleVolkan H. Ozguz; John Leon10/178,390
    
    US
    
    6/24/2002
    
    Video event capture,
storage and processing
method and apparatusRandolph S. Carlson60/993,689
    
    US
    
    
    
    Inventorship not available11/150712
    
    US
    
    6/10/2005
    
    Stackable semiconductor
chip layer comprising
prefabricated trench
interconnect viasW. Eric Boyd; Angel Pepe;
James Yamaguchi; Volkan
Ozguz; Andrew Camien;
Douglas Albert11/062,507
    
    US
    
    2/22/2005
    
    BGA-scale stacks comprised
of layers containing
integrated circuit die and
a method for making the
sameGann Keith; William E. Boyd12/008,253
    
    US
    
    
    
    Inventorship not available61/007,497
    
    US
    
    
    
    Inventorship not available




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorTR1596433
(TR04394026.1)
    
    TR
    
    1/2/2008
(5/12/2004)
    
    A method for creating
neo-wafers from singulated
integrated circuit die and
a device made according to
the methodStern, Jonathan MichaelSK1596433
(SK04394026.1)
    
    SK
    
    1/2/2008 
(5/12/2004)
    
    A method for creating
neo-wafers from singulated
integrated circuit die and
a device made according to
the methodStern, Jonathan MichaelSE0570479
(SE92905662.0)
    
    SE
    
    10/10/2001
(1/29/1992)
    
    Hardware for electronic
neural networkCarson, John C.SE83902618.4
    
    SE
    
    7/25/1983
    
    Multiplexer circuitry for
high density analog signals 

Inventorship not availableNL0570479
(NL92905662.0)
    
    NL
    
    10/10/2001 
(1/29/1992)
    
    Hardware for electronic
neural networkCarson, John C.NL83902618.4
    
    NL
    
    7/25/1983
    
    Multiplexer circuitry for
high density analog signals 

Inventorship not availableJP2098125
(JP12-505387)
    
    JP
    
    11/20/1985
    
    Apparatus and method for
fabricating modules 

Inventorship not availableJP2098125
(JP12-2098125)
    
    JP
    
    10/20/1987
    
    High-density electronic
modules, process and product




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorInventorship not availableJP2005-507894
    
    JP
    
    1/16/2006
    
    Stackable layers containing
ball grid array packages
Inventorship not availableJP2006-286556
    
    JP
    
    10/20/2006
    
    Stackable tier structure
comprising high density
feedthrough
Volkan Ozguz; Jonathan SternJP2000-591490
    
    JP
    
    12/30/1999
    
    Neural processing module with
input architectures that make
maximal use of a weighted
synapse array
Carson, John C.; Saunders,
Christ H.JP3308265
(JP12-554175)
    
    JP
    
    6/10/1999
    
    IC stack utilizing flexible
circuits with BGA contacts
Eide, Floyd K.JP3511008
(JP12-553982)
    
    JP
    
    6/10/1999
    
    IC stack utilizing secondary
leadframes
Eide, Floyd K.JP3544974
(JP06-0502691)
    
    JP
    
    5/5/1993
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.JP3354937
(JP06-524367)
    
    JP
    
    4/19/1994
    
    Electronic module comprising a
stack of IC chips
Carson, John C.; Some, Raphael
R.IT1097467
(IT99928571.1)
    
    IT
    
    11/2/2006
(6/10/1993)
    
    IC stack utilizing secondary
leadframes
Eide, Floyd K.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorIT1596433
(IT04394026.1)
    
    IT
    
    1/2/2008
(5/12/2004)
    
    A method for creating
neo-wafers from singulated
integrated circuit die and a
device made according to the
method
Stern, Jonathan MichaelIE1596433
(IE04394026.1)
    
    IE
    
    1/2/2008
(5/12/2004)
    
    A method for creating
neo-wafers from singulated
integrated circuit die and a
device made according to the
method
Stern, Jonathan MichaelGB0570479
(GB92905662.0)
    
    GB
    
    10/10/2001
(1/29/1992)
    
    Hardware for electronic neural
network
Carson, John C.GB1097467
(GB99928571.1)
    
    GB
    
    11/2/2006
(6/10/1993)
    
    IC stack utilizing secondary
leadframes
Eide, Floyd K.GB1596433
(GB04394026.1)
    
    GB
    
    1/2/2008 (5/12/2004)
    
    A method for creating
neo-wafers from singulated
integrated circuit die and a
device made according to the
method Stern, Jonathan MichaelGB83902618.4
    
    GB
    
    7/25/1983
    
    Multiplexer circuitry for high
density analog signals
Inventorship not availableGB05996075
(GB93911250.4)
    
    GB
    
    8/22/2001
(5/5/1993)
    
    Non-conductive end layer for
integrated stack of IC chips
Miyake, Michael K.GB0683968
(GB94903352.6)
    
    GB
    
    10/24/2002
(12/1/1993)
    
    Module comprising IC memory
stack dedicated to and
structurally combined with an




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorIC microprocessor chip
Carson, John C.; Indin, Ronald
J.; Shanken, Stuart N.GB0695494
(GB94915397.7)
    
    GB
    
    2/24/2001
(4/19/1994)
    
    Electronic module comprising a
stack of IC chips
Carson, John C.; Some, Raphael
R.GB0713609
(GB94925876.8)
    
    GB
    
    5/7/2003
(8/12/1994)
    
    Stack of IC chips as
substitute for single IC
chip Ludwig, David E.;
Saunders, Christ H.; Some,
Raphael R.; Stuart, John J.GB067087
(GB94909418.9)
    
    GB
    
    (12/16/1993)
    
    Fabricating stacks of ic chips
by segmenting a larger stack
MINIHAN JOSEPH A; PEPE ANGEL AFR1097467
(FR99928571.1)
    
    FR
    
    11/2/2006
(6/10/1993)
    
    IC stack utilizing secondary
leadframes
Eide, Floyd K.FR1596433
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Title of Patent and FirstPatent or Application No.
    
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Title of Patent and FirstPatent or Application No.
    
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Title of Patent and FirstPatent or Application No.
    
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R.




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Title of Patent and FirstPatent or Application No.
    
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Wall, Llewellyn E.




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Title of Patent and FirstPatent or Application No.
    
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    STACKING LAYERS CONTAINING
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    Inventorship not available




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##### 



Title of Patent and FirstPatent or Application No.
    
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Abbas




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##### 



Title of Patent and FirstPatent or Application No.
    
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##### 



Title of Patent and FirstPatent or Application No.
    
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Title of Patent and FirstPatent or Application No.
    
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Title of Patent and FirstPatent or Application No.
    
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---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named Inventor5,701,233
(08/376,799)
    
    US
    
    12/23/1997
(1/23/1995)
    
    Stackable modules and
multimodular assembliesCarson, John C.; DeCaro, Robert
E.; Hsu, Ying; Miyake, Michael K.5,745,631
(08/592,691)
    
    US
    
    4/28/1998
(1/26/1996)
    
    Self-aligning optical beam systemReinker, David M.SE0511218
(SE90917886.5)
    
    SE
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic circuitry
unit containing stacked IC
layers having lead reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.NL0511218
(NL90917886.5)
    
    NL
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic circuitry
unit containing stacked IC
layers having lead reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.NL0683968
(NL94903352.6)
    
    NL
    
    10/24/2002
(12/1/1993)
    
    Module comprising IC memory
stack dedicated to and
structurally combined with an IC
microprocessor chipCarson, John C.; Indin, Ronald
J.; Shanken, Stuart N.LU0511218
(LU90917886.5)
    
    LU
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic circuitry
unit containing stacked IC
layers having lead reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.LI0511218
(LI90917886.5)
    
    LI
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic circuitry
unit containing stacked IC
layers having lead reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.JP06-0515293
    
    JP
    
    12/16/1993
    
    Inventorship not available




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##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorJP05-0513453
    
    JP
    
    12/1/1993
    
    Inventorship not availableJP07-0513369
    
    JP
    
    9/27/1995
    
    Inventorship not availableJP02-0506137
    
    JP
    
    3/23/1990
    
    Inventorship not availableJP04-0505734
    
    JP
    
    1/29/1992
    
    Hardware for electronic neural
networkCarson, John C.JP58-502699
    
    JP
    
    7/25/1983
    
    Inventorship not availablePCT/US98/021798
    
    JP
    
    10/14/1998
    
    Multi-element micro gyro Hsu,
Ying WenIT0511218
(IT90917886.5)
    
    IT
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic circuitry
unit containing stacked IC
layers having lead reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.IT0683968
(IT94903352.6)
    
    IT
    
    10/24/2002
(12/1/1993)
    
    Module comprising IC memory
stack dedicated to and
structurally combined with an IC
microprocessor chipCarson, John C.; Indin, Ronald
J.; Shanken, Stuart N.GB0511218
(GB90917886.5)
    
    GB
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic circuitry
unit containing stacked IC
layers having lead reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.




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##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorFR0511218
(FR90917886.5)
    
    FR
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic
circuitry unit containing
stacked IC layers having lead
reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.ESP0511218
(ES90917886.5)
    
    ES
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic
circuitry unit containing
stacked IC layers having lead
reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.EP0116072
(EP83902618.4)
    
    EP
    
    10/11/1989
(7/25/1983)
    
    Multiplexer circuitry for high
density analog signalsEP01979633.3
    
    EP
    
    10/9/2001
    
    High speed multi-stage stacked
layer switchJohn C. Carson; Volkan H. OrguzEP02797722.2
    
    EP
    
    3/4/2002
    
    Retro-reflector warm stop for
uncooled thermal imaging
cameras and method of using the
sameKaufman, Charles S.EP0511218
(EP90917886.5)
    
    EP
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic
circuitry unit containing
stacked IC layers having lead
reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.EP0570479
(EP92905662.0)
    
    EP
    
    10/10/2001
(1/29/1992)
    
    Hardware for electronic neural
networkCarson, John C.EP067087(EP94909418.9)
    
    EP
    
    (12/16/1993)
    
    Fabricating stacks of ic chips
by segmenting a larger
stack MINIHAN JOSEPH A; PEPE
ANGEL A




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##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorEP0683968
(EP94903352.6)
    
    EP
    
    10/24/2002
(12/1/1993)
    
    Module comprising IC memory
stack dedicated to and
structurally combined with an
IC microprocessor chipCarson, John C.; Indin, Ronald
J.; Shanken, Stuart N.EP0695494
(EP94915397.7)
    
    EP
    
    2/24/2001
(4/19/1994)
    
    Electronic module comprising a
stack of IC chipsCarson, John C.; Some, Raphael
R.EP0713609
(EP94925876.8)
    
    EP
    
    5/7/2003
(8/12/1994)
    
    Stack of IC chips as substitute
for single IC chipLudwig, David E.; Saunders,
Christ H.; Some, Raphael R.;
Stuart, John J.EP90906503.9
    
    EP
    
    3/23/1990
    
    Analog to digital conversion in
Z-technology moduleWall, Llewellyn E.EP92916059.6
    
    EP
    
    6/24/1992
    
    Fabricating electronic
circuitry unit containing
stacked IC layers having lead
reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.EP93922760.9
    
    EP
    
    9/27/1993
    
    Fabrication of dense parallel
solder bump connectionsPepe, Angel A.; Reinker, David
M.; Minahan, Joseph A.EP96902733.3
    
    EP
    
    1/22/1996
    
    Stackable modules and
multimodular assembliesCarson, John C.; DeCaro, Robert
E.; Hsu, Ying; Miyake, Michael
K.




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##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorEP98957755.6
    
    EP
    
    11/10/1998
    
    Method for thinning
semiconductor wafers with
circuits and wafers made by the
sameAlbert, Douglas; Ogzuz Volkhan HEP98964683.1
    
    EP
    
    10/14/1998
    
    Multi-element micro gyroHsu, Ying WenDK0511218(DK90917886.5)
    
    DK
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic
circuitry unit containing
stacked IC layers having lead
rerouting Go, Tiong
C.(deceased,); Minahan, Joseph
A.; Shanken, Stuart N.DE0683968
(DE94903352.6)
    
    DE
    
    10/24/2002
(12/1/1993)
    
    Module comprising IC memory
stack dedicated to and
structurally combined with an
IC microprocessor chipCarson, John C.; Indin, Ronald
J.; Shanken, Stuart N.DE69030195
(DE69030195)
    
    DE
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic
circuitry unit containing
stacked IC layers having lead
reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.CH0511218
(CH90917886.5)
    
    CH
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic
circuitry unit containing
stacked IC layers having lead
reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.BE0511218
(BE90917886.5)
    
    BE
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic
circuitry unit containing
stacked IC layers having lead
reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.




---



##### 



Title of Patent and FirstPatent or Application No.
    
    Country
    
    Filing Date
    
    Named InventorAU20020332937
    
    AU
    
    9/9/2002
    
    Stacking of multilayer modulesYamaguchi, James Satsuo; Pepe,
Angel Antonio; Ozguz, Volkan
H.; Camien, Andrew NelsonAU20020353894
    
    AU
    
    10/25/2002
    
    A method of stacking layers
containing encapsulated
integrated circuit chips with
one or more overlaying
interconnect layersPepe, Angel Antonio; Yamaguchi,
James SatsuoAU20020365422
    
    AU
    
    7/16/2002
    
    Wearable biomonitor with
flexible thinned integrated
circuitOgzuz, Volkhan H; Khashayar,
AbbasAU20030225259
    
    AU
    
    4/22/2003
    
    Method and apparatus for
connecting vertically stacked
integrated circuit chipsGann, Keith D.; Albert, Douglas
M.AU20030261429
    
    AU
    
    8/8/2003
    
    Stackable layers containing
ball grid array packagesEide, Floyd K.AT0511218
(AT90917886.5)
    
    AT
    
    3/12/1997
(6/28/1990)
    
    Fabricating electronic
circuitry unit containing
stacked IC layers having lead
reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.AT150210
(WO1992US05348)
    
    AT
    
    5/13/1997
(6/24/1992)
    
    Fabricating electronic
circuitry unit containing
stacked IC layers having lead
reroutingGo, Tiong C.(deceased,);
Minahan, Joseph A.; Shanken,
Stuart N.