# Patent

## Title
Automatic-gain control circuit

## Abstract

An automatic-gain control circuit includes a variable-gain amplifier, a peak-detecting circuit, and an adjustable charge/discharge circuit. The variable-gain amplifier receives an input signal and adjusts the input signal based on a gain-factor control signal for generating a corresponding output signal. The peak-detecting circuit is coupled to the variable-gain amplifier for generating a comparing signal according to a reference signal and the output signal. The adjustable charge/discharge circuit is coupled to the peak-detecting circuit and the variable-gain amplifier for outputting a charge current or a discharge current based on the comparing signal, thereby generating the gain-factor control signal. The ratio between the charge current and the discharge current is adjustable.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic-gain control circuit, and more particularly, to an automatic-gain control circuit capable of controlling the gain using a variable current source.
2. Description of the Prior Art
In a modernized society, various paper, data, information and video/audio signals can be processed and transmitted as electronic signals. Therefore, signal-processing circuits capable of processing electronic signals have become very important. In order to efficiently process electronic signals in a data system, many gain-amplifying circuits are required for maintaining the amplitude of the electronic signals adequately. A gain-amplifying circuit is an amplifier capable of enlarging an input signal, outputting the enlarged input signal and adjusting the amount of gain based on a control signal. Among various gain-amplifying circuits, a variable gain-amplifying circuit capable of adjusting the amplitude of the electronic signals adequately is often designed as an automatic-gain control (AGC) circuit in order to adjust the amplitude of the electronic signals automatically.
Since the gain of a variable gain-amplifying circuit can be controlled by a control signal, the variable gain characteristics of the variable gain-amplifying circuit can be represented by how the gain varies with the control signal. Generally speaking, it is preferable to design a variable gain-amplifying circuit having a wider amplifying range, better control characteristics (such as high linearity), and higher resistance against characteristic shifts due to process or temperature variations. A variable gain-amplifying circuit having a wider amplifying range can adjust its gain to a larger degree, provide electronic signals with more distinct amplitudes, and thus can be used in more applications. A variable gain-amplifying circuit having better control characteristics can be controlled more accurately. In a variable gain-amplifying circuit having higher resistance against characteristic shifts due to process or temperature variations, external influences on the variable gain characteristics can be reduced, and the overall performance of the system can be improved.
Reference is made to FIG. 1 for a diagram of a prior art AGC circuit 10. The AGC circuit 10 includes a variable-gain amplifier (VGA) 12, a peak-detecting circuit 14, a constant charge/discharge circuit 16, and a digital-to-analog converter (DAC) 1 8. The VGA 12 receives an input signal VIN at an input end and adjusts the input signal VIN based on a gain-factor control signal VCTL, thereby generating a corresponding output signal VOUT at an output end. In the prior art AGC circuit 10, the gain-factor control signal VCTL is generated by the peak-detecting circuit 14 and the constant charge/discharge circuit 16 based on the output signal VOUT. Therefore, automatic-gain control can be performed in a feedback mechanism.
In the prior art AGC circuit 10, the gain-factor control signal VCTL can be varied when the DAC 18 outputs different threshold signals VT′, and the gain of the VGA 12 can be adjusted accordingly. The peak-detecting circuit 14 includes a positive-phase differential comparator 21, negative-phase differential comparator 22, and an OR gate 23. The positive-phase differential comparator 21 includes a positive input end coupled to the VGA 12 for receiving the output signal VOUT and an negative input end coupled to the DAC 18 for receiving the threshold signal VT′. The positive-phase differential comparator 21 can differentially compare the output signal VOUT with the threshold signal VT′, thereby generate a corresponding positive-phase comparing signal V+ at its output end. The negative-phase differential comparator 22 includes a positive input end coupled to the DAC 18 for receiving the threshold signal VT′ and a negative input end coupled to the VGA 12 for receiving the output signal VOUT. The negative-phase differential comparator 22 can differentially compare the output signal VOUT with the threshold signal VT′, thereby generate a corresponding negative-phase comparing signal V− at its output end. The OR gate 23, coupled between the output ends of the positive-phase differential comparator 21 and the negative-phase differential comparator 22, can generate a corresponding comparing signal VGATE based on the positive-phase comparing signal V+ and the negative-phase comparing signal V−.
The constant charge/discharge circuit 16 includes a capacitor C, a constant charge current source IP, a constant discharge current source IN, a charge switch SWP, and a discharge switch SWN. The charge switch SWP can include a P-type metal oxide semiconductor (PMOS) transistor, and the discharge switch SWN can include an N-type metal oxide semiconductor (NMOS) transistor. The gates of the charge switch SWP and the discharge switch SWN are coupled to the OR gate 23. When the comparing signal VGATE has a high voltage level, the charge switch SWP is turned off (open-circuited) and the discharge switch SWN is turned on (short-circuited). Therefore, the constant charge/discharge circuit 16 can discharge the capacitor C using the constant discharge current source IN and the discharge switch SWN. When the comparing signal VGATE has a low voltage level, the charge switch SWP is turned on and the discharge switch SWN is turned off. Therefore, the constant charge/discharge circuit 16 can charge the capacitor C using the constant charge current source IP and the charge switch SWP. In the prior art AGC circuit 10, the constant charge current source IP and the constant discharge current source IN provide constant charging and discharge currents, respectively.
Reference is made to FIG. 2 for a signal diagram illustrating the operation of the prior art AGC circuit 10. In FIG. 2, the waveform of the output signal VOUT is represented by a sine wave having an amplitude VM and a central level VREF. The transverse axle represents time, and a period (0 ̃2π) is depicted in FIG. 2. When the absolute value of the output signal VOUT is smaller than that of the threshold signal VT′, the constant charge/discharge circuit 16 performs charging operation, such as during the time periods 0 ̃θ, (π−θ) ̃(π+θ) and (2π−θ) ̃2π (as illustrated by diagonal regions of the sine wave in FIG. 2). When the absolute value of the output signal VOUT is larger than that of the threshold signal VT′, the constant charge/discharge circuit 16 performs discharging operation, such as during the time periods θ ̃(π−θ) and (π+θ) ̃(2π−θ) (as illustrated by blank regions of the sine wave in FIG. 2). The value of θ depends on the level of the threshold voltage VT′. As the absolute value of the threshold voltage VT′ increases, the charging time TP(TP=4θ) of the constant charge/discharge circuit 16 becomes longer. As the absolute value of the threshold voltage VT′ decreases, the discharging time TN(TN=2π−4θ) of the constant charge/discharge circuit 16 becomes longer.
When the AGC circuit 10 performs charging and discharging operations, corresponding charging electronic charges QP and discharging electronic charges QN can be represented by the following formulae:

QP=IPTP=IP(4θ)

QN=INTN=IN(2π−4θ)

When the AGC circuit 10 is stabilized, the charging electronic charges QP and the discharging electronic charges QN reach an equilibrium state. Therefore, the following relationships can be obtained:

QP=QN 

IN/IP=2θ/(π−274 )

If N is used for representing the value of IN/IP, the value of θ can be represented by the following formula:




  θ
  =
  
    
      π
      2
    
    ×
    
      N
      
        N
        +
        1
      
    
  




Also, the relationship between the amplitude VM of the output signal VOUT and the threshold signal VT′ can be represented by the following formula:

VM sin θ=VT′

As a result, the following relationships can be obtained:




  
    V
    M
  
  =
  
    
      
        
          V
          T
          ′
        
        /
        sin
      
      ⁢
      
        
      
      ⁢
      θ
    
    =
    
      
        V
        T
        ′
      
      /
      
        sin
        ⁡
        
          (
          
            
              π
              2
            
            ×
            
              N
              
                N
                +
                1
              
            
          
          )
        
      
    
  




In order for the AGC circuit 10 to have better control characteristics, the value of the threshold signal VT′ has to be close to the target amplitude VM of the output signal VOUT, so that the amplitude VM of the output signal VOUT can be varied by adjusting the threshold signal VT′. Therefore, in order to reduce the difference between the absolute values of VT′ and VM, it is preferable when the value of θ approaches π/2 and the value of N approaches infinity. In the prior art AGC circuit 10, N is normally set to a constant value (such as N=10). The AGC circuit 10 can have better control characteristics as the target amplitude VM of the output signal VOUT is varied by adjusting the threshold signal VT′.
Since the threshold signal VT′ is close to the target amplitude VM of the output signal VOUT in the prior art AGC circuit 10, a high-speed positive-phase differential comparator 21 and a high-speed negative-phase differential comparator 22 are required for determining the difference between the threshold signal VT′ and the output signal VOUT accurately, so that the AGC circuit 10 can switch between charging/discharging operations correctly. Also, the DAC 18 for providing the threshold signal VT′ occupies large circuit space in the prior art AGC circuit 10 and consumes more power.
SUMMARY OF THE INVENTION
The present invention provides an automatic-gain control circuit comprising a variable-gain amplifier for receiving an input signal and adjusting the input signal based on a gain-factor control signal, thereby generating a corresponding output signal; a peak-detecting circuit coupled to the variable-gain amplifier for generating a comparing signal based on a reference signal and the output signal; and an adjustable charge/discharge circuit having an input end coupled to the peak-detecting circuit and an output end coupled to the variable-gain amplifier for outputting a charge current or a discharge current based on the comparing signal, thereby generating the gain-factor control signal, wherein a ratio between the charge current and the discharge current is adjustable.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram of a prior art AGC circuit.
FIG. 2 is a signal diagram illustrating the operation of the prior art AGC circuit in FIG. 1.
FIG. 3 is a diagram of an AGC circuit according to a first embodiment of the present invention.
FIG. 4 is a signal diagram illustrating the operation of the AGC circuit in FIG. 3.
FIG. 5 is a diagram of an AGC circuit according to a second embodiment of the present invention.
FIG. 6 is a diagram of an AGC circuit according to a third embodiment of the present invention.



DETAILED DESCRIPTION
Reference is made to FIG. 3 for a diagram of an AGC circuit 30 according to a first embodiment of the present invention. The AGC circuit 30 includes a VGA 32, a peak-detecting circuit 34, an adjustable charge/discharge circuit 36, and a filter 38. The VGA 32 receives an input signal VIN at an input end and adjusts the input signal VIN based on a gain-factor control signal VCTL, thereby generating a corresponding output signal VOUT at an output end. The filter 38, coupled between the VGA 32 and the peak-detecting circuit 34, adjusts the operating voltage point of the output signal VOUT by removing bias voltages of the VGA 32. In the AGC circuit 30, the gain-factor control signal VCTL is generated by the peak-detecting circuit 34 and the adjustable charge/discharge circuit 36 based on the output signal VOUT. Therefore, automatic-gain control can be performed in a feedback mechanism.
In the AGC circuit 30 of the present invention, the gain of the VGA 32 can be adjusted by varying the gain-factor control signal VCTL using the adjustable charge/discharge circuit 36. The peak-detecting circuit 34 includes a positive-phase differential comparator 41, negative-phase differential comparator 42, and an operational logic unit 43. The positive-phase differential comparator 41 includes a positive input end coupled to the VGA 32 for receiving the output signal VOUT and a negative input end for receiving a constant first reference signal VT1. The positive-phase differential comparator 41 can differentially compare the output signal VOUT with the first reference signal VT1, thereby generate a corresponding positive-phase comparing signal V+ at its output end. The negative-phase differential comparator 42 includes a positive input end for receiving a constant second reference signal VT2 and a negative end coupled to the VGA 32 for receiving the output signal VOUT. The negative-phase differential comparator 42 can differentially compare the output signal VOUT with the second reference signal VT2, thereby generate a corresponding negative-phase comparing signal V− at its output end. The operational logic unit 43 can include an OR gate coupled to the output ends of the positive-phase differential comparator 41 and the negative-phase differential comparator 42 and are capable of generating a corresponding comparing signal VGATE based on the positive-phase comparing signal V+ and the negative-phase comparing signal V−.
The adjustable charge/discharge circuit 36 includes a capacitor C, a constant charge current source IP, a variable discharge current source IN′, a charge switch SWP, and a discharge switch SWN. The charge switch SWP can include a PMOS transistor, and the discharge switch SWN can include an NMOS transistor. The gates of the charge switch SWP and the discharge switch SWN are coupled to the operational logic unit 43. When the comparing signal VGATE has a high voltage level, the charge switch SWP is turned off (open-circuited) and the discharge switch SWN is turned on (short-circuited). Therefore, the adjustable charge/discharge circuit 36 can discharge the capacitor C using the variable discharge current source IN′ and the discharge switch SWN. When the comparing signal VGATE has a low voltage level, the charge switch SWP is turned on and the discharge switch SWN is turned off. Therefore, the adjustable charge/discharge circuit 36 can charge the capacitor C using the constant charge current source IP and the charge switch SWP. In the AGC circuit 30 of the present invention, the constant charge current source IP and the variable discharge current source IN′ respectively provide a constant charge current and a variable discharge current, and the ratio between the charge current and the discharge current is adjustable based on a ratio control signal ICTL. In such a situation, the AGC circuit 30 of the present invention implicitly includes a current ratio control module (not shown in FIG. 3) coupled to the adjustable charge/discharge circuit 36 for generating the ratio control signal ICTL. It is noted that implementation of the current ratio control module has no concern with the spirit of the present invention, and that those skilled in the art can utilize any controller regardless of hardware or software to implement the current ratio control module as long as the ratio between the charge current IP and the discharge current IN′ can be adjusted.
Reference is made to FIG. 4 for a signal diagram illustrating the operation of the AGC circuit 30 according to the present invention. In FIG. 4, the waveform of the output signal VOUT is represented by a sine wave having an amplitude VM and a central level VREF. The transverse axle represents time, and a period (0 ̃2π) is depicted in FIG. 4. In the embodiment shown in FIG. 4, the first reference signal VT1 and the second reference signal VT2 are both set to a constant threshold signal VT. When the absolute value of the output signal VOUT is smaller than that of the threshold signal VT, the adjustable charge/discharge circuit 36 performs charging operation, such as during the time periods 0 ̃θ, (π−θ) ̃(π+θ) and (2−θ) ̃2π (as illustrated by diagonal regions of the sine wave in FIG. 4). When the absolute value of the output signal VOUT is larger than that of the threshold signal VT, the adjustable charge/discharge circuit 36 performs discharging operation, such as during the time periods θ ̃(π−θ) and (π+θ) ̃(2π−θ) (as illustrated by blank regions of the sine wave in FIG. 4). The value of 0 depends on the level of the threshold voltage VT. As the absolute value of the threshold voltage VT increases, the charging time TP(TP=4θ) of the adjustable charge/discharge circuit 36 becomes longer. As the absolute value of the threshold voltage VT decreases, the discharging time TN(TN=2π−4θ) of the adjustable charge/discharge circuit 36 becomes longer.
When the AGC circuit 30 performs charging and discharging operations, corresponding charging electronic charges QP and discharging electronic charges QN can be represented by the following formulae:

QP=IPTP=IP(4θ)

QN=INTN=IN(2π−4θ)

When the AGC circuit 30 is stabilized, the charging electronic charges QP and the discharging electronic charges QN reach an equilibrium state. Therefore, the following relationships can be obtained:

QP=QN 

IN/IP=2θ/(π−2θ)

If N′ is used for representing the value of IN′/IP, the value of θ can be represented by the following formula:




  θ
  =
  
    
      π
      2
    
    ×
    
      
        N
        ′
      
      
        
          N
          ′
        
        +
        1
      
    
  




Also, the relationship between the amplitude VM of the output signal VOUT and the threshold signal VT can be represented by the following formula:

VM sin θ=VT 

Therefore, the following relationship can be obtained:




  
    V
    M
  
  =
  
    
      
        
          V
          T
        
        /
        sin
      
      ⁢
      
        
      
      ⁢
      θ
    
    =
    
      
        V
        T
      
      /
      
        sin
        ⁡
        
          (
          
            
              π
              2
            
            ×
            
              
                N
                ′
              
              
                
                  N
                  ′
                
                +
                1
              
            
          
          )
        
      
    
  




In the AGC circuit 30 of the first embodiment of the present invention, the value of the threshold signal VT is constant and does not have to be close to the target amplitude VM of the output signal VOUT. The gain of the VGA 32 can be varied by adjusting the value of N′. Therefore, the AGC circuit 30 only requires a mid/low-speed positive-phase differential comparator 21 and a mid/low-speed negative-phase differential comparator 22 for accurately determining the difference between the threshold signal VT and the output signal VOUT, so that the AGC circuit 30 can switch between charging/discharging operations correctly. The costs for the differential comparators can thus be reduced. Also, instead of providing the threshold signals VT′ of distinct amplitudes in the prior art, the first embodiment of the present invention occupies less circuit space and consumes less power by providing the constant first and second threshold signals VT1 and VT2 (the first and second threshold signals VT1 and VT2 can be set to a constant threshold signal VT simultaneously).
Reference is made to FIG. 5 for a diagram of an AGC circuit 50 according to a second embodiment of the present invention. The AGC circuit 50 includes a VGA 32, a peak-detecting circuit 34, an adjustable charge/discharge circuit 56, and a filter 38. In the second embodiment of the present invention, the adjustable charge/discharge circuit 56 includes a capacitor C, a variable charge current source IP′, a constant discharge current source IN, a charge switch SWP, and a discharge switch SWN. Similarly, the ratio between the charge current IP′ and the discharge current IN is adjustable based on a ratio control signal ICTL, generated by a current ratio control module. If N′ is used for representing the value of IN/IP′ and the first reference signal VT1 and the second reference signal VT2 are both set to a constant threshold signal VT, the relationship between the amplitude VM of the output signal VOUT and the threshold signal VT can be represented by the following formula:




  
    V
    M
  
  =
  
    
      
        
          V
          T
        
        /
        sin
      
      ⁢
      
        
      
      ⁢
      θ
    
    =
    
      
        V
        T
      
      /
      
        sin
        ⁡
        
          (
          
            
              π
              2
            
            ×
            
              
                N
                ′
              
              
                
                  N
                  ′
                
                +
                1
              
            
          
          )
        
      
    
  




Therefore, in the AGC circuit 50 of the second embodiment of the present invention, the gain of the VGA 32 can be varied by adjusting the value of N′. A mid/low-speed positive-phase differential comparator 41 and a mid/low-speed negative-phase differential comparator 42 are required for determining the difference between the threshold signal VT and the output signal VOUT accurately, so that the AGC circuit 50 can switch between charging/discharging operations correctly. The costs for the differential comparators can thus be reduced. Also, instead of providing the threshold signals VT′ of distinct amplitudes as in the prior art, the second embodiment of the present invention occupies less circuit space and consumes less power by providing the constant first and second threshold signals VT1 and VT2 (the first and second threshold signals VT1 and VT2 can be set to a constant threshold signal VT simultaneously).
Reference is made to FIG. 6 for a diagram of an AGC circuit 60 according to a third embodiment of the present invention. The AGC circuit 60 includes a VGA 32, a peak-detecting circuit 34, an adjustable charge/discharge circuit 66, and a filter 38. In the third embodiment of the present invention, the adjustable charge/discharge circuit 66 includes a capacitor C, a variable charge current source IP′, a variable discharge current source IN′, a charge switch SWP, and a discharge switch SWN. Similarly, the ratio between the charge current IP′ and the discharge current IN is adjustable based on ratio control signals ICTL1 and ICTL2, generated by a current ratio control module. If N′ is used for representing the value of IN′/IP′ and the first reference signal VT1 and the second reference signal VT2 are both set to a constant threshold signal VT, the relationship between the amplitude VM of the output signal VOUT and the threshold signal VT can be represented by the following formula:




  
    V
    M
  
  =
  
    
      
        
          V
          T
        
        /
        sin
      
      ⁢
      
        
      
      ⁢
      θ
    
    =
    
      
        V
        T
      
      /
      
        sin
        ⁡
        
          (
          
            
              π
              2
            
            ×
            
              
                N
                ′
              
              
                
                  N
                  ′
                
                +
                1
              
            
          
          )
        
      
    
  




Therefore, in the AGC circuit 60 of the third embodiment of the present invention, the gain of the VGA 32 can be varied by adjusting the value of N′. A mid/low-speed positive-phase differential comparator 41 and a mid/low-speed negative-phase differential comparator 42 are required for determining the difference between the threshold signal VT and the output signal VOUT accurately, so that the AGC circuit 50 can switch between charging/discharging operations correctly. The costs for the differential comparators can thus be reduced. Also, instead of providing the threshold signals VT′ of distinct amplitudes as in the prior art, the third embodiment of the present invention occupies less circuit space and consumes less power by providing the constant first and second threshold signals VT1 and VT2 (the first and second threshold signals VT1 and VT2 can be set to a constant threshold signal VT simultaneously).
In the present invention, the gain of the VGA can be changed by adjusting the charge/discharge currents using a variable current source. Since only a low/mid-speed differential comparator is required, the manufacturing costs can thus be reduced. Also, by providing a constant threshold signal instead of providing various threshold signals using a DAC, the present invention occupies less circuit space and consumes less power.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

## Claims

1. An automatic-gain control circuit comprising:
a variable-gain amplifier for receiving an input signal and adjusting the input signal based on a gain-factor control signal, thereby generating a corresponding output signal;
a peak-detecting circuit coupled to the variable-gain amplifier for generating a comparing signal based on a reference signal and the output signal;
an adjustable charge/discharge circuit having an input end coupled to the peak-detecting circuit and an output end coupled to the variable-gain amplifier for outputting a charge current or a discharge current based on the comparing signal, thereby generating the gain-factor control signal, wherein a ratio between the charge current and the discharge current is adjustable based on a ratio control signal; and
a current ratio control module coupled to the adjustable charge/discharge circuit for generating the ratio control signal.

2. The automatic-gain control circuit of claim 1 wherein the adjustable
charge/discharge circuit comprises:
a variable charge current source for providing a variable charge current;
a constant discharge current source for providing a constant discharge current;
a first switch for controlling a current transmission path between the variable charge current source and the output end of the adjustable charge/discharge circuit based on the comparing signal; and
a second switch for controlling a current transmission path between the constant discharge current source and the output end of the adjustable charge/discharge circuit based on the comparing signal.

3. The automatic-gain control circuit of claim 2 further comprising:
a capacitor coupled to the output end of the adjustable charge/discharge circuit for generating the gain-factor control signal based on the variable charge current and the constant discharge current.

4. The automatic-gain control circuit of claim 2 wherein the first switch includes a P-type metal oxide semiconductor (PMOS) transistor and the second switch includes an N-type metal oxide semiconductor (NMOS) transistor.

5. The automatic-gain control circuit of claim 1 wherein the adjustable
charge/discharge circuit comprises:
a constant charge current source for providing a constant charge current;
a variable discharge current source for providing a variable discharge current;
a first switch for controlling a current transmission path between the constant charge current source and the output end of the adjustable charge/discharge circuit based on the comparing signal; and
a second switch for controlling a current transmission path between the variable discharge current source and the output end of the adjustable charge/discharge circuit based on the comparing signal.

6. The automatic-gain control circuit of claim 5 further comprising:
a capacitor coupled to the output end of the adjustable charge/discharge circuit for generating the gain-factor control signal based on the constant charge current and the variable discharge current.

7. The automatic-gain control circuit of claim 6 wherein the first switch includes a PMOS transistor and the second switch includes an NMOS transistor.

8. The automatic-gain control circuit of claim 1 wherein the adjustable
charge/discharge circuit comprises:
a variable charge current source for providing a variable charge current;
a variable discharge current source for providing a variable discharge current;
a first switch for controlling a current transmission path between the variable charge current source and the output end of the adjustable charge/discharge circuit based on the comparing signal; and
a second switch for controlling a current transmission path between the variable discharge current source and the output end of the adjustable charge/discharge circuit based on the comparing signal.

9. The automatic-gain control circuit of claim 8 further comprising:
a capacitor coupled to the output end of the adjustable charge/discharge circuit for generating the gain-factor control signal based on the variable charge current and the variable discharge current.

10. The automatic-gain control circuit of claim 8 wherein the first switch includes a PMOS transistor and the second switch includes an NMOS transistor.

11. The automatic-gain control circuit of claim 1 wherein the peak-detecting circuit comprises:
a positive-phase differential comparator coupled to the variable-gain amplifier for differentially comparing a first reference signal with the output signal, thereby generating a corresponding positive-phase comparing signal;
a negative-phase differential comparator coupled to the variable-gain amplifier for differentially comparing a second reference signal with the output signal, thereby generating a corresponding negative -phase comparing signal; and
an operational logic unit coupled to the positive-phase differential comparator, the negative-phase differential comparator and the adjustable charge/discharge circuit for generating the comparing signal based on the positive-phase comparing signal and the negative-phase comparing signal.

12. The automatic-gain control circuit of claim 11 wherein the operational logic unit includes an OR gate.

13. The automatic-gain control circuit of claim 11 wherein the first and second reference signals are identical.

14. The automatic-gain control circuit of claim 1 further comprising a filter coupled between the variable-gain amplifier and the peak-detecting circuit.