# Patent

## Title
Systems with bias offset and gain mismatch removal from parallel transmitted signals

## Abstract

A system includes converters, first modules, second modules, and a multiplexer. The converters receive an analog signal and a respective one of multiple clock signals. Each of the converters samples the analog signal based on a respective clock signal to generate a respective digital signal. Each of the clock signals is out-of-phase with other ones of the clock signals. The first modules receive the digital signals generated by the converters, remove bias offsets from the digital signals to generate first output signals, and output each of the first output signals on a multiple channels. The second modules receive the first output signals, and based on the first output signals, remove or equalize gain mismatch between the channels to generate second output signals. The multiplexer receives the second output signals, and generates an output based on the second output signals. The output is a digital representation of the analog signal.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. patent application Ser. No. 12/924,708, filed Sep. 30, 2010, which is a continuation of and claims priority to U.S. patent application Ser. No. 12/157,452, filed Jun. 9, 2008, now U.S. Pat. No. 7,808,407, which claims priority to U.S. Provisional Application No. 60/934,738, filed Jun. 15, 2007. The entire disclosures of the above applications are incorporated herein by reference.


FIELD
The disclosure relates to data communication and in particular a method and apparatus for mitigating sub-channel distortion in a communication system.
BACKGROUND
There is a continuing demand for electronic systems to operate at higher rates or process greater amounts of data. This often necessitates that data within the electronic system or between remote electronic systems be exchanged or processed at rates greater than that performed by prior systems. As can be appreciated, it may not be possible to achieve such data processing or exchange at the desired rates utilizing methods and apparatus of the prior art. Hence, there exists a need in the art for an ability to increase processing speeds and data exchange rates.
It is common in the area of data processing and exchange to convert analog signals to a digital format for processing, storage, transmission, or the like. As is understood by one of ordinary skill in the art, the analog to digital signal conversion (A/D conversion) is a common procedure and hence, the numerous applications utilizing an A/D conversion are known by those of skill in the art.
As data rate processing and exchange rates increase, so too does the need to perform the analog to digital conversion at higher rates. One proposed solution has been to simply increase the rate at which the A/D converters (ADC) operate to thereby accommodate the increased operating rate. This proposed solution, however, suffers from the drawback that prior art ADCs are limited in speed, and performance suffers as the processing rate increases. Thus, prior art ADCs are simply unable to perform at higher rates while maintaining desired performance levels. Among other reasons, the track and hold operation performed by the ADC may not occur rapidly enough to match the received data rate for a particular performance level.
To address this need in the art, it has been proposed to distribute the processing such that a high data rate signal is split into multiple signals, each of which operate at a data rate that is lower than the high data rate signal. Processing may then occur on these distributed signals. This may be referred to as distributed processing. Although beneficial to reduce the processing rate for each signal, the separation of a high data rate signal into multiple lower data rate signals is not without drawbacks.
One such drawback is that as the signal is separated, such as onto sub-channel, the processing associated with the different paths for the sub-channels may differ from one sub-channel to the next. As a result, the signals on each sub-channel may experience processing variation and hence, certain aspects of the signal may vary across the sub-channels. In particular, each of the sub-channels may vary in the level of gain, DC offset, or skew. The processing variations may occur as a result of differences during the manufacturing process, or because of differences between the clock signals provided to each sub-channel processing path.
Disclosed herein is a method and apparatus to mitigate one or more DC offset, skew and gain offset between signals in a communication device that utilizes distributed processing.
SUMMARY
A system is provided and includes converters, first modules, second modules and a multiplexer. The converters are configured to receive (i) an analog signal, and (ii) a respective one of multiple clock signals. Each of the converters is configured to sample the analog signal based on the respective clock signal received by the converter to generate a respective one of multiple digital signals. Each of the clock signals is out-of-phase with other ones of the clock signals. The first modules are configured to (i) receive the digital signals generated by the converters, (ii) remove bias offsets from each of the digital signals to generate multiple first output signals, and (iii) output each of the first output signals on a respective one of multiple channels. The second modules are configured to (i) receive the first output signals, and (ii) based on the first output signals, remove or equalize gain mismatch between the channels to generate second output signals. The multiplexer is configured to (i) receive the second output signals, and (ii) generate an output based on the second output signals. The output of the multiplexer is a digital representation of the analog signal.
A method is provided and includes receiving (i) an analog signal, and (ii) a respective one of multiple clock signals. The analog signal is sampled based on each of the clock signals to generate digital signals. Each of the clock signals is out-of-phase with other ones of the clock signals. Bias offsets are removed from each of the digital signals to generate first output signals. Each of the first output signals are outputted on a respective one of multiple channels. Based on the first output signals, gain mismatch between the channels is removed or equalized to generate second output signals. An output is generated based on the second output signals. The output is a digital representation of the analog signal.
A system for processing an analog signal to convert the analog signal to a digital signal is disclosed herein. In one implementation, the system includes a time-interleaving analog to digital conversion system includes an input configured to receive an analog signal, two or more analog to digital converters, two or more sub-channel outputs configured to carry the two or more digital signals, a DC offset compensation system, and a multiplexer configured to receive and combine at least one compensated digital signal and at least one digital signal or two or more compensated digital signals to create a digital signal representative of the analog signal.
The two or more analog to digital converters may be configured to convert at least a portion of the analog signal to two or more digital signals. The DC offset compensation system may be associated with at least one sub-channel output, and configured to receive a digital signal and remove bias offset from the received digital signal to create at least one compensated digital signal. It is noted that, in one or more implementations, the bias offset may include the difference in voltage values for a constant input between the digital signals output from the time-interleaving analog to the digital conversion system.
The DC offset compensation system may have various configurations. For example, the DC offset compensation system may include a DC loop. In addition, the DC offset compensation system may include a DC loop associated with each sub-channel and configured to perform DC offset removal on each digital signal from the time-interleaving analog to digital conversion system. Further, the DC offset compensation system may include a feedback filter configured to subtract the DC offset from digital signal.
In another implementation, a parallel analog to digital converter system configured to perform analog signal to digital signal conversion of an analog signal is disclosed. This system may include an input configured to receive an analog signal, two or more parallel analog to digital converters configured to process the analog signal to thereby generate and output two or more digital signals on two or more sub-channels, and at least one DC loop configured to process at least one of the two or more digital signals to remove unwanted offset from at least one of the two or more digital signals. In this implementation, each digital signal outputted by the two or more parallel analog to digital converters represents at least a portion of the analog signal.
It is contemplated that a DC loop may be associated with each sub-channel in some implementations. In addition, a multiplexer may be provided in some implementations to combine the output from each DC loop to create a composite digital signal representing the analog signal. The multiplexer may be configured to accurately combine the digital signals due to the removal of unwanted bias offset by the two or more DC loops. It is noted that the DC loop itself may include an accumulator configured to generate a DC offset value, and a subtractor configured to remove the DC offset value from at least one of the one or more digital signals. A multiplier configured to receive a control value selected to control the rate of change of the accumulator may be provided in one or more implementations.
A method for removing inconsistencies in two or more digital signals from an analog to digital converter structure to enable accurate re-assembly of the two or more digital signals is provided. It is contemplated that these inconsistencies may include DC offsets resulting from differences between analog to digital converters within the analog to digital converter structure.
In one implementation, the method includes receiving two or more digital signals on two or more sub-channels received from the analog to digital converter structure, providing the two or more digital signals to an offset compensation system, and processing the two or more digital signals to remove unwanted DC offset from each digital signal to thereby establish each digital signal at a generally similar DC offset level. It is noted that the two or more digital signals on the two or more sub-channels may be recombined into a single digital signal in some implementations.
Each digital signal on the two or more sub-channels received from the analog to digital converter structure may be associated with a sub-channel. In addition, the offset compensation system may include a DC offset compensation module associated with each channel in some implementations.
In one implementation, the step of processing the two or more digital signals may include multiplying a digital signal by a control value to obtain a scaled digital signal, processing the scaled digital signal to generate an offset value representative of the DC offset generated by the analog to digital converter associated with the sub-channel, and subtracting the offset value from the digital signal to create a digital signal without DC offset. The value of the digital signal may be scaled prior to DC offset compensation to accommodate a fixed point processing environment if desired.
A method for converting a high frequency analog signal to a digital signal is also provided herein. The method may occur within a 10 gigabit communication system operating over CAT 5 cable if desired. In one implementation this method includes providing the analog signal to one or more analog to digital converters, converting the analog signal to two or more digital signals, receiving the two or more digital signals from the one or more analog to digital converters, processing at least one of the digital signals to establish the offset of the two or more digital signals at a generally similar offset level, and combining the two or more digital signal into a combined digital signal. Such combining may accurately occur due to the generally similar offset level of the two or more digital signal. The two or more digital signals received from the one or more analog to digital converters may be associated with two or more sub-channel according to this method. In addition, the processing of at least one of the digital signals may include subtracting a DC offset value, created by inconsistencies between the two or more analog to digital converters, from the digital signal.
According to this method, the offset level may be a generally zero DC offset, combining may be performed by a multiplexor, and a sub-channel gain mismatch compensation may be used to process the signal to remove gain mismatch between sub-channels in addition to processing to remove offset. Various sub-channel configurations are permitted as well. For example, in one implementation, two or more sub-channels includes four sub-channels. In another implementation, two or more sub-channels includes eight sub-channels.
In another implementation of the system, an analog to digital converter system configured to perform analog signal to digital signal conversion of an analog signal is provided. In one implementation, this system includes an input configured to receive an analog signal, two or more parallel analog to digital converters configured to process the analog signal to thereby generate one or more digital signals representing at least a portion of analog signal, two or more sub-channel gain mismatch compensation modules configured to process the digital signal to remove unwanted gain offset from the one or more digital signals to create processed digital signals, and a switch or multiplexer configured to received and combine the processed digital signals to create a signal digital signals representing of the analog signal.
In this implementation, the analog digital converters may be associated with a sub-channel, and the analog to digital converters may be part of a time interleaved analog to digital conversion system. In addition, the sub-channel gain mismatch compensation modules may include an accumulator configured to generate the gain offset value, and a subtractor configured to remove the gain offset value from at least one of the one or more digital signals. A multiplier configured to receive a control value selected to control the rate of change of the accumulator may be provided as well.
Other systems, methods, features and advantages will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description.



BRIEF DESCRIPTION OF DRAWINGS
The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the disclosure. In the figures, like reference numerals designate corresponding parts throughout the different views.
FIG. 1 illustrates a block diagram of an example environment.
FIG. 2 illustrates a block diagram of an example environment.
FIG. 3 illustrates a prior art analog to digital converter.
FIG. 4 illustrates an example implementation of a distributed processing system.
FIGS. 5A through 5C illustrate various plots of signals in various stages of processing and the effect of mismatch between distributed systems.
FIG. 6 illustrates an example implementation of a parallel ADC structure configured to mitigate mismatch between sub-channels or after distributed processing.
FIG. 7A illustrates a block diagram of an example implementation of a DCL.
FIG. 7B illustrates a block diagram of an example implementation of a DCL with dual multipliers.
FIG. 7C illustrates a block diagram of an example implementation of a feed forward configuration for DC offset correction.
FIG. 8A illustrates a block diagram of an example implementation of a sub-channel gain mismatch compensation (SCGMC) system.
FIG. 8B illustrates a block diagram of an example implementation of a SCGMC system with first and second multipliers.
FIG. 9 illustrates a block diagram of an exemplary implementation of a two channel de-skew system configured to eliminate or greatly reduce inter-channel skew.
FIG. 10 illustrates a block diagram of an example implementation of a four channel de-skew system.
FIG. 11 illustrates a detailed block diagram of an example implementation of a four channel de-skew system.



DESCRIPTION
As a solution to the drawbacks in the prior art, disclosed herein is a method and apparatus to minimize DC offset, gain offset, interchannel skew. To overcome the drawbacks of the prior art and to achieve an effective high data transmit rate, an interleaved analog to digital converter is utilized in conjunction with a parallel processing structure to distribute the processing of a received signal. In one implementation, a four-way interleaved analog to digital converter (A/D converter) is utilized such that each A/D converter operates at a clock rate that is lower than would be required for a system utilizing a single A/D converter. In addition, each of the sub-channels may utilize an independent processing path that provides the benefit of operation at a lower effective data rate, which in turn improves accuracy. However, although each processing path is intended and designed to be identical there are differences that exist in the processing path and hence, the effect that the processing has on each signal. Although there is a benefit to be gained by processing each sub-channel individually, these differences in processing result in signal anomalies and evidence themselves as differences in the signals found on each sub-channel. For example, as a result of the interleaved analog to digital conversion and the other distributed processing that occurs as a signal is processed on each sub-channel, unwanted signal mismatch may occur to the signals on the sub-channels. This signal mismatch may include one or more of DC offset, gain offset, and skew.
To overcome the drawbacks of gain offset, DC offset, and skew that may occur as a result of the distributed processing across sub-channels, the sub-channels may utilize one or more of a DC offset correction module, gain offset correction module, and de-skew system. These systems are discussed in more detail below.
Before discussing the particulars of the various implementations of this method and apparatus, a discussion of an example environment of a communication system is provided. While it is contemplated that the method and apparatus described herein may be beneficially utilized in various communication system, it is also contemplated that numerous different systems will benefit from the advantages of the implementations disclosed herein. By way of example and not limitation, the method and apparatus described herein may be utilized in environments where high rate conversion of an analog signal to a digital signal is desired. Thus, environments that may benefit include, but are not limited to, video processing or display systems, computer processing or computer architectures, audio processing systems, communication systems, and/or other systems and environments that utilize a high rate analog to digital conversion process.
Turning now to FIG. 1, an example environment of the method and apparatus is shown as a communication system configured to exchange data between remote locations. A block diagram of a receiver/transmitter pair is shown. A channel 112 connects a first transceiver 130 to a second transceiver 134. The first transceiver 130 connects to the channel 112 via an interface 144. The interface 144 is configured to isolate incoming from outgoing signals and may provide DC isolation. The interface may include a transformer. In one implementation, the channel 112 may include numerous conductors, and hence, the interface 144 may perform isolation or separation of signals on the numerous conductors based on direction of data flow or based on connection to either of a receiver module 138 or a transmitter module 142. The receiver module 138 and transmit module 142 may include an assembly of hardware, software, and/or combination of both configured to: operate in accordance with the principles described herein; operate with various communication systems; and/or satisfy various communication standards.
The receiver module 138 and transmit module 142 communicate with a processor 146. The processor 146 may include or communicate with memory 150. The memory 150 may include one or more of the following types of memory: RAM, ROM, hard disk drive, flash memory, or EPROM and/or other types of memory and registers. The processor 146 may be configured to perform one or more calculations and/or various types of signal analysis. In one implementation, the processor 146 is configured to execute machine readable code stored on the memory 150. The processor 146 may perform additional signal processing tasks as described below.
The second transceiver 134 is configured similarly to the first transceiver 130. The second transceiver 134 includes an interface 152 connected to a receiver module 156 and a transmitter module 160. The receiver module 156 and a transmitter module 160 communicate with a processor 164, which in turn connects to a memory 168.
The transformer configurations and associated circuitry shown and described herein may be located within the interfaces 144, 152 or at another location in the channel 112 or transceivers 130, 134. The transformer configurations and associated circuitry provide isolation between the one or more transmission lines or conductors and the other aspects of the transceivers 130, 134.
It is further contemplated that one or more additional transceivers and channels, shown as additional communication system 180 and shown within the dashed line, may operate in conjunction with the communication system shown at the top of FIG. 1. Each additional communication system 180 may be configured generally similar to that described above and hence, is not described in detail. It should be noted that the methods and apparatus described herein may be utilized in a single or multi-channel environment or in a sub-channel environment. The term sub-channel is defined to mean a separation or division of the content on a channel into two or more sub-channels. Sub-channels may include physically separate channels, or time, frequency, or coding divisions. In one example implementation, each channel of a multi-channel communication system is divided into sub-channels aid in processing.
FIG. 2 illustrates yet another example environment. It should be noted that these example environments should not be considered as the only type systems that will benefit from the principles disclosed and claimed herein. It is contemplated that numerous high, low, or mid-frequency applications will benefit from the teachings of this patent. The communication system illustrated in FIG. 2 is configured as an exemplary multi-channel point-to-point communication system. One exemplary application is a 10 gigabit transceiver utilizing a Category 5 UTP cable supporting Ethernet protocols. As shown, it includes physical coding sublayers 202 and 204, shown as coupled over a channel 212. In one implementation, each channel includes twisted pair conductors. Each of the channels 212 is coupled between transceiver blocks 220 through line interfaces 208 and 206. Each channel is configured to communicate information between transmitter/receiver circuits (transceivers) and the physical coding sublayer (PCS) blocks 202, 204. Any number of channels and associated circuitry may be provided. In one implementation, the transceivers 220 are capable of full-duplex bi-directional operation. In one implementation, the transceivers 220 operate at an effective rate of about 2.5 gigabits per second thereby providing a 10 gigabit effect transfer rate. It is further contemplated that the channels 212 or the content on a channel may be further divided, separated, or allocated into sub-channels to achieve desired processing.
FIG. 3 illustrates a prior art analog to digital converter (ADC) 300. As shown, an input 304 defined by an analog input signal X(t), arrives at the ADC 300. Based on the timing of the clock signal CLK on clock input 308, the ADC 300 generates a corresponding digital signal on output 312. The output signal is defined by X0, X1, X2, X3, X4, X5, . . . As discussed above, due to physical limitations, the ADC 300 may be unable to operate at the desired processing rate with the desired performance level. As a result, the structure of FIG. 4 may be utilized to distribute the processing of an analog to digital converter.
FIG. 4 illustrates an example implementation of a distributed analog to digital converter in accordance with the method and apparatus described herein. As shown, the input 304 provides an analog signal X(t) to a wide band front end (WBFE) 404. The WBFE 404 performs processing on the received signal. The output of the WBFE 404 feeds into two or more ADC's 408A, 408B, 408C, . . . 408N where N is any positive integer. Each ADC 408 may receive a clock signal defined by C0, C1, C2, CN. The clock signal, is generated from a primary clock C(t) 430 which may feed into the WBFE 404 and to a splitter 440. The splitter 440 is configured to divide the clock signal to create sub-clock signals, or generate sub-clock signals that are related to the primary clock 430. In one implementation, the splitter 440 includes phase splitter, one or more PLL with frequency dividers, and/or other device capable of accurately generating one or more sub-clock signals.
It is contemplated that the sub-clock signal, hereinafter clock signal, may have a phase that is N degrees out of phase relative to at least one of the other clock signals and hence, each ADC 408 may operate on a different portion of signal X(t) as compared to the other ADCs. For the example of a primary clock being used to reference four sub-clock signals, the primary clock signal may be written as:



  
    
      C
      h
    
    =
    
      C
      ⁡
      
        (
        
          
            t
            N
          
          -
          
            
              2
              ⁢
              n
              ⁢
              
                
              
              ⁢
              π
            
            N
          
        
        )
      
    
  




  
    
      where
      ⁢
      
        
      
      ⁢
      n
    
    =
    
      
        0
        ⟶
        n
      
      -
      1
    
  



And, the four independent sub-clock signals may be written as:



  
    
      C
      0
    
    =
    
      C
      ⁡
      
        (
        
          t
          4
        
        )
      
    
  




  
    
      C
      1
    
    =
    
      C
      ⁡
      
        (
        
          
            t
            4
          
          -
          
            π
            2
          
        
        )
      
    
  




  
    
      C
      2
    
    =
    
      C
      ⁡
      
        (
        
          
            t
            4
          
          -
          π
        
        )
      
    
  




  
    
      C
      3
    
    =
    
      C
      ⁡
      
        (
        
          
            t
            4
          
          -
          
            
              3
              ⁢
              π
            
            2
          
        
        )
      
    
  



where each clock is 90 degrees out of phase.

As a result, the output of the ADCs 408 include digital signals that represent the analog signal yet which are spread over the N number of channels as shown based on the sub-clock signals. Thus, the first sub-channel 420 outputs samples X0, X4, X8 . . . , while the second sub-channel 424 outputs digital samples X1, X5, X9 . . . . The outputs on the sub-channels continue in this manner to thereby divide the signal X(t) into N number of parallel channels based on the individual but related sub-clocks.
In one example implementation, there exist four A/D converters per channel 304 and each clock C/N has a 90 degrees shift such that the four clock signals are 90 degrees out of phase. This may also be referred to as a polyphase component clock signal. This results in each ADC sampling a different portion of the analog signal and allows each ADC to operate at a lower rate than in the implementation of FIG. 3. Sampling may occur on the rising clock edge or the falling clock edge. This overcomes the drawbacks of the prior art thereby allowing the received signal to be converted with great precision into a digital signal.
It is fully contemplated that additional processing apparatus, which is not shown, may be present in the system of FIG. 4 to achieve desired processing. In addition, one or more of the signal paths shown in FIG. 4 may represent two or more parallel conductors.
Thus, the single high rate ADC of the prior art may be replaced by two or more parallel ADC that reduce the required rate of operation for each ADC. This allows the ADC system, shown by parallel ADCs 408 to achieve processing rates and performance levels that may meet specification. Notwithstanding the drawback discussed herein, such a configuration provides the benefit of low cost system capable of processing a high speed signal.
In addition to interleaved analog to digital conversion, additional processing may occur in distributed fashion across the N number of sub-channels. However, during the A/D conversion and during subsequent processing, unwanted mismatch differences may develop on each of the sub-channels that can interfere with subsequent processing, such as where interaction or interface between the sub-channels is necessary, or if it is necessary to recombine the sub-channels into a unified signal that is in either a serial or parallel format.
In one example implementation, the system is configured to operate in an Ethernet environment utilizing four channels, each of which includes twisted pair conductors. In this implementation, each channel may be divided into four or more sub-channels. Thus, in an implementation using four sub-channels per channel, sixteen ADC would process the signals received over the four twisted pair conductors to achieve the desired performance and processing rate. In another implementation, each channel is divided into 8 ADC sub-channels thereby utilizing 32 ADCs.
As can be appreciated, with sixteen parallel sub-channels, each having similar, but independent, processing paths, it is likely that variations may exist between the signals on each of the sixteen channels due to differences in each processing path, device behavior, clocking differences, and/or a variety of other factors.
While the implementation of FIG. 4 is an improvement over prior art systems that utilize a single A/D converter, it still suffers from the drawback of having signal mismatches that are generated as a result of the distributed processing. In reference to FIG. 4, each output from the ADC 408A, 408B, 408C, . . . 408N is processed by a different ADC and undergoes separate subsequent processing in devices 410. As a result, there may be minor differences between the output signals that make subsequent processing or recombination challenging or infeasible. The devices 410 may include a processing device.
By way of example and not limitation, the ADC 408 may suffer from minute differences as a result in variations in the manufacturing process, each ADC 408 and subsequent processing devices 410 may operate different based on changing temperature, or due to differences that may exist due to the variation in the manufacturing process. In turn, the output signal from each ADC 408 and the subsequent processing devices may not be identical, even though generated by an identical input signal. In systems requiring precision, the differences may be sufficient to impede subsequent processing or successful recombination, such as in a re-combination unit. For example, the parallel ADC 408 and the subsequent processing units 410 may cause the signal to suffer from gain offset or gain error, bias offset or DC offset, and skew mismatch.
To aid in understanding, gain offset includes differences between the gain levels, i.e. magnitude, of each output signal. In short, each of the processing paths, i.e. the combined effects of the ADC 408 and the subsequent processing devices 410, may generate a signal having a different magnitude as compared to the signal on the other paths. Thus, in a parallel processing system, the difference in gain between the parallel processing path creates signal mismatches that could hinder subsequent processing and/or recombination of the signals on the sub-channels.
FIGS. 5A-5C illustrate exemplary signal mismatches that may result from gain offset, DC offset, or skew. FIG. 5A shows a plot of an exemplary desired digital output signal. As can be seen, the signal portion 504 is generally constant over time.
As shown in FIG. 5B, the signal 504 when parallelized onto sub-channels may be represented as two or more outputs 512, 516, 520, 524 of a parallel ADC structure or subsequent processing devices. FIG. 5B illustrates an ideal representation of the signal that has been divided into four portions, as would be present on the four sub-channels, if recombined. Hence, the original signal 504 is now shown in an ideal or desired format as being divided into signal portions 512, 516, 520, 524 by the signal outputs shown in FIG. 5B. These signal portions 512, 516, 520, and 524 may be generated by different, but parallel processing paths. Although the four portions 512, 516, 520, 524 are shown as ideal output values, i.e. they are all perfectly matched, in actual practice, the different processing paths, and the processing on these paths, results in mismatches in these signals.
Thus, in actual practice, the signal on a processing path may suffer from signal mismatch, as compared to the signals on the other processing paths, which may be referred to as sub-channels. These signal mismatches may lead to errors when performing subsequent processing or re-combining the signals on the sub-channels.
FIG. 5C illustrates an example of a signal generated as a result of re-combining signals suffering from mismatch. As can be seen, the signal portions 530, 534 are not generally consistent (smooth) over time since each of the sub-channels may have different gain offset, bias offset, or skew.
In addition, signal portions 530, 532 vary in magnitude over time. Hence, there is a gain offset or DC offset 540 shown between adjacent signal portions 530, 532. Skew is shown by the non-vertical transition 544 between logic values. Thus, the final output after combination of the sub-channel signals varies over time. This problem, when the precision requirements of the communication system are increased, leads to errors, undesired operation, and degradation in performance.
Stated another way, if each output of each of the four ADCs is defined by a gain value gx where x represents the particular ADC and each ADC generates a value per clock cycle then the output signal, if recombined may consist of four different output values for an identical input, such as g1, g2, g3, g4. Thus, when recombined the resulting signal may undesirably consist of four different values. This problem is made worse when the number of parallel ADCs is increased or when the number of samples contributed from each ADC is increased.
An additional possible consequence of the processing done by the implementation shown in FIG. 4 is bias offset. In contrast to gain offset, which affects the magnitude of a sample's positive and negative swing, bias offset shifts the entire signal. Hence, a signal suffering from bias offset is shifted in magnitude in the bias offset direction. It is contemplated that both positive and negative sample values may be biased in the direction of the bias offset. It is also contemplated that each processing path may introduce a different bias offset. Bias offset hinders system operation by causing each of the processing paths to output different values in response to an identical input signal.
It is contemplated that as a result of the distributed ADC processing, and the other processing that occurs independently on each sub-channel, one or more of the signals within the communication system may be out of phase. For example, in a multi-channel communication system, skew may be undesirably introduced which in turn disturbs the phase relation between the signals on the multiple channels. In addition, if a channel is interleaved into sub-channels, then skew may also be introduced across the signals on the sub-channels. The skew may be introduced or exist for numerous reasons including, but not limited to, interleaved analog to digital conversion, and/or clock errors. For example, it may be not be possible, expensive or complex to generate sub-clock signals that are exactly in phase or to create ADCs that operate exactly identical. In some instances, the manufacturing process of the integrated circuits may create a mismatch. The solution disclosed herein may find use in various environments and address skew, regardless of the source or cause of the skew.
To overcome the skew that may exist between channels, it is contemplated that the structure of FIG. 9 may be adopted to adjust the phase of the signals on the sub-channels. FIG. 9 illustrates an exemplary two channel de-skew implementation configured to eliminate or reduce inter-channel skew. Although shown in a two channel environment, it is contemplated that this concept for skew correction may be expanded to any number of channels. In general, one or more filters are utilized to process the signals to remove unwanted skew. In one implementation, one or more filters are associated with each channel and configured to perform de-skew processing. As an advantage, certain filters may already be provided within a communication system to perform signal processing that mitigates signal anomalies other than skew. Modification of these filters or adding additional filters may provide for de-skew processing. This departs from prior art motivations which generally avoid increasing the complexity of a communication system by adding one or more additional filters and/or delays to the processing associated with the channels or sub-channels. In addition to the other novel aspects disclosed herein, use of one or more digital filters configured as FIR filters or IIR type filters to perform de-skew processing is considered an improvement over prior art methods.
As shown in FIG. 9, a time-interleaved ADC 900 is configured to receive and process an analog signal SA to create a digital signal S.sub.D0 and S.sub.D1 which are associated with channel 0 and channel 1 as shown. A clock signal C(t) 904 may be provided to the time-interleaved ADC 900 as shown or generated within the ADC. The operation of the time-interleaved ADC 900 is described above and hence, not described again other than the analog signal is time-interleaved into two output signals SD0 and SD1. It is contemplated that other processing devices, which are not shown in FIG. 9, may be associated with each channel or sub-channel and that these additional processing devices may also introduce the skew between signals.
The digital signals S.sub.D0 and S.sub.D1 are provided to one or more de-skew filters 910, 914, 918, 922. In particular, filter H00(z) 910 and filter H10(z) 914 process signal SD0 while filter H01(z) 918 and filter H11(z) 922 process signals SD1. The filters 910, 914, 918, 922 may include various types of filters or other signal processing devices configured to modify the phase or amplitude or both of the output from the time interleaved ADC 900. In one implementation, the filters 910, 914, 918, 922 include digital filters configured as FIR filters or IIR filters, or a combination thereof. In addition, the filters 910, 914, 918, 922 may possess any number of taps or filter coefficients depending on the particular application and desired resolution. In one implementation, the coefficient(s) include a scalar capable of modifying the phase and magnitude of a signal. In one implementation, the filters 910, 914, 918, 922 are configured to mitigate inter-channel skew. In one implementation, the system shown in FIG. 9 is configured as part of a communication system and also configured to account for intersymbol interference that occurs during transmission of the analog signal through a channel. Thus, the filter structure shown in FIG. 9, may be configured to mitigate the effects of the signal's transmission through the channel, and also be configured to mitigate skew.
The output of filter 918 feeds into a delay 930 which in turn have a delayed output that feeds into a junction 932 that is configured to combine the output of the delay 930 and the output of filter 910. The resulting signal is provided on output 940 and includes a digital signal representing SD0 but which will not suffer from skew in relation to the other channel(s) after processing of the other channel(s). A junction 936 combines the output of filter 914 and filter 922 to create a signal on output 944 representing the signal SD1 but which does not suffer from skew in relation to the other processed channel. The junctions 932, 938 may be configured as summing junctions.
In operation, after time interleaved A/D conversion and other processing, the digital signals SD0 and SD1 may suffer from skew in relation to each other and hence, it may be desired to remove such skew to achieve desired processing or to eventually re-combine the signals into a single high rate digital signal or both. The signals SD0 and SD1 may be considered as containing even and odd samples, respectively. In one implementation, prior to operation, the filters 910, 918 are trained concurrently or as a pair while filters 914, 922 are also trained concurrently or as a pair. As a result, the coefficients of the filters are selected to modify a received signal to thereby generate outputs, that when combined, reduce or eliminate skew between channels. It is further contemplated that the filters 910, 914, 918, 922 may also be configured to account for and mitigate intersymbol interference. Various types training or adaptation may be utilized, such as, but not limited to, adaptation utilizing the least mean square algorithm. Adaptation and training of filters is understood by those of ordinary skill in the art, and hence, is not discussed in detail herein.
During operation and after training, signal SD0 is provided to de-skew filter 910 and de-skew filter 914. In such an implementation, the filter 910 is configured to precisely adjust the phase of the received signal SD0 to account for skew originating in channel 0. As such, filters 910 have a transfer function H00(z) which is defined as a transfer function that accounts for or mitigates phase error affecting channel 0 (victim) and which originates from channel 0 (source). Similarly, filter 918 is configured with a transfer function H01(z) which is defined as a transfer function that accounts for or mitigates phase error affecting channel 0 and originating from channel 1. Filter 918 is configured to modify the signal SD1 such that when combined with the output of filter 910, the resulting signal does not suffer from skew as compared to the signal on output 944. The delay 930 serves to align the samples for combination at junction 932 to account for the delay that may originate in the filters 910, 914, 918, 922 or other element.
To generate the signal on output 944, filter 914 processes signal SD0 while filters 922 process SD1. As described above, together these filters modify the received signals such that when the filter outputs are combined the resulting signal output from junction 936 does not suffer from skew as compared to the signal on output 940. In one implementation, the filters are operating in a polyphase format and, as such, it is beneficial to receive filtered input from the other channels to thereby reconstruct the signal associated with a particular channel, based on all the received signals. By receiving the input from the other channels, the desired signal may be modified as desired thereby overcoming effects of processing at a sub-sampling rate.
In various other implementations, it is contemplated that the one or more filters may be configured to adjust the amplitude or other aspects of the signals SD0 and SD1. It is also contemplated that these principles may be applied to any number of channels and hence, although two channels are shown, it is contemplated that this principle may be applied to greater than two channels without departing from the scope of the claims that follows. As a result of the processing shown and described in conjunction with FIG. 9, the high speed analog signal may be accurately and precisely converted to two or more time-interleaved digital signals and the resulting time-interleaved digital signals may be subsequently processed to remove unwanted skew and/or other anomalies.
FIG. 10 illustrates a block diagram of an example implementation of a four channel de-skew system. As shown, an analog signal SA is provided to a time interleaved analog to digital converter and/or other processing device 1004 that is configured to convert a high speed analog signal into a greater number of time-interleaved digital signals. In this example implementation, the single analog input is interleaved into four sub-channels as shown here. Although not shown, it is contemplated that additional processing may be performed on each sub-channel and that this processing may also introduce skew across the signals on the channels and/or sub-channels. Other signal anomalies may also be introduced. The output of the time-interleaver 1004 includes four digital signals SD0, SD1, SD2, SD3. This process is described above in greater detail and hence, not described again.
Although the four signals SD0, SD1, SD2, SD3 represent the analog signal, each of the signals is intended to be out of phase in relation to another signal by 90 degrees (corresponding to a four sub-channel interleaving), but due to skew, each signal may not be out of phase by the proper amount from any of the signals on the other channels. For example, there may be 88 degrees or 89 degrees phase mismatch between signals on adjacent channels instead of 90 degrees. As a result, it is desired re-align the signals to eliminate or greatly reduce the skew.
As shown, each of the signals SD0, SD1, SD2, SD3 is routed to de-skew systems 1010, 1014, 1018, 1022. In particular, the signal SD0 is routed to each de-skew system 1010, 1014, 1018, 1022. The notation shown as SD10 represents that the digital signal SD0 is routed from channel 0 to the de-skew system associated with channel 1. Likewise, the signal routing path SD31 represents a routing of signal SD1 from channel 1 to channel 3.
The de-skew systems 1010, 1014, 1018, 1022 are configured to uniquely process the received digital signals SD0, SD1, SD2, SD3 to thereby generate signals that do not suffer from skew as compared to the other signals. As a result, the de-skew system output is out of phase by the desired amount.
In one implementation, the de-skew systems 1010, 1014, 1018, 1022 include a combination of one or more filters, summing or subtracting junctions, and one or more delays. In other implementations, it is contemplated that the de-skew systems 1010, 1014, 1018, 1022 may include a processor and associated software and/or other device or system. Although not shown, communication may occur between de-skew systems. It is further contemplated that the de-skew systems 1010, 1014, 1018, 1022 may be further configured to mitigate other distortion or inconsistencies between the digital signals SD0, SD1, SD2, SD3 such as, but not limited to, differences in amplitude, gain, or bias settings, or deal with intersystem interference or other signal distortions.
The output of the de-skew systems 1010, 1014, 1018, 1022 include digital signals S′D0, S′D1, S′D2, S′D3 which due to the processing of the de-skew systems 1010, 1014, 1018, 1022 include the digital signals SD0, SD1, SD2, SD3 but without the unwanted skew between channels.
FIG. 11 illustrates a detailed block diagram of an example implementation of a four channel de-skew system. This is but one example implementation and it is contemplated that one of ordinary skill in the art may arrive at other implementations that differ from this implementation yet do not depart from the claims that follow. To aid in understanding, a single channel is described in detail. The other channels are generally similar in construction, although the filters H associated with a channel may have different coefficient values. The structure shown may be provided for other channels, and this concept may be expanded to any number of channels. Although not shown, it is contemplated that a time interleaved analog to digital converter and/or other processing system may provide the signal signals SD0, SD1, SD2, SD3 to the de-skew system of FIG. 11.
In reference to a channel 0 system 1104, an input SD0 is provided to a filter bank 1108. In the implementation shown in FIG. 11, the filter bank 1108 includes a filter configured to process the signal SD0 to create a signal tailored for each of the channels 0-3. Thus, filters in the filter bank 1108 generate outputs includes a processed version of the signal SD0 and these outputs are tailored by the filters in the bank 1108 to mitigate skew between signals on the channels. For example, the output of filter H00 includes the primary components of the signal SD0 with an optional degree of processing. Filter H10 generates an output includes a processed version of the signal SD0 that is tailored to supplement or modify the signal on channel 1. Filter H20 generates an output includes a processed version of the signal SD0 that is tailored to supplement the signal on channel 2. Filter H30 generates an output includes a processed version of the signal SD0 that is tailored to supplement the signal on channel 3.
The output of filter H00 is provided to a junction bank 1120, which may include summing junctions. The bank 1120 includes one or more junctions configured to combine the output of filter H00 with the supplementing signals from the other channels, in this implementation, channels 1, 2, and 3.
A delay 1124 provides a delayed version of a filtered version of signal SD1 to the junction bank 1120. A delay 1128 provides a delayed version of a filtered version of signal SD2 to the junction bank 1120. A delay 1132 provides a delayed version of a filtered version of signal SD3 to the junction bank 1120.
The output of the junction bank 1120 includes a modified version of the signal SD0. The configuration of filters, summing junctions, and delays associated with the other channels 1-3 is generally similar to that described for channel 0 and thus, is not described in detail.
After processing occurs in this manner shown for each of the channels and through appropriate training and adaptation of the filters Hxx, the resulting signals on outputs 1140, 1144, 1148, 1152 do not suffer from skew or skew is greatly reduced. The amount of skew may be controlled by the complexity of the filters H and the particular needs of the system.
In operation, the filters are trained to generate signals, which when combined with the filtered signals from the other channels in the junction banks, and delayed as shown to maintain alignment between time-interleaved samples, do not suffer from skew. This results in a known and intended amount of phase difference between sub-channels. In one implementation, the filters H00, H01, H02, and H03 are trained together to generate the desired signal on output 1140. Training may occur based on the error term of a decision device, such as a slicer (not shown in FIG. 11) which may be fed back from subsequent signals. For example, in certain implementations a phase error feedback signal may be generated and fed back for training and adaptation. In addition, the filters may be trained to account for or mitigate other unwanted distortion such as, but not limited to, gain mismatch resulting from the time-interleaved ADC or inter-symbol interference.
It is also contemplated that in addition to skew mismatch between signals on different channels, other factors may undesirably affect the signals. For example, gain mismatch and DC offset may be present.
FIG. 6 illustrates an example implementation of a communication system configured with gain offset and DC offset mitigation. In comparison to FIG. 4, similar elements are identified with identical reference numbers. In this example implementation, a channel is divided or interleaved into two or more sub-channels. As shown, the input signal X(t) is first processed by the WBFE 404 and then provided to a device 600 configured to perform time interleaved ADC and/or other processing. It is contemplated that in the implementation shown, the device 600 may include four ADCs and each ADC may operate at a rate that is less than the rate of the input signal X(t). In one implementation, the rate is 1/Nth the rate that would be required if a parallel processing arrangement was not adopted where N is the number of sub-channels.
The output of the processing device 600 feeds into a DC loop (DCL) 604A, 604B, 604C, . . . 604N, where N represents the number of sub-channels and may include any positive integer. A DCL 604 includes processing apparatus configured to remove or mitigate the bias offset from a signal on each sub-channel. By removing the bias offset, accuracy is improved during subsequent processing and signal recombination, if so desired, may be achieved. The term bias offset is defined to mean a difference in the bias level as compared between the sub-channels, differences in bias level as compared to a reference value, or both. The method and apparatus described herein may be configured to mitigate or remedy all forms of bias offset.
In one implementation, the DCL 604 estimates the mean of the signal and, based on the mean, removes the unwanted bias offset from the signal, which is to say removes signal portions that vary from the mean. In one implementation, the DCL is implemented as a high order filter. Example implementations of DCLs 604 are shown and discussed below.
In this example implementation, the output of the DCL 604 is provided to and processed by two or more sub-channel gain mismatch compensation modules (SCGMC) 608A, 608B, 608C, . . . 608N. The SCGMCs 608 are configured to mitigate or remove the gain offset from each channel. The gain offset may include differences in gain between sub-channels, differences as compared to a reference value, or both. Details regarding the SCGMC 608 are discussed below in greater detail.
The output of the two or more SCGMC 608 may connect to or eventually feed into a digital signal processor 624. Due to the nature of the processing within the DSP 624, it is desired to minimize or eliminate bias offset and gain offset prior to processing by the DSP 624 or other device. This is particularly true if the signals on the multiple channels are to be recombined, or if processing across channels is to occur.
It is also contemplated that the output of the two or more SCGMC 608 may connect to or eventually feed into a multiplexer for recombination into a single signal. In one implementation, the multiplexer processes the N number of sub-channels into fewer than N channels. In one implementation, the N sub-channels are mixed into a single channel for subsequent processing by the DSP 624. Due to the processing by the devices 600, DCLs 604, and SCGMCs 608, the signal output from the MUX is an accurate digital format representation of the signal X(t).
This is but one example implementation of a multiple sub-channel structure with bias offset and gain offset mitigation. It is contemplated that one of ordinary skill in the art may generate alternative implementations that do not depart from the claims. It is contemplated that the implementation of FIG. 6 may be implemented with only the DCLs 604 or only the SCGMC 608 based on the distortion contained in the output of the time interleaved ADC 600.
As an advantage to the structure shown in FIG. 6, the DCL 604 and the gain mitigation devices 608 may be shared between both the DSP 624 and the ADC and associated processing. By sharing the devices 604, 608, the gain offset and bias offset associated with sub-channel processing may be mitigated. As compared to an alternative implementation which may associate bias offset and gain offset with both the ADC aspects and the DSP, the implementation of FIG. 6 utilized a shared structure to achieve generally identical or equivalent processing benefits and effect while reducing components.
Turning now to FIG. 7A, an example implementation of a DCL is shown. This is but one example implementation and it is contemplated that one of ordinary skill in the art may be able to enable a DCL that differs from this particular implementation yet does not depart from the scope of the claims. As with all implementations and systems shown herein, the paths within the DCL and the accumulator 712 may include two or more parallel conductors or connections. The DCL receives a signal Xn on input 704. Input 704 feeds into a junction 708. The junction 708 includes a device configured to combine two or more signals, either by addition, subtraction, or some other manner. The junction 708 also receives an input from an accumulator 712, shown in a dashed line enclosure, which is discussed below in more detail.
The output of the junction 708 is provided as an output signal Yn on output 716 and as an input to a multiplier 724. The multiplier 724 also receives as an input a value a where a represents a control value that determines the rate of change of the accumulator 712. In one implementation, the multiplier 724 and value a control the rate of training of the accumulator. The value of α may change over time. In another implementation, the control value α is provided to an accumulator 712. The multiplier output connects to or is in communication with the accumulator 712 as shown.
The accumulator 712 is now described. In this example implementation, the accumulator 712 includes a junction 730 configured as a summing junction and a delay element 734. The output of the multiplier 724 feeds into the junction 730. The junction 730 also receives as an input a feedback signal from the delay 734. The output of the junction 730 feeds into the delay element 734, the output of which is the input to the junction 708. At junction 708, the accumulator output is subtracted or removed from the incoming signal Xn.
During operation of this example implementation, the incoming signal is desired to have a mean signal value of zero and a bias offset of zero. Thus, the DCL as shown in FIG. 7 removes the bias offset. An incoming signal Xn arrives on input 704 at the junction 708, where the accumulator value is subtracted. Assuming at start-up the accumulator value is zero, the output of the junction 708 is then equal to Xn. The Xn value is provided to the multiplier 724 where it is reduced, increased, or otherwise modified in relation to α and provided to junction 730 within the accumulator 712. The feedback from the delay at this point in operation is zero, unless the delay is preloaded. Over time the accumulator 712 generates a value that approximates the bias offset due to the feedback delay structure. The bias offset is then subtracted from the incoming signal Xn in the junction 708. In this manner, the bias offset is removed from the signal Xn thereby maintaining a mean of zero for Xn over time as desired. When applied to each output of the time interleaved ADC, the bias is removed from each sub-channel, which in turn provides the benefits described herein. In one implementation, this provides for an accurate combination of the parallel sub-channels to create a combined output signal that has a uniform and consistent output value for a given input value.
FIG. 7B illustrates an example implementation of a DCL with dual multipliers. The implementation of FIG. 7A may be ideally suited in a floating point environment whereas the implementation shown in FIG. 7B may be ideally suited to a fixed point environment. The term floating point defines an environment. The decimal point in a numeric value may float thereby allowing for representation of very small numbers. In contrast, the term fixed point defines an environment where the decimal point in a numeric value is fixed at a particular point thereby making the representation of very small numbers challenging. As a result, the system of FIG. 7B scales a small number to a larger value to achieve desired processing and thereafter rescale the processed numeric value to a small value. The concept of fixed point and floating point numeric representations are known in the art and hence, not described in great detail herein. As compared to FIG. 7A, identical elements in FIG. 7B are identified with identical reference numerals. In addition, only the aspects of FIG. 7B that differ from FIG. 7A are discussed.
In contrast to FIG. 7A, the implementation of FIG. 7B includes a second multiplier 750 located between the accumulator 712 and the junction 708. In this implementation, the control value provided to the first multiplier 724 includes α1 and the control value provided to the second multiplier 750 includes α2 The second multiplier 750 utilizes the value α1 to scale the output of the accumulator 712. In one implementation, the control value α1 represents a value greater than one that increases the value of the feedback provided to the accumulator 712. This increases this value so that processing may occur without rounding errors or multiplication operations that result in zero values. Then after processing by the accumulator 712, the second control value α2 reduces the feedback value back to the appropriate level for combination in the summing junction 708. It is contemplated that the second multiplier 750 may also include a divider, which may be made to have a similar function to a multiplier, or other apparatuses or devices configured to achieve the goals set forth herein.
FIG. 7C illustrates an example implementation of a feed forward configuration for DC offset correction. An input 754 connects to a mean value estimator 758 and a junction 762. The mean value estimator 758 includes a device configured to calculate the mean value of the signal Xn received over input 754. In one implementation, the mean value estimator 758 includes, alone or in any combination, a processor, logic, ASIC, subtractor, comparator, summing junction, control logic, software code, or any other element as would be understood in the art to perform the desired function. The output of the mean value estimator 758 is subtracted from the received signal X.sub.n in the junction 762 to thereby remove the unwanted DC offset from Xn to yield the output signal Yn on output 766.
It is contemplated that the mean value estimator 758 may reside in or be associated with one or more of the two or more sub-channels to thereby remove the unwanted and differing levels of DC offset from each sub-channel. In this manner, the sub-channels may be combined after parallel processing.
FIG. 8A illustrates an example implementation of a sub-channel gain mismatch compensation (SCGMC) system. The SCGMC removes or equalizes gain mismatch between the signals on the sub-channels. This is but one possible configuration and thus, the claims that follow should not be limited to this particular configuration. An input 804 provides a signal Xn to a junction 808. The junction 808 includes a device configured to combine two or more signals. The junction 808 also receives an input from an accumulator 812, shown within the dashed line enclosure. The output of the summing junction 808 is provided as signal Yn on output 816 and as an input to an absolute value module 820. The absolute value module 820 calculates or generates the absolute value of a received signal. The output of the absolute value module 820 feeds into a junction 822, which also receives as an input value T. T represents a threshold value selected as a gain convergence point such that the value of T is the value at which the accumulator converges to over numerous cycles or iterations.
The output of the junction 822 arrives at a multiplier 824. The multiplier 824 also receives as an input a value α where a represents a control value to determine the rate of change of the accumulator 812. In one implementation, the multiplier 824 and value α is used to control the rate of training or rate of change of the accumulator 812. In another implementation, the control value α is provided directly into the accumulator 816. The multiplier output connects to or is in communication with the accumulator 812.
The accumulator 812 is now described. In this example implementation, the accumulator 812 includes a junction 830 and a delay element 834. As discussed above, all the paths within the SCGMC and the accumulator 812 may include two or more parallel conductor or connections. The output of the multiplier 824 feeds into the junction 830. The junction 830 also receives as an input a feedback signal from the delay 834. The output of the summing junction 830 feeds into the delay element 834, the output of which is the input to the junction 808. In junction 808, the accumulator output is subtracted or removed from the incoming signal X.sub.n.
The operation of the SCGMC is generally similar to the operation of the DCL described above. It is contemplated that any level of gain may be desired, or no gain at all, and, as such, the SCGMC may match, across the different signals on the sub-channels, the level of gain associated with each sub-channel corresponding to the output of the two or more parallel ADCs or a time interleaved ADC system, such as that shown in FIG. 6.
Accordingly, during operation, an incoming signal Xn arrives on input 804 at the junction 808, where the accumulator output value is subtracted. Assuming at start-up the accumulator value is zero, the output of the junction 808 is then equal to Xn. The Xn value is provided to the absolute value module 820. The absolute value module 820 generates a representation of the received signal. Negative portions of the received signal are converted to positive values having generally similar or identical positive magnitudes. The positive values from the absolute value module 820 are combined with the threshold value T in the summing junction 822 and the resulting output is provided to the multiplier 824 and modified by the control value α. The threshold value T added to the feedback sets the gain on the sub-channel output 816. In this manner, all of the sub-channels may be established at the same gain level to facilitate combination of the sub-channels into a single channel, for subsequent processing, or both. The gain level may be adjusted relative to the other sub-channels or other reference value.
Thereafter, the multiplier output is provided to the accumulator 812. The feedback to the junction 830 from the delay 834 at this stage is zero, unless preloaded with a value. Over time the accumulator 812 generates a value that approximates the gain offset on the sub-channel. This gain offset is added to the incoming signal Xn in the junction 808. In this manner, the gain offset is established and may be made constant across two or more sub-channels.
FIG. 8B illustrates an example implementation of a SCGMC system with first and second multipliers 824, 850. The implementation of FIG. 8A may be ideally suited in a floating point environment whereas the implementation shown in FIG. 7B may be ideally suited to a fixed point environment. The concept of fixed point and floating point numeric representations are described above and known in the art and hence not described in great detail. As compared to FIG. 8A, identical elements in FIG. 8B are identified with identical reference numerals. In addition, only the aspects of FIG. 8B that differ from FIG. 8A are discussed.
In contrast to FIG. 8A, the implementation of FIG. 8B includes a second multiplier 850 located between the accumulator 812 and the summing junction 808. In this implementation, the control value provided to the first multiplier 824 includes α1 and the control value provided to the second multiplier 850 includes α2. The second multiplier 850 utilizes the value α2 to scale the output of the accumulator 812. In one implementation, the control value α1 represents a value greater than one to thereby increase the value of the feedback provided to the accumulator 812. This allows processing to occur utilizing the available numeric range of a fixed point representation used for processing within the accumulator 812. By way of example, this scaling may prevent rounding errors or multiplication operations that yield values of zero.
After processing by the accumulator 812, the second control value α2 reduces the accumulator output to an appropriate level for combination in the junction 808. In one implementation, the control value α2 includes a value that is less than one to re-scale the accumulator output. It is contemplated that the second multiplier 850 may also include a divider, which may be made to have similar function to a multiplier, or other apparatus or device configured to achieved the goals set forth herein.
In one implementation, the values of α1 and α2 as shown in FIG. 8A may be set equal to value of α1/α2. In other implementations, the values of α1 and α2 may set to other values as can be calculated by one of ordinary skill in the art.
It is further contemplated that any of the above-described solutions for dealing with signal distortion or inconsistencies between sub-channels after analog to digital conversion, or other aspect of signal processing disclosed herein, may be enabled in combination or individually. Thus, the de-skew systems, DCL systems, and SCGMC system may be embodied individually in a system or in any combination to suit the particular needs of a communication or other type system.

## Claims

1. A system comprising:
a plurality of converters configured to receive (i) an analog signal, and (ii) a respective one of a plurality of clock signals, wherein each converter of the plurality of converters is configured to sample the analog signal based on the respective clock signal received by the converter to generate a respective one of a plurality of digital signals, wherein each of the plurality of clock signals is out-of-phase with other ones of the plurality of clock signals;
a plurality of first modules configured to (i) receive the plurality of digital signals generated by the plurality of converters, (ii) remove bias offsets from each of the plurality of digital signals to generate a plurality of first output signals, and (iii) output each of the plurality of first output signals on a respective one of a plurality of channels;
a plurality of second modules configured to (i) receive the plurality of first output signals, and (ii) based on the plurality of first output signals, remove or equalize gain mismatch between the plurality of channels to generate a plurality of second output signals; and
a multiplexer configured to (i) receive the plurality of second output signals, and (ii) generate an output based on the plurality of second output signals, wherein the output of the multiplexer is a digital representation of the analog signal.

2. The system of claim 1, wherein each of the plurality of clock signals is 90° out-of-phase with other ones of the plurality of clock signals.

3. The system of claim 1, wherein each of the plurality of first modules comprises:
an accumulator configured to generate one of the bias offsets based on one of the plurality of digital signals;
a subtractor configured to remove the one of the bias offsets from the one of the plurality of digital signals to generate one of the plurality of first output signals; and
a multiplier configured to multiply the one of the plurality of first output signals by a control value, wherein the control value sets a rate of change, in the accumulator, of the one of the bias offsets, and
wherein the accumulator is configured to accumulate outputs of the multiplier to generate the one of the bias offsets.

4. The system of claim 3, wherein the accumulator comprises:
a summer configured to sum each of the outputs of the multiplier with the one of the bias offsets; and
a delay element configured to delay an output of the summer to provide the one of the bias offsets.

5. The system of claim 1, wherein each of the plurality of first modules comprises:
an accumulator configured to generate an output based on one of the plurality of digital signals;
a first multiplier configured to multiply one of the plurality of first output signals by a first control value, wherein the control value sets a rate of change of the output of the accumulator, and wherein the accumulator is configured to accumulate outputs of the first multiplier to generate a second bias offset;
a second multiplier configured to multiply the second bias offset by a second control value to generate one of the bias offsets; and
a subtractor configured to remove the one of the bias offsets from the one of the plurality of digital signals to generate the one of the plurality of first output signals.

6. The system of claim 1, wherein each of the plurality of first modules comprises:
an estimator configured to estimate a mean value of one of the plurality of digital signals; and
a subtractor configured to remove the mean value from the one of the plurality of digital signals to generate one of the plurality of first output signals.

7. The system of claim 1, wherein each of the plurality of second modules comprises:
an accumulator configured to generate an output based on one of the plurality of first output signals;
a subtractor configured to remove the output of the accumulator from one of the plurality of first output signals to provide one of the plurality of second output signals;
a third module configured to determine an absolute value of the one of the plurality of second output signals;
a first summer configured to sum the absolute value of the one of the plurality of second output signals with a threshold value; and
a multiplier configured to multiply an output of the summer by a first control value, wherein the control value sets a rate of change of the output of the accumulator, and
wherein the accumulator is configured to accumulate outputs of the multiplier to generate the output of the accumulator.

8. The system of claim 7, wherein the accumulator comprises:
a second summer configured to sum each of the outputs of the multiplier with the output of the accumulator; and
a delay element configured to delay an output of the second summer to provide the output of the accumulator.

9. The system of claim 1, wherein each of the plurality of second modules comprises:
an accumulator configured to generate an output based on one of the plurality of first output signals;
a third module configured to determine an absolute value of one of the plurality of second output signals;
a first summer configured to sum the absolute value of the one of the plurality of second output signals with a threshold value;
a first multiplier configured to multiply an output of the first summer by a first control value, wherein the control value sets a rate of change of the output of the accumulator, and wherein the accumulator is configured to accumulate outputs of the multiplier to generate the output of the accumulator;
a second multiplier configured to multiply the output of the accumulator by a second control value; and
a subtractor configured to remove an output of the second multiplier from the one of the plurality of first output signals to generate the one of the plurality of second output signals.

10. The system of claim 1, wherein each of the bias offsets comprises a difference in voltage values between two of the plurality of digital signals.

11. A method comprising:
receiving (i) an analog signal, and (ii) a respective one of a plurality of clock signals;
sampling the analog signal based on each of the plurality of clock signals to generate a plurality of digital signals, wherein each of the plurality of clock signals is out-of-phase with other ones of the plurality of clock signals;
removing bias offsets from each of the plurality of digital signals to generate a plurality of first output signals;
outputting each of the plurality of first output signals on a respective one of a plurality of channels;
based on the plurality of first output signals, removing or equalizing gain mismatch between the plurality of channels to generate a plurality of second output signals; and
generating an output based on the plurality of second output signals, wherein the output is a digital representation of the analog signal.

12. The method of claim 11, wherein each of the plurality of clock signals is 90° out-of-phase with other ones of the plurality of clock signals.

13. The method of claim 11, further comprising:
generating, via an accumulator, one of the bias offsets based on one of the plurality of digital signals;
removing the one of the bias offsets from the one of the plurality of digital signals to generate one of the plurality of first output signals;
multiplying, via a multiplier, the one of the plurality of first output signals by a control value, wherein the control value sets a rate of change, in the accumulator, of the one of the bias offsets; and
accumulating outputs of the multiplier to generate the one of the bias offsets.

14. The method of claim 13, further comprising:
summing, via a summer, each of the outputs of the multiplier with the one of the bias offsets; and
delaying an output of the summer to provide the one of the bias offsets.

15. The method of claim 11, further comprising:
generating, via an accumulator, an output based on one of the plurality of digital signals;
multiplying, via a multiplier, one of the plurality of first output signals by a first control value, wherein the control value sets a rate of change of the output of the accumulator;
accumulating outputs of the multiplier to generate a second bias offset;
multiplying the second bias offset by a second control value to generate one of the bias offsets; and
removing the one of the bias offsets from the one of the plurality of digital signals to generate the one of the plurality of first output signals.

16. The method of claim 11, further comprising:
estimating a mean value of one of the plurality of digital signals; and
removing the mean value from the one of the plurality of digital signals to generate one of the plurality of first output signals.

17. The method of claim 11, further comprising:
generating, via an accumulator, an output based on one of the plurality of first output signals;
removing the output of the accumulator from one of the plurality of first output signals to provide one of the plurality of second output signals;
determining an absolute value of the one of the plurality of second output signals;
summing, via a first summer, the absolute value of the one of the plurality of second output signals with a threshold value;
multiplying, via a multiplier, an output of the first summer by a first control value, wherein the control value sets a rate of change of the output of the accumulator; and
accumulating outputs of the multiplier to generate the output of the accumulator.

18. The method of claim 17, further comprising:
summing, via a second summer, each of the outputs of the multiplier with the output of the accumulator; and
delaying an output of the second summer to provide the output of the accumulator.

19. The method of claim 11, further comprising:
generating, via an accumulator, an output based on one of the plurality of first output signals;
determining an absolute value of one of the plurality of second output signals;
summing, via a summer, the absolute value of the one of the plurality of second output signals with a threshold value;
multiplying, via a first multiplier, an output of the summer by a first control value, wherein the control value sets a rate of change of the output of the accumulator;
accumulating outputs of the first multiplier to generate the output of the accumulator;
multiplying, via a second multiplier, the output of the accumulator by a second control value; and
removing an output of the second multiplier from the one of the plurality of first output signals to generate the one of the plurality of second output signals.

20. The method of claim 11, wherein each of the bias offsets comprises a difference in voltage values between two of the plurality of digital signals.