# Patent

## Title
Method and apparatus to regulate an output voltage of a power converter at light/no load conditions

## Abstract

An example controller for a primary side control power converter includes a feedback circuit, a driver circuit, and an adjustable voltage reference circuit. The feedback circuit compares a feedback signal representative of a bias winding voltage of the power converter with a voltage reference. The driver circuit outputs a switching signal having a switching period to control a switch to regulate an output of the power converter in response to the feedback signal and enables or disables a switching period based on the output of the feedback circuit. The adjustable voltage reference circuit adjusts the voltage reference by a first amount in response to a first number of disabled switching periods indicating a first load condition at the output of the power converter and by a second amount in response to a second number of disabled switching periods indicating a second load condition at the output of the power converter.

## Background
REFERENCE TO PRIOR APPLICATIONS
This application is a continuation of U.S. application Ser. No. 13/411,297, filed Mar. 2, 2012, which is a continuation of U.S. application Ser. No. 12/363,657, filed Jan. 30, 2009, now U.S. Pat. No. 8,159,843. U.S. application Ser. Nos. 13/411,297 and 12/363,657 are hereby incorporated by reference.


BACKGROUND INFORMATION
1. Field of the Disclosure
The present invention relates generally to power converters, and more specifically, the invention relates to improving output voltage regulation at light/no load conditions.
2. Background
Many electrical devices such as cell phones, personal digital assistants (PDA's), laptops, etc. are powered by a source of dc power. Because power is generally delivered through a wall outlet as high-voltage ac power, a device, such as a power converter, is required to transform the high-voltage ac power to usable dc power for many electrical devices. In operation, a power converter may use a controller to regulate energy delivered to an electrical device that may be generally referred to as a load. In one instance a controller may control the transfer of energy pulses by switching a power switch on and off in response to feedback information of an output voltage to keep the output voltage at the output of the power converter regulated.
In certain applications, power converters may include an energy transfer element to separate an input side from an output side of the power converter. More specifically, the energy transfer element may provide galvanic isolation which prevents dc current from flowing between the input and the output of the power converter and may be required due to certain safety regulations. A common example of an energy transfer element is a coupled inductor, where electrical energy received by an input winding on the input side is stored as magnetic energy and then converted back to electrical energy at the output side of the power converter across an output winding.
For certain power converter designs it may be required to regulate the output voltage within a specified voltage range. To accomplish this, some power converters may use ‘primary feedback’ to allow indirect sensing of the output voltage from the input side of the power converter in order to regulate an output voltage within a specified range. Primary feedback may be used instead of circuitry that directly senses an output voltage at the output of the power converter in order to reduce costs. One example of primary feedback is to electrically couple a bias winding to the input side of the power converter such that it is also magnetically coupled (not directly connected) to the output winding of the energy transfer element. This allows the bias winding to produce a voltage representative of the output voltage of the power converter across the bias winding, which shares an electrical connection with the input side of the power converter. In this manner, the power converter acquires a feedback signal representative of the output voltage without directly sensing the output voltage at the output of the power converter.
However, when implementing a primary feedback for regulation in a power converter at substantially light/no load conditions (where the load demands very little or no power), the output voltage may deviate substantially from its desired value. This may prevent the output voltage from being within the specified output voltage range at light/no load conditions.



BRIEF DESCRIPTION OF THE DRAWINGS
Non-limiting and non-exhaustive embodiments and examples of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
FIG. 1A is a functional block diagram illustrating an example power converter, in accordance with the teachings of the present invention.
FIG. 1B is an example waveform illustrating a switch current ISW through power switch 106 of FIG. 1A, in accordance with the teachings of the present invention.
FIG. 2 is an example graph illustrating an output voltage of a primary feedback power converter without adjusting the bias winding voltage waveform, in accordance with the teachings of the present invention.
FIGS. 3A and 3B illustrate example waveforms of an adjusted bias voltage, in accordance with the teachings of the present invention.
FIG. 4 is a functional block diagram of an example controller for adjusting a voltage reference to change a bias voltage, in accordance with the teachings of the present invention.
FIG. 5 is a functional block diagram of an example controller for adjusting a current limit to change a bias voltage, in accordance with the teachings of the present invention.
FIG. 6 is a functional block diagram illustrating an example adjustable voltage reference circuit, in accordance with the teachings of the present invention.
FIG. 7 is a functional block diagram illustrating an example integrated circuit including a power switch and a controller, in accordance with the teachings of the present invention.
FIG. 8 is an example schematic of an adjustable voltage reference circuit, in accordance with the teachings of the present invention.
FIG. 9 is a graph illustrating a relationship between an adjusted voltage reference in FIG. 8 in response to output current of a power converter, in accordance with the teachings of the present invention.
FIG. 10 is a flow chart illustrating a method to adjust a bias voltage in response to output current, in accordance with the teachings of the present invention.



DETAILED DESCRIPTION
A method and apparatus to improve regulation of an output voltage of a power converter over a range of load conditions is disclosed. More specifically, a method and apparatus for adjusting a bias voltage nonlinearly in response to varying load conditions of the power converter is disclosed. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention.
Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.
Referring now to FIG. 1A, a functional block diagram illustrates a power converter 100, in accordance with the teachings of the present invention. In the illustrated example, power converter 100 includes an integrated circuit 102 further including a controller 104 and a power switch 106, an energy transfer element 108, a feedback circuit 110, a diode D1, an output capacitor COUT, and a pre-load resistor RPL. Integrated circuit 102 further includes a drain terminal D, source terminal S, feedback terminal FB, and bypass terminal BP. As shown, feedback circuit 110 is illustrated as including a bias winding 128, a diode D2, a first resistor and second resistor R1 and R2, respectively, and a bias capacitor CBIAS.
As shown, power converter 100 is configured as a flyback converter. In operation, power converter 100 provides output power to a load 119 from an unregulated dc input voltage VIN, from hereon referred to as “input voltage”. In the example of FIG. 1, energy transfer element 108 is a coupled inductor, from hereon referred to as a ‘transformer’, with an input winding 124 and an output winding 126. An “input winding” may also be referred to as a “primary winding” and an “output winding” may also be referred to as a “secondary winding.” In one example, energy transfer element 108 may provide galvanic isolation. More specifically, galvanic isolation prevents dc current from flowing between the input side and the output side of power converter 100, and is usually required to meet safety regulations. As shown, an input return 105 is electrically coupled to circuitry as being referenced on the ‘input side’ of power converter 100. Similarly, an output return 107 is electrically coupled to circuitry on the ‘output’ side of power converter 100.
In one example, primary winding 124 is coupled to power switch 106 such that, in operation, energy transfer element 108 receives energy with an input current IIN when power switch 106 is in an on state and energy transfer element 108 delivers energy to the output of power converter 100 when power switch 106 is in an off state.
As shown, power switch 106 may be switched between an ‘on’ state, thereby allowing current to be conducted through the switch, and an ‘off’ state, thereby preventing current to be conducted through the switch. In operation, controller 104 outputs a switching signal Usw to switch power switch 106 between an on state and an off state. In one example, controller 104 may operate switch 106 to regulate the output voltage VOUT to its desired value. In one example, controller 104 includes an oscillator (not shown) that defines substantially regular switching periods TS during which switch 106 may be conducting or not conducting. More specifically, regulation of output voltage VOUT is accomplished by switching power switch 106 in response to a feedback signal UFB, which is indirectly representative of output voltage VOUT, to control the amount of energy transferred from the input to the output of power converter 100. In one example, the feedback signal UFB may directly regulate bias voltage VBIAS to a desired voltage which is representative of a desired value for output voltage VOUT. For example, bias voltage VBIAS may be regulated at 20 V in order to indirectly regulate an output voltage VOUT at 5 V.
In one example, power switch 106 is a metal oxide semiconductor field effect transistor (MOSFET). In one example, integrated circuit 102 may be implemented as a monolithic integrated circuit or may be implemented with discrete electrical components or a combination of discrete components and integrated circuits. In one example, integrated circuit 102 is manufactured as a hybrid or monolithic integrated circuit that includes both controller 104 and power switch 106. In another example, power switch 106 is not included in integrated circuit 102 where controller 104 is to be coupled to a power switch that is manufactured as a device separate from controller 104. During operation of power converter 100, the switching of power switch 106 produces pulsating currents in diode D1 which are filtered by output capacitor COUT to produce a substantially constant output voltage VOUT.
As shown, feedback circuit 110 is adapted to provide primary feedback, which allows indirect sensing of the output voltage VOUT from the input side of the power supply. In operation, feedback circuit 110 provides feedback signal UFB to controller 104. In one example, feedback signal UFB may be representative of a bias voltage VBIAS. As shown, bias winding 128 is magnetically coupled to output winding 126. Due to the magnetic coupling, during operation, energy transfer element 108 delivers energy to output winding 126 and to bias winding 128 when power switch 106 is in an off state. More specifically, the voltage induced across output winding 126 may be substantially proportional to the voltage across bias winding 128. In this manner, bias voltage VBIAS, defined as the voltage across capacitor CBIAS, increase to a voltage representative of the output voltage VOUT when diode D2 is conducting during the off state of power switch 106 to charge capacitor CBIAS.
As shown, diode D2 is coupled between bias winding 128 and bias capacitor CBIAS to prevent bias capacitor CBIAS from discharging when power switch 106 is conducting. In one example, bias winding voltage VBIAS includes a dc voltage and also includes a component of time-varying voltage also referred to as ripple voltage. In one example, the ripple voltage of VBIAS occurs due to the charging and discharging of capacitor CBIAS. More specifically, charging of capacitor CBIAS occurs when energy is transferred to bias winding 128 and diode D2 is conducting. Discharging of capacitor CBIAS occurs when diode D2 is not conducting and energy discharges through resistors R1 and R2 at a substantially constant rate. As shown, a resistor divider including resistor R1 and resistor R2 is coupled across bias capacitor CBIAS. In one example, the resistor divider is coupled to provide a divided down bias voltage VBIAS to feedback pin FB of integrated circuit 102.
In operation, power converter 100 implements primary feedback by directly regulating bias voltage VBIAS which is indirectly (through magnetic coupling) representative of the desired value of the output voltage VOUT. Therefore, if the output voltage VOUT changes from its desired value, the change in output voltage will proportionately change bias voltage VBIAS. Controller 104 will switch power switch 106 accordingly to bring bias voltage VBIAS back to its desired value by adjusting the amount of power delivered to the output. In this manner, output voltage VOUT is regulated indirectly by bias winding voltage VBIAS.
In one example, for power switch 106 to regulate the output voltage VOUT, controller 104 determines whether or not the power switch 106 will be allowed to conduct during a switching period TS in response to the feedback signal UFB. As stated above, a switching period TS may be a constant time period set by an oscillator (not shown) in controller 104. A switching period TS wherein the switch 106 is allowed to conduct is an ‘enabled’ period. A switching period TS wherein the switch 106 is not allowed to conduct is a ‘disabled’ period. In other words, controller 104 decides to either enable or disable power switch 106 during each switching period to control the transfer of energy to the output of power converter 100. In this manner, controller 104 may regulate the output voltage VOUT of power converter 100 in response to feedback signal UFB.
Referring now to FIG. 1B, an example waveform of switch current ISW of FIG. 1A for several enabled and disabled switching periods TS is illustrated, in accordance with the teachings of the present invention. As shown, an example waveform of switch current ISW in the switch 106 is illustrated in FIG. 1B for several enabled and disabled switching periods TS from T0 through TN+1. In the example of FIG. 1B, switch 106 turns on at the beginning of each enabled switching period T0, T1, and TN. Switch 106 conducts until switch current ISW in switch 106 reaches a current limit ILIMIT. When switch current ISW reaches current limit ILIMIT, switch current is at its peak value, referred to as a peak switch current ISWPEAK. By adjusting the current limit ILIMIT, the peak of switch current ISW in a switching period TS is changed, thus changing the amount of energy stored during the on time of power switch 106 during an enabled switching period. The relationship between energy stored and peak current is represented as:




  
    
      
        
          E
          TS
        
        =
        
          
            1
            2
          
          ⁢
          
            LI
            SWPEAK
            2
          
        
      
    
    
      
        EQ
        .
        
          
        
        ⁢
        1
      
    
  




where ETS is the energy stored during a switching period TS, L is the inductance of primary winding 124, and ISWPEAK is the peak current in power switch 106. Continuing with the example as shown, switch 106 does not conduct during disabled switching periods T2, TN−2, TN−1, and TN+1.

Referring back to FIG. 1A, as shown in the depicted example, a current sensor 146 is coupled to sense a switch current ISW flowing through power switch 106. More specifically, current sensor 146, which can in various examples be a current transformer, or a discrete resistor, or a main conduction channel of a transistor when the transistor is conducting, or a senseFET element forming part of a transistor, may be used to measure switch current ISW. During operation, current sensor 146 generates a current sense signal USENSE that is representative of switch current ISW. In one example, current sense signal USENSE is used by controller 104 to determine when switch current ISW reaches a current limit ILIMIT during each enabled switching period TS as shown in FIG. 1B.
In operation, controller 104 may continuously detect a load condition at the output of power converter 100 and adjust a bias voltage VBIAS in response to the load condition. In one example, a load condition may be detected in response to switching signal USW. For example, when switching signal USW indicates power switch 106 is enabled for nearly all switching periods TS, this may correspond to a high load condition because power converter 100 is delivering close to a maximum amount of power to the output of power converter 100. Conversely, if switching signal USW indicates power switch 106 is disabled for nearly all switching periods TS, this may corresponds to light/no load condition because power converter 100 is delivering a small amount of power to power converter 100. A no load condition may be defined as when load 119 coupled to the output of the power converter 100 requires substantially no output current IOUT. A high load condition may be defined as when load 119 requires close to a maximum amount of output current IOUT. To further clarify, as the load requires more power, output current IOUT delivered to the output of power converter 100 increases. As the load coupled to the output requires less power, the output current IOUT delivered to the output of power converter 100 decreases. In certain instances, such as a no-load/light load conditions, power converter 100 may still need to maintain a desired output voltage at the output of power converter 100. However, during a no load condition, when load 119 requires low amounts of power, energy delivered during a switching period TS to the output of power converter 100, may substantially increase the output voltage VOUT across capacitor COUT.
In one example, a pre-load resistor RPL may be coupled across output of power converter 100 to provide an additional pathway for output current IOUT at the output of power converter 100 such that the output voltage VOUT does not substantially increase at light/no load conditions (when load 119 receives little or no output current IOUT). In other words, pre-load resistor RPL may be designed to always allow for a minimum amount of output current IOUT to be used at the output of power converter 100.
As discussed above, switching of power switch 106 is controlled to regulate the bias voltage VBIAS which is intended to be representative of output voltage VOUT. During operation, when the bias voltage VBIAS is above a desired value it is representative of output voltage VOUT being above a desired value. In this scenario, feedback signal UFB will indicate to controller 104 to disable power switch 106 for subsequent switching periods until bias voltage VBIAS drops below its desired value (e.g., by discharging through resistors R1 and R2 when diode D2 is not conducting), thus indicating that output voltage VOUT has dropped below its desired value.
During light/no load conditions, the bias voltage VBIAS may drop to a desired value at a faster rate than the output voltage VOUT may drop to its desired value. The rate at which the bias voltage drops is based on a resistor capacitor (RC) time constant and is related to the values of R1, R2 and CBIAS. Therefore, under all load conditions, the time it takes to discharge a certain amount of charge from capacitor CBIAS will be substantially constant. However, the time it takes to discharge a certain amount of charge from capacitor COUT will be dependent on the load condition at the output of power converter 100. More specifically, power converter 100 varies the amount of power delivered to load 119 based on operational needs. Therefore, load 119 may be seen as a variable resistance that is adjusted to allow for a varying output current IOUT to be delivered to the output of power converter 100. During light/no load conditions, the rate of decrease of the output voltage VOUT may be substantially lower than the rate of decrease of the bias winding voltage VBIAS. Therefore, when feedback signal UFB indicates to controller 104 to enable a switching period because bias voltage VBIAS has dropped below its desired value, it may be that the output voltage VOUT is still above its desired value and will receive more energy than desired. In this manner, the output voltage VOUT further increases from its desired value at light/no load conditions.
Referring now to FIG. 2, a graph 200 illustrates an output voltage plot 202 representative of output voltage VOUT. As shown, plot 202 illustrates the nonlinear change of output voltage VOUT in response to output current IOUT. This relationship is described by equation 2 below:




  
    
      
        
          
            V
            OUT
          
          
            V
            OUTDESIRED
          
        
        =
        
          1
          +
          
            
              
                LI
                SWpeak
                2
              
              
                2
                ⁢
                
                  V
                  BIAS
                  2
                
                ⁢
                
                  C
                  BIAS
                
              
            
            ⁢
            
              (
              
                1
                
                  1
                  +
                  
                    
                      P
                      OUT
                    
                    
                      P
                      BIAS
                    
                  
                
              
              )
            
          
        
      
    
    
      
        EQ
        .
        
          
        
        ⁢
        2
      
    
  




where VOUTDESIRED is representative of the desired (the regulated) output voltage (shown in FIG. 2), VOUT is representative of the actual output voltage at the output of power converter 100, L is representative of the inductance value of primary winding 124, ISWPEAK is representative of the peak switch current (shown in FIG. 1B) through power switch 106, VBIAS is the bias voltage, CBIAS is the capacitance of the bias capacitor, and POUT is the amount of power (VOUT multiplied by IOUT) delivered to the output of power converter 100, and PBIAS is the amount of power delivered to the bias winding 128 of power converter 100.

As shown in EQ. 2, the expression in parenthesis shows that the output voltage increases nonlinearly as the output power POUT approaches zero. More specifically, the greatest difference between desired output voltage VOUTDESIRED and output voltage VOUT is at light/no load conditions. While power converter 100 is operating, the goal is to maintain VOUT/VOUTDESIRED ratio to substantially 1, in other words, to keep the output voltage VOUT substantially the same as the desired output voltage VOUTDESIRED.
Referring now to FIGS. 3A and 3B, bias voltage waveforms are shown in accordance with the teachings of the present invention. As shown in FIG. 3A a first bias voltage waveform 302 is compared to a second bias winding voltage 304 to show a change between a first average bias voltage VAVGBIAS1A and a second average bias voltage VAVGBIAS2A when a voltage reference is adjusted. As shown, bias voltage waveforms 302 and 304 illustrate a ripple portion of the voltage on capacitor CBIAS. In one example, the dc value of the bias voltage VBIAS may be about 20 V and the ripple voltage may be about 1 V. As further shown, a periodicity is associated with bias voltage waveform 302 and 304. One period is defined as a ripple period TRIP. More specifically, ripple period TRIP identifies the time between on states of power switch 106 during regulation of bias voltage VBIAS. More specifically, power switch 106 switches to an on state when bias voltage waveform 302 reaches a first adjustable reference value VADJREF1. In one example, voltage reference VADJREF1 may be used to regulate bias voltage VBIAS such that output voltage VOUT is indirectly regulated.
In one example, during a light/no load condition, ripple period TRIP is substantially greater than a switching period TS. For example, the ripple period TRIP may consist of between 50 to 200 consecutive skipped switching periods TS. As shown, at the beginning of ripple period TRIP, waveform 302 approaches a voltage peak VPEAK1A. More specifically, voltage peak VPEAK1A is reached in one switching period when diode D2 of power converter 100 is conducting. In one example, the change in voltage from first reference VADJREF1 to voltage peak VPEAK1A may represent the amount of energy delivered to bias capacitor CBIAS of power converter 100 during a switching period TS.
During the remainder of ripple period TRIP, voltage in waveform 302 is decreasing until reference voltage VADJREF1 is reached. More specifically, bias voltage of waveform 302 decreases at a rate based on an RC time constant that is determined by the values of R1, R2, and CBIAS. As shown in one example by waveform 302, during operation of power converter 100, when power switch 106 is not conducting, bias capacitor CBIAS discharges through resistors R1 and R2. Average bias winding voltage VAVGBIAS1A is an average voltage of bias voltage waveform 302.
As shown, voltage waveform 304 resembles voltage waveform 302 but is shifted downward. As is further illustrated, average bias voltage VAVGBIAS2A, representative of the average voltage of bias voltage waveform 304, is shifted downwards from average bias voltage VAVGBIAS1A. This downward shift occurs because a second voltage reference VADJREF2 is lower with respect to first voltage reference VADJREF1. In one example operation, power switch 106 switches to an on state when bias voltage waveform 304 reaches a second reference value VADJREF2. As shown, at the beginning of ripple period TRIP, waveform 304 approaches a voltage peak VPEAK2A. More specifically, voltage peak VPEAK2A is reached in one switching period when diode D2 of power converter 100 is conducting. During the remainder of ripple period TRIP, voltage of waveform 304 is decreasing until reference voltage VADJREF2 is reached. As shown, ripple of voltage waveform 304 has been reduced from first voltage peak VPEAK1A to second voltage peak VPEAK2A by lowering the voltage reference from first voltage reference VADJREF1 to second voltage reference VADJREF2. As shown, the change in voltage between a first reference voltage VADJREF1 and first peak voltage VPEAK1A is the same change in voltage between a second reference voltage VADJREF2 and second peak voltage VPEAK2A. This is because the energy delivered to bias capacitor VBIAS per switching period TS has not substantially changed. In other words, only the magnitude of the peak voltage has changed from first peak voltage VPEAK1A to second peak voltage VPEAK2A. In this manner, first average bias voltage VAVGBIAS1A has been reduced to second average bias voltage VAVGBIAS2A. In one example according to the teachings of the present invention, bias voltage VBIAS is adjusted in response to a load condition or, in other words, the amount of output power POUT demanded by load 119. Since, the output voltage VOUT is regulated, a change in load may also be referred to as a change in output current IOUT. In one example, a feedback voltage reference in controller 104 may be adjusted nonlinearly to substantially compensate for the rise in output voltage VOUT at light/no load conditions.
Referring now to FIG. 3B, a first bias voltage waveform 310 is compared to a second bias voltage waveform 312 to illustrate a change between a first average bias voltage VAVGBIAS1B and a second average bias voltage VAVGBIAS2B when a current limit ILIMIT to control the peak switch current ISWPEAK is adjusted. As shown, bias voltage waveforms 310 and 312 illustrate the ripple portion of voltage on capacitor CBIAS. As further shown, a periodicity is associated with bias voltage waveform 310 and 312. A first ripple period TRIP1 corresponds with voltage waveform 310 and a second ripple period TRIP2 corresponds with voltage waveform 312. In operation, power switch 106 is allowed to switch to an on state during the next switching period TS, when bias voltage waveform 302 reaches a reference value VADJREF. In one example, current limit ILIMIT may be used to regulate bias voltage VBIAS such that output voltage VOUT is indirectly regulated.
As shown, at the beginning of ripple period TRIP1, waveform 310 approaches a voltage peak VPEAK1B. More specifically, voltage peak VPEAK1B reached in one switching period when diode D2 of power converter 100 is conducting. In one example, the change in voltage in waveform 310 from voltage reference VADJREF to first voltage peak VPEAK1B may represent the amount of energy delivered to bias capacitor CBIAS of power converter 100 during a switching period TS. During the remainder of ripple period TRIP1, voltage waveform 310 drops until reference voltage VADJREF is reached. Average bias winding voltage VAVGBIAS1B is an average voltage of bias voltage waveform 310.
As shown, the average of voltage waveform 312 is shifted downward from voltage waveform 310 as a result of peak voltage VPEAK1B shifting down to voltage peak VPEAK2B. As is further illustrated, average bias voltage VAVGBIAS2B, representative of the average voltage of bias voltage waveform 312, is also shifted downwards. During an on state, power switch 106 limits switch current ISW in response to a current limit ILIMIT. In one example, adjusting the current limit ILIMIT in controller 104 changes the amount of energy delivered to bias winding 128 during an enabled switching period TS. This relationship between energy and peak current is represented in equation 3 below:




  
    
      
        E
        =
        
          
            1
            2
          
          ⁢
          
            LI
            SWPEAK
            2
          
        
      
    
    
      
        EQ
        .
        
          
        
        ⁢
        3
      
    
  




E=1⁄2LISWPEAK2  EQ. 3

where E is the energy delivered during a switching period, L is the inductance of primary winding 124, and ISWPEAK is the peak current in power switch 106. In this manner, a change in peak voltage may be controlled across bias capacitor CBIAS, thus controlling an average bias voltage.
As shown, at the beginning of ripple period TRIP2, waveform 312 approaches voltage peak VPEAK2B. More specifically, voltage peak VPEAK2B is reached in one switching period when diode D2 of power converter 100 is conducting. During the remainder of ripple period TRIP2, voltage of waveform 312 is decreasing until reference voltage VADJREF is reached. As shown, ripple of voltage waveform 312 has been reduced from first voltage peak VPEAK1B to second voltage peak VPEAK2B by lowering the current limit ILIMIT in controller 104 such that switch current ISW through power switch 106 is limited.
In one example according to the teachings of the present invention, bias voltage VBIAS is adjusted in response to a load condition, in other words bias voltage VBIAS is adjusted in response to the amount of output power POUT demanded by load 119. Since output voltage VOUT is kept regulated, a change in load may also be referred to as a change in output current IOUT. In one example, a feedback voltage reference in controller 104 may be adjusted nonlinearly to substantially reduce the rise in output voltage VOUT at light/no load conditions.
Referring now to FIG. 4, an example controller 400 is illustrated in accordance with the teachings of the present invention. More specifically, controller 400 may be incorporated in a power converter to adjust a bias winding voltage by adjusting a feedback voltage reference according to the teachings of the present invention. The illustrated example of power converter 400 includes a controller power supply 402, a protection circuit 404, a driver circuit 406, an oscillator 408, a feedback circuit 410, and an adjustable voltage reference circuit 412. As shown, controller 400 receives a power signal UPOWER, a feedback signal UFB and outputs a switching signal USW to switch a power switch. In one example, controller 400, power signal UPOWER, feedback signal UFB, and switching signal USW may represent possible implementations of controller 104, power signal UPOWER, feedback signal UFB, and switching signal USW, respectively of FIG. 1A.
As shown, controller power supply 402 is coupled to supply power to operate protection circuitry 404, driver circuitry 406, oscillator 408, feedback circuitry 410, and adjustable voltage reference circuit 412. In one example, protection circuit 404 is coupled to driver circuit 406 and outputs a protection signal UPROTECT to inhibit operation of switching signal USW in the event circuitry in controller 400 is receiving inadequate voltage or excessive voltage. As shown, oscillator 408 is coupled to driver circuit 406. In operation, oscillator 408 outputs a clock signal UCLOCK that sets the time period of a switching period of a power switch in a power converter. In one example, clock signal UCLOCK indicates a beginning of each switching period so that driver circuit 406 is able to decide to enable or disable the next switching period. An ‘enabled’ switching period may be defined as a switching period in which a power switch of a power converter is able to conduct current for a portion of that switching period. A ‘disabled’ switching period may be defined as a switching period in which a power switch of a power converter cannot conduct current.
As shown, feedback circuit 410 feedback signal UFB. In one example, feedback signal UFB is representative of a bias voltage VBIAS which is indirectly representative of an output voltage of a power converter. Feedback circuit 410, is coupled to driver circuit 406 and is coupled to output decision signal UDECISON. In operation, decision signal UDECISION may be used by driver circuit 406 to regulate a voltage across a bias capacitor, thus indirectly regulating an output voltage of a power converter. In one example, feedback circuit 410 compares feedback signal UFB, representative of a bias voltage, to a reference (not shown). If a bias voltage falls below a voltage reference, then decision signal UDECISION will indicate to driver circuit 406 to switch a power switch of a power converter to deliver more energy to the output. In this manner, decision signal UDECISION determines whether a switching period should be enabled or disabled. As shown, adjustable voltage reference circuit 412 is coupled to driver circuit 406 and feedback circuit 410. In operation, adjustable voltage reference circuit 412 outputs an adjustable voltage reference signal UADJIREF which adjusts a feedback reference voltage in feedback circuit 410. Adjustable voltage reference circuit 412 receives switching signal USW from driver circuit 406 to determine the load at the output of a power converter. In one example, adjustable voltage reference circuit 412 determines the amount to adjust the voltage reference in feedback circuit 410 in response to an output current drawn by a load coupled to an output of a power converter. In operation, adjustable voltage reference circuit 412 may determine the output current drawn by a load based on the effective switching frequency. More specifically, the effective switching frequency may be defined as the average switching frequency of a power switch over several switching periods. The switching signal received by adjustable voltage reference circuit 412 allows for an effective switching frequency to be determined. In one example, the adjustable voltage reference circuit 412 adjusts the voltage reference of feedback circuit 410 nonlinearly in response to a load condition of a load coupled to the output of a power converter.
Referring now to FIG. 5, an example controller 500 is illustrated in accordance with the teachings of the present invention. More specifically, controller 500 may be incorporated in a power converter to adjust a bias winding voltage by adjusting a current limit of a power switch according to the teachings of the present invention. In operation, controller 500 controls the peak current through a power switch of a power converter. By adjusting the current limit in controller 500 the peak current through a power switch can be controlled, thus adjusting the bias winding voltage. In one example, switching signal USW will be output from driver circuit 506 to disable a power switch when current sense signal USENSE detects a switch current in a power switch that has reached a current limit. The illustrated example of power converter 500 includes a controller power supply 502, a protection circuit 504, a driver circuit 506, an oscillator 508, feedback circuitry 510, and a current limit adjust circuit 512. As shown, controller 500 receives a power signal UPOWER, a feedback signal UFB, and a current sense signal USENSE, and outputs a switching signal USW to switch a power switch. In one example, controller power supply 502, protection circuit 504, driver circuit 506, oscillator 508, and feedback circuit 510, power signal UPOWER, feedback signal UFB, and switching signal USW may represent possible implementations of controller power supply 402, protection circuit 404, driver circuit 406, oscillator 408, and feedback circuit 410, power signal UPOWER, feedback signal UFB, and switching signal USW, respectively of FIG. 4.
As shown, driver circuit 506 receives a sense signal USENSE. In one example, sense signal USENSE is representative of a switch current conducting through a power switch of a power converter. In operation, driver circuit 506 controls the current through power switch to adjust a voltage across a bias winding of a power converter. In one example, driver circuit 506 adjusts the current limit of a power switch in response to an output current delivered to a load coupled to an output of a power converter. As shown, current limit adjust circuit 512 is coupled to driver circuit 506. In operation, current limit adjust circuit 512 outputs an adjusted current limit signal UADJLIMIT which adjusts the current limit in driver circuit 506. Current limit adjust circuit 512 receives switching signal USW from driver circuit 506 to determine the load at the output of a power converter. In one example, current limit adjust circuit 512 determines how much to adjust the current limit in driver circuit 506 in response to the output current drawn by a load coupled to the output of a power converter. In operation, current limit adjust circuit 512 may determine the output current drawn by a load based on the switching signal USW. In one example, current limit adjust circuit may determine the effective switching frequency of a power switch from switching signal USW. In one example, the current limit adjust circuit 512 adjusts the current limit of driver circuit 506 nonlinearly in response to a load condition of a load coupled to the output of a power converter.
Referring now to FIG. 6, an example adjustable reference voltage circuit 600 is illustrated in accordance with the teachings of the present invention. The illustrated example of adjustable reference voltage circuit 600 includes a first threshold adjust circuit 602, a second threshold adjust circuit 604, ‘Nth’ threshold adjust circuit 608, and averaging circuit 606. As shown, adjustable voltage reference circuit 600 is coupled to receive a switching signal USW representative of a switching of a power switch, and is coupled to output an adjustable voltage reference signal UADJREF. In one example, adjustable voltage reference 600 may be a possible implementation of adjustable voltage reference in FIG. 4. In another example, adjustable voltage reference signal VADJREF and switching signal USW may represent possible implementations of adjustable voltage reference signal VADJREF and switching signal USW respectively of FIGS. 1 and 4. As shown, first threshold adjust circuit 602 is coupled to averaging circuit 606 and is coupled to receive a switching signal representative of the switching of a power switch of a power converter. In operation, first threshold adjust circuit 602 outputs a first threshold adjust signal UTHRESH1 representative of a first adjustment to a reference threshold. In one example, first threshold adjust circuit 602 determines a first load condition and outputs a first threshold adjust signal UTHRESH1, representative of a load below the first load condition, to averaging circuit 606. In another example, second threshold adjust circuit 604 determines a second load condition and outputs a second threshold adjust signal UTHRESH2, representative of a load below the second load condition to averaging circuit 606. First and second adjust circuits 602 and 604 respectively, may determine a load condition in response to an effective switching frequency.
As shown, an averaging circuit 606 outputs an adjusted reference signal UADJREF in response to a first and second threshold adjust signal UTHRESH1 and UTHRESH2. In one example, averaging circuit 606 outputs adjusted reference voltage signal UADJREF in response to calculating the average of the threshold adjust signals over a substantially large number of switching periods. Therefore, adjusted voltage reference signal UADJREF changes gradually in magnitude and can be considered substantially constant over a few switching periods. As shown, additional threshold circuits may be added such that there are ‘N’ threshold adjusts circuits, to contribute to adjustable voltage reference UADJREF. By adding a second threshold adjust circuit the averaging circuit 606 non-linearly adjusts the adjustable voltage reference UADJREF in response to a switching signal. More specifically, the switching signal may be used to determine the load condition coupled to the output of a power converter.
Referring now to FIG. 7, a schematic of an example integrated circuit 700 for a power converter is illustrated in accordance to the teachings of present invention. As shown, integrated circuit 700 includes a drain terminal D, a source terminal S, a bypass terminal BP, and a feedback terminal FB. Integrated circuit 700 further includes a power switch 701, regulator 702 (to regulate VSUPPLY), a protection circuit 704, an adjustable voltage reference circuit 706, a driver circuit 708, an oscillator 710, a signal converter 711, and a feedback circuit 712. In one example, protection circuit 704, driver circuit 708, adjustable voltage reference circuit 706, oscillator 710 and feedback circuit 712 may represent possible implementations of their corresponding counterparts in FIGS. 4 and 5. Protection circuit 704 further includes a first comparator 714 and a second comparator 716. Driver circuit 708 further includes a current limit comparator 718, a leading edge blanking LEB circuit 720, a first AND gate 722 an second AND gate 724, a third AND gate 726, an OR gate 728, and an RS flip-flop 730.
As shown, power switch 701 is coupled between drain terminal D and source terminal S. In operation, a switch current flows through power switch 701, when power switch is in an ON state and able to conduct current. A regulator 702 is coupled directly to the drain terminal D to receive power to supply to the circuitry in integrated circuit 700. Although not shown, regulator 702 is coupled to provide a regulated supply voltage to supply power for operation to components in integrated controller 700. A first comparator 714 is coupled to regulator 702. In operation, comparator 714 compares a supply voltage VSUPPLY to an under-voltage reference VUNDER. In the event that supply voltage VSUPPLY drops below under-voltage reference VUNDER, comparator 714 will output a low signal to AND gate 722 thus inhibiting the switching of power switch 701. As shown, a second comparator 716 is coupled to regulator 702. In operation, comparator 716 compares supply voltage VSUPPLY to over-voltage reference VOVER. In the event supply voltage VSUPPLY is greater than over-voltage reference VOVER, comparator 716 will output a low signal to AND gate 726 thus inhibiting the turning on of power switch 701.
As shown, adjustable voltage reference circuit 706 is coupled to feedback circuit 712 and coupled to receive enable signal UENABLE from signal converter 711. In one example, enable signal UENABLE is determined from switching signal USW, and is high for an entire enabled switching period TS and will be low for an entire disabled switching period TS. In another example, voltage reference circuit 706 may directly receive switching signal USW. In operation, adjustable voltage reference circuit 706 adjusts a voltage reference of feedback circuit 712 in response to a load condition at the output of a power converter. More specifically, adjustable voltage reference circuit 706 determines the load condition in response to receiving enable signal UENABLE from signal converter 711. As shown a feedback circuit 712 is coupled to feedback pin FB and adjustable voltage reference circuit 706. In operation, feedback circuit 712 outputs a low signal when the bias winding voltage signal UVBIAS is greater than adjustable voltage reference UADJREF to inhibit switching of power switch 701. As shown, oscillator 710 is coupled to AND gate 726 and RS flip flop 730. In operation, oscillator 710 outputs a clock signal UCLOCK to set the switching frequency of power switch 701. In one example UCLOCK is a fixed signal. Oscillator 710 is further coupled to output a maximum duty cycle signal DCMAX to prevent power switch 701 from being in an on state for a defined time. More specifically, a duty cycle is the ratio of on time of power switch 701 to total time of a switching period TS.
As shown, current limit comparator 718 is coupled to AND gate 724. In operation, current limit comparator 718 compares a switch current ISW to a current limit ILIMIT. When switch current reaches current limit ILIMIT, comparator 718 outputs a high signal to turn power switch 701 to an OFF state. In this manner, the switch current through power switch 701 is controlled. As shown a leading edge blanking (LEB) circuit 720 is coupled to the output of AND gate 722 and input of AND gate 724. In operation, leading edge blanking circuit 720 prevents power switch 701 from turning off due to a spike in current when the power switch 701 turns on. More specifically, LEB circuit 720 provides a delay at the beginning of each ON time such that an overshoot in current does not cause current limit comparator 718 to switch power switch to an OFF state prematurely.
As shown, OR gate 728 is coupled to output a signal to switch power switch 701 from an ON state to an OFF state. AND gate 726 is coupled to output a signal to switch power switch 701 from an OFF state to an ON state. As shown, RS flip flop 730 is coupled to AND gate 726 and OR gate 728. In operation, RS flip flop 730 is coupled to outputs a switching signal USW in response to outputs from AND gate 726 and OR gate 728. A current source 732 is coupled to sink current from feedback terminal FB.
Referring now to FIG. 8, an example adjustable voltage reference circuit 800 is illustrated in accordance with the teachings of the present invention. As shown, adjustable voltage reference circuit 800 includes a first threshold adjust circuit 802, a second threshold adjust circuit 804, an inverter 805, and an averaging circuit 806. In one example, threshold adjust circuit 802, threshold adjust circuit 804, and adjuster circuit 806 maybe possible implementations of first threshold adjust circuit 602, second threshold adjust circuit 604, and averaging circuit 606 respectively of FIG. 6. As shown, threshold adjust circuit 802 includes an n-channel transistor 808, a p-channel transistor 810, a current source 812, capacitor 814, and an inverter 816. Similarly, threshold adjust circuit 804 includes an n-channel transistor 818, a p-channel transistor 820, a current source 822, capacitor 824, and an inverter 826. As further shown, averaging circuit 806 includes current source 828, current source 830, current source 832, current source 834, resistor 836, resistor 838, capacitor 840, n-channel transistor 842, n-channel transistor 844, and n-channel transistor 846. More specifically, n-channel and p-channel transistors perform opposite functions, such that a logic signal that causes an n-channel to turn on will cause a p-channel to turn off.
As shown, transistor 842 is coupled to receive an inverted enable signal UEN. According to one embodiment, enable signal UENABLE is representative of an enabled or disabled switching period. More specifically, enable signal UENABLE is high throughout the whole switching period in which a power switch has conducted (enabled period) and low throughout the whole switching period when the power switch is not conducting (disabled switching period). In operation, inverted enable signal UEN goes high during a disabled switching period (i.e., power switch has not turned on during the switching period), and transistor 842 is turned on to conduct current. More specifically current source 828 provides current to conduct through transistor 842. In this manner, voltage across resistor 836 is reduced since the current through resistor 836 will be reduced by an amount of current from current source 828. According to the example embodiment, each time a power switch does not switch during a switching period, voltage across resistor 836 is reduced by a certain amount. In operation, capacitor 840 averages the voltage across resistor 836. In one example, when enable signal UENBLE is enabled after a disabled switching period, transistor 842 turns off, allowing the full current of current source 834 to charge capacitor 840 and raise adjustable voltage reference VADJREF to a maximum value. If ‘x’ number of switching periods are consecutively disabled, then transistor 844 will turn on and the voltage across resistor 836 will be reduced by an even greater amount for any subsequent consecutive disabled switching periods thus reducing the voltage VADJREF by at a greater rate. If ‘y’ number of switching periods are consecutively disabled, then transistor 846 will turn on and capacitor 840 will discharge by an even greater amount per disabled switching period. In one example ‘x’ number of switching periods is less than ‘y’ number of switching periods. For example, ‘x’ number of switching periods may be 5 and ‘y’ number of switching periods may be 10. The value of ‘x’ and ‘y’ may be determined by the size of capacitors 814 and 824, respectively. More specifically, if the size of capacitor 814 or 824 is increased, additional disabled switching periods will be needed to pass by before the voltage on capacitors 814 or 824 gets low enough to trigger either transistor 844 or 846 to further reduce adjustable reference voltage VADJREF. Therefore, as the output current delivered to the output of the power converter is reduced, the bias voltage will be adjusted nonlinearly by adjusting the voltage reference in this manner to keep an output voltage at the output of the power converter at its desired value. In one example, adjustable voltage circuit 800 may include additional threshold adjust circuits to improve resolution of the rate of change of the feedback voltage reference.
As shown, first voltage threshold adjuster 802 is coupled to receive an inverted enable signal UEN. As shown, a voltage supply VSUPPLY is coupled to transistor 810. During operation, when inverted enable signal UEN is high, transistor 808 is turned on and transistor 810 is turned off, and capacitor 814 discharges from the initial voltage of supply voltage VSUPPLY. When capacitor 814 has discharged for ‘x’ number of switching periods, inverter 816 will output a high signal. In this manner, transistor 844 is triggered to turn on and voltage across resistor 836 is reduced further for subsequent disabled switching periods, to further increase the rate of change of feedback voltage reference VREF. Similarly, second voltage threshold adjuster 804 is coupled to receive an inverted enable signal UEN. As shown, a voltage supply VSUPPLY is coupled to transistor 820. During operation, when inverted enable signal UEN is high, transistor 818 is turned ON and transistor 820 is turned OFF, and capacitor 824 discharges from supply voltage VSUPPLY. When capacitor 824 has discharged for ‘y’ number of switching periods, inverter 826 will output a high signal. In this manner, transistor 846 is triggered to turn ON and voltage on capacitor 840 is reduced to further increase the rate of change of feedback voltage reference VREF. As shown, capacitor 840 is coupled to discharge through resistor 838 and resistor 836. In one example, capacitor 840 has a relatively high time constant with respect to the time frame of a switching period of a power switch. This allows for the voltage reference VREF to change gradually over multiple switching periods. In one example the value of resistor 838 is 14 M Ohms and the value of capacitor 840 is 14 pF.
Referring now to FIG. 9, a graph 900 illustrates the voltage reference VREF of FIG. 8 in response to load conditions. As shown, the change of voltage reference waveform 902 without output current IOUT is greater for output currents closer to zero. That is, in the illustrated example, the slope of voltage reference waveform 902 is greatest for output currents between zero and the second threshold. Voltage reference waveform 902 further includes a different (e.g., smaller) slope for output currents between the second and first thresholds and a third slope (e.g., even smaller) for output currents greater than the first threshold. Thus, in one example, a nonlinear adjustment of the reference voltage may include a plurality of linear segments each with differing slopes. In this manner, the adjustable voltage reference is designed in a piecewise linear way to more accurately maintain the desired output voltage at the output of a power converter.
Referring now to FIG. 10, a flow chart illustrates a method 1000 to improve regulation for a primary side feedback power converter. More specifically, method 1000 reduces an adjustable reference voltage nonlinearly such that a bias voltage is reduced nonlinearly in response to a load condition. In process block 1010, a controller regulates an output voltage of a power converter in response to the adjustable voltage reference. In decision block 1020, if a load is less than a first load condition, then method 1000 proceeds to decision block 1030. Otherwise, method 1000 proceeds back to decision block 1010. In one example, a first load condition may be determined in response to the switching frequency of a power switch in a power converter. During process block 1030, control initiates reduction of the adjustable reference voltage at a first rate in response to load. In process block 1040, it is determined if the load is below a second load condition. If the load is below the second load condition, method 1000 proceeds to block 1050. Otherwise, method 1000 proceeds back to 1030. In process block 1050, the rate of reduction of the adjustable reference voltage is further increased in response to a load. In one example, the second rate is higher than a first rate. During operation, as a load condition moves towards a no load condition (zero output power consumed by load), the adjustable reference voltage will be reduced at a faster rate in response to load. In one example, more than two rates to adjust the adjustable reference voltage may be used. As mentioned above, by adjusting the feedback voltage reference, the bias winding voltage is adjusted. Since a proportional relationship exists between the adjustable reference voltage and bias voltage, in this manner, method 1000 nonlinearly adjusts a bias voltage in response to a load condition.

## Claims

1. A controller for a primary side control power converter, the controller comprising:
a feedback circuit coupled to compare a feedback signal representative of a bias winding voltage of the power converter with a voltage reference;
a driver circuit coupled to output a switching signal having a switching period to control a switch to regulate an output of the power converter in response to the feedback signal, wherein the driver circuit allows the switch to turn on and off during an enabled switching period and prevents the switch from turning on during a disabled switching period, and wherein the driver circuit enables the switching period in response to the feedback circuit indicating that the feedback signal is less than or equal to the voltage reference and disables the switching period in response to the feedback circuit indicating that the feedback signal is greater than the voltage reference; and
an adjustable voltage reference circuit coupled to adjust the voltage reference by a first amount in response to a first number of disabled switching periods indicating a first load current at the output of the power converter, and by a second amount in response to a second number of disabled switching periods indicating a second load current at the output of the power converter, wherein a difference between the first amount that the voltage reference is adjusted and the second amount that the voltage reference is adjusted is nonlinear with respect to a difference between the first load current and the second load current at the output of the power converter.

2. The controller of claim 1, wherein the first number of disabled switching periods is one.

3. The controller of claim 1, wherein the first number of disabled switching periods is a plurality of consecutively disabled switching periods.

4. The controller of claim 1, wherein the first number of disabled switching periods is less than the second number of disabled switching periods.

5. The controller of claim 1, wherein the adjustable voltage reference circuit comprises:
a first threshold adjust circuit coupled to adjust the reference voltage by the first amount, the first threshold adjust circuit including a first capacitor, wherein the first number is based on a size of the first capacitor; and
a second threshold adjust circuit coupled to adjust the reference voltage by the second amount, the second threshold circuit including a second capacitor, wherein the second number is based on a size of the second capacitor.

6. The controller of claim 5, wherein the adjustable voltage reference circuit further comprises an averaging circuit coupled to the first and second threshold adjust circuits to generate the adjusted reference voltage in response to calculating an average of an output of the first threshold adjust circuit and an output of the second threshold adjust circuit over a plurality of switching periods.

7. The controller of claim 6, wherein the averaging circuit comprises a third capacitor having a time constant that is greater than the switching period of the switching signal to allow the voltage reference to change gradually over multiple switching periods.

8. A controller for a primary side control power converter, the controller comprising:
a feedback circuit coupled to compare a feedback signal representative of a bias winding voltage of the power converter with a voltage reference;
a driver circuit coupled to output a switching signal having a switching period to control a switch to regulate an output of the power converter in response to the feedback signal and a current limit, wherein the driver circuit allows the switch to turn on and off during an enabled switching period and prevents the switch from turning on during a disabled switching period, and wherein the driver circuit enables the switching period in response to the feedback circuit indicating that the feedback signal is less than or equal to the voltage reference and disables the switching period in response to the feedback circuit indicating that the feedback signal is greater than the voltage reference; and
a current limit adjust circuit coupled to adjust the current limit by a first amount in response to a first number of disabled switching periods indicating a first load current at the output of the power converter, and by a second amount in response to a second number of disabled switching periods indicating a second load current at the output of the power converter, wherein a difference between the first amount that the voltage reference is adjusted and the second amount that the voltage reference is adjusted is nonlinear with respect to a difference between the first load current and the second load current at the output of the power converter.

9. The controller of claim 7, wherein the first number of disabled switching periods is one.

10. The controller of claim 7, wherein the first number of disabled switching periods is a plurality of consecutively disabled switching periods.

11. The controller of claim 7, wherein the first number of disabled switching periods is less than the second number of disabled switching periods.

12. The controller of claim 7, wherein the current limit adjust circuit comprises:
a first threshold adjust circuit coupled to adjust the current limit by the first amount, the first threshold adjust circuit including a first capacitor, wherein the first number is based on a size of the first capacitor; and
a second threshold adjust circuit coupled to adjust the current limit by the second amount, the second threshold circuit including a second capacitor, wherein the second number is based on a size of the second capacitor.

13. The controller of claim 12, wherein the current limit adjust circuit further comprises an averaging circuit coupled to the first and second threshold adjust circuits to generate the adjusted current limit in response to calculating an average of an output of the first threshold adjust circuit and an output of the second threshold adjust circuit over a plurality of switching periods.

14. The controller of claim 13, wherein the averaging circuit comprises a third capacitor having a time constant that is greater than the switching period of the switching signal to allow the current limit to change gradually over multiple switching periods.