# Patent

## Title
Modular high-frequency converter and method for operating the same

## Abstract

A modular high-frequency converter includes submodules, each having an input-side half bridge and a DC link circuit with a DC link capacitance connected in parallel to the half bridge. A DC link circuit voltage drop across the DC link capacitance of each submodule is controlled to a target voltage by adjusting a duty cycle with a closed-loop control structure having a pilot control and a downstream closed-loop error control. Within the framework of the pilot control, a target value for each duty cycle and a target value for the supply current are determined, using a mathematical model of the converter, based on the load-side output currents flowing out of the DC link voltage circuits and on target values of the DC link circuit voltages. Switch position parameters, which map the effect of the switch positions of the input-side half bridges, are each replaced by an associated duty cycle.

## Background
CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims the priority of German Patent Application, Serial No. 10 2013 203 706.6, filed Mar. 5, 2013, pursuant to 35 U.S.C. 119(a)-(d), the content of which is incorporated herein by reference in its entirety as if fully set forth herein.
BACKGROUND OF THE INVENTION
The present invention relates to a modular high-frequency converter. The invention further relates to a method for operating such a converter.
The following discussion of related art is provided to assist the reader in understanding the advantages of the invention, and is not to be construed as an admission that this related art is prior art to this invention.
Conventional modular high-frequency converters (abbreviated to MHF converter) are designed to convert a DC voltage from a traction battery of the vehicle into a number of AC voltages. The individual AC voltages in such cases are generated by a number of submodules which are connected in series into the supply circuit of the traction battery. Each submodule is connected here on the input side to the supply circuit via a half bridge. To generate the AC voltage each submodule has a single-phase full bridge (H bridge) on its output side, which is connected via a load circuit to a phase winding of the drive motor of the vehicle. Within the submodule the input-side half bridge and the full bridge are connected in parallel, together with a link circuit capacitance, in a (DC) link circuit.
In normal operation (drive mode) of the MHF converter, in which electrical power is transported via the submodules of the converter out of the supply circuit into the respective load circuit, the input-side half bridges of the submodules are operated in collaboration with an inductance arranged in the supply circuit as boost converters. For this purpose the DC link circuit capacitances of the submodules are usually switched into the supply circuit with offset clocking. For this purpose, the input-side half bridges are activated as a rule with periodic carrier signals which are offset by the same phase angle.
In addition to the drive mode, the input-side half bridges of the submodules can also be operated in a feedback mode, in which electrical power is fed back from the load circuit via the respective associated submodule into the supply circuit.
The DC link circuit voltages of the submodules are regulated individually for each submodule by variation of the sampling cycle (also known as the control factor, pulse-pause ratio or duty cycle), with which the respective input-side half bridge of the respective submodule is activated.
It would therefore be desirable and advantageous to obviate prior art shortcomings and to provide an improved MHF converter and an improved method for its operation.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a method for operating a modular high-frequency converter having a plurality of submodules which are connected in series on an input side to a supply circuit supplied by a DC voltage source via an inductance, wherein each submodule has an associated input-side half bridge and a DC link circuit connected downstream of the associated input-side half bridge and wherein a DC link circuit capacitance is connected in parallel with the associated input-side half bridge, includes clocking the associated input-side half bridge with a predetermined duty cycle so as to connect the DC link circuit capacitance of each submodule to the supply circuit; controlling the DC link circuit voltage dropping across the DC link circuit capacitance of each submodule to a predetermined voltage target value by adjusting the predetermined duty cycle with a closed-loop control structure having a pilot control and a closed-loop error control connected downstream of the pilot control; determining, in conjunction with the pilot control and by using a model that mathematically models approximately an interaction of currents and voltages in the supply circuit and currents and voltages in the submodules, a target duty cycle value for each duty cycle and a target current value for the supply current based on load-side output currents flowing out from the DC link circuits of the submodules and based on the predetermined target voltage values of the DC link circuit voltages; in the model, replacing switch position parameters that map an effect of switch positions of the input-side half bridges based on the determined duty cycle value; and operating the converter with the replaced switch position parameters.
According to another aspect of the present invention, a modular high-frequency converter includes a plurality of submodules having input sides connected in series via an inductance in a supply circuit supplied by a DC voltage source, wherein each submodule comprises an input-side half bridge, a DC link circuit connected downstream of the input-side half bridge and a DC link circuit capacitance connected in parallel with the input-side half bridge, and a control device configured to automatically carry out the aforedescribed method.
The invention is based on an MHF converter comprising a number of submodules. The submodules here are connected in series as per specification on the input side via an inductance into a supply circuit fed by a DC voltage source. On its input side each submodule has a half bridge (called the input bridge below) with which the submodule is connected into the supply circuit. The input bridge is connected within the submodule downstream from a (DC) link circuit, within which the input bridge is connected in parallel to a DC link circuit capacitance—especially in the form of one or more capacitors.
On the output side each submodule preferably has an output circuit, via which the submodule is connected in accordance with specification to a load circuit. Depending on the type of load disposed in the load circuit, the output circuit can differ in its nature. In particular the output circuit—in a similar way to the known MHF converter—can involve a single-phase full bridge for generating a single-phase AC voltage for the load circuit. As an alternative to this the output circuit can be embodied as a multiphase, especially three-phase, full bridge (pulse converter) for generating a corresponding multiphase AC voltage. Another alternative is for the output circuit to be embodied as a DC-DC converter for generating a DC voltage in the load circuit. In the last-mentioned embodiment the output circuit serves especially for downwards conversion of the DC link circuit voltage into a low voltage for the supply of electrical control devices, lighting and low voltage drives and/or for charging a low-voltage battery. Provided the submodule is intended for load-side output of a DC voltage, the output circuit can optionally also be omitted entirely, so that in this case the DC link circuit passes directly into the load circuit. The MHF converter can in accordance with the invention especially include submodules with different output circuits. In one exemplary embodiment the MHF converter includes four submodules, each of which contains a three-phase full bridge (pulse converter) as its output circuit, as well is a fifth submodule with a buck converter as its output circuit.
The MHF converter is especially designed for use in the vehicle drive of an electric vehicle. In this application the traction battery (high-voltage battery) of the vehicle is designed as the DC voltage source for the supply circuit. The load to be connected to the submodule on the output side here especially involves an electric motor or a phase winding of such a motor. Preferably in this case each phase winding of the electric motor is assigned a separate submodule. As an alternative to this however, within the framework of the invention, a number of phase windings of a multiphase electric motor can be connected to a common submodule. In a specific application of the invention a number of electric motors—which for example serve to selectively drive different wheels of the vehicle—can be activated by different submodules of the MHF converter.
As part of the method the DC link circuit capacitance of each submodule, clocked in each case with a predetermined duty cycle by the associated input half bridge, is connected into the supply circuit. The DC link circuit voltage dropping via the DC link circuit capacitance of the submodule is regulated to a predetermined voltage target in such cases by specifying the associated duty cycle.
In accordance with the invention, for regulation of the DC link circuit voltages, a regulation structure with two degrees of freedom is included, which comprises a pilot control and a closed-loop subsequent error control connected downstream from said pilot control. At the heart of the pilot control in this case is a model which approximately mathematically maps the interaction of the currents and voltages in the supply circuit and the submodules in accordance with Kirchhoff's rules. The model is preferably implemented in the form of an equation system.
As part of the pilot control, target values for the DC link circuit voltages and the output currents of the submodules are included as input variables for the model. The “output current” here refers to the current flowing out in the DC link circuit of a submodule—the current flowing into the respective DC link circuit from the associated load circuit is accordingly evaluated as the output current with a negative sign. The model further contains switching position parameters, which map the influence of the switching positions of the input bridges (more precisely the influence of the position of the switching elements disposed in the half bridges) on the voltages and currents in the MHF converter. The switching position parameters typically involve binary parameters which assume the value “0” if the associated link circuit capacitance is switched into the supply circuit and which assume the value “1” if the DC link circuit capacitance is uncoupled in switching terms from the supply circuit.
By means of the model—especially by resolving the equation system forming the model—a target value for each duty cycle and also a target value for the supply current is determined as part of the pilot control. The target values determined by the pilot control in such cases represent specifications with large granularity and which change slowly over time which can be finely adjusted by the subsequent closed-loop control.
In accordance with the invention the model used in the pilot control-compared to an exact mapping of the currents and voltages in the MHF converter according to Kirchhoff's rules—is simplified to the extent that, for the determination of the target values specified above, the switching position parameters will be replaced in each case by the assigned duty cycle, i.e. by that duty cycle with which the associated input bridge is activated. Preferably additional temporal changes of the DC link circuit voltages and of the supply current are ignored in the model (i.e. set to the value zero).
The inventive closed-loop control method makes possible an especially flexible, yet still precise and stable control of the MHF converter at different operating points. Thus the method also especially makes it possible to supply the load circuit by means of single-phase output bridges at a low to disappearing output frequency. Furthermore the method makes possible, within the system's own limitations, the simultaneous supply of loads of different types, especially the simultaneous supply of AC consumers and DC consumers. In addition the method is especially suitable for the operation of the MHF converter in supplying a number of loads with greatly differing power consumption.
Basically, within the framework of the pilot control, time-discrete measured values of the output currents (e.g. values, especially measured values, which the respective output current assumes at a defined point in time) can be included as input variables for the model. Preferably, within the framework of the pilot control, instead of time-discrete values, average current values over time of the output currents are taken into account as input variables, since it is known that this significantly contributes to the stable function of the pilot control. In an especially expedient version of the method the average current values of the output currents are determined by means of a recursive average value filter. As an alternative to the direct measurement of the output currents, the output currents are calculated even before the recursive averaging from measured values of the load-side AC currents and by taking into account the switch positions in the output circuits of the submodules.
Preferably the target values cited here are determined by the pilot control by numerical resolution of the model in an iterative optimization method, for example using the Levenberg-Marquardt algorithm.
The voltage of the DC voltage source (referred to below as the “supply voltage”) is included as an additional input variable in the model implemented in the pilot control. The supply voltage can be measured as part of the invention. In an alternate embodiment of the method, much easier to implement yet still sufficiently precise for most applications, a constant predetermined assumed value is used for the supply voltage. Fluctuations of the supply voltage (when the MHF converter is used in an electric vehicle, especially fluctuations of the battery voltage) are ignored in such cases. As another alternative, as part of the pilot control, a value of the supply voltage calculated by state reconstruction is used. This makes it possible, by comparison with the constant specification of the supply voltage, to enhance the precision of the pilot control without having to take into account the hardware outlay associated with voltage measurement.
For the same reasons, in an expedient variant of the method, an (actual) value of the supply current also needed for subsequent error control is calculated in a state reconstruction, wherein, as an alternative, detecting the supply current by measuring is also possible within the framework of the invention.
In an expedient variant of the method any periodic disruption to the DC link circuit voltages which might be present can be compensated for wholly or in part by applying a corresponding periodic compensation signal to the duty cycles. This relieves the strain on the subsequent error control. The function of the closed-loop control with two degrees of freedom is further stabilized overall. This variant of the method is used especially if the MHF converter is operated for supplying single-phase AC current consumers as the load, since the output currents drawn by such a load always have a marked ripple.
In an expedient embodiment of the invention the MHF converter carries out the inventive method automatically. For this purpose it comprises a control device, which is configured in terms of circuitry and/or programming to carry out the inventive method, especially in one of the embodiment variants described above. The control device in such cases especially comprises a microcontroller in which a control program (firmware) automatically executing during operation of the converter is implemented as an executable program. As an alternative or in addition, within the framework of the invention, the control device can however also include at least one non-programmable hardware switching circuit (e.g. an ASIC), in which the function for automatically carrying out the method or a part thereof is implemented with circuit technology means.
The control device can be formed within the framework of the invention by a single (central) control unit which activates all submodules together, thus for example by a single microcontroller. As an alternative or in addition to this however the control device can also be structured within the framework of the invention entirely or partly decentrally, in that each submodule is (at least also) assigned its own control unit.



BRIEF DESCRIPTION OF THE DRAWING
Other features and advantages of the present invention will be more readily apparent upon reading the following description of currently preferred exemplified embodiments of the invention with reference to the accompanying drawing, in which:
FIG. 1 shows schematically in a simplified electronic circuit diagram an MHF converter with a number of submodules connected in series, wherein each of the submodules comprises an input-side half bridge (input bridge), an output-side single-phase full bridge (output bridge) and a (DC) link circuit with a link circuit capacitance, and also with a control unit for activating the submodules,
FIG. 2 shows one of the submodules in accordance with FIG. 1 in an enlarged diagram,
FIG. 3 shows a schematic block circuit diagram of the functional layout of the control unit embodied as the closed-loop control structure with two degrees of freedom according to the present invention, and
FIG. 4 shows an alternate design of the control unit in accordance with FIG. 3.



DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Throughout all the figures, same or corresponding elements may generally be indicated by same reference numerals. These depicted embodiments are to be understood as illustrative of the invention and not as limiting in any way. It should also be understood that the figures are not necessarily to scale and that the embodiments are sometimes illustrated by graphic symbols, phantom lines, diagrammatic representations and fragmentary views. In certain instances, details which are not necessary for an understanding of the present invention or which render other details difficult to perceive may have been omitted.
Turning now to the drawing, and in particular to FIG. 1, there is shown a vehicle drive 1 for an electric vehicle (not shown in detail). The vehicle drive 1 includes a number of electric loads 2j (with j=1, 2, . . . , n) for example. Each of the loads 2j can involve a drive motor or a phase winding of a drive motor of the vehicle. At least one of the loads 2j can, as an alternative, involve another consumer in the vehicle, especially a DC consumer such as e.g. the on-board network or its low-voltage battery.
The vehicle drive 1 further includes an (MHF) converter 3, which supplies the loads 2j with electrical power from an electrical DC voltage source. The DC voltage source, in the example shown, involves the (traction) battery 4 (also: high-voltage battery) of the vehicle.
In the example in accordance with FIG. 1, the converter 3 includes a number of submodules 5j (with j=1, 2, . . . , n). In the example shown the number of submodules 5j is selected merely for reasons of simplification to be the same as the number of loads 2j to be supplied. In the general case a number of loads 2j can be supplied by one of the submodules 5j.
The converter 3 also includes a central control unit 6 as a control device as well as additionally an inductance 7.
The inductance 7, which is realized in terms of circuit technology especially by one or more coils, and the submodules 5j are connected to the battery 4 in a series circuit via a supply circuit (referred to as the battery circuit 8 below). Each submodule 5j is connected here by two input terminals 9 and 10 into the battery circuit 8.
On the load side each of the submodules 5j is connected in each case via a load circuit 11 to the associated load 2j.
One of the submodules 5j is shown in FIG. 2 in greater detail by way of example. As can be seen in this figure, the submodule 5j has a half bridge, referred to below as the input bridge 20, on its input side. Furthermore the submodule 5j has an output circuit 21 on the load side. The submodule 5j also includes a DC link circuit capacitance 22 in the form of a capacitor, via which a DC link circuit voltage vaj (with j=1, 2, . . . , n) drops. The input bridge 20, the output circuit 21 and the DC link circuit capacitance 22 are connected here in parallel to one another between a plus rail 23 and a minus rail 24 of a (DC) link circuit 25.
The input bridge 20 has two branches 27 and 28 separated by a central tap 26, of which the branch 27 extends between the central tap 26 and the plus rail 23, and the branch 28 between the central tap 26 and the minus rail 24. Arranged in each of the branches 27, 28 is a (semiconductor) switch 29 or 30, which is preferably formed in each case by a MOSFET. The input terminals 9 and 10 of each submodule 5j are connected on both sides of the switch 29 to the plus rail 23 or to the central tap 26.
The output circuit 21 is formed in the example in accordance with FIG. 2 by a single-phase full bridge (H bridge) and is operated as an inverter to generate a single-phase alternating current (load current) in the load circuit 11. In a variation of FIG. 2 the output circuit 21 in one or more of the submodules 5j can be embodied in a different way and for generating different types of load currents, e.g. as a three-phase full bridge (pulse converter) for generating a three-phase alternating current or as a DC-DC converter for generating a DC current, especially for feeding a vehicle on-board network or for charging a low-voltage battery. Such a submodule can also be arranged in a parallel circuit to the series circuit of the submodules 5j.
In operation of the converter 3 a battery voltage uq (FIG. 1) is applied to the converter 3 by the battery 4 via the battery circuit 8. Under the effect of the battery voltage uq and the inductance 7 a supply current with a battery voltage strength of iL (abbreviated to “battery current iL” below) flows in the battery circuit 8.
In a drive mode of the converter 3 the submodules 5j are connected to the battery circuit 8 for feeding the loads 2j with electrical energy from the battery 4 in an alternating sequence over time. To this end the semiconductor switch 29 in the input bridge 20 of the respective submodule 5j to be connected is opened, so that the DC link circuit capacitance 22 of this submodule 5j is switched via the input terminals 9 and 10 and the semiconductor switch 30 into the battery circuit 8. As a rule a number of submodules 5j are connected in simultaneously in this way.
The other submodule or each remaining submodule 5j on the other hand is disconnected from the battery circuit 8, in that the input terminals 9 and 10 of this submodule 5j are short-circuited by the respective semiconductor switch 29 in each case.
For a positive current flow direction of the battery current iL flowing in the battery circuit 8 the DC link circuit capacitance 22 of the respective submodule 5j connected is charged from the battery circuit 8, so that the DC link circuit voltage vaj falling via the DC link circuit capacitance changes over time.
The input bridge 20 of the submodule 5j connected in each case is operated in such cases in conjunction with the inductance 7 as a boost converter. The semiconductor switch 29 is switched on and off in clocked operation for this purpose. The second semiconductor switch 30 of the input bridge 20 is preferably always switched in opposition to the semiconductor switch 29.
In a feedback mode the converter 3 can alternatively also be employed for feeding back electrical energy into the battery circuit 8. During generation of a negative current flow direction in the battery circuit 8 the input bridges 20 of the submodules 5j are activated and deactivated alternately especially in clocked operation once again. Also in feedback mode the semiconductor switch 29 is preferably always activated in opposition to the semiconductor switch 30 in this case.
For activation of the semiconductor switches 29 and 30 of each submodule 5j the gate terminals of the semiconductor switches 29 and 30 each have a binary input control signal applied to them by the control unit 6, which is also referred to below as the switching position parameter q (with j=1, 2, . . . , n). In the exemplary embodiment each of the switching position parameters qj has the value “1”, when the associated submodule 5j is disconnected from the battery circuit 8 (semiconductor switch 29 closed, semiconductor switch 30 opened). Each of the switching position parameters qj on the other hand has the value “0” when the associated submodule 5j is connected to the battery circuit 8 (semiconductor switch 29 opened, semiconductor switch 30 closed). In respect of its time curve each switching position parameter qj corresponds to a pulse signal with periodic clocking (i.e. a pulse and a pulse interval within a constant clock cycle in each case) and varying duty cycle dj (j=1, 2, . . . , n).
In return the control unit 6 receives a measured value of the respective link circuit voltage vaj from the submodules 5j as an input variable. The DC link circuit voltage vaj is tapped for this purpose in each submodule 5 in each case by means of a measuring converter 31 (FIG. 2) which supplies the control unit 6 with a voltage signal proportional to the respective DC link circuit voltage vaj.
As further input variables the control unit 6 obtains a measured value (the current strength) of the output current iaj (j=1, 2, . . . , n) from each submodule 5j, which flows out on the load side in the DC link circuit 25 of the respective submodule 5j. The respective output current iaj is tapped off by a measurement converter 32 connected into the DC link circuit (FIG. 2). As an alternative the respective output current iaj is determined computationally on the basis of the measured load-side AC currents and the switching positions of the output bridges 21.
In addition the control unit 6 receives a measured value (the current strength) of the battery current iL, which is tapped off by a measurement converter 33 (FIG. 1) in the battery circuit 8.
The DC link circuit voltages vaj of the submodules 5 are regulated by the control unit to a voltage target value vajs (with j=1, 2 . . . , n) assigned in each case. The voltage target values vajs in such cases, in the general application case of the inventive converter 3, are predetermined specifically for each submodule 5 and can be accordingly optionally defined with the same or with a different amount. The control unit 6 also controls the battery current iL in addition to the closed-loop control of the DC link circuit voltages vaj.
The control unit 6 is formed by a microcontroller, in which the functionality for automatically carrying out the closed-loop control outlined here is implemented in software by a control program (firmware). The functional layout of this control program is shown schematically in FIG. 3. In this figure the control unit 6 is embodied functionally as a closed-loop control structure 40 with two degrees of freedom with a pilot control 41 and closed-loop subsequent error control 42 connected downstream therefrom.
The pilot control 41 receives as input variables the voltage target values vajs of the DC link circuit voltages vaj and also the temporal average current values <iaj> of the measured output currents iaj. The average current values <iaj> are generated by means of a recursive average value filter (not shown in any greater detail) which with each new measurement of the output currents iaj, calculates an updated value of the respective average current value <iaj> by weighted summation of the previous average current value <iaj> with the new measured value of the output current iaj:

w·iaj+(1−w)·iaj→iaj  EQ. 1

The parameter w (0<w<1) in EQ. 1 stands here for an empirically selectable weighting parameter.
Furthermore a constant assumed value ûq for the battery voltage uq is permanently predetermined to the pilot control 41.
On the basis of the voltage target values vajs of the DC link circuit voltages vaj, of the average current values <iaj> and of the predetermined assumed value ûq, the pilot control 41 calculates a target value djs (j=1, 2, . . . n) for each duty cycle dj in a way explained in greater detail below.
The pilot control 41 preferably outputs the target values djs in such cases in the form of a target setting variable vector us with

us=[d1s,d2s, . . . ,dns]T  EQ. 2

to the closed-loop subsequent error control 42. The notation [ . . . ]T here identifies the transposed (in the mathematical sense) value of the specified row vector. In other words us is generated and processed in the mathematical sense as a column vector.

Furthermore the pilot control 41 determines a target value iLs for the battery current iL. The pilot control 41 preferably forms a target output variable vector ys from the target values vajs of the DC link circuit voltages vaj with

ys=[va1s,va2s, . . . ,vans]T  EQ. 3

and also a target state variable vector xs from the target values iLs and vajs of the battery current iL or of the DC link circuit voltages vaj 

xs=[iLs,va1s,va2s, . . . ,vans]T  EQ. 4

and supplies these vectors ys and xs to the closed-loop subsequent error control 42.

The closed-loop subsequent error control 42 compares the target output variable vector ys in a differentiation element 43 with an output variable vector y containing the actual values of the DC link circuit voltages vaj measured at the converter 3:

y=[va1,va2, . . . ,van]T  EQ. 5

An output error signal ey resulting from this

ey=[va1s−va1,va2s−va2, . . . ,vans−van]T  EQ. 6

is supplied within the closed-loop subsequent error control 42 to a closed-loop output control 44, which by multiplication with a control parameter Kv, calculates a first correction variable du1 in accordance with

du1=Kv·v,  EQ. 7

with




  
    
      
        
          
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The regulation parameter Kv, as well as the parameters S and Bey, each have the mathematical form of an n×n matrix. The correction variable du1 and the variables v each have the mathematical form of an n-dimensional column vector. In accordance with normal convention the notation d/dt stands for the temporal change (i.e. the derivation after the time t). The parameter S is given in most application cases by the null matrix (S=0). The above equation thus reduces as a rule to

dv/dt=Bey·ey,  EQ. 9

through which an integration in the closed-loop output control 44 is carried out.

In individual cases the parameter S can be occupied by various values other than zero (see e.g. Annex 3).
The target state variable vector xs is compared, in closed-loop subsequent error control 42 in a differential element 45 with a state variable vector x, which contains the actual values of the battery current iL measured at the converter 3 and also the DC link circuit voltages vaj:

x=[iL,va1,va2, . . . ,van]T  EQ. 10

A state error signal ex resulting from this comparison with

ex=[iLs−iL,va1s−va1,va2s−va2, . . . ,vans−van]T  EQ. 11

is supplied within the closed-loop subsequent error control 42 to a closed-loop state control 46, which, by multiplication with a regulation parameter Kx, calculates a second correction variable du2 in accordance with

du2=Kx·ex.  EQ. 12

The closed-loop control parameter Kx and the correction variable du2 in their turn have the mathematical form of an n×n matrix of an n-dimensional column vector.
The correction variables du1 and du2 are summed in a summation element 47 with the target setting variable vector us. A setting variable vector u resulting from this with

u=us+du1+du2,  EQ. 13

which contains the actual duty cycles dj to be set

u=[d1,d2, . . . ,dn]T,  EQ. 14

is supplied in the way described above to the converter 3. The duty cycles dj contained in the setting variable vector u are naturally restricted in each case to a range of values from 0≦dj≦1. Optionally a closed-loop output control 44 can additionally be supplied in a manner known per se with a correction signal of an anti-windup structure, provided the setting variable vector u contains duty cycles dj outside the range of values 0≦dj≦1.

During operation of the converter 3 the pilot control 41 guides the system. In this case the average current values <iaj> of the output currents iaj entered into the pilot control 41 determine the target value iLs of the battery current strength iL. The closed-loop subsequent error control 42 merely has to compensate for subsequent errors and mapping inaccuracies of the pilot control 41 and therefore only intervenes a little into the system behavior. The integral component of the closed-loop control provided in the closed-loop output control 44 balances out fluctuations in the battery voltage uq, without said voltage having to be measured for this purpose. In addition the integral component of the closed-loop control structure 40 with two degrees of freedom lends robustness.
The pilot control 41 is based on an approximate inverse mathematical mapping of the electrical system formed by the converter 3.
The pilot control 41 is based here on a mathematical model of the converter 3, which relates the currents and voltages to one another in the converter 3 according to Kirchhoffs rules:




  
    
      
        
          
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                          a
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      
                        C
                        1
                      
                    
                  
                
              
              
                
                  
                    -
                    
                      
                        i
                        a2
                      
                      
                        C
                        2
                      
                    
                  
                
              
              
                
                  ⋮
                
              
              
                
                  
                    -
                    
                      
                        i
                        
                          a
                          ⁢
                          
                            
                          
                          ⁢
                          n
                        
                      
                      
                        C
                        n
                      
                    
                  
                
              
            
            )
          
          +
          
            
              (
              
                
                  
                    
                      1
                      L
                    
                  
                
                
                  
                    0
                  
                
                
                  
                    0
                  
                
                
                  
                    ⋮
                  
                
                
                  
                    0
                  
                
              
              )
            
            ·
            
              u
              q
            
          
        
      
    
    
      
        EQ
        .
        
          
        
        ⁢
        15
      
    
  




In this equation

    
    
        Ri is the internal resistance of the battery 4
        L is the inductance 7
        Rj is the assumed loss resistance of the output circuit 21 in submodule 5j (j=1, 2, . . . , n) and
        Cj is the DC link circuit capacitance 22 of the submodule 5j (j=1, 2, . . . , n).
    
    


For the purpose of pilot control 41 this model is modified such that the switch position parameters qj will always be replaced by the respective associated duty cycle dj.




  
    
      
        
          
            d
            x
          
          
            d
            t
          
        
        =
        
          
            
              [
              
                
                  
                    
                      -
                      
                        
                          R
                          i
                        
                        L
                      
                    
                  
                  
                    
                      -
                      
                        
                          (
                          
                            1
                            -
                            
                              d
                              1
                            
                          
                          )
                        
                        L
                      
                    
                  
                  
                    
                      -
                      
                        
                          (
                          
                            1
                            -
                            
                              d
                              2
                            
                          
                          )
                        
                        L
                      
                    
                  
                  
                    ...
                  
                  
                    
                      -
                      
                        
                          (
                          
                            1
                            -
                            
                              d
                              n
                            
                          
                          )
                        
                        L
                      
                    
                  
                
                
                  
                    
                      
                        (
                        
                          1
                          -
                          
                            d
                            1
                          
                        
                        )
                      
                      
                        C
                        1
                      
                    
                  
                  
                    
                      -
                      
                        1
                        
                          
                            R
                            1
                          
                          ⁢
                          
                            C
                            1
                          
                        
                      
                    
                  
                  
                    0
                  
                  
                    ...
                  
                  
                    0
                  
                
                
                  
                    
                      
                        (
                        
                          1
                          -
                          
                            d
                            2
                          
                        
                        )
                      
                      
                        C
                        2
                      
                    
                  
                  
                    0
                  
                  
                    
                      -
                      
                        1
                        
                          
                            R
                            2
                          
                          ⁢
                          
                            C
                            2
                          
                        
                      
                    
                  
                  
                    ...
                  
                  
                    0
                  
                
                
                  
                    ⋮
                  
                  
                    ⋮
                  
                  
                    ⋮
                  
                  
                    ⋱
                  
                  
                    ⋮
                  
                
                
                  
                    
                      
                        (
                        
                          1
                          -
                          
                            d
                            n
                          
                        
                        )
                      
                      
                        C
                        n
                      
                    
                  
                  
                    0
                  
                  
                    0
                  
                  
                    ...
                  
                  
                    
                      -
                      
                        1
                        
                          
                            R
                            n
                          
                          ⁢
                          
                            C
                            n
                          
                        
                      
                    
                  
                
              
              ]
            
            ·
            x
          
          +
          
            (
            
              
                
                  0
                
              
              
                
                  
                    -
                    
                      
                        i
                        
                          a
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      
                        C
                        1
                      
                    
                  
                
              
              
                
                  
                    -
                    
                      
                        i
                        a2
                      
                      
                        C
                        2
                      
                    
                  
                
              
              
                
                  ⋮
                
              
              
                
                  
                    -
                    
                      
                        i
                        
                          a
                          ⁢
                          
                            
                          
                          ⁢
                          n
                        
                      
                      
                        C
                        n
                      
                    
                  
                
              
            
            )
          
          +
          
            
              (
              
                
                  
                    
                      1
                      L
                    
                  
                
                
                  
                    0
                  
                
                
                  
                    0
                  
                
                
                  
                    ⋮
                  
                
                
                  
                    0
                  
                
              
              )
            
            ·
            
              u
              q
            
          
        
      
    
    
      
        EQ
        .
        
          
        
        ⁢
        16
      
    
  




In addition

    
    
        The temporal change in the state variable vector x is ignored (dx/dt=0),
        the time-discrete values of the output currents iaj are always replaced by the assigned average current value <iaj>,
        the actual battery voltage ug is replaced by the assumed value ûq,
        the state variable vector x is replaced by the target state variable vector xs, and
        the duty cycles dj are replaced by the respective assigned target value djs. In addition the state variable vector is replaced by the target state variable vector xs.
    
    


Thus EQ. 16 reduces to




  
    
      
        
          0
          =
          
            
              
                [
                
                  
                    
                      
                        -
                        
                          
                            R
                            i
                          
                          L
                        
                      
                    
                    
                      
                        -
                        
                          
                            (
                            
                              1
                              -
                              
                                d
                                
                                  1
                                  ⁢
                                  s
                                
                              
                            
                            )
                          
                          L
                        
                      
                    
                    
                      
                        -
                        
                          
                            (
                            
                              1
                              -
                              
                                d
                                
                                  2
                                  ⁢
                                  s
                                
                              
                            
                            )
                          
                          L
                        
                      
                    
                    
                      ...
                    
                    
                      
                        -
                        
                          
                            (
                            
                              1
                              -
                              
                                d
                                
                                  n
                                  ⁢
                                  
                                    
                                  
                                  ⁢
                                  s
                                
                              
                            
                            )
                          
                          L
                        
                      
                    
                  
                  
                    
                      
                        
                          (
                          
                            1
                            -
                            
                              d
                              
                                1
                                ⁢
                                s
                              
                            
                          
                          )
                        
                        
                          C
                          1
                        
                      
                    
                    
                      
                        -
                        
                          1
                          
                            
                              R
                              1
                            
                            ⁢
                            
                              C
                              1
                            
                          
                        
                      
                    
                    
                      0
                    
                    
                      ...
                    
                    
                      0
                    
                  
                  
                    
                      
                        
                          (
                          
                            1
                            -
                            
                              d
                              
                                2
                                ⁢
                                s
                              
                            
                          
                          )
                        
                        
                          C
                          2
                        
                      
                    
                    
                      0
                    
                    
                      
                        -
                        
                          1
                          
                            
                              R
                              2
                            
                            ⁢
                            
                              C
                              2
                            
                          
                        
                      
                    
                    
                      ...
                    
                    
                      0
                    
                  
                  
                    
                      ⋮
                    
                    
                      ⋮
                    
                    
                      ⋮
                    
                    
                      ⋱
                    
                    
                      ⋮
                    
                  
                  
                    
                      
                        
                          (
                          
                            1
                            -
                            
                              d
                              
                                n
                                ⁢
                                
                                  
                                
                                ⁢
                                s
                              
                            
                          
                          )
                        
                        
                          C
                          n
                        
                      
                    
                    
                      0
                    
                    
                      0
                    
                    
                      ...
                    
                    
                      
                        -
                        
                          1
                          
                            
                              R
                              n
                            
                            ⁢
                            
                              C
                              n
                            
                          
                        
                      
                    
                  
                
                ]
              
              ·
              
                x
                s
              
            
            +
            
              (
              
                
                  
                    0
                  
                
                
                  
                    
                      -
                      
                        
                          〈
                          
                            i
                            
                              a
                              ⁢
                              
                                
                              
                              ⁢
                              1
                            
                          
                          〉
                        
                        
                          C
                          1
                        
                      
                    
                  
                
                
                  
                    
                      -
                      
                        
                          〈
                          
                            i
                            
                              a
                              ⁢
                              
                                
                              
                              ⁢
                              2
                            
                          
                          〉
                        
                        
                          C
                          2
                        
                      
                    
                  
                
                
                  
                    ⋮
                  
                
                
                  
                    
                      -
                      
                        
                          〈
                          
                            i
                            
                              a
                              ⁢
                              
                                
                              
                              ⁢
                              n
                            
                          
                          〉
                        
                        
                          C
                          n
                        
                      
                    
                  
                
              
              )
            
            +
            
              
                (
                
                  
                    
                      
                        1
                        L
                      
                    
                  
                  
                    
                      0
                    
                  
                  
                    
                      0
                    
                  
                  
                    
                      ⋮
                    
                  
                  
                    
                      0
                    
                  
                
                )
              
              ·
              
                
                  u
                  ^
                
                q
              
            
          
        
        ,
      
    
    
      
        EQ
        .
        
          
        
        ⁢
        17
      
    
  




the right-hand side of which is referred to as function f(iLs,us).

The modified model of the converter 3 in accordance with EQ. 17 is resolved by the pilot control 41 after insertion of the voltage target values vajs specified as input variables and the average current values <iaj>, by the pilot control 41 minimizing the quadratic norm of the function f(iLs,us) by means of an iterative optimization method while varying the target values iLs and djs,

min{∥f(iLs,us)∥2;iLsεR,usεRn}→iLs,us,  EQ. 18

wherein R stands for the quantity of real numbers.

For this purpose the pilot control 41 uses a suitable optimization algorithm, especially what is referred to as the Levenberg-Marquardt algorithm. The pilot control 41 assumes iLs=djs=0 as start values for the optimization.
In an expanded version of the closed-loop control structure 40 with two degrees of freedom in accordance with FIG. 4, the target setting variable vector us will additionally be modified in the summation element 47 by a periodic compensation signal uv in the form




  
    
      
        
          
            
              
                u
                v
              
              =
              
              ⁢
              
                
                  [
                  
                    
                      u
                      
                        v
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    ,
                    
                      u
                      
                        v
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    ,
                    ...
                    ⁢
                    
                      
                    
                    ,
                    
                      u
                      
                        v
                        ⁢
                        
                          
                        
                        ⁢
                        n
                      
                    
                  
                  ]
                
                T
              
            
          
        
        
          
            
              =
              
              ⁢
              
                [
                
                  
                    k
                    ·
                    
                      (
                      
                        1
                        -
                        
                          sin
                          ⁡
                          
                            (
                            
                              
                                2
                                ⁢
                                
                                  
                                
                                ⁢
                                
                                  φ
                                  ω
                                
                              
                              +
                              
                                φ
                                1
                              
                            
                            )
                          
                        
                      
                      )
                    
                  
                  ,
                  
                    k
                    ·
                    
                      (
                      
                        1
                        -
                        
                          sin
                          ⁡
                          
                            (
                            
                              
                                2
                                ⁢
                                
                                  φ
                                  ω
                                
                              
                              +
                              
                                φ
                                2
                              
                            
                            )
                          
                        
                      
                      )
                    
                  
                  ,
                  ...
                  ⁢
                  
                    
                  
                  ,
                
              
            
          
        
        
          
            
              
                
                ⁢
                
                  k
                  ·
                  
                    (
                    
                      1
                      -
                      
                        sin
                        ⁡
                        
                          (
                          
                            
                              2
                              ⁢
                              
                                φ
                                ω
                              
                            
                            +
                            
                              φ
                              n
                            
                          
                          )
                        
                      
                    
                    )
                  
                
                ]
              
              T
            
          
        
      
    
    
      
        EQ
        .
        
          
        
        ⁢
        19
      
    
  




u=us+du1+du2+uv  EQ. 20

In the above equation φω stands for an angle of rotation with




  
    
      
        
          
            φ
            ω
          
          =
          
            
              ∫
              0
              t
            
            ⁢
            
              
                
                  ω
                  el
                
                ⁡
                
                  (
                  
                    t
                    ′
                  
                  )
                
              
              ·
              
                
              
              ⁢
              
                d
                
                  t
                  ′
                
              
            
          
        
        ,
      
    
    
      
        EQ
        .
        
          
        
        ⁢
        21
      
    
  




wherein ωei refers to the rotational frequency of the load currents. The size φj (with j=1, 2, . . . , n) refers to a phase offset of the load current for the respective submodule 2j. The parameter k can be set empirically and, depending on battery voltage, uq in the range of values 0≦k≦0.5.

Ripples of the DC link circuit voltages vaj as a result of currents which especially occur in single-phase AC consumers as loads 2j can be effectively reduced by the compensation signal uv. However in an expedient embodiment of the method, for very small output frequencies, the compensation signal uv for its part can be switched off, since the closed-loop output control 44 can operate the compensation of the voltage fluctuations more effectively under these circumstances.
In quasi mains mode of the converter 3, i.e. with an essentially constant rotational frequency ωei of the load currents generated by the submodules 5j, the voltage fluctuations caused by the ripples of the output currents iaj can as an alternative also be compensated for in accordance with Annex 3 by the closed-loop output control 44.
The closed-loop control parameters Kv, Kx and the further parameters Bey of the closed-loop output control 44 can basically be determined empirically. Preferably the closed-loop control parameters Kv, Kx can however be calculated in accordance with Annex 1 by linearization and development of the system by one or more working points.
As an alternative to the measuring detection described here, the battery voltage ug and/or the battery current iL can also be determined in accordance with Annex 2 by state reconstruction.
The target values vajs of the DC link circuit voltages vaj are preferably predetermined to be the same values for all submodules 5j and are especially defined such that their sum corresponds to double the battery voltage uq




  
    
      
        
          v
          ajs
        
        =
        
          
            2
            n
          
          ·
          
            
              u
              q
            
            .
          
        
      
    
    
      
        EQ
        .
        
          
        
        ⁢
        22
      
    
  




With this dimensioning, differences in power of the individual submodules 5j in boost mode of the converter 2 can be balanced out in the best possible way.
The stability of the closed-loop control structure 40 with two degrees of freedom is constantly monitored by the control unit 6. As part of this monitoring, if at least one of the duty cycles dj becomes saturated, i.e. assumes a limit value of 0 or 1 for more than a predetermined period of time, the target values for the DC link circuit voltages vaj can be temporarily increased or reduced. In this way unstable states of the closed-loop control structure 40 with two degrees of freedom can be avoided.
Evidently the function of the pilot control 41 of the closed-loop control structure 40 with two degrees of freedom can be disrupted with disappearing battery current iL (iL=0) and small load currents iaj (iaj≈0) since in this case fluctuations and measurement imprecisions of the output currents iaj have a critical effect on the results of the calculation within the pilot control 41.
It is known that the control unit 6 achieves an effective error clearance of the pilot control 41 here in that, instead of the submodule-specific average current values <iaj>, it once again employs its average value




  
    
      
        
          〈
          
            i
            a
          
          〉
        
        =
        
          
            1
            n
          
          ·
          
            
              ∑
              
                j
                =
                1
              
              n
            
            ⁢
            
              〈
              
                i
                aj
              
              〉
            
          
        
      
    
    
      
        EQ
        .
        
          
        
        ⁢
        23
      
    
  




as the input variable for the pilot control 41.

The invention is not restricted to the exemplary embodiments described here. Instead further embodiments of the invention can be derived by the person skilled in the art from the present description and the following Annexes.
Annex 1: System Linearization and Development
EQ. 16 can be rewritten into




  
    
      
        
          
            d
            x
          
          
            d
            t
          
        
        =
        
          
            x
            .
          
          =
          
            
              f
              ⁡
              
                (
                
                  x
                  ,
                  u
                
                )
              
            
            +
            
              z
              i
            
            +
            
              z
              q
            
          
        
      
    
    
      
        
          EQ
          .
          
            
          
          ⁢
          A1
        
        ⁢
        .1
      
    
  




with





  
    
      f
      ⁡
      
        (
        
          x
          ,
          u
        
        )
      
    
    =
    
      (
      
        
          
            
              
                
                  -
                  
                    
                      R
                      i
                    
                    L
                  
                
                ·
                
                  i
                  L
                
              
              -
              
                
                  
                    (
                    
                      1
                      -
                      
                        d
                        1
                      
                    
                    )
                  
                  L
                
                ·
                
                  v
                  
                    a
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
              
              -
              
                
                  
                    (
                    
                      1
                      -
                      
                        d
                        2
                      
                    
                    )
                  
                  L
                
                ·
                
                  v
                  
                    a
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
              -
            
          
        
        
          
            
              ...
              -
              
                
                  
                    
                      (
                      
                        1
                        -
                        
                          d
                          n
                        
                      
                      )
                    
                    L
                  
                  ·
                  
                    v
                    an
                  
                
                ⁢
                
                  
                    
                      (
                      
                        1
                        -
                        
                          d
                          1
                        
                      
                      )
                    
                    
                      C
                      1
                    
                  
                  ·
                  
                    i
                    L
                  
                
              
              -
              
                
                  1
                  
                    
                      R
                      1
                    
                    ⁢
                    
                      C
                      1
                    
                  
                
                ·
                
                  v
                  
                    a
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
              
            
          
        
        
          
            
              
                
                  
                    (
                    
                      1
                      -
                      
                        d
                        2
                      
                    
                    )
                  
                  
                    C
                    2
                  
                
                ·
                
                  i
                  L
                
              
              -
              
                
                  1
                  
                    
                      R
                      2
                    
                    ⁢
                    
                      C
                      2
                    
                  
                
                ·
                
                  v
                  
                    a
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
          
        
        
          
            ⋮
          
        
        
          
            
              
                
                  
                    (
                    
                      1
                      -
                      
                        d
                        n
                      
                    
                    )
                  
                  
                    C
                    n
                  
                
                ·
                
                  i
                  L
                
              
              -
              
                
                  1
                  
                    
                      R
                      n
                    
                    ⁢
                    
                      C
                      n
                    
                  
                
                ·
                
                  v
                  
                    a
                    ⁢
                    
                      
                    
                    ⁢
                    n
                  
                
              
            
          
        
      
      )
    
  
  ;








  
    z
    i
  
  =
  
    
      
        (
        
          
            
              0
            
          
          
            
              
                -
                
                  
                    i
                    
                      a
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  
                    C
                    1
                  
                
              
            
          
          
            
              
                -
                
                  
                    i
                    
                      a
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                  
                    C
                    2
                  
                
              
            
          
          
            
              ⋮
            
          
          
            
              
                -
                
                  
                    i
                    
                      a
                      ⁢
                      
                        
                      
                      ⁢
                      n
                    
                  
                  
                    C
                    n
                  
                
              
            
          
        
        )
      
      ⁢
      and
      ⁢
      
        
      
      ⁢
      
        z
        q
      
    
    =
    
      
        (
        
          
            
              
                1
                L
              
            
          
          
            
              0
            
          
          
            
              0
            
          
          
            
              ⋮
            
          
          
            
              0
            
          
        
        )
      
      ·
      
        u
        q
      
    
  




The following also applies

x=[iL,va1,Va2, . . . van]T and h(x)=y=[va1,va2, . . . ,van]T 

The system is operated in working point AP with

x=xAP,u=uAP and ia=iAP.

Around this working point AP a system linearization takes place, from which for small deviations Δx and Δu from the working point of the system description is

Δ{dot over (x)}=A·Δx+B·Δu and Δy=C·Δx  EQ. A1.2

with the Jacobi matrices





  
    A
    =
    
      
        
          ∂
          
            f
            ⁡
            
              (
              
                x
                ,
                u
              
              )
            
          
        
        
          ∂
          x
        
      
      ⁢
      
        |
        
          A
          ⁢
          
            
          
          ⁢
          P
        
      
      ⁢
      
        +
        
          
            ∂
            
              z
              i
            
          
          
            ∂
            
              i
              a
            
          
        
      
      ⁢
      
        |
        AP
      
    
  
  ;
  
    B
    =
    
      
        
          ∂
          
            (
            
              f
              ⁡
              
                (
                
                  x
                  ,
                  u
                
                )
              
            
            )
          
        
        
          ∂
          u
        
      
      ⁢
      
        |
        AP
      
    
  
  ;
  
    C
    =
    
      
        ∂
        
          h
          ⁡
          
            (
            x
            )
          
        
      
      
        ∂
        x
      
    
  




For the faults zi and zq, Δzi=0 and Δzq=0 should apply. The row development for the working point linearization is aborted after the first row element.
As a rule the linearized system description is expanded in accordance with EQ. A1.2 by an integral component




  
    
      
        
          
            v
            .
          
          =
          
            
              
                d
                v
              
              
                d
                t
              
            
            =
            
              
                S
                ·
                v
              
              +
              
                
                  
                    B
                    
                      e
                      ⁢
                      
                        
                      
                      ⁢
                      y
                    
                  
                  ·
                  
                    e
                    y
                  
                
                ⁢
                
                  
                
                ⁢
                with
              
            
          
        
        ⁢
        
          
        
        ⁢
        
          

        
        ⁢
        
          S
          =
          0
        
      
    
    
      
        
          EQ
          .
          
            
          
          ⁢
          A1
        
        ⁢
        .3
      
    
  




This produces the expanded path

Δ{dot over (x)}e=Ae·xe+Be·u  EQ. A1.4

with





  
    
      A
      e
    
    =
    
      (
      
        
          
            A
          
          
            0
          
        
        
          
            
              
                B
                
                  e
                  ⁢
                  
                    
                  
                  ⁢
                  y
                
              
              ⁢
              C
            
          
          
            0
          
        
      
      )
    
  
  ;
  
    
      B
      e
    
    =
    
      
        
          (
          
            
              
                B
              
            
            
              
                0
              
            
          
          )
        
        ⁢
        and
        ⁢
        
          
        
        ⁢
        
          x
          e
        
      
      =
      
        
          (
          
            
              
                x
              
            
            
              
                v
              
            
          
          )
        
        .
      
    
  




For stabilization of the expanded system the feedback





  u
  =
  
    
      -
      
        (
        
          
            
              
                K
                x
              
            
            
              
                K
                v
              
            
          
        
        )
      
    
    ·
    
      (
      
        
          
            x
          
        
        
          
            v
          
        
      
      )
    
  




is employed, which is generally designed for a number of working points AP.

The time-discrete values of the output currents iaj are preferably replaced in the above calculation by the average current values <iaj>. Likewise the setting variable vector u is preferably replaced in the above calculation by the setting variable vector us.

Annex 2: Reconstruction of the Battery Voltage and/or of the Battery Current

For the model in accordance with EQ. 16, with zi=uq, the assumed relationship is





  
    
      
        
          
            d
            
              x
              b
            
          
          
            d
            t
          
        
        =
        
          
            
              x
              .
            
            b
          
          =
          
             
            
              
                
                  [
                  
                    
                      
                        
                          -
                          
                            
                              R
                              i
                            
                            L
                          
                        
                      
                      
                        
                          -
                          
                            
                              (
                              
                                1
                                -
                                
                                  d
                                  1
                                
                              
                              )
                            
                            L
                          
                        
                      
                      
                        
                          -
                          
                            
                              (
                              
                                1
                                -
                                
                                  d
                                  2
                                
                              
                              )
                            
                            L
                          
                        
                      
                      
                        ...
                      
                      
                        
                          -
                          
                            
                              (
                              
                                1
                                -
                                
                                  d
                                  n
                                
                              
                              )
                            
                            L
                          
                        
                      
                      
                        
                          1
                          L
                        
                      
                    
                    
                      
                        
                          
                            (
                            
                              1
                              -
                              
                                d
                                1
                              
                            
                            )
                          
                          
                            C
                            1
                          
                        
                      
                      
                        
                          -
                          
                            1
                            
                              
                                R
                                1
                              
                              ⁢
                              
                                C
                                1
                              
                            
                          
                        
                      
                      
                        0
                      
                      
                        ...
                      
                      
                        0
                      
                      
                        0
                      
                    
                    
                      
                        
                          
                            (
                            
                              1
                              -
                              
                                d
                                2
                              
                            
                            )
                          
                          
                            C
                            2
                          
                        
                      
                      
                        0
                      
                      
                        
                          -
                          
                            1
                            
                              
                                R
                                2
                              
                              ⁢
                              
                                C
                                2
                              
                            
                          
                        
                      
                      
                        ...
                      
                      
                        0
                      
                      
                        0
                      
                    
                    
                      
                        ⋮
                      
                      
                        ⋮
                      
                      
                        ⋮
                      
                      
                        ⋱
                      
                      
                        ⋮
                      
                      
                        ⋮
                      
                    
                    
                      
                        
                          
                            (
                            
                              1
                              -
                              
                                d
                                n
                              
                            
                            )
                          
                          
                            C
                            n
                          
                        
                      
                      
                        0
                      
                      
                        0
                      
                      
                        ...
                      
                      
                        
                          -
                          
                            1
                            
                              
                                R
                                n
                              
                              ⁢
                              
                                C
                                n
                              
                            
                          
                        
                      
                      
                        0
                      
                    
                    
                      
                        0
                      
                      
                        0
                      
                      
                        0
                      
                      
                        ...
                      
                      
                        0
                      
                      
                        0
                      
                    
                  
                  ]
                
                ·
                
                  x
                  b
                
              
              +
              
                (
                
                  
                    
                      0
                    
                  
                  
                    
                      
                        -
                        
                          
                            i
                            
                              a
                              ⁢
                              
                                
                              
                              ⁢
                              1
                            
                          
                          
                            C
                            1
                          
                        
                      
                    
                  
                  
                    
                      
                        -
                        
                          
                            i
                            
                              a
                              ⁢
                              
                                
                              
                              ⁢
                              2
                            
                          
                          
                            C
                            2
                          
                        
                      
                    
                  
                  
                    
                      ⋮
                    
                  
                  
                    
                      
                        -
                        
                          
                            i
                            
                              a
                              ⁢
                              
                                
                              
                              ⁢
                              n
                            
                          
                          
                            C
                            n
                          
                        
                      
                    
                  
                  
                    
                      0
                    
                  
                
                )
              
            
          
        
      
    
    
      
        
          EQ
          .
          
            
          
          ⁢
          A2
        
        ⁢
        .1
      
    
  




and y=[va1, va2, . . . , van]T with the expanded state vector xb=[iL, va1, va2, . . . , van, ZI]T.

EQ. A2.1 is summarized as follows:

{dot over (x)}b=fb(xb,u)+zib  EQ. A2.2

By means of the state reconstruction the battery voltage uq and the battery current iL are now determined without direct measurement. For this purpose an observer in the general form





  
    
      
        
          
            
              
                
                  
                    x
                    ^
                  
                  .
                
                b
              
              =
              
                
                  
                    f
                    b
                  
                  ⁡
                  
                    (
                    
                      
                        
                          x
                          ^
                        
                        b
                      
                      ,
                      u
                    
                    )
                  
                
                +
                
                  z
                  
                    i
                    ⁢
                    
                      
                    
                    ⁢
                    b
                  
                
                +
                
                  L
                  ⁡
                  
                    (
                    
                      y
                      -
                      
                        y
                        ^
                      
                    
                    )
                  
                
              
            
          
        
        
          
            
              
                y
                ^
              
              =
              
                
                  [
                  
                    
                      
                        v
                        ^
                      
                      
                        a
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    ,
                    
                      
                        v
                        ^
                      
                      
                        a
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    ,
                    ...
                    ⁢
                    
                      
                    
                    ,
                    
                      
                        v
                        ^
                      
                      an
                    
                  
                  ]
                
                T
              
            
          
        
      
    
    
      
        
          EQ
          .
          
            
          
          ⁢
          A2
        
        ⁢
        .3
      
    
  




is implemented in the control unit 6.

The observer includes all states for reconstruction. Typically an observer in accordance with Luenberger is used. Other methods such as e.g. a Kalman filtering can however likewise be used within the framework of the invention.

As an alternative just the battery current iL can be reconstructed with the observer structure. The battery voltage uq is measured in this case or estimated by the constant assumed value ûq.

The time-discrete values of the output currents iaj are preferably replaced in the above calculation by their average current values <iaj>.

Annex 3: Closed-Loop Control in Quasi Mains Mode

The compensation for voltage fluctuations as a result of rippling of the output currents iaj described in conjunction with FIG. 4 requires knowledge of the rotational frequency ωei as well as the electrical phase angle φj (j=1, 2, . . . , n). Provided the rotational frequency ωei is approximately constant, the compensation can also be undertaken by implementing a corresponding interference model in the closed-loop output control 44.
For this purpose each row of the (column-vectoral) EQ. 8 is written as




  
    
      
        
          (
          
            
              
                
                  
                    v
                    .
                  
                  
                    j
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
              
            
            
              
                
                  
                    v
                    .
                  
                  
                    j
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
          
          )
        
        =
        
          
            
              
                (
                
                  
                    
                      0
                    
                    
                      1
                    
                  
                  
                    
                      
                        -
                        
                          
                            (
                            
                              2
                              ⁢
                              
                                ω
                                el
                              
                            
                            )
                          
                          2
                        
                      
                    
                    
                      0
                    
                  
                
                )
              
              
                }
                
                  S
                  i
                
              
            
            ·
            
              (
              
                
                  
                    
                      v
                      
                        j
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                  
                
                
                  
                    
                      v
                      
                        j
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                
              
              )
            
          
          +
          
            
              B
              eyj
            
            ·
            
              e
              yj
            
          
        
      
    
    
      
        
          EQ
          .
          
            
          
          ⁢
          A3
        
        ⁢
        .1
      
    
  




with j=1, 2, . . . , n.

Provided an approximately sinusoidal interference with the frequency 2ωei, as is typically caused by single-phase AC consumers as loads 2j, is present in the error signal eyj, the interference model is excited with its inherent frequency. The states v are echoed, but are stabilized by the feedback u=−Kv·v. If the states v are restricted, the fault can no longer be contained in the DC link circuit voltages vaj.
In order to not only compensate for the basic frequency of the interference but also for any harmonics which might be present, further oscillators with correspondingly high inherent frequencies can also be used in the closed-loop output control 44.
The method described here has the advantage of only requiring the DC link circuit voltages vaj to be detected by measurement and of especially not requiring any knowledge of the phase offset φj of the loads 2j to be available.
While the invention has been illustrated and described in connection with currently preferred embodiments shown and described in detail, it is not intended to be limited to the details shown since various modifications and structural changes may be made without departing in any way from the spirit and scope of the present invention. The embodiments were chosen and described in order to explain the principles of the invention and practical application to thereby enable a person skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.
What is claimed as new and desired to be protected by Letters Patent is set forth in the appended claims and includes equivalents of the elements recited therein:

## Claims

1. A method for operating a modular high-frequency converter having a plurality of submodules with input-side half bridge connected in series via an inductance to a supply circuit supplied by a DC voltage source, with each of the input-side half bridge having a DC link circuit with a DC link circuit capacitance connected across an output of the input-side half bridge, the method comprising:
clocking the associated input-side half bridge with a predetermined duty cycle so as to connect the DC link circuit capacitance of each input-side half bridge to the supply circuit,
controlling a DC link circuit voltage drop across the DC link circuit capacitance of each submodule to a predetermined DC link voltage target value by adjusting the predetermined duty cycle with a closed-loop control structure having a pilot control and a closed-loop error control connected downstream of the pilot control,
determining, for the pilot control, with a model that approximately mathematically models an interaction of currents and voltages in the supply circuit and currents and voltages in the submodules, a target duty cycle value for the predetermined duty cycle of each submodule and a target current value for a supply current supplied by the supply circuit, based on load-side output currents flowing out from the DC link circuits and based on the predetermined DC link voltage target values,
in the model, replacing switch position parameters that map an effect of switch positions of the input-side half bridges based on the determined duty cycle value, and
operating the converter with the replaced switch position parameters.

2. The method of claim 1, wherein changes over time in the DC link circuit voltages and in the supply current are neglected in the model.

3. The method of claim 1, wherein time-discrete measured values of the load-side output currents are used as input variables for the model.

4. The method of claim 1, wherein time-averaged values of the load-side output currents are used as input variables for the model.

5. The method of claim 4, wherein the time-averaged values of the load-side output currents are determined by using a recursive mean value filter.

6. The method of claim 1, wherein a target value for each duty cycle and a target value for the supply current are determined by numerically solving of the model by using an iterative optimization method.

7. The method of claim 1, wherein a voltage of the DC voltage source is used as an additional input variable for the model.

8. The method of claim 7, wherein the voltage of the DC voltage source is a predetermined constant value.

9. The method of claim 7, wherein the voltage of the DC voltage source is a value reconstructed by state reconstruction.

10. The method of claim 9, wherein a value for the supply current of the DC voltage source determined from state reconstruction is used for the closed-loop error control.

11. The method of claim 1, further comprising applying a periodic compensation signal applied to the duty cycles outputted by the closed-loop control structure so as to completely or partially compensate a periodic fault of the DC link circuit voltages.

12. A modular high-frequency converter, comprising:
a plurality of submodules having input sides connected in series via an inductance in a supply circuit supplied by a DC voltage source, wherein each submodule comprises an input-side half bridge, a DC link circuit connected downstream of the input-side half bridge and a DC link circuit capacitance connected in parallel with the input-side half bridge, and
a control device configured to automatically
clock the associated input-side half bridge with a predetermined duty cycle so as to connect the DC link circuit capacitance of each input-side half bridge to the supply circuit,
control a DC link circuit voltage drop across the DC link circuit capacitance of each submodule to a predetermined DC link voltage target value by adjusting the predetermined duty cycle with a closed-loop control structure having a pilot control and a closed-loop error control connected downstream of the pilot control,
determine, for the pilot control, with a model that approximately mathematically models an interaction of currents and voltages in the supply circuit and currents and voltages in the submodules, a target duty cycle value for the predetermined duty cycle of each submodule and a target current value for a supply current supplied by the supply circuit, based on load-side output currents flowing out from the DC link circuits and based on the predetermined DC link voltage target values,
in the model, replace switch position parameters that map an effect of switch positions of the input-side half bridges based on the determined duty cycle value, and
operate the converter with the replaced switch position parameters.