# Patent

## Title
Method for controlling a switching regulator and related switching regulator

## Abstract

An embodiment of a power-supply controller comprises a switching-control circuit, an error amplifier, and a signal generator. The switching-control circuit is operable to control a switch coupled to a primary winding of a transformer, and the error amplifier has a first input node operable to receive a feedback signal, a second input node operable to receive a comparison signal, and an output node operable to provide a control signal to the switching-control circuit. The signal generator is operable to generate either the feedback signal or the comparison signal in response to a compensation signal that is isolated from a secondary winding of the transformer and that is proportional to a load current through a conductor disposed between the secondary winding and a load.

## Background
TECHNICAL FIELD
An embodiment of the disclosure relates to techniques for generating a controlled voltage and more particularly to the methods for controlling a switching regulator.
BACKGROUND
A block diagram of a voltage regulator that supplies a load L through a cable C is depicted in FIG. 1. A control system keeps the voltage generated by the converter at a constant value when changes of the input voltage Vin and/or the load L occur.
Optionally, a second control system may be present to regulate the current delivered by the converter.
The two control systems are mutually exclusive: if the current demanded by the load is lower than the current regulation setpoint, the voltage control system will regulate the output voltage and the current control system will be inoperative; contrarily, the current control system will take over and the voltage loop will be inoperative. Voltage control and, when present, current control use a closed-loop negative feedback: the voltage generated by the converter and current through the load, respectively VOUT and IOUT, are fed back to the error amplifiers EAV and EAC and they are compared with their references VREF and IREF, respectively.
The input signals VCV, VCC to the controller come from the error amplifiers that sense the difference between reference values (VREF and IREF) and the feedback signals (VOUT and IOUT). Depending on the input signals, the controller generates a PWM signal that drives power switches. Through a transformer, an output rectifier and a filter, energy is transferred from the supply voltage source VIN to the load L. The diagram shown in FIG. 1 is quite general and may have several possible alternative embodiments.
Typically, energy is transferred to the load through a cable C. The voltage control loop keeps the voltage Vout regulated but, depending on the output current, the voltage on the load, VLOAD, will be affected by a voltage drop along the cable, out of the control loop. Thus if a zero load regulation is to be achieved, it may be necessary to compensate the drop along the cable in some way.
A simple known way of meeting this potential need is illustrated in FIG. 2 and consists in using an additional sensing wire to sense the voltage VLOAD. In this way a zero load regulation may be achieved, but an additional wire is needed. A three-wire cable is not as common as a two-wire one and may be more expensive.
Another solution, that avoids the need of additional wires, is to adjust the voltage loop reference (VREF) by an amount proportional to the average output current, the value of which can be sensed directly even with a remote load. Cable drop compensation (briefly CDC) can be performed if the value of the cable resistance Rcable is known. This solution is depicted in FIG. 3.
The transfer function of the CDC block is:

V′REF=VREF+kCDC·IOUT,

where kCDC is the cable drop compensation gain and VREF is the adjusted reference.

In the circuit of FIG. 1, during voltage regulation, it is:

VOUT=kCV·VREF 

and

VLOAD=VOUT−Rcable·IOUT,

where kCV is the voltage loop gain, VOUT is the regulated voltage and VLOAD is the real voltage on the load.

With reference to the diagram of the FIG. 3 the output voltage is:

V′OUT=kCV·V′REF=V′REF=kCV·(VREF+kCDC·IOUT)=VOUT+kCV·kCDC·IOUT.

As the resistance Rcable is known by the application, the kCDC value is chosen in order to satisfy the condition VLOAD=VOUT, hence:




  
    
      k
      CV
    
    ·
    
      k
      CDC
    
  
  =
  
    
      
        R
        cable
      
      ⇒
      
        k
        CDC
      
    
    =
    
      
        
          R
          cable
        
        
          k
          CV
        
      
      .
    
  




Typically, the output current is sensed directly.
A common way of sensing the output current and adjusting the voltage reference proportionally in a non-isolated step-down switching converter is illustrated in FIG. 4 (from the STMicroelectronics AN1061 applications note, all versions of which are incorporated by reference). In particular, by connecting the resistor RK as shown in FIG. 4, it is possible to adjust the voltage reference value by shifting the ground voltage of the IC by an amount proportional to the current ILOAD.
A similar technique applied to an isolated flyback switching converter is shown in FIG. 5 (from the STMicroelectronics TSM1052 datasheet, all versions of which are incorporated by reference). Only the secondary side is shown; VOUT and IOUT are sensed and compared against their respective references; the error signal (of the loop in control) is transferred to the primary side via an optocoupler, where it is properly handled.
A typical isolated flyback configuration using the optocoupler to transfer the output information from secondary side to the primary one is shown in FIG. 6 (from the STMicroelectronics Viper53 datasheet, all versions of which are incorporated by reference).
There is a special class of low-cost isolated converters, in which output voltage regulation is quite loosely specified and use a simpler approach, according to which there is no sensing element or any reference on the secondary side and, therefore, no specific means for crossing the isolation barrier to transfer the error signal to the primary side, as depicted in FIG. 7 (from the STMicroelectronics Viper53 datasheet, all versions of which are incorporated by reference). In these systems, the voltage drop along the output cable adds to their inherently poor load regulation and can make unacceptable the use of such low-cost systems. In this case, a cable drop compensation circuit would make the difference. However, there is no known technique to compensate the cable resistance for this type of switching converter.
SUMMARY
It has been found that it is possible to use the technique of adjusting the voltage reference even in flyback switching converters that do not have any voltage or current sensing means on the secondary side, and also do not have means for transferring an error signal from the secondary side to the primary side of the converter.
It has been demonstrated that the average output current delivered by the converter may be accurately estimated using signals available on the primary side, by providing a dedicated circuit block for estimating such a value.
More precisely, the average output current IOUT is proportional to the product of Is and the ratio TONSEC/T wherein IS is the secondary peak current, TONSEC is the time during which the secondary current is flowing and T is the switching cycle.
It has been found that signals accurately proportional to the ratio TONSEC/T and to IS can be extracted from the primary side in any switching converter with primary feedback, thus it is not necessary to use dedicated sensors nor means for crossing the isolation barrier from the secondary side to the primary side.
For example, a signal accurately proportional to the ratio TONSEC/T may be produced in different alternative ways:

    
    
        measuring, with counters or with any other suitable digital means, the time interval TONSEC in which the logic control signal that flags the beginning and the end of demagnetization phases is active and the duration T of the switching period; and
        calculating the ratio between the above times for producing a signal the level of which represents the ratio TONSEC/T.
    
    


As an alternative, a signal proportional to the ratio TONSEC/T may be produced by integrating over each switching period the logic control signal that flags the beginning and the end of demagnetization phases.
Another signal proportional to the ratio (TONSEC/T)−1 may be obtained using the charge voltage of a filter capacitor on the primary side of the switching regulator that is discharged during each demagnetization phase by a resistor and is charged by a constant current in the remaining part of each switching period.
These signals representative of the current delivered to a load are used for estimating the voltage drop on the cable that connects the regulator to the load. Therefore, it is possible to control the effective voltage on the load instead of the voltage generated on the secondary side by the switching regulator.
Embodiments of the techniques herein described for estimating the output current of a flyback switching regulator without using sensing elements on the secondary side may be used also for other useful purposes.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 depicts a known architecture of a voltage regulator.
FIG. 2 depicts a known architecture of a voltage regulator using an additional sensing wire.
FIG. 3 depicts a known architecture of a voltage regulator with a compensation circuit for the voltage drop on the cable that connects the output of the regulator to a load.
FIG. 4 depicts a known architecture of a voltage regulator.
FIG. 5 depicts a known architecture of a voltage regulator.
FIG. 6 depicts a known architecture of a voltage regulator.
FIG. 7 depicts a known architecture of a voltage regulator.
FIG. 8 is a graph of typical current waveforms in the primary side and in the secondary side of a flyback switching regulator.
FIG. 9 reproduces a Zero Voltage Switching regulator disclosed in U.S. Pat. No. 6,590,789, which is incorporated by reference.
FIG. 10 depicts sample waveforms of the voltage across an auxiliary winding of the circuit of FIG. 9 for several values of the current absorbed by the load.
FIG. 11 reproduces a Zero Voltage Switching regulator disclosed in U.S. Pat. No. 5,729,443, which is incorporated by reference.
FIG. 12 is a graph of typical waveforms of the main signals of a Zero Voltage Switching regulator of FIG. 11.
FIG. 13 depicts a first analog embodiment of a CDC circuit block for adjusting the reference voltage of a voltage error amplifier of a switching regulator.
FIG. 14 depicts a first embodiment of a switching regulator that includes a CDC block for adjusting the reference voltage.
FIG. 15 depicts an alternative embodiment of a switching regulator that includes a CDC block for adjusting the feedback voltage of the regulator.
FIG. 16 depicts another alternative embodiment of a switching regulator that includes a CDC block for adjusting the feedback voltage of the regulator.
FIG. 17 shows a first digital embodiment of a circuit for generating a signal proportional to the ratio TONSEC/T.
FIG. 18 shows an alternative digital embodiment of a circuit for generating a signal proportional to the ratio TONSEC/T.
FIG. 19 shows a first analog embodiment of a circuit for generating a signal proportional to the ratio TONSEC/T.
FIG. 20 depicts an alternative analog embodiment of a circuit for generating a signal proportional to the ratio TONSEC/T.
FIG. 21 depicts another embodiment of a switching regulator that includes the CDC block for adjusting the reference voltage and a circuit for generating a signal proportional to the ratio TONSEC/T.



DETAILED DESCRIPTION
Primary and secondary sample current waveforms of a flyback switching converter working in discontinuous mode are depicted in FIG. 8. It will be assumed that its PWM modulator uses a current mode control. The average output current IOUT is:




  
    
      I
      OUT
    
    =
    
      
        
          I
          S
        
        2
      
      ·
      
        
          T
          ONSEC
        
        T
      
    
  
  ,




where, IS is the secondary peak current, TONSEC is the time during which the secondary current is flowing, and T is the switching-cycle period.

By adding a dedicated circuit, able to estimate the ratio TONSEC/T in the current mode IC controller, it is possible to calculate the IOUT value by the above formula. This approach may be applied to any current-mode-controlled switching converter with primary feedback.
In order to better understand the gist of this technique, the functioning of an off-line all-primary-sensing switching regulator, disclosed in U.S. Pat. Nos. 5,729,443 and 6,590,789 (which are incorporated by reference) will be discussed.
An equivalent high-level circuit scheme of the switching regulator disclosed in U.S. Pat. No. 6,590,789 for regulating the output voltage is reproduced in FIG. 9. An accurate image of the output voltage is obtained by sampling the voltage on the auxiliary winding immediately at the end of transformer's demagnetization phase, as illustrated in the graph of FIG. 10. The switch Q1 is turned on after the end of the demagnetization phase and then turned off by a comparator that monitors the source current of Q1 using a sense resistor RS.
An equivalent high level circuit scheme of the switching regulator disclosed in U.S. Pat. No. 5,729,443 for regulating the output current is reproduced in FIG. 11. The switch Q1 is operated by the PWM signal, set by the end of the demagnetization phase of the transformer, and reset by a comparator that monitors the source current of Q1 through the sense resistor RS.
The voltage of an auxiliary winding is used by a demagnetization block DEMAG through a protection resistor. The demagnetization block DEMAG generates a logic flag EOD that is high as long as the transformer delivers current to secondary side. Waveforms of the currents in the primary side and in the secondary side of the regulator, of the logic flag EOD, and of the current IC through the filter capacitor C during a switching period, are shown in FIG. 12.
The logic flag EOD is used to turn on and off a MOSFET switch Q2 for discharging/charging the filter capacitor C. A resistor R in series with it absorbs a current UC/R, where UC is the voltage across the capacitor C. This capacitor C filters the charge current IREF and the discharge current (IREF−UC/R) so that UC is practically a DC voltage, that is applied to an input of the current mode comparator.
At steady state, the average current IC is zero. If TONSEC is the time during which the secondary current IS is flowing, it is:




  
    
      
        
          I
          REF
        
        ·
        
          (
          
            T
            -
            
              T
              ONSEC
            
          
          )
        
      
      +
      
        
          (
          
            
              I
              REF
            
            -
            
              
                U
                C
              
              R
            
          
          )
        
        ·
        
          T
          ONSEC
        
      
    
    =
    0
  
  ,




which can be simplified in:





  
    
      
        
          U
          C
        
        =
        
          R
          ·
          
            I
            REF
          
          ·
          
            T
            
              T
              ONSEC
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




The voltage UC is then used to set the peak primary current IP:




  
    
      I
      P
    
    =
    
      
        U
        C
      
      
        R
        S
      
    
  
  ,




which defines the peak secondary current IS:





  
    
      
        
          I
          S
        
        =
        
          
            n
            ·
            
              I
              P
            
          
          =
          
            n
            ·
            
              
                U
                C
              
              
                R
                S
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




The average output current IOUT can be expressed as:




  
    
      
        
          I
          OUT
        
        =
        
          
            
              I
              S
            
            2
          
          ·
          
            
              T
              ONSEC
            
            T
          
        
      
    
    
      
        (
        3
        )
      
    
  




By combining the previous equations, we obtain:




  
    I
    OUT
  
  =
  
    
      n
      2
    
    ·
    
      
        
          R
          ·
          
            I
            REF
          
        
        
          R
          S
        
      
      .
    
  




Thus it is possible to set the average output current of the switching regulator by fixing the reference current IREF and the resistances R and RS.
It has been found that a signal proportional to the output current can be generated by using signals already available in the primary side of the converter.
Indeed, combining equations (1) and (3), leads to the following expression:




  
    
      
        
          U
          C
        
        =
        
          
            
              R
              ·
              
                I
                REF
              
            
            2
          
          ·
          
            
              I
              S
            
            
              I
              OUT
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




Hence the charge voltage of the filter capacitor contains information concerning the average output current, thus it can be used for compensating the voltage drop on the cable that connects a load to a flyback switching regulator.
Moreover, during the voltage regulation, the voltage control loop signal establishes the peak primary current




  
    
      
        
          I
          P
        
        =
        
          
            V
            CV
          
          
            R
            S
          
        
      
    
    
      
        (
        5
        )
      
    
  




wherein VCV is the voltage generated by the error amplifier EAV (in the circuit of FIG. 1) proportional to the difference between the reference voltage VREF and the output voltage VOUT generated by the controller.

Therefore, by combining the equations (4) and (5) it results:




  
    U
    C
  
  =
  
    
      n
      2
    
    ·
    
      
        R
        ·
        
          I
          REF
        
      
      
        R
        S
      
    
    ·
    
      
        V
        CV
      
      
        I
        OUT
      
    
  




In the above formula all the signals are known except for the IOUT value.
In the IC controller is inserted a dedicated CDC block for performing the division between the signals VCV and UC in order to obtain a signal proportional to the output current:




  
    
      
        
          
            V
            CV
          
          
            U
            C
          
        
        =
        
          
            2
            n
          
          ·
          
            
              R
              S
            
            
              R
              ·
              
                I
                REF
              
            
          
          ·
          
            I
            OUT
          
        
      
    
    
      
        (
        6
        )
      
    
  




In an embodiment, the CDC block is analog, as depicted in FIG. 13, and comprises an analog divider the output of which is multiplied by a constant k, a filter and an analog subtractor of the output of the filter and the reference voltage VREF.
As an alternative, the CDC block could be digital, converting the signals VCV and UC in digital form, carrying out the division, subtracting the result from the voltage value VREF, and converting the result back into an analog signal.
The next step is to adjust the voltage reference VREF by an amount depending on the output current, as explained previously. In fact, the CDC block is designed to implement the following transfer function:




  
    V
    REF
    ′
  
  =
  
    
      V
      REF
    
    -
    
      k
      ·
      
        2
        n
      
      ·
      
        
          R
          S
        
        
          R
          ·
          
            I
            REF
          
        
      
      ·
      
        
          I
          OUT
        
        .
      
    
  




The CDC block, during the output voltage regulation, introduces a positive feedback that may compromise the stability of the primary loop. For this reason a low-pass filter is preferably added, as shown in FIG. 13.
Looking at FIG. 13 it is possible to notice the analog divider, the output signal of which is multiplied by a constant k, the filter and the analog subtractor.
FIG. 14 shows the architecture of an embodiment of a voltage mode converter, that includes a CDC block in the primary loop for adjusting the voltage reference value (VREF) by an amount proportional to the output current. The new voltage loop reference is VREF′. This allows to compensate the voltage drop along the output cable and, ideally, to achieve a zero load regulation.
This technique may be applied even by modifying the feedback voltage on the capacitor C* instead of directly acting on VREF. A sample embodiment of this type is shown in FIG. 15, where the CDC block sinks a current proportional to the output current from the feedback resistor divider in order to modify the sampled value:




  
    I
    CDC
  
  =
  
    k
    ·
    
      2
      n
    
    ·
    
      
        R
        S
      
      
        R
        ·
        
          I
          REF
        
      
    
    ·
    
      
        I
        OUT
      
      .
    
  




Another way to modify the voltage feedback signal value is to generate a voltage proportional to the output current:




  
    V
    CDC
  
  =
  
    
      V
      REF
    
    -
    
      k
      ·
      
        2
        n
      
      ·
      
        
          R
          S
        
        
          R
          ·
          
            I
            REF
          
        
      
      ·
      
        I
        OUT
      
    
  




and to connect a resistor RCDC as shown in the FIG. 16. The resistor RCDC is an external component which gives the user the possibility to set the CDC gain depending on the application. Its value is calculated by the following equation:





  
    
      R
      CDC
    
    =
    
      k
      ·
      
        2
        n
      
      ·
      
        
          N
          OUT
        
        
          N
          AUX
        
      
      ·
      
        
          R
          1
        
        
          R
          cable
        
      
      ·
      
        
          R
          S
        
        
          R
          ·
          
            I
            REF
          
        
      
    
  
  ,




where, n is the ratio between primary and secondary windings, NOUT is the number of the windings on the secondary, NAUX is the number of the windings on the auxiliary, Rcable is the cable resistance and RS is the sensing resistor connected to the power MOSFET source. The use of that resistor is a possible way to set the CDC gain depending on the application. In fact, applying the previous embodiments, without RCDC, the same objective can be reached by trimming the constant k value.

A signal proportional to the ratio TONSEC/T may be generated by exploiting the logic control signal EOD that flags the beginning and the end of magnetization phases, for example using the embodiment of the circuit depicted in FIG. 17. Two pulse counters COUNTER generate digital signals corresponding to the duration of the time intervals TONSEC and T−TONSEC by counting clock pulses while the signal EOD and the inverted replica thereof are active, respectively, then a calculation block DIGITAL CALCULATOR generates a digital signal that represents the ratio TONSEC/T, that is converted in a corresponding analog signal Vratio by a digital-to-analog converter DAC.
If the CDC block can be input with digital signals, then the converter DAC is not necessary.
According to an alternative embodiment, a signal proportional to the ratio TONSEC/T may be generated by the circuit of FIG. 18, that uses three monostable flip-flops for switching three capacitors C, C1 and C2. In correspondence of the leading edge of the signal EOD, the charge voltage of the capacitor C is sampled and held on the capacitor C1, and the capacitor C is discharged (signal RESET). The capacitor C is charged again by the current generator IREF and its charge voltage is sampled and held on the capacitor C2 when the signal EOD switches low (that is at the end of each demagnetization phase). Therefore, the charge voltages VC1 and VC2 of the capacitors C1 and C2 represent the duration of a period and of the magnetization phase, respectively:




  
    
      V
      
        C
        ⁢
        
          
        
        ⁢
        1
      
    
    =
    
      
        
          I
          REF
        
        C
      
      ·
      T
    
  
  ,
  
    
      V
      
        C
        ⁢
        
          
        
        ⁢
        2
      
    
    =
    
      
        
          I
          REF
        
        C
      
      ·
      
        T
        ONSEC
      
    
  




A divider generates the signal Vratio as the ratio VC2/VC1.
The signal RESET used for discharging the capacitor C is substantially a delayed replica of the pulse T, such to zero the charge voltage of the capacitor C substantially immediately after it has been held on the capacitor C1.
According to an alternative embodiment, the voltage Vratio may be generated by integrating the signal EOD over a switching period T, as schematically depicted in FIG. 19.
A CDC block suitable for using the voltage Vratio for adjusting the reference voltage VREF′ is depicted in FIG. 20. This CDC block is similar to that depicted in FIG. 13, but it has an input multiplier instead of an input divider.
An embodiment of a switching regulator that employs the CDC block of FIG. 20 and a circuit for generating a voltage Vratio proportional to the ratio TONSEC/T, such as the circuits of FIGS. 17 to 19, is shown in FIG. 21. The functioning of this switching regulator is evident in view of the description made referring to FIGS. 14 to 16. Furthermore, some to all of the components of the switching regulator of FIG. 21 may be disposed on an Integrated Circuit (IC) die, and the regulated output voltage VOUT may provide power to a circuit, such as a controller processor, that is disposed on the same die or on a different die.
Naturally, in order to satisfy local and specific requirements, a person skilled in the art may apply to the solution described above many modifications and alterations. Particularly, although the present disclosure has been described with a certain degree of particularity with reference to described embodiment(s) thereof, it should be understood that various omissions, substitutions and changes in the form and details as well as other embodiments are possible. Moreover, it is expressly intended that specific elements and/or method steps described in connection with any disclosed embodiment of the disclosure may be incorporated in any other embodiment as a general matter of design choice.

## Claims

1. A primary-sensing flyback switching regulator, having a primary side generating a primary voltage magnetically coupled to a secondary side that generates a regulated output voltage on output terminals of the regulator, the primary side including a feedback control circuit that generates a feedback voltage representative of said output voltage, a logic flag for flagging demagnetization phases of said switching regulator and a control voltage that fixes the maximum current level that may circulate in the primary side of the regulator in function of the difference between a reference voltage and said feedback voltage, said feedback control circuit further comprises:
a circuit for generating a signal representative of the ratio between the duration of a demagnetization phase and the respective switching period from signals in the primary side of the converter;
an auxiliary block input with said control voltage and with said representative signal and adapted to adjust said difference between the reference voltage and the feedback voltage in order to compensate eventual voltage differences between the regulated output voltage and the voltage effectively provided to a load supplied by the regulator.

2. The switching regulator of claim 1, wherein said circuit is a filter capacitor that is coupled to a current generator and to a resistor through a switch controlled by said logic flag, such to be discharged on said resistor during demagnetization phases and charged by said current generator during magnetization phases.

3. The switching regulator of claim 1, wherein said circuit is an integrator that generates said representative signal as the integral average of said logic flag over a switching period.

4. The switching regulator of claim 1, wherein said circuit comprises:
a first counter that counts externally provided clock pulses when said logic flag is high and is reset when said logic flag is low;
a second counter that counts said externally provided clock pulses when said logic flag is low and is reset when said logic flag is high;
a processor input with the countings of said counters first and second, that generates said representative signal of said ratio.

5. The switching regulator of claim 4, wherein said circuit further comprises a digital-to-analog converter downstream said processor that generates an analog replica of said representative signal.

6. The switching regulator of claim 1, wherein said circuit comprises:
a first monostable flip-flop input with said logic flag, that generates a first pulse signal in correspondence of trailing or leading edges of said logic flag;
a second monostable flip-flop input with said logic flag, that generates a second pulse signal in correspondence of leading or trailing edges of said logic flag;
a circuit block connected in cascade to said first monostable flip-flop, that generates a third pulse signal as a delayed replica of said first pulse signal;
a linear voltage ramp generator, reset at each assertion of said third pulse signal;
a first sample-and-hold circuit that samples the voltage generated by said ramp generator at each assertion of said first pulse signal;
a second sample-and-hold circuit that samples the voltage generated by said ramp generator at each assertion of said second pulse signal;
a divider that generates said representative signal as the ratio between the sampled voltages of said second sample-and-hold circuit and of said first sample-and-hold circuit.

7. The switching regulator of claim 6, wherein said sample-and-hold circuits first and second are switched capacitors first and second respectively, charged with said voltage ramp when said first and second pulse signals are asserted, respectively, and said circuit block is a third monostable flip-flop that generates a pulse in correspondence of each trailing edge of said second signal.

8. The switching regulator of claim 1, wherein said feedback control circuit comprises:
a voltage divider coupled to the winding of the primary side for generating a scaled replica of said output voltage;
an error amplifier generating said control voltage representative of the difference between the reference voltage and said feedback voltage;
a logic circuit that flags magnetization and demagnetization phases of said switching regulator and generates said logic flag.

9. The switching regulator of claim 8, wherein said auxiliary block is input with said reference voltage and generates an adjusted reference voltage input to the error amplifier instead of said reference voltage.

10. The switching regulator of claim 2, wherein said auxiliary block is coupled to said voltage divider such to adjust said feedback voltage in function of the ratio between said threshold voltage and the charge voltage of said filter capacitor.

11. The switching regulator of claim 2, wherein said auxiliary block comprises:
a divider input with said threshold voltage and the charge voltage of said filter capacitor, generating a quotient signal representative of said ratio;
an operational amplifier in cascade to said divider and input with said reference voltage, generating said adjusted reference voltage.

12. The switching regulator of claim 11, wherein said auxiliary block further comprises a low-pass filter that generates a low-pass replica of said quotient signal that is input to said operational amplifier.

13. The switching regulator of claim 10, wherein said auxiliary block comprises:
a divider input with said threshold voltage and the charge voltage of said filter capacitor, generating a quotient signal representative of said ratio;
an adjustable current generator controlled by said quotient signal, that absorbs a current proportional to said quotient signal from the middle node of said resistive voltage divider.

14. The switching regulator of claim 13, wherein said adjustable current generator of the auxiliary block is coupled to said middle node of the resistive voltage divider through an auxiliary resistor.

15. A method of controlling a primary-sensing flyback switching regulator, having a primary side generating a primary voltage magnetically coupled to a secondary side that generates a regulated output voltage on output terminals of the regulator, the primary side including a feedback control circuit that generates a feedback voltage representative of said output voltage, a logic flag for flagging demagnetization phases of said switching regulator and a control voltage that fixes the maximum current level that may circulate in the primary side of the regulator in function of the difference between a reference voltage and said feedback voltage, the method comprising:
generating a signal representative of the ratio between the duration of a demagnetization phase and the respective switching period, from signals in the primary side of the converter;
adjusting the difference between said reference voltage and the feedback voltage in function of said representative signal.

16. The method of claim 15, further comprising:
discharging a filter capacitor during demagnetization phases through a resistor and charging it with a constant current during the remaining part of switching periods flagged by said logic flag;
adjusting the difference between said reference voltage and said feedback signal in function of the ratio between said control voltage and the charge voltage of said filter capacitor.

17. A system, comprising:
a paired winding having a primary side and a secondary side;
a primary-sensing flyback switching regulator coupled to the paired winding such that the primary side generates a primary voltage magnetically coupled to the secondary side, the secondary side operable to generate a regulated output voltage on output terminals of the regulator; and
a feedback control circuit coupled to the primary winding that generates a feedback voltage representative of said output voltage, a logic flag for flagging demagnetization phases of said switching regulator and a control voltage that fixes the maximum current level that may circulate in the primary side of the regulator in function of the difference between a reference voltage and said feedback voltage, the feedback control circuit further comprising:
a comparison circuit for generating a signal representative of the ratio between the duration of a demagnetization phase and the respective switching period from signals in the primary side of the converter;
an auxiliary block input with said control voltage and with said representative signal and adapted to adjust said difference between the reference voltage and the feedback voltage in order to compensate eventual voltage differences between the regulated output voltage and the voltage effectively provided to a load supplied by the regulator.

18. The system of claim 17, further comprising a power supply coupled to the paired winding.

19. The system of claim 17 wherein the control circuit comprises an integrated circuit disposed on a single die.

20. The system of claim 17 further comprising a load coupled to the output terminals of the secondary side.