# Patent

## Title
Transconductance amplifier

## Abstract

The present invention is intended to achieve a transconductance amplifier and a voltage/current converting method which can provide a sufficient amplitude and a high degree of design freedom. The method comprises the steps of converting a first voltage signal to a first current signal; converting a second voltage signal to a second current signal; obtaining the common-mode components of the first and second current signals; and subtracting the common-mode components from the first and second current signals to obtain third and fourth signals, and further, subtracting the fourth current signal from the third current signal to generate a first output, while subtracting the third current signal from the fourth current signal to generate a second output.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a divisional of U.S. patent application Ser. No. 12/950,462, filed on Nov. 19, 2010, which is a divisional of U.S. patent application Ser. No. 11/994,792, filed on Jan. 4, 2008, which is a national stage of International Application No. PCT/JP2006/312495, filed on Jun. 22, 2006, which claims priority from Japanese Patent Application Nos. 2005-196107 and 2005-196108, both filed on Jul. 5, 2005, the contents of all of which are incorporated herein by reference in their entirety.


TECHNICAL FIELD
The present invention relates to a transconductance amplifier and a voltage-to-current converting method which are effective in RF low-pass filter circuits.
BACKGROUND ART
In recent years, RF systems have been used as means for communicating information between devices in portable electronic devices, electric home appliances, peripheral devices for personal computers, and the like. Wireless systems used in these electronic devices are fabricated in semiconductor integrated circuits to reduce size and weight and to lower price. Generally, an RF system requires a filter which has an abrupt cut-off frequency in order to separate a particular frequency component. However, since elements used in semiconductor integrated circuits suffer from substantial variability in manufacturing, it has been difficult to accomplish a filter circuit which has an abrupt cut-off frequency. Accordingly, a Gm-C filter composed of a transconductance amplifier [hereinafter called “OTA” (Operational Transconductance Amplifier) and a capacitance has been used.]
FIG. 1 is a diagram showing the basic configuration of a transconductance amplifier (hereinafter called “OTA” (Operational Transconductance Amplifier).
As illustrated, the OTA is an element for generating currents GmVin/2, −GmVin/2 which are proportional to input voltage Vin, and ideally has infinite input impedance and output impedance.
In this event, proportion coefficient Gm is a parameter called mutual conductance, and an OTA applied to a filter and the like is configured to have the ability to control the mutual conductance with a signal from the outside.
FIG. 2 is a circuit diagram showing a specific configuration of an OTA which is controlled mutual conductance Gm, for example, a degenerated differential OTA presented in Bran Nauta, “Analog CMOS Filters for Very High Frequencies”, Kluwer Academic Publishers, 1993, pp. 87-88.
Current sources 404, 405, 406, 407 each apply the same current value. Also, a resistive component of variable resistive element 403 connected to sources of input transistors 401, 402 varies in resistance in response to mutual conductance control signal 408 applied from the outside.
When input transistors 401, 402 have large transconductance, a current of ΔV/R/2 appears at the output, where R represents a resistive component of variable resistive element 403. Here, ΔV represents a voltage of a differential component of a voltage signal applied to the input. Therefore, arbitrary mutual conductance Gm can be accomplished by controlling the resistance of variable resistive element 403 with control signal 408. This configuration of an input stage is generally called a total differential input stage.
With the miniaturization of processes in recent years, lower voltages have been required for power supplies. In particular, when a source voltage is equal to or lower than one volt, limitations are imposed on the number of vertically stacked stages of transistors which can be used between the power supply and GND, thus making it impossible to use conventional circuit configurations. In the circuit configuration shown in FIG. 2, at least one or more transistors are required in the current source, three stages of transistors are used between the power supply and GND when they are vertically stacked. A transistor generally requires a drain-source voltage of approximately 200 mV when it operates in a saturation region, so that when transistors are vertically stacked in three stages, 600 mV is required irrespective of the magnitude of the signal. Accordingly, when the source voltage is one volt, only 400 mV is available for a signal amplitude, giving rise to a problem of the inability to provide a sufficient amplitude.
FIG. 3 includes diagrams showing the configuration of a pseudo-differential input type OTA disclosed in Ahmed Nader Mohieldin, “Nonlinear Effects in Pseudo Differential OTAs with CMFB”, IEEE Transactions on Circuits and Systems, Vol. 50, No. 10, October 2003, pp. 762-769, where FIG. 3a is a circuit diagram, and FIG. 3b is an equivalent circuit diagram of an output stage.
In FIG. 3a, sources of p-moss transistors M2A, M2B,M02A, M02B are commonly connected to a power supply, while source of n-moss transistors M1A, M1B, M01A, M01B are commonly grounded. Each drain of p-mos transistor M2A, M2B,M02A, M02B is connected to each drain of n-moss transistors M1A, M1B, M01A, M01B, while gates of p-moss transistors M2A, M02A are connected to a drain of p-moss transistor M02A, and gates of p-mos transistors M2B, M02B are connected to a drain of p-mos transistor M02B, to form a current mirror circuit. Each gate of n-moss transistor M1A, M01A is connected in common, and each gate of n-mos transistors M1B, M01B is connected in common to define an input part of gate signals Va, Vb. Output current Iout1 is generated from the drains of transistors M1A, M2A, while output current Iout2 is generated from the drains of transistors M1B, M2B.
In the circuit configured as described above, transistors M1A, M1B are input transistors, transistors M01A, M01B convert common-mode components of a signal from a voltage to a current, and a current proportional to the common-mode components is supplied to transistors M1A, M1B by the current mirror circuit composed of transistors M02A, M02B and transistors M2A, M2B.
A current flowing through a current source has a current value one half of a current value proportional to the common-mode components of the signal generated by transistors M01A, M01B.
Generally, drain current ID of a MOSFET is represented by:

ID=1⁄2μCax[W/L](VGS−VT)2 

When the drain current of a transistor applied with a gate-source voltage Va is I1, and the drain current of a transistor applied with a gate-source voltage Va is I2, where the size (W/L) of each transistor is the same, I1, I2 can be represented in the following manner through simplification of the above equation:

I1=k(Va−VT)2 

I2=k(Vb−VT)2 

Here, when Vc=Va+Vb,

I1−I2=k(Vc−2VT)(Va−Vb),

and difference ΔI of the current is represented by:

ΔI=Gm(Va−Vb)

As shown in this equation, difference ΔI of currents which flow through the two types of transistors has a value proportional to the difference between gate signals Va, Vb applied to their gates, thus permitting the transistors to act as an OTA.
The example shown in FIG. 3 will be described. Assuming that transistors M1A, M1B, M01A, M01B are equal in size to one another, and M2A, M2B,M02A, M02B are equal in size to one another, drain current I1 flows into transistors M1A, M01A applied with signal Va between the gate and source, while drain current I2 flows into transistors M1B, M01B applied with signal Vb between the gate and source, respectively. Since drain currents I1, I2 of M01A, M01B are mirrored by the current mirror circuit composed of M2A, M02A and M2B, M02B, a current of (I1+I2)/2 flows into the drains of transistors M2A and M2B, respectively. Here, since the drain currents of transistors M1A and M1B are I1, I2, respectively, currents of (I1−I2)/2, (I2−I1)/2 are output from the output stage of FIG. 3b. Thus, since the difference between Ii and I2 is output in proportion to the difference between gate signals Va, Vb, they act as an OTA. In this regard, in the exemplary OTA shown in FIG. 3, when the mutual conductance is changed from the outside, it can be controlled by controlling an common-mode bias voltage of an input signal.
FIG. 4 is a diagram showing a pseudo differential input type OTA shown in FIG. 3 in a functional block form. In FIG. 4, first voltage/current converting element 1701 and third voltage/current converting element 1703 correspond to transistors M1A, M1B, while second voltage/current converting element 1702 and fourth voltage/current converting element 1704, which form part of common-mode current generating part 1705, correspond to transistors M01A, M01. Current mirror circuit 1706, which corresponds to transistors M02A, M02B and transistors M2A, M2B, is a circuit for inverting the polarity of an input current to output a current which is proportional to the input current.
As described above, the output impedance of the OTA is ideally infinite. As such, in the circuits shown in FIGS. 1 to 3, an output DC bias overshoots to the power supply side or to the ground side, being incapable of acquiring a signal. Accordingly, a CMFB (Common Mode Feed Back) circuit is known for setting an output DC bias (see Non-Patent Document 2).
FIG. 5 includes diagrams showing the configuration of a CMFB circuit, where FIG. 5a is a block diagram conceptually showing the configuration of the CMFB circuit, FIG. 5b is a circuit diagram showing a specific configuration, and FIG. 5c is a block diagram showing an exemplary application of the CMFB circuit.
First, the operation of the CMFB circuit will be described with reference to FIG. 5a. Common-mode bias detecting circuit 703, which forms part of CMFB circuit 702, is applied with outputs VOUT+, VOUT− of OTA 701, and feeds an common-mode bias component of them back to OTA 701 as output bias control signal 704. In addition to output bias control signal 704, OTA 701 is applied with reference signal 705 as a control signal, such that OTA 701 compares output bias control signal 704 with reference signal 705 to control its output such that output bias control signal 704 provides a predetermined constant bias.
In this regard, while the CMFB circuit can refer to an common-mode bias detecting circuit provided externally to the OTA, as shown in FIG. 5a, the CMFB circuit includes circuits within the OTA for receiving the output bias control signal and reference signal for performing the comparison and feedback, in addition to the common-mode bias detecting circuit.
As shown in FIG. 5b, this conventional example comprises n-mos transistors M3A′, M3A, M03A, M2A, M3B′, M3B, M03B, M2B and p-mos transistors M04A′, M4A, M04A, M1A, M04B′, M4B, M04B, M1B.
Respective p-mos transistors M1A, M1B, M04A, M04B, M4A, M4B correspond to n-mos transistor M2A, M2B, M03A, M03B, M3A, M3B, and these corresponding transistors have a common drain, and are provided between the power supply and ground to form an OTA. P-mos transistors M1A, M1B and n-mos transistors M2A, M2B make up an input differential pair, and VIN+, VIN− are supplied to the gates of p-mos transistors M1A, M1B. Transistors M1A, M2A have their drains connected to the gates of transistors M2A, M03A, M3A, while transistors M1B, M2B have their drains connected to the gates of transistors M2B, M03B, M3B.
Each gate of p-mos transistors M1A, M1B, M04A, M04B, M4A, M4B is made common, serve as node VX (preceding stage), and is connected to the drains of transistors M04A, M04B. Transistors M3A, M3B, M4A, M4B make up an output stage of the OTA, where the drains of transistors M3A, M3B are used for an output node of VOUT+, while the drains of transistors M4A, M4B are used for an output node of VOUT−.
Transistors M3A′, M3B′, M4A′, M4B′ form part of the CMFB circuit, where transistor M3A′ which is supplied with reference signal VY at a gate has a source grounded, and has a drain connected to the drains of transistors M3A, M4A. Transistor M3B′ which is applied with reference signal VY at a gate has a source grounded, and has a drain connected to the drains of transistors M3B, M4B. Transistor M4A′, the gate of which serves as node VX (next stage), has a source connected to a power supply, and a drain connected to drains of transistors M3A, M4A. Transistor M4B′, whose gate serves as node VX (next stage), has a source connected to the power supply, and a drain connected to drains of transistors M3B, M4B.
In FIG. 5b, a circuit made up of transistors M1A, M1B, M2A, M2B is a circuit at an input stage for generating Va, Vb at the gates of transistors M2A, M2B, and is a circuit corresponding to a circuit for generating Va, Vb in the circuit diagram shown in FIG. 3a. Other parts corresponding to the circuit diagram of FIG. 3a are as follows.
Transistors M03A, M03B, M04A, M04B in FIG. 5b correspond to transistors M01, M02 in FIG. 3a, and transistors M3A, M3B, M4A, M4B correspond to transistors M1, M2 in FIG. 3a. Also, among the transistors shown in FIG. 5b, transistors M3A′, M3B′, M4A′, M4B′ which have no corresponding transistors in FIG. 3a form part of the CMFB circuit.
Next, the operation of the circuit shown in FIG. 5b will be described.
The operation of the OTA part in this conventional example is similar to the operation described with reference to FIG. 3a. As VIN+, VIN− are applied to input transistor pair M1A, M1B, Va, Vb are generated at the gates of transistors M03A, M03B, and are converted from voltage to current to remove a differential component at node VX (preceding stage). When OTAs are connected in series at two or more stages, for example, OTA1 and OTA2 are connected in series at two stages as shown in FIG. 5c, VX (preceding stage) of OTA2 is connected to node VX (next stage) of OTA1 which is provided at the preceding stage. In this conventional example, an common-mode bias component of the output signal of OTA1 appears at node VX (preceding stage) of OTA2. By returning this common-mode bias component to node VX (next stage) of OTA1, a negative feedback is applied to an output common-mode bias of OTA1. Also, in this event, by supplying reference signal VY to the gates of transistors M3A′, M3B′, the common-mode biases of outputs VOUT+, VOUT− are set at predetermined biases.

    Non-Patent Document 1: Bran Nauta, “Analog CMOS Filters for Very High Frequencies”, Kluwer Academic Publishers, 1993, pp. 87-88
    Non-Patent Document 2: Ahmed Nader Mohieldin, “Nonlinear Effects in Pseudo Differential OTAs with CMFB”, IEEE Transactions on Circuits and Systems, Vol. 50, No. 10, October 2003, pp. 762-769


DISCLOSURE OF THE INVENTION
Problems to be Solved by the Invention
In the related art shown in FIG. 2, even if the common-mode bias component of an input signal changes, the common-mode component of a current flowing through a transistor is constant with the aid of a current source connected to the source of the input transistor, but there is a problem that a sufficient amplitude cannot be provided because a high source voltage is required.
In the related art shown in FIG. 3, the operation can be performed at a low source voltage, but since there is no current source at the source of a transistor which is at the input stage, the common-mode component of a current flowing through the transistor changes depending on the common-mode component of the input signal. For this reason, there is a problem that its changing amount appears at the output of the OTA as an common-mode signal. When the common-mode component of the signal appears at the output, fluctuations in the operating point of the signal can cause a reduced signal dynamic range, an error in a differential signal, and even oscillations in the worst case, so that it is deemed as desirable that the gain be at least one tenth or less. While a general OTA-based circuit is designed to remove common-mode components of signals as much as possible, in the related art shown in FIG. 3, it is, however, difficult to sufficiently remove the common-mode component.
In the OTA which is provided with a CMFB circuit for setting a DC bias of the output, shown in FIG. 5, the drains of transistors M3A, M3B, M4A, M4B, which serve as the output node of the OTA, are provided with transistors M4A′, M4B′ which supply a signal indicative of an common-mode bias component from the OTA provided at the next stage when connected in series, and are provided with transistors M3A′, M3B′ which supply a reference signal. Thus, four transistors are connected to the output node, resulting in a parallel connection of the output conductance and parasitic capacitance of each transistor. This leads to a problem that the output impedance of the OTA is reduced such that it degrades the characteristics as the OTA.
The present invention has been made in view of the problems inherent to the related art as described above, and has an object to accomplish a transconductance amplifier and a voltage-to-current converting method which are capable of reducing the common-mode component of a signal appearing at an output to provide a sufficient amplitude.
Also, the present invention has been made in view of the problems inherent to the related art as described above, and has an object to accomplish an OTA which comprises a CMFB circuit and is prevented from degrading the characteristics as an OTA.
Means for Solving the Problems
A voltage-to-current converting method of the present invention is a voltage-to-current converting method for generating a first current and a second current proportional to the difference between an input first voltage signal and second voltage signal, characterized by comprising the steps of:
converting the first voltage signal to a first current signal;
converting the second voltage signal to a second current signal;
generating an common-mode component of the first current signal and the second current signal;
generating a third current signal and a fourth current signal by subtracting the common-mode component from the first current signal and the second current signal, respectively, generating a first output by subtracting the fourth current signal from the third current signal, and generating a second output by subtracting the third current signal from the fourth current signal.
A transconductance amplifier of the present invention is characterized by comprising:
a first and a second voltage/current converting element for converting a first voltage signal to a current signal;
a third and a fourth voltage/current converting element for converting a second voltage signal to a current signal;
an common-mode current generating part for converting each of the first voltage signal and the second voltage signal to a current signal, and further generating an common-mode current in accordance with an common-mode component of each current signal;
a first current circuit for subtracting the common-mode component by the common-mode component generating part from each current signal converted by each of the first to fourth voltage/current converting elements;
a second current circuit for supplying the difference between a current signal by the first voltage/current converting element from which the common-mode component is subtracted by the first current circuit and a current signal by the third voltage/current converting element as a first current output; and
a third current circuit for supplying the difference between a current signal by the fourth voltage/current converting element from which the common-mode component is subtracted by the first current circuit and a current signal by the second voltage/current converting element as a second current output.
In this event, the common-mode current generating part may comprise a fifth voltage/current converting element and a sixth voltage/current converting element for converting the first voltage signal and the second voltage signal to current signals, respectively.
Further, the first to sixth voltage/current converting elements may comprise a first to a sixth first conductivity type transistor supplied with the first voltage signal or the second voltage signal at bases or gates,
the first current circuit may comprise a plurality of second conductivity type transistors, the plurality of second conductivity type transistors may have their gates in common, and at least one of the plurality of second conductivity type transistors may have a gate short-circuited to a drain, and
an output of the second conductivity type transistor may be connected to any of the outputs of the first to sixth voltage/current converting elements.
Also, the first current circuit may comprise a first to a sixth second conductivity type transistor provided between a power supply and a ground together with the first to sixth voltage/current converting elements,
the second conductivity type transistors may have their gates and sources in common, and at least one of the second conductivity type transistors has a gate short-circuited to a drain, and
outputs of the second conductivity type transistor may be connected to outputs of the first to sixth voltage/current converting elements, respectively.
Also, the fifth first conductivity type transistor and the sixth first conductivity type transistor may be first transistors which have the same size with each other,
the first to fourth first conductivity type transistors may be second transistors which have the same size with one another,
the fifth second conductivity type transistor and the sixth second conductivity type transistor may be third transistors which have the same size with each other,
the first to fourth second conductivity type transistors may be fourth transistors which have the same size with one another, and
the ratio of the size of the first transistor to the size of the second transistor may be equal to the ratio of the size of the third transistor to the size of the fourth transistor.
Also, the first first conductivity type transistor may form part of a first current output supplying part, and the fourth first conductivity type transistor forms part of a second current output supplying part,
the second current circuit may comprise a seventh first conductivity type transistor having an output in common with an output of the first first conductivity type transistor, and an eighth first conductivity type transistor having an output and a gate in common with an output of the third first conductivity type transistor and a gate of the seventh first conductivity type transistor,
the third current circuit may comprise a ninth first conductivity type transistor having an output in common with an output of the second first conductivity type transistor, and a tenth first conductivity type transistor having an output and a gate in common with an output of the fourth first conductivity type transistor and a gate of the ninth first conductivity type transistor,
the second, third, fifth, and sixth first conductivity type transistors may be first transistors which have the same size with one another,
the first first conductivity type transistor and the fourth first conductivity type transistor may be second transistors which have the same size with each other,
the eighth first conductivity type transistor and the tenth first conductivity type transistor may be third transistors which have the same size with each other,
the seventh first conductivity type transistor and the ninth first conductivity type transistor may be fourth transistors which have the same size with each other,
the fifth second conductivity type transistor, the sixth second conductivity type transistor, the second second conductivity type transistor, and the third second conductivity type transistor may be fifth transistors which have the same size with one another,
the first second conductivity type transistor and the fourth second conductivity type transistor may be sixth transistors which match in size with each other, and
the ratio of the size of the first transistor to the size of the second transistor, the ratio of the size of the third transistor to the size of the fourth transistor, and the ratio of the size of the fifth transistor to the size of the sixth transistor may be equal.
Also, a transconductance amplifier may comprise a plurality of transconductance amplifiers described in any of the foregoing,
a fourth current circuit provided in one transconductance amplifier for generating a difference between a first current output and a second current output in the one transconductance amplifier as a first current output; and
a fifth current circuit provided in another transconductance amplifier for generating a difference between a second current output and a first current output in the other transconductance amplifier as a second current output.
Further, the common-mode current generating part may comprise a seventh voltage/current converting element supplied with a third voltage signal at a base or a gate, and generate an common-mode current including a bias current in accordance with the third voltage signal as the common-mode current.
Also, the transconductance amplifier may comprise a first bias current generating element for generating a first bias current added to a reference current supplied by the first current circuit to the second current circuit; and
a second bias current generating element for generating a second bias current added to a reference current supplied by the first current circuit to the third current circuit.
A filter circuit of the present invention is a first-order filter circuit configured using the transconductance amplifiers described above, wherein:
the filter circuit comprises the transconductance amplifier and a capacitance, and is made up of a first and a second transconductance amplifier, the first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of the second transconductance amplifier, respectively, and grounded through capacitances, the second transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and an input terminal of the second transconductance amplifier.
A filter circuit according to another aspect of the present invention is a fourth-order filter circuit configured using the transconductance amplifiers described above, wherein:
the filter circuit comprises a first to a fourth transconductance amplifier, the first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of the second transconductance amplifier and grounded through capacitances, the second transconductance amplifier having an output terminal and an inverting output terminal connected to the input terminal and an inverting input terminal of the second transconductance amplifier and grounded through capacitances, the third transconductance amplifier having an output terminal and an inverting output terminal connected to an inverting input terminal and an input terminal of the third transconductance amplifier, the fourth transconductance amplifier having an input terminal and an inverting input terminal connected to the output terminal and inverting output terminal of the second transconductance amplifier, the fourth transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of the second transconductance amplifier.
A filter circuit according to a further aspect of the present invention comprises one first-order filter circuit described above connected in series with two fourth-order filter circuits described above.
A voltage generating circuit according to the present invention is a voltage generating circuit configured using the transconductance amplifier described above, characterized in that:
the transconductance amplifier has an output terminal and an inverting output terminal connected to an inverting input terminal and an input terminal, and
the voltage generating circuit comprises a capacitance for alternatingly grounding one output part of the transconductance amplifier.
A voltage generating circuit according to another aspect of the present invention is a voltage generating circuit configured using the transconductance amplifier described above, characterized in that:
the voltage generating circuit comprises a first and a second transconductance amplifier and a capacitance, the first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of the second transconductance amplifier and connected to an inverting input terminal and an input terminal of the first transconductance amplifier, the input terminal and inverting input terminal of the first transconductance amplifier connected to an input through capacitances, respectively, an output terminal and an inverting output terminal of the second transconductance amplifier respectively serving as outputs.
A current controlled oscillator of the present invention is a current controlled oscillator configured using the voltage generating circuit described above, which comprises:
a plurality of resistors provided in series between a power supply and a ground;
a switch group provided between the plurality of resistors and an input of the voltage generating circuit for selectively applying a voltage divided by the plurality of resistors to the voltage generating circuit;
a first and a second comparator for comparing terminal voltages of the plurality of resistors provided in series with an output of the voltage generating circuit; and
a flip-flop whose state changes in accordance with outputs of the first and second comparators and which generates an output which defines an oscillation frequency and is used as a switching control signal for the switch group.
A PLL circuit of the present invention is a PLL circuit configured using the current controlled oscillator described above, which comprises:
a current controlled oscillator, whose oscillation frequency is controlled by a current control signal;
a phase detector for receiving a reference frequency signal and an output of the current controlled oscillator to generate a signal in accordance with a phase difference therebetween; and
a voltage/current converter for converting an output of the phase detector to a current, and supplying the same to the control signal input terminal of the current controlled oscillator.
In the present invention configured as described above, the common-mode current generating circuit generates a current of an common-mode component alone. This current of the common-mode component is distributed by the first current mirror circuit, and is subtracted from the output of each voltage/current converting element, thereby leaving only the current of a differential component at each output. In this event, while the error component of an amount depending on the common-mode component generated by the first current mirror circuit is added to each output, these error components are removed by the second current mirror circuit and third current mirror circuit.
A transconductance amplifier according to another aspect of the present invention is a transconductance amplifier for generating a first output voltage signal and a second output voltage signal proportional to the difference between a first input voltage signal and a second input voltage signal applied thereto from a first and a second output stage, respectively. The transconductance amplifier is characterized by comprising:
a feedback signal output terminal for outputting common-mode components of the first output voltage signal and second output voltage signal;
a feedback signal input terminal; and
a reference signal input terminal,
provided in the first and second output stages, respectively; and
feedback signal conveying means for controlling the first output voltage signal or second output voltage signal in accordance with an input signal to the feedback signal input terminal and an input signal to the reference signal input terminal,
wherein the feedback signal conveying means is connected to each output stage.
In this event, the feedback signal conveying means may comprise:
a current mirror circuit having an output part connected to the output stage;
a first transistor of a first conductivity type having a control terminal connected to the feedback signal input terminal; and
a second transistor of a second conductivity type having a control terminal connected to the reference signal input terminal for determining a reference current for the current mirror circuit together with the first transistor.
A transconductance amplifier according to a second aspect of the present invention is a transconductance amplifier for generating a first output voltage signal and a second output voltage signal proportional to the difference between a first input voltage signal and a second input voltage signal applied thereto from a first and a second output stage, respectively. The transconductance amplifier is characterized by comprising:
a feedback signal output terminal for outputting common-mode components of the first output voltage signal and second output voltage signal;
a reference signal input terminal for receiving a reference signal for bringing each of the first and second output stages into a predetermined bias state;
a feedback signal input terminal; and
feedback signal communicating means for controlling the first output voltage signal or the second output voltage signal in accordance with an input signal to the feedback signal input terminal and an input signal to the reference signal input terminal,
provided in the first and second output stages, respectively; and
feedback signal conveying means for controlling the first output voltage signal or second output voltage signal in accordance with an input signal to the feedback signal input terminal and an input signal to the reference signal input terminal,
wherein the feedback signal conveying means is connected to each output stage.
In this event, the feedback signal conveying means may comprise:
a current mirror circuit having an output part connected to the output stage;
a first transistor of a first conductivity type having a control terminal connected to the feedback signal input terminal; and
a second transistor of a second conductivity type for receiving the first input voltage signal or the first input voltage signal at a control terminal to determine a reference current for the current mirror circuit together with the first transistor.
Also, the feedback signal conveying means may be a transistor which has a control terminal connected to the feedback signal input terminal and an output part connected to the output stage.
A filter circuit of the present invention is a first-order filter circuit configured using the transconductance amplifier described above, wherein:
the filter circuit comprises the transconductance amplifier and a capacitance, and is made up of a first and a second transconductance amplifier, the first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of the second transconductance amplifier, respectively, and grounded through capacitances, the second transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of the second transconductance amplifier.
A filter circuit according to another aspect of the present invention is a fourth-order filter circuit configured using the transconductance amplifiers described above, wherein:
the filter circuit comprises a first to a fourth transconductance amplifier, the first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of the second transconductance amplifier and grounded through capacitances, the second transconductance amplifier having an output terminal and an inverting output terminal connected to the input terminal and inverting input terminal of the second transconductance amplifier and grounded through capacitances, the third transconductance amplifier having an output terminal and an inverting output terminal connected to an inverting input terminal and an input terminal of the third transconductance amplifier, the fourth transconductance amplifier having an input terminal and an inverting input terminal connected to the output terminal and inverting output terminal of the second transconductance amplifier, the fourth transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of the second transconductance amplifier.
A filter circuit according to a further aspect of the present invention comprises one first-order filter circuit described above connected in series with two fourth-order filter circuits described above.
A voltage generating circuit of the present invention is a voltage generating circuit configured using the transconductance amplifier described in any of the foregoing, characterized in that:
a feedback signal input terminal is used as a control signal input terminal for generating a bias current to change mutual conductance, and
the voltage generating circuit comprises a capacitance for alternatingly grounding an output current.
A current controlled oscillator of the present invention is a current controlled oscillator configured using the voltage generating circuit described above, comprising:
a plurality of resistors provided in series between a power supply and a ground;
a switch group provided between the plurality of resistors and an input of the voltage generating circuit for selectively applying a voltage divided by the plurality of resistors to the voltage generating circuit;
a first and a second comparator for comparing terminal voltages of the plurality of resistors provided in series with an output of the voltage generating circuit; and
a flip-flop whose state changes in accordance with outputs of the first and second comparators and which generates an output which defines an oscillation frequency and is used as a switching control signal for the switch group.
A PLL circuit of the present invention is a PLL circuit configured using the current controlled oscillator described above, comprising:
a current controlled oscillator, whose oscillation frequency is controlled by a current control signal;
a phase detector for receiving a reference frequency signal and an output of the current controlled oscillator to generate a signal in accordance with a phase difference therebetween; and
a voltage/current converter for converting an output of the phase detector to a current, and supplying the same to the control signal input terminal of the current controlled oscillator.
Effects of the Invention
In the present invention, since the gain of the common-mode component is reduced in the output, it is possible to effectively provide a sufficient amplitude and to increase the degree of freedom of design.
Also, in the present invention configured as described above, the output stage is connected only to the feedback signal conveying means, more specifically, to the output part of the current mirror circuit or transistor, so that only one transistor is connected other than the transistor which forms part of the output stage of the transconductance amplifier. Accordingly, a smaller number of transistors is connected than before, making it possible to accomplish an OTA which comprises a CMFB circuit that restrains degradations in characteristics.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
A diagram showing the basic configuration of a transconductance amplifier.
FIG. 2
A circuit diagram showing a specific configuration of a degenerated differential OTA which is an OTA, whose mutual conductance Gm of which is controlled.
FIG. 3a 
A circuit diagram showing the configuration of a pseudo differential input type OTA.
FIG. 3b 
An equivalent circuit diagram showing the configuration of an output stage of the pseudo differential input type OTA.
FIG. 4
A diagram showing the pseudo differential input type OTA shown in FIG. 3 in a functional block form.
FIG. 5a 
A block diagram conceptually showing the configuration of a CMFB circuit.
FIG. 5b 
A circuit diagram showing a specific configuration of a CMFB circuit.
FIG. 5c 
A block diagram showing an exemplary application of a CMFB circuit.
FIG. 6
An equivalent circuit diagram showing the configuration of a first embodiment according to the present invention.
FIG. 7
A circuit diagram showing the configuration of the first embodiment according to the present invention.
FIG. 8
A diagram for describing effects of the first embodiment according to the present invention.
FIG. 9
A diagram for describing effects of the first embodiment according to the present invention.
FIG. 10
A diagram for describing effects of the first embodiment according to the present invention.
FIG. 11
A diagram for describing effects of the first embodiment according to the present invention.
FIG. 12
A diagram for describing effects of the first embodiment according to the present invention.
FIG. 13
A diagram for describing effects of the first embodiment according to the present invention.
FIG. 14
A diagram for describing effects of the first embodiment according to the present invention.
FIG. 15
A diagram for describing effects of the first embodiment according to the present invention.
FIG. 16
A diagram for describing effects of the first embodiment according to the present invention.
FIG. 17
A circuit diagram showing a first exemplary modification to the first embodiment according to the present invention.
FIG. 18
A circuit diagram showing a second exemplary modification to the first embodiment according to the present invention.
FIG. 19
An equivalent circuit diagram showing the configuration of a second embodiment according to the present invention.
FIG. 20
A circuit diagram showing the configuration of the second embodiment according to the present invention.
FIG. 21
An equivalent circuit showing the configuration of a third embodiment according to the present invention.
FIG. 22
An equivalent circuit diagram showing the configuration of a fourth embodiment according to the present invention.
FIG. 23
A circuit diagram showing the configuration of the fourth embodiment according to the present invention.
FIG. 24
A circuit diagram showing the configuration of a fifth embodiment according to the present invention.
FIG. 25
A circuit diagram showing the configuration of a sixth embodiment according to the present invention.
FIG. 26
A circuit diagram showing the configuration of a seventh embodiment according to the present invention.
FIG. 27
A circuit diagram showing the configuration of an eighth embodiment according to the present invention.
FIG. 28
A circuit diagram showing the configuration of a ninth embodiment according to the present invention.
FIG. 29a 
A diagram showing a tenth embodiment according to the present invention.
FIG. 29b 
A circuit diagram showing the configuration of first-order filter 241 in FIG. 29a. 
FIG. 29c 
A circuit diagram showing the configuration of fourth-order filters 242, 243 in FIG. 29a. 
FIG. 30a 
A block diagram showing the circuit configuration of a PLL of an eleventh embodiment according to the present invention.
FIG. 30b 
A circuit diagram showing the configuration of current controlled oscillator 255 in FIG. 30a. 
FIG. 30c 
A circuit diagram specifically showing the configuration of a comparison voltage generating circuit 257 shown in FIG. 30b. 
FIG. 31
A circuit diagram showing the configuration of a twelfth embodiment of the present invention.
FIG. 32
A circuit diagram showing the configuration of a thirteenth embodiment of the present invention.
FIG. 33
A circuit diagram showing the configuration of a fourteenth embodiment of the present invention.
FIG. 34a 
A block diagram showing the configuration of a filter of a fifteenth embodiment according to the present invention.
FIG. 34b 
A circuit diagram showing the configuration of first-order filter 241 in FIG. 34a. 
FIG. 34c 
A circuit diagram showing the configuration of fourth-order filters 242, 243 in FIG. 34a. 
FIG. 35a 
A block diagram showing the circuit configuration of a pLL of a sixteenth embodiment according to the present invention.
FIG. 35b 
A circuit diagram showing the configuration of current controlled oscillator 255 in FIG. 35a. 



DESCRIPTION OF REFERENCE NUMERALS


    101 First Voltage/Current Converting Element
    102 Second Voltage/Current Converting Element
    103 Third Voltage/Current Converting Element
    104 Fourth Voltage/Current Converting Element
    105 Fifth Voltage/Current Converting Element
    106 Sixth Voltage/Current Converting Element
    107 In-Phase Current Generating Part
    108 First Current Mirror Circuit
    109 Second Current Mirror Circuit
    110 Third Current Mirror Circuit
    M03A, M3A, M5A, M6A, M7A, M03B, M3B, M5B, M6B, M7B n-mos Transistors
    M04A, M4A, M8A, M04, M4B, M8B p-mos Transistors


BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
First Embodiment
FIGS. 6 and 7 are diagrams showing the configuration of a first embodiment according to the present invention, where FIG. 6 is an equivalent circuit diagram, and FIG. 7 is a circuit diagram.
As shown in the equivalent circuit of FIG. 6, this embodiment comprises first to sixth voltage/current converting elements 101-106, common-mode current generating part 107, first to third current mirror circuits 108-110.
Replacing the configuration of FIG. 6 with a specific circuit shown in FIG. 7, first to sixth voltage/current converting elements 101-106 are made up of n-mos transistors M1F, M1C, M1B, M1E, M1D, M1A. The first current mirror circuit is made up of p-mos transistors M2A-M2F. The second current mirror circuit is made up of n-mos transistors M3C, M3D, while the third current mirror circuit is made up of n-mos transistors M3A, M3B. Also, common-mode current generating part 107 is made up of second voltage/current converting element 102 (M1C) and fifth voltage/current converting element 105 (M1D).
With regard to the size of the transistors, in the first embodiment, transistors M1A-M1F are identical in size to one another, but transistors M2A-M2F may differ in size from transistors M1A-M1F. Also, transistors M3A, M3B may differ in size. In this regard, the size of each of transistors M1A-M1F may be changed to a different size depending on a particular usage as in the exemplary modifications shown below.
Sources and gates of p-mos transistors M2A-M2F are made common, and the sources are connected to a power supply. Each drain of p-mos transistors M2A-M2F is connected to each drain of n-mos transistors M1F, M1C, M1A, M1B, M1E, M1A. Sources of n-mos transistors M1A-M1F, M3A-M3D are grounded. N-mos transistors M3C, M3D which form part of second current mirror circuit have their drains connected to the drains of p-mos transistors M2E, M2F, and have their gates connected commonly to the drain of n-mos transistor M3C. N-mos transistors M3A, M3B which form part of the third current mirror circuit have their drains connected to the drains of p-mos transistors M2A, M2B, and have their gates connected in common to the drain of n-mos transistor M3B. N-mos transistors M1C, M1D which form part of common-mode current generating part 107 have their respective gates connected to respective gates of n-mos transistors M1B, M1E, respectively, and have their drains connected commonly to each gate of p-mos transistors M2A-M2F.
In this regard, transistors have their drain, gate, and source connected, respectively, for example, p-mos transistors M2C and M2D can be separately provided as shown in FIG. 7, these transistors may be integrated into one by increasing the size twice. When p-mos transistors M2C and M2D are integrated into one, the first current mirror circuit is made up of five p-mos transistors.
In the circuit configured as described above, signal voltages Va and Vb are converted to currents by the first to sixth voltage/current converting elements. Common-mode current generating circuit 107 generates a current proportional to an common-mode component of an input signal. The first current mirror circuit inverts the characteristic of this current proportional to the common-mode component, and subtracts the same from outputs of the first, third, fourth, and sixth voltage/current converting elements. Among the subtracted signals, the polarity of one is inverted by the second and third current mirror circuits such that the one signal is subtracted from the other to generate outputs IOUT1, IOUT2.
In this embodiment, signals converted from voltage to current corresponding to signal voltages Va and Vb include a current of an common-mode component and a current of a differential component added thereto. In the common-mode current generating circuit, the outputs of the second and fifth voltage/current converting elements are short-circuited, so that the current of the differential component is removed, with the current of the common-mode component alone being output. This current of the common-mode component is distributed by the first current mirror circuit, and subtracted from outputs of the first, fourth, third, and sixth voltage/current converting elements, thereby causing each output to comprise the current of the differential component alone. However, generally, a circuit made up of transistors has transistors with limited output conductance, and thus the error component of an amount depending on the common-mode component is added to the output of the first current mirror circuit in this embodiment in addition to the current of the common-mode component. Consequently, the error component of the same amount is added to all of the outputs of the first, fourth, third, and sixth voltage/current converting elements. In this embodiment, the error components included in the outputs of the first and fourth voltage/current converting elements are removed by the second current mirror circuit, while the error components included in the outputs of the third and sixth voltage/current converting elements are removed by the third current mirror circuit. These outputs free from the error components are labeled output IOUT1, output IOUT2, respectively. Accordingly, in this embodiment, the error components attributable to the common-mode components can be reduced to provide sufficient amplitude.
The foregoing effect will be described by calculating the gain of the common-mode component.
First, a diode model is analyzed. FIG. 8 shows equivalent circuits of a n-mos transistor and a P-mos transistor, where the relationship of the current is represented by the following Equation (1):




  
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          1
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          
            
              
                -
                
                  g
                  o
                
              
              ⁢
              
                v
                x
              
            
            -
            
              
                g
                m
              
              ⁢
              
                v
                x
              
            
            +
            
              I
              x
            
          
          =
          0
        
        ⁢
        
          

        
        ⁢
        
          
            Z
            M
          
          =
          
            
              
                V
                x
              
              
                I
                x
              
            
            =
            
              1
              
                
                  g
                  m
                
                +
                
                  g
                  o
                
              
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




where gm, go are mutual conductance and output conductance of the transistor, respectively. In the following, the mutual conductance and output conductance of a transistor are labeled gm, go with a suffix added thereto, unless otherwise noted.

FIG. 9 is an equivalent circuit of a source-grounded circuit with a diode added thereto, where the relationship between input voltage vi and output voltage vo is represented by the following Equation (2):




  
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          2
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              ⁢
              
                v
                i
              
            
            +
            
              
                g
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              ⁢
              
                v
                o
              
            
            +
            
              
                (
                
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                  +
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                
                )
              
              ⁢
              
                v
                o
              
            
          
          =
          0
        
        ⁢
        
          

        
        ⁢
        
          
            
              v
              o
            
            
              v
              i
            
          
          =
          
            -
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              
                (
                
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  +
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                  +
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                
                )
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




FIG. 10 is a circuit diagram showing only a one-side portion of the circuit shown in FIG. 3, and FIG. 11 is an equivalent circuit diagram thereof.
In the circuit shown in FIG. 10, the relationship between input (common-mode input) Vi and output V01 is represented by Equation (3) shown below:




  
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          3
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          v
          
            o
            ⁢
            
              
            
            ⁢
            1
          
        
        =
        
          
            -
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                +
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
          
          ⁢
          
            v
            i
          
        
      
    
    
      
        (
        3
        )
      
    
  




where gm1 represents mutual conductance of M1A, M01A, and gm2 represents mutual conductance of M2A, M02A, respectively, while g01 represents output conductance of M1A, M01A, and g02 represents output conductance of M2A, M02A, respectively.

From the equivalent circuit shown in FIG. 11 and Equation (3), the equation is expanded to derive the gain:




  
    
      
        
          
        
        ⁢
        
          [
          
            Equation
            ⁢
            
              
            
            ⁢
            4
          
          ]
        
      
    
    
      
        
      
    
  
  
    
      
        
          
        
        ⁢
        
          
            
              
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  v
                  i
                
              
              +
              
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                ⁢
                
                  v
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
              
              +
              
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  v
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
              +
              
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                ⁢
                
                  v
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
            =
            0
          
          ⁢
          
            

          
          ⁢
          
            
          
          ⁢
          
            
              
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  v
                  i
                
              
              -
              
                
                  
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    ⁢
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    +
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                
                ⁢
                
                  v
                  i
                
              
              +
              
                
                  (
                  
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  )
                
                ⁢
                
                  v
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
            =
            0
          
          ⁢
          
            

          
          ⁢
          
            
          
          ⁢
          
            
              
                
                  v
                  i
                
                ⁡
                
                  (
                  
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    -
                    
                      
                        
                          g
                          
                            m
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                        
                        ⁢
                        
                          g
                          
                            m
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                        
                      
                      
                        
                          g
                          
                            o
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                        
                        +
                        
                          g
                          
                            o
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                        
                        +
                        
                          g
                          
                            m
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                        
                      
                    
                  
                  )
                
              
              +
              
                
                  (
                  
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  )
                
                ⁢
                
                  v
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
            =
            0
          
          ⁢
          
            

          
          ⁢
          
            
              
                
                  v
                  i
                
                ⁡
                
                  (
                  
                    
                      
                        
                          g
                          
                            o
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                        
                        ⁢
                        
                          g
                          
                            m
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                        
                      
                      +
                      
                        
                          g
                          
                            o
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                        
                        ⁢
                        
                          g
                          
                            m
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                        
                      
                      +
                      
                        
                          g
                          
                            m
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                        
                        ⁢
                        
                          g
                          
                            m
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                        
                      
                      -
                      
                        
                          g
                          
                            m
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                        
                        ⁢
                        
                          g
                          
                            m
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                        
                      
                    
                    
                      
                        g
                        
                          o
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      +
                      
                        g
                        
                          o
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                      +
                      
                        g
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                    
                  
                  )
                
              
              +
              
                
                  (
                  
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  )
                
                ⁢
                
                  v
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
            =
            0
          
          ⁢
          
            

          
          ⁢
          
            
          
          ⁢
          
            
              
                (
                
                  
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    +
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                
                )
              
              ⁢
              
                v
                i
              
              ⁢
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            =
            
              
                -
                
                  (
                  
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  )
                
              
              ⁢
              
                v
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
          
          ⁢
          
            

          
          ⁢
          
            
          
          ⁢
          
            
              
                v
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              
                v
                i
              
            
            =
            
              -
              
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                
                  (
                  
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    +
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




Here, mutual conductance gm of a transistor is generally larger than output conductance g0 by a factor of 10 to 100, so that when Equation (4) is simplified on the assumption that gm>>go is satisfied, the resulting equation is represented as follows:




  
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          5
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          
            v
            
              o
              ⁢
              
                
              
              ⁢
              2
            
          
          
            v
            i
          
        
        ≈
        
          -
          
            
              g
              
                m
                ⁢
                
                  
                
                ⁢
                1
              
            
            
              g
              
                m
                ⁢
                
                  
                
                ⁢
                2
              
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




From the foregoing, in the example shown in FIG. 3, when an equal value is selected for mutual conductance gm1, gm2 of transistors M1A, M01A, M2A, M02A, the common-mode gain of the output with respect to the input signal is approximately −1 time from Equation (5). Also, supposing that values are selected for mutual conductance gm1, gm2 of transistors M1A, M01A, M2A, MO02A such that Equation (2) derives − 1/10, mutual conductance gm is proportional to the size of the transistors, so that the shapes of p-ch transistors and n-ch transistors must be at 1:10. While the size of a transistor is determined in consideration of a reduction in source voltage, a noise margin, variations in performance of the transistor, and the like, the design becomes further difficult due to the ratio as mentioned above which is included in the condition.
Next, the OTA of this embodiment is analyzed. FIG. 12 is a circuit diagram showing only one-side portion of the circuit shown in FIG. 7. For purposes of analysis, transistors M2C, M3B are replaced with loads ZM2, ZM3, as shown in FIG. 13.
First, vo1 is derived. By considering the equivalent circuit shown in FIG. 14 in a manner similar to the derivation of Equation (2), the input/output relationship is represented as follows:




  
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          6
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          v
          
            o
            ⁢
            
              
            
          
        
        =
        
          
            -
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              
                (
                
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  +
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                  +
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                
                )
              
            
          
          ⁢
          
            v
            i
          
        
      
    
    
      
        (
        6
        )
      
    
  




Next, vo2 is derived. Taking into account the equivalent circuit shown in FIG. 15 in which ZM3, the input/output relationship is represented as follows:




  
    
      
        
          
        
        ⁢
        
          [
          
            Equation
            ⁢
            
              
                
              
              ⁢
              
                
              
            
            ⁢
            7
          
          ]
        
      
    
    
      
        
      
    
  
  
    
      
        
          0
          =
          
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              ⁢
              
                v
                i
              
            
            -
            
              
                
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  ⁢
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                
                
                  (
                  
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    +
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  )
                
              
              ⁢
              
                v
                i
              
            
            +
            
              
                (
                
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                  +
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                
                )
              
              ⁢
              
                v
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
            +
            
              
                g
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              ⁢
              
                v
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
            +
            
              
                g
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              ⁢
              
                v
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
          
        
        ⁢
        
          

        
        ⁢
        
          
        
        ⁢
        
          
            
              v
              i
            
            ⁡
            
              (
              
                
                  
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    ⁢
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  
                    (
                    
                      
                        g
                        
                          o
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      +
                      
                        g
                        
                          o
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                      +
                      
                        g
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                    
                    )
                  
                
                -
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
              
              )
            
          
          =
          
            
              (
              
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                +
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
                +
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
              )
            
            ⁢
            
              v
              
                o
                ⁢
                
                  
                
                ⁢
                2
              
            
          
        
        ⁢
        
          

        
        ⁢
        
          
        
        ⁢
        
          
            v
            
              o
              ⁢
              
                
              
              ⁢
              2
            
          
          =
          
            
              (
              
                
                  
                    
                      
                        g
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      ⁢
                      
                        g
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                    
                    
                      
                        g
                        
                          o
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      +
                      
                        g
                        
                          o
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                      +
                      
                        g
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                    
                  
                  -
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                
                
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  +
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                  +
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                  +
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                
              
              )
            
            ⁢
            
              v
              i
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




Next, vo3 is derived using vo1, vo2 which was calculated in the foregoing manner. The equivalent circuit is, as shown in FIG. 16, and the input/output relationship is represented as follows:



  
    
      
    
    ⁢
    
      [
      
        Equation
        ⁢
        
          
        
        ⁢
        8
      
      ]
    
  




  
    0
    =
    
      
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            1
          
        
        ⁢
        
          v
          i
        
      
      +
      
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            3
          
        
        ⁢
        
          v
          
            o
            ⁢
            
              
            
            ⁢
            2
          
        
      
      +
      
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            2
          
        
        ⁢
        
          v
          
            o
            ⁢
            
              
            
            ⁢
            1
          
        
      
      +
      
        
          g
          
            o
            ⁢
            
              
            
            ⁢
            1
          
        
        ⁢
        
          v
          
            o
            ⁢
            
              
            
            ⁢
            3
          
        
      
      +
      
        
          g
          
            o
            ⁢
            
              
            
            ⁢
            2
          
        
        ⁢
        
          v
          
            o
            ⁢
            
              
            
            ⁢
            3
          
        
      
      +
      
        
          g
          
            o
            ⁢
            
              
            
            ⁢
            3
          
        
        ⁢
        
          v
          
            o
            ⁢
            
              
            
            ⁢
            3
          
        
      
    
  




  
    0
    =
    
      
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            1
          
        
        ⁢
        
          v
          i
        
      
      +
      
        
          (
          
            
              
                
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  ⁢
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                
                
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  +
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                  +
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                
              
              -
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            
              
                g
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              +
              
                g
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              +
              
                g
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
              +
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
            
          
          )
        
        ⁢
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            3
          
        
        ⁢
        
          v
          i
        
      
      -
      
        
          (
          
            
              g
              
                m
                ⁢
                
                  
                
                ⁢
                1
              
            
            
              
                g
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              +
              
                g
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              +
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
            
          
          )
        
        ⁢
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            2
          
        
        ⁢
        
          v
          i
        
      
      +
      
        
          (
          
            
              g
              
                o
                ⁢
                
                  
                
                ⁢
                1
              
            
            +
            
              g
              
                o
                ⁢
                
                  
                
                ⁢
                2
              
            
            +
            
              g
              
                o
                ⁢
                
                  
                
                ⁢
                3
              
            
          
          )
        
        ⁢
        
          v
          
            o
            ⁢
            
              
            
            ⁢
            3
          
        
      
    
  




  
    0
    =
    
      
        
          (
          
            1
            +
            
              
                
                  
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    ⁢
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                  
                  
                    
                      g
                      01
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    +
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                
                -
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
              
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                +
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
                +
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
            
            -
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
                +
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
          
          )
        
        ⁢
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            1
          
        
        ⁢
        
          v
          i
        
      
      +
      
        
          (
          
            
              g
              
                o
                ⁢
                
                  
                
                ⁢
                1
              
            
            +
            
              g
              
                o
                ⁢
                
                  
                
                ⁢
                2
              
            
            +
            
              g
              
                o
                ⁢
                
                  
                
                ⁢
                3
              
            
          
          )
        
        ⁢
        
          v
          
            o
            ⁢
            
              
            
            ⁢
            3
          
        
      
    
  



When go1+go2=A,



  
    
      
    
    ⁢
    
      [
      
        Equation
        ⁢
        
          
        
        ⁢
        9
      
      ]
    
  




  
    0
    =
    
      
        
          (
          
            1
            +
            
              
                
                  
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    ⁢
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                  
                  
                    A
                    +
                    
                      g
                      m2
                    
                  
                
                -
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
              
                A
                +
                
                  g
                  
                    o
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
                +
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
            
            -
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              
                A
                +
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
          
          )
        
        ⁢
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            1
          
        
        ⁢
        
          v
          i
        
      
      +
      
        
          (
          
            A
            +
            
              g
              
                o
                ⁢
                
                  
                
                ⁢
                3
              
            
          
          )
        
        ⁢
        
          v
          
            o
            ⁢
            
              
            
            ⁢
            3
          
        
      
    
  




  
    0
    =
    
      
        
          (
          
            1
            +
            
              
                -
                
                  Ag
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
              
                
                  (
                  
                    A
                    +
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  )
                
                ⁢
                
                  (
                  
                    A
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                    +
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                  
                  )
                
              
            
            -
            
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              
                A
                +
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
          
          )
        
        ⁢
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            1
          
        
        ⁢
        
          v
          i
        
      
      +
      
        
          (
          
            A
            +
            
              g
              
                o
                ⁢
                
                  
                
                ⁢
                3
              
            
          
          )
        
        ⁢
        
          v
          
            o
            ⁢
            
              
            
            ⁢
            3
          
        
      
    
  




  
    0
    =
    
      
        
          (
          
            
              
                
                  
                    
                      A
                      2
                    
                    +
                    
                      Ag
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                    +
                    
                      Ag
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                    +
                    
                      Ag
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    +
                    
                      
                        g
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                      ⁢
                      
                        g
                        
                          o
                          ⁢
                          
                            
                          
                          ⁢
                          3
                        
                      
                    
                    +
                  
                
              
              
                
                  
                    
                      
                        g
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                      ⁢
                      
                        g
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          3
                        
                      
                    
                    -
                    
                      Ag
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                    -
                    
                      Ag
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    -
                    
                      
                        g
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                      ⁢
                      
                        g
                        
                          o
                          ⁢
                          
                            
                          
                          ⁢
                          3
                        
                      
                    
                    -
                    
                      
                        g
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                      ⁢
                      
                        g
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          3
                        
                      
                    
                  
                
              
            
            
              
                (
                
                  A
                  +
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                
                )
              
              ⁢
              
                (
                
                  A
                  +
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                  +
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                
                )
              
            
          
          )
        
        ⁢
        
          g
          
            m
            ⁢
            
              
            
            ⁢
            1
          
        
        ⁢
        
          v
          i
        
      
      +
      
        
          (
          
            A
            +
            
              g
              
                o
                ⁢
                
                  
                
                ⁢
                3
              
            
          
          )
        
        ⁢
        
          v
          
            o
            ⁢
            
              
            
            ⁢
            3
          
        
      
    
  




  
    
      
    
    ⁢
    
      0
      =
      
        
          
            (
            
              
                A
                ⁡
                
                  (
                  
                    A
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                  
                  )
                
              
              
                
                  (
                  
                    A
                    +
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  )
                
                ⁢
                
                  (
                  
                    A
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                    +
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                  
                  )
                
              
            
            )
          
          ⁢
          
            g
            
              m
              ⁢
              
                
              
              ⁢
              1
            
          
          ⁢
          
            v
            i
          
        
        +
        
          
            (
            
              A
              +
              
                g
                
                  o
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
            
            )
          
          ⁢
          
            v
            
              o
              ⁢
              
                
              
              ⁢
              3
            
          
        
      
    
  




  
    
      
    
    ⁢
    
      
        v
        
          o
          ⁢
          
            
          
          ⁢
          3
        
      
      =
      
        
          -
          
            
              Ag
              
                m
                ⁢
                
                  
                
                ⁢
                1
              
            
            
              
                (
                
                  A
                  +
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                
                )
              
              ⁢
              
                (
                
                  A
                  +
                  
                    g
                    
                      o
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                  +
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                
                )
              
            
          
        
        ⁢
        
          v
          i
        
      
    
  



A substitution of A results in the following equation:




  
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          10
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          v
          
            o
            ⁢
            
              
            
            ⁢
            3
          
        
        =
        
          
            -
            
              
                
                  (
                  
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  )
                
                ⁢
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
              
              
                
                  (
                  
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    +
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                  
                  )
                
                ⁢
                
                  (
                  
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    +
                    
                      g
                      
                        o
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                    +
                    
                      g
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                  
                  )
                
              
            
          
          ⁢
          
            v
            i
          
        
      
    
    
      
        (
        8
        )
      
    
  




When go1+go2<<gm2 and go1+go2+go3<<gm3,




  
    
      
        [
        
          Equation
          ⁢
          
            
          
          ⁢
          11
        
        ]
      
    
    
      
        
      
    
  
  
    
      
        
          v
          
            o
            ⁢
            
              
            
            ⁢
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where gm1, gm2, gm3 represent the mutual conductance of transistors M1A, M1B, M1C, M2A, M2B, M2C,M3A, M3B, and g01, g02, g03 represent the output conductance of M1A, M1B, M1C, M2A, M2B, M2C,M3A, M3B. Generally, the mutual conductance of transistors is larger than the output conductance by a factor of 10 to 100, Equation (9) can be simplified as Equation (10).

Here, for comparing the circuit of this embodiment with the related art described with reference to FIG. 3, gm1, gm2 of the transistors in FIG. 3 and the transistors in FIG. 7 are made the same, and the ratio of Equation (4) to Equation (8) is taken as follows:




  
    
      
        
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As is apparent from Equation (11), assuming that the mutual conductance gm of the transistors is larger than output conductance go by a factor of 10 to 100, it is understood that the gain of the common-mode component can be reduced to 1⁄5 to 1/50. Accordingly, when the circuit configuration of this embodiment is used, the design can be made without paying any concern to limiting the size of transistors due to the common-mode gain, resulting in the design with a higher degree of freedom.
While this embodiment has been described on the assumption that the transistors which form part of the circuit comprise p-mos transistors and n-mos transistors, the circuit may be made up of JFETs and bipolar transistors. Also, the p-mos transistors shown in FIG. 7 may be replaced with n-mos transistors, and the n-mos transistors may be replaced with p-mos transistors. This applies to other embodiments.
Exemplary Modification 1 to First Embodiment
FIG. 17 is a circuit diagram showing an exemplary modification to the first embodiment. FIG. 17 differs from the first embodiment in that the second voltage/current converting element and fifth voltage/current converting element, which form part of the common-mode current generating part, are smaller than the remaining voltage/current converting elements. Here, the size of transistors M1C and M1D (=W/L) is chosen to be a, while the size of transistors M1A, M1B, M1E, M1F is chosen to be 2a. While the size of transistors M3A, M3B, M3C, M3D can be determined irrespective of transistors M1C, M1D and transistors M1A, M1B, M1E, M1F, the size is herein chosen to be 2a.
Likewise, the size of transistors M2C, M2D which forms part of the first current mirror circuit is also chosen to be a, and the size of transistors M2A, M2B, M2E, M2F is 2a. In other words, the ratio of the size of transistors M1C and M1D which make up the common-mode current generating circuit to the size of transistors M1A, M1B, M1E, M1F, which are the remaining voltage/current converting elements, is set to 1:2, and within the first mirror circuit, the ratio of the size of transistors M2C, M2D connected to transistor M1C, M1D to the size of remaining transistors M2A, M2B, M2E, M2F is also set to 1:2 in a similar manner.
Such a configuration can reduce the current flowing through common-mode current generating part 107, making it possible to reduce the input impedance. Also, the power consumption can be reduced by reducing transistors not related to transistors which make up the output stage (M1A, M2A, M3A, M1F, M2F, M3D).
Also, in this embodiment, the ratio of the sizes (transistors M1C, M1D):(transistors M1A, M1B, M1E, M1F, M3A, M3B, M3C, M3D) is set to 1:2, but transistors of any size may be used as long as 1:n (n>1). Also, the size of M3A, M3B, M3C, M3D can be independently set.
Exemplary Modification 2 to First Embodiment
FIG. 18 is a circuit diagram showing an exemplary modification to the first embodiment. FIG. 18 differs from the first embodiment in that the size of transistors M1C, M1B, M1D, M1E is chosen to be a, while the size of transistors M1A, M1F is chosen to be 2a, so that they are at a ratio of 2:1; the size of transistors M3B, M3C is chosen to be b, while the size of transistors M3A, M3D is chosen to be 2b, so that they are at a ratio of 2:1; and the size of transistors M2B, M2D, M2B, M02E is chosen to be c, while the size of transistors M2A, M2F is chosen to be 2c, so that they are in a ratio of 1:2.
With such a configuration, part of transistors can be reduced in area, thus making it possible to produce an effect of reducing the overall circuit area, while having similar effects to those of the first embodiment. Also, in this embodiment, the ratio of the sizes is set to 2:1, but transistors of any size may be used as long as n:1 (n>1), in a manner similar to Exemplary Modification 1 to the first embodiment. Also, the sizes of the transistors can be changed in a similar manner.
Alternatively, a well separation type, which is effective in reducing noise, can be used for the n-mos transistors.
The foregoing contents related to the transistors are similar in each embodiment described below.
Second Embodiment
FIGS. 19 and 20 are diagrams showing the configuration of a second embodiment, where FIG. 19 is an equivalent circuit, and FIG. 20 is a circuit diagram.
This embodiment comprises seventh voltage/current converting element 401 in common-mode current generating part 107 in the first embodiment to provide common-mode current generating part 107′. In the circuit diagram specifically shown in FIG. 20, seventh voltage/current converting element 401 comprises source-grounded n-mos transistor M4. N-mos transistor M4 has a drain connected in common to each gate of p-mos transistors M2A-M2F, and a gate applied with bias voltage VC.
In the first embodiment, when an error component included in an output current of first current mirror circuit 108 is very small, the current flowing through transistors M2A-M2F is substantially the same as the current flowing through transistors M1A-M1F. In this state, no bias current flows into transistors M3A-M3D which make up second current mirror circuit 109 and third current mirror circuit 110, but instead the current flows into transistors M3A-M3D only in half waves of a signal, causing a loss in the signal.
In this embodiment, the seventh voltage/current converting element is provided at an input of first current mirror circuit 108 to supply the input of first current mirror circuit 108 with DC voltage VC not related to a signal, thus making it possible to cause the current flowing through transistors M2A-M2F to be larger than the current flowing through transistors M1A-M1F at all times. DC current VC, called herein, may be of any magnitude as long as it has a value from a grounding point to a source voltage. As a result, it is possible to solve a problem in which a bias current experiences difficulties in flowing into transistors M3A-M3D, which make up second current mirror circuit 109 and third current mirror circuit 110, and to process a differential signal over a full wave rather than half wave, making it less likely to produce a loss in the signal.
Third Embodiment
FIG. 21 is an equivalent circuit showing the configuration of a third embodiment according to the present invention.
In the configuration of this embodiment, in addition to the OTA made up of first to sixth voltage/current converting elements 101-106, common-mode current generating part 107, and first to third current mirror circuits 108-110 of the first embodiment shown in FIG. 6, an OTA having the same configuration as this is provided. Seventh to twelfth voltage/current converting elements 101′-106′, common-mode current generating part 107′, and fifth to seventh current mirror circuits 108′-110′, respectively, operate in a similar manner to first to sixth voltage/current converting elements 101-106, common-mode current generating part 107, and first to third current mirror circuits 108-110.
In this embodiment, fourth current mirror circuit 601 is provided between third current mirror circuit 110 of the OTA which generates IOUT1 and the output, and eighth current mirror 601′ is provided between sixth current mirror circuit 109′ of the OTA which generates IOUT2 and the output, to remove common-mode components by each current mirror circuit, thus further improving the common-mode gain reduction effect.
Fourth Embodiment
FIGS. 22 and 23 are diagrams showing the configuration of a fourth embodiment according to the present invention, where FIG. 22 is an equivalent circuit diagram, and FIG. 23 is a circuit diagram.
This embodiment comprises eighth voltage/current converting element 701 and ninth voltage/current converting element 702 added to the first embodiment. In the circuit diagram specifically shown in FIG. 23, eighth voltage/current converting element 701 and ninth voltage/current converting element 702 are shown as p-mos transistors M4B, M4A. P-mos transistor M4B has a source connected to a power supply, and a drain connected to gates of M3C, M3D which make up the second current mirror circuit, while p-mos transistor M4A has a source connected to the power supply, and a drain connected to gates of M3A, M3B which make up the third current mirror circuit. Gates of p-mos transistors M4B, M4A are applied with bias voltage VC.
As described above, in the first embodiment, when an error component included in an output current of first current mirror circuit 108 is very small, no bias current flows into transistors M3A-M3D which make up second current mirror circuit 109 and third current mirror circuit 110, but instead a current flows into transistors M3A-M3D only in half waves of a signal, causing a loss in the signal.
In this embodiment, eighth voltage/current converting element 701 and ninth voltage/current converting element 702 are provided at inputs of second current mirror circuit 109 and third current mirror circuit 110 to supply the inputs of second current mirror circuit 109 and third current mirror circuit 110 with DC voltage VC not related to a signal, thereby making it possible to address the problem in which no bias current flows into transistors M3A-M3D which make up second current mirror circuit 109 and third current mirror circuit 110, and to process a differential signal over a full wave rather than half wave, making it less likely to produce a loss in the signal.
Fifth Embodiment
FIG. 24 is a circuit diagram showing the configuration of a fifth embodiment according to the present invention.
In this embodiment, first current mirror circuit 108 made up of p-mos transistors M2A-M2F in the first embodiment shown in FIG. 7 is designed in a two-stage configuration with p-mos transistors M2A′-M2F′, identical in configuration to p-mos transistors M2A-M2F, provided between first current mirror circuit 108 and a power supply, for use as first current mirror circuit 108′.
Some transistors developed in recent years have low threshold voltages, and this embodiment employs such transistors as transistors which make up the first current mirror circuit. By arranging the transistors at two stages, the output impedance can be increased, though the proportion of the amplitude width occupying in a source voltage becomes lower, thus improving the amplification accuracy.
Sixth Embodiment
FIG. 25 is a circuit diagram showing the configuration of a sixth embodiment.
This embodiment is also based on the premise that it uses transistors which have low threshold voltages, as is the case with the fifth embodiment.
In this embodiment, second current mirror circuit 109 made up of n-mos transistors M3C, M3D and third current mirror circuit 110 made up of n-mos transistors M3A, M3B in the first embodiment shown in FIG. 7 are designed in a two-stage configuration with n-mos transistors M3C′, M3D′, identical in configuration to n-mos transistors M3C, M3D, and n-mos transistors M3A′, M3B′, identical in configuration to n-mos transistors M3A, M3B, provided between second and third current mirror circuit 108, 109 and a ground, for use as second current mirror circuit 109′, and third current mirror circuit 110′. Likewise, in this embodiment, the amplification accuracy is improved as is the case with the fifth embodiment.
Seventh Embodiment
FIG. 26 is a circuit diagram showing the configuration of a seventh embodiment according to the present invention.
This embodiment is a combination of the fifth embodiment shown in FIG. 24 with the sixth embodiment shown in FIG. 25, wherein first mirror circuit 108 shown in FIG. 7 is replaced with current mirror circuit 108′ shown in FIG. 24, and second mirror circuit 109 and third current mirror circuit 110 shown in FIG. 7 are replaced with second current mirror circuit 109′ and third current mirror circuit 110′ shown in FIG. 25. In this embodiment, the effects of the fifth embodiment can be synergistically combined with the effects of the sixth embodiment.
While the foregoing fifth to seventh embodiments have been described in connection with examples in which each current mirror circuit is designed in a two-stage configuration, the current mirror circuit can be designed in a more-stage configuration in accordance with a reduction in threshold voltage, and may of course be in such a configuration.
Eighth Embodiment
FIG. 27 is a circuit diagram showing the configuration of an eighth embodiment.
In this embodiment, seventh voltage/current converting element 401, second current mirror circuit 109, and third current mirror circuit 110, which are made up of n-mos transistors in the second embodiment shown in FIG. 10, are replaced with seventh voltage/current converting circuit 401′, second current mirror circuit 109′, and third current mirror circuit 110′ which are made up of p-mos transistors.
P-mos transistor M4′′, which is seventh voltage/current converting element 401′, which is applied at a gate with DC voltage VC for generating a bias current, has a source connected to a power supply, and a drain connected to the gates of p-mos transistors M2A-M2F which make up the first current mirror circuit.
Each of p-mos transistors M3C′′, M3D′′ which make up second current mirror circuit 109′ has a source connected to the power supply, and a gate connected to the drains of p-mos transistor M2E and n-mos transistor M1E. P-mos transistor M3C′′ has a drain connected to the gate of each p-mos transistor M3C′′, M3D′′, while p-mos transistor M3D′′ has a drain connected to the drains of p-mos transistor M2F and n-mos transistor M1F.
Each of p-mos transistors M3A′′, M3B′′ which make up third current mirror circuit 110′ has a source connected to the power supply, and a gate connected to the drains of p-mos transistor M2B and n-mos transistor M1B. P-mos transistor M3B′′ has a drain connected to a gate of each p-mos transistor M3A′′, M3B′′, while p-mos transistor M3A′′ has a drain connected to the drains of p-mos transistor M2A and n-mos transistor M1A.
This embodiment configured as described above is similar to the second embodiment in that seventh voltage/current converting element 107′ is provided at an input of first current mirror circuit 108 to supply the input of first current mirror circuit 108 with DC voltage VC not related to a signal, thereby making it possible to cause a current flowing through transistors M2A-M2F to be larger than a current flowing through transistors M1A-M1F at all times. As a result, it is possible to solve a problem in which a bias current experiences difficulties in flowing into transistors M3A-M3D which make up second current mirror circuit 109′ and third current mirror circuit 110′, and to process a differential signal over a full wave rather than half wave, making it less likely to produce a loss in the signal.
Ninth Embodiment
FIG. 28 is a circuit diagram showing the configuration of a ninth embodiment according to the present invention.
In this embodiment, common-mode current generating part 107 in the first embodiment shown in FIG. 7 is replaced with common-mode current generating part 107′′ which comprises a current mirror circuit, thus causing it to have a function as the seventh voltage/current converting element shown in FIG. 9.
Common-mode current generating part 107′′ is provided with n-mos transistors M4A′, M4B′ in addition to the configuration of common-mode current generating part 107 shown in FIG. 7. Each of n-mos transistors M4A′, M4B′ has a source grounded, and a drain and a gate supplied with DC voltage VC connected to the gates of p-mos transistors M2A-M2F in common with the drains of n-mos transistors M1C, M1D′.
In this embodiment configured in the foregoing manner, by applying reference current Iref into the gates of n-mos transistors M4A′, M4B′, a current flowing through transistors M2A-M2F can be made larger than a current flowing through transistors M1A-M1F at all times, as is the case with the second embodiment. As a result, it is possible to solve a problem in which a bias current experiences difficulties in flowing into transistors M3A-M3D which make up third current mirror circuit 110, and to process a differential signal over a full wave rather than half wave, making it less likely to produce a loss in the signal.
Among the respective embodiments described above, by combining those embodiments which can be combined, effects in the respective embodiments can be synergistically combined. For example, the configuration for adding a bias current shown in the second, fourth, eighth, and ninth embodiments can be combined with a configuration having current mirror circuits at multiple stages shown in the fifth to seventh embodiments, and moreover, transconductance amplifiers provided thereby can of course be designed in a dual configuration, as shown in the second embodiment. These configurations are also included in the present invention.
Tenth Embodiment
FIG. 29 is a diagram showing a tenth embodiment. In this embodiment, the transconductance amplifiers in the first to ninth embodiment are used in filter circuits. As shown in FIG. 29a, in this embodiment, first-order filter 241 is connected in series with fourth-order filters 242, 243.
Each filter is a Gm-C filter which comprises a transconductance amplifier, in any of the configurations of the first to ninth embodiments, and a capacitance. First-order filter 241 comprises transconductance amplifiers 244, 245 and a capacitance as shown in FIG. 29b, while fourth-order filters 242, 243 each comprise four transconductance amplifiers 246-249 and a capacitance as shown in FIG. 29c. 
Transconductance amplifier 244 which forms part of first-order filter 241 has an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of transconductance amplifier 245, respectively, and grounded through capacitances as well. Transconductance amplifier 245 in turn has an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of transconductance amplifier 245, and is thus applied with negative feedback.
Transconductance amplifier 246 which forms part of fourth-order filter 242 or 243 has an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of transconductance amplifier 248, respectively, and grounded through capacitances as well. Transconductance amplifier 248 has an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of transconductance amplifier 249, respectively, and grounded through capacitances as well. Transconductance amplifier 249 has an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of transconductance amplifier 249, and is thus applied with negative feedback. Transconductance amplifier 247 has an input terminal and an inverting input terminal connected to the output terminal and inverting output terminal of transconductance amplifier 248, and transconductance amplifier 247 has an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of transconductance amplifier 248.
By configuring first-order filter 241 and fourth-order filters 242, 243 using the transconductance amplifiers of the first to ninth embodiments and the capacitances, the filters can be configured with reduced common-mode components in signals which appear at their output terminals. Also, it is not essential to combine first-order filter 241 with fourth-order filters 242, 243, but they may be used as discrete filters, as a matter of course.
Eleventh Embodiment
FIG. 30 is a diagram showing an eleventh embodiment. In this embodiment, a Gm-C type current controlled oscillator is configured using the transconductance amplifier of the ninth embodiment, and is applied to a frequency control loop to configure a PLL circuit.
FIG. 30a shows the configuration of a PLL circuit which uses a frequency control loop. The PLL circuit of this embodiment comprises phase detector 251, charge pump circuit 252, loop filter 253, voltage/current converter 254, current controlled oscillator 255, and core filter 256.
Phase detector 251 receives reference frequency signal S1 from the outside and current controlled oscillator 255 to generate a signal in accordance with a phase difference therebetween. An output signal of phase detector 251 is amplified by charge pump circuit 252, converted to a current in voltage/current converter 254 after high frequency components thereof are removed by loop filter 253, and supplied to current controlled oscillator 255 and core filter 256 as current control signal S2.
Current controlled oscillator 255 has its oscillation frequency controlled in accordance with the value of current control signal S2, while core filter 256 changes a frequency response characteristic in accordance with the value of current control signal S2.
FIG. 30b is a circuit diagram showing the configuration of current controlled oscillator 255.
Current controlled oscillator 255 shown in FIG. 30b comprises comparison voltage generating circuit 257, comparators 2581, 2582, RS flip-flop 259, resistors R2, R1, R2 provided between a power supply and a ground, and a switch, whose open/close state is controlled by RS flip-flop 259, for selectively supplying comparison voltage generating circuit 257 with a voltage divided by each resistor. The comparison voltage generating circuit is made up of transconductance amplifier gmm and capacitance Cm.
Comparators 2581, 2582, provided in front of RF flip-flop 259, compare output voltage Vgm of comparison voltage generating circuit 257 with Vh and Vl, and switch the stage of RS flip-flop 259 in accordance with the result. RS flip-flop 259 is set and reset to cause a change in its output, to change an input voltage to comparison voltage generating circuit 257, charging and discharging capacitance Cm to cause a change in output voltage Vgm of comparison voltage generating circuit 257. This operation is repeated every half period of the oscillation frequency of current controlled oscillator 255, and the output of RS flip-flop 259 is supplied to phase detector 251 as the output of current controlled oscillator 255.
Oscillation frequency tOSC of current controlled oscillator 255 is estimated by:

tOSC=2×(1/(gmu/Cm)×(R1/(R1+2×R2))+td)

where gmu represents mutual conductance of transconductance amplifier gmm, and td represents a delay on a switching path indicated by the broken arrow in FIG. 30b. Oscillation frequency tOSC of current controlled oscillator 255 is dominated by the ratio gmu/Cm of the mutual transconductance to the capacitance, and by delay td on the switching path. The ratio of the resistances 1/(R1+2×R2) determines the ratio of input and output voltages to comparison voltage generating circuit 257, and does not directly relate to oscillation frequency tOSC of current controlled oscillator 255. Stated another way, current controlled oscillator 255 will never be affected by processing steps, temperature, or supplied voltage. This means that an adjusted oscillation accuracy is ideal.

FIG. 30c is a circuit diagram specifically showing the configuration of comparison voltage generating circuit 257 shown in FIG. 30b. 
Comparison voltage generating circuit 257 is made up of transconductance amplifiers 260, 261 which comprises transconductance amplifier gmm, and capacitance Cm. Transconductance amplifier 260 has an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of transconductance amplifier 261, and also connected to an inverting input terminal and an input terminal of transconductance amplifier 260 and is thus applied with a negative feedback. Transconductance amplifier 260 has the input terminal and inverting input terminal connected to an input terminal of comparison voltage generating circuit 257 through capacitances C1, C2, respectively, and an output terminal and an inverting output terminal of transconductance amplifier 261 are respectively used as output terminals of comparison voltage generating circuit 257.
Each of transconductance amplifiers 260, 261 is the transconductance amplifier according to the ninth embodiment, and is supplied with current control signal S2 to control signal input terminal s current Iref. By connecting transconductance amplifier 260 to apply the same with a negative feedback in the foregoing manner, a current flowing through an output stage is controlled in accordance with the value of current control signal S2 to control a signal bias at the output. As a result of controlling the signal bias, the mutual conductance changes to cause a change in gmu/Cm which is the ratio of the mutual conductance to the capacitance, dominating oscillation frequency tOSC of current controlled oscillator 255, resulting in a change in oscillation frequency tOSC of current controlled oscillator 255.
While this embodiment has been described on the assumption that the transconductance amplifiers shown in the ninth embodiment are used as transconductance amplifiers 260, 261, the transconductance amplifiers shown in the second embodiment, fourth embodiment, and eighth embodiment can be used as well. By connecting these transconductance amplifiers likewise so as to apply a negative feedback thereto, a current flowing through the output stage is controlled in accordance with voltage VC, causing a change in the mutual conductance. By converting current control signal S2 to a voltage through a resistor, and by supplying voltage VC, a signal bias generating circuit, a current controlled oscillator, and a PLL circuit can be configured in a manner similar to this embodiment.
Further, the circuit characteristics are improved by using transconductance amplifiers which exhibit the same characteristics for transconductance amplifiers 260, 261, but it is not essential to design the transconductance amplifiers shown in the second, fourth, eighth, and ninth embodiments. Transconductance amplifier 260 is provided for the purpose of setting an input bias, and a similar circuit operation can be performed, for example, by providing a capacitance between outputs of transconductance amplifier 260. In configuring transconductance amplifier gmm in this embodiment, the importance to recognize that the transconductance amplifier, shown in the second, fourth, eighth, ninth embodiment, is used as transconductance amplifier 260 which is connected so that it can be applied with a negative feedback to control current flowing through the output stage in accordance with the value of current control signal S2, such that the signal bias of the output is controlled.
Twelfth Embodiment
FIG. 31 is a circuit diagram showing the configuration of a twelfth embodiment according to the present invention.
This embodiment is made up of n-mos transistors M03A, M3A, M5A, M6A, M7A, M03B, M3B, M5B, M6B, M7B, and p-mos transistors M04A, M4A, M8A, M04, M4B, M8B.
P-mos transistors M4A, M04A, M04B, M04B correspond to n-mos transistors M3A, M03A, M03B, M3B, respectively, where these corresponding transistors are provided between a power supply and a ground with their drains being in common. P-mos transistors M4A, M04A, M04B, M04B have their gates connected to the drains of p-mos transistors M04A, M04B to configure a current mirror circuit. N-mos transistors M3A, M03A have their gates connected commonly to gate of M03B, M3B to configure an OTA similar to the OTA shown in FIG. 1a. 
Source-grounded n-mos transistors M5A, M6A, M5B, M6B respectively form part of a current mirror circuit, where transistors M5A, M6A have their gates connected commonly to a drain of transistor M6A, while transistors M5B, M6B have their gates connected commonly to a drain of transistor M6B. Transistor M5A has a drain connected to the drains of transistors M3A, M4A which serve as an output node of VOUT+ of the OTA, while transistor M5B has a drain connected to the drains of transistors M3B, M4B which serve as an output node of Vout− of the OTA.
Transistors M7A, M7B, M8A, M8B form part of a CMFB circuit, where transistor M7A supplied with reference signal VY at a gate has a grounded source, and transistor M8A having a gate used as node VX (next stage) which is a feedback signal input terminal, has a source connected to the power supply. Transistors M7A, M8A have their drains connected to the gates of n-mos transistors M5A, M6A and to a drain of transistor M6A to supply a reference current of a current mirror circuit which is made up of transistors M5A, M6A.
Transistor M7B supplied with reference signal VY at a gate has a grounded source, and transistor M8B having a gate used as node VX (next stage), has a source connected to the power supply. Transistors M7B, M8B have their drains connected to the gates of n-mos transistors M5B, M6B and to a drain of transistor M6B to supply a reference signal to a current mirror circuit which is made up of transistors M5B, M6B.
In the circuit configured as described above, the operation in an OTA portion is similar to the operation which has been described with reference to FIG. 1a. 
A description will be given of the operation of the circuit of this embodiment which is connected as shown in FIG. 2c to increase common-mode voltages of VIN+, VIN− supplied from the OTA at the preceding stage.
As gate voltages of transistors M03A, M03B increase due to an increase in common-mode components of VIN+, VIN− supplied from the OTA at the preceding stage, drain currents of transistors M3A, M3B increase, while voltage decreases at node VX (preceding stage), which is a feedback signal output terminal. Since node VX (preceding stage) is connected to node VX (next stage) of the OTA disposed at the preceding stage, gate voltages decrease in transistor M8A, M8B of the OTA at the preceding stage, while drain currents of transistors M8A, M8B increase. In this event, the difference between a current which flows through transistors M7A, M7B, whose drain current is determined at a predetermined value by reference signal VY, and a current which flows through transistors M8A, M8B, flows into transistors M6A, M6B to increase the current which flows into transistors M6A, M6B. Since transistors M6A, M6B form part of a current mirror circuit together with transistors M5A, M5B, a current flowing through transistors M5A, M5B also increases to the accompaniment of an increase in the current which flows through transistors M6A, M6B. As the current which flows through transistors M5A, M5B increases, the voltages of VOUT+, VOUT− decrease. Since VOUT+ and VOUT− of the OTA at the preceding stage are VIN+, VIN− of the OTA at the next stage, a feedback circuit is configured.
In this embodiment configured as described above, the drains of transistors M3A, M4A, M5A or the drains of transistors M3B, M4B, M5B are connected to each output node of the OTA, and three transistors are connected to the output node. As a result, the connected quantity is reduced from before to reduce output conductance and parasitic capacitance caused by each transistor connected in parallel, thus making it possible to prevent a reduction in output impedance of the OTA, and a degradation in characteristics as the OTA.
Thirteenth Embodiment
FIG. 32 is a circuit diagram showing the configuration of a thirteenth embodiment according to the present invention.
In this embodiment, n-mos transistor M9 supplied with reference signal VY at a gate is provided between each gate of p-mos transistors M4A, M04A, M04B, M4B and a ground in the circuit of the twelfth embodiment shown in FIG. 31, to supply VIN+, VIN− to the sources of transistors M7A, M7B which are supplied with reference signal VY in the first embodiment.
In this embodiment configured as described above, an common-mode bias of outputs VOUT+, VOUT− is determined to a predetermined bias by n-mos transistor M9. Also, as common-mode components of VIN+, VIN− supplied from the OTA at the preceding stage increase to increase the gate voltages of transistors M03A, M03B, the drain currents of transistors M03A, M03B increase, while a voltage at node VX (preceding stage) decreases. Since node VX (preceding stage) is connected to node VX (next stage) of the OTA disposed at the preceding stage, the gate voltages of transistors M8A, M8B decrease in the OTA at the preceding stage, while the drain currents of transistors M8A, M8B increase. In this event, a current flowing into transistors M6A, M6B further increases due to an increase in the gate voltage of transistors M7A, M7B which are supplied with VIN+, VIN− at the gates, where the amount of current amounts to approximately twice as much as the twelfth embodiment. Since transistors M6A, M6B form part of a current mirror circuit together with transistors M5A, M5B, a current flowing through transistors M5A, M5B also increases to the accompaniment of an increase in the current which flows through transistors M6A, M6B. As the current flowing through transistors M5A, M5B increases, the voltages of VOUT+ and VOUT− decrease.
In this embodiment configured as described above, three transistors are connected to each output node of the OTA, making it possible to prevent a reduction in output impedance of the OTA and a degradation in the characteristics as the OTA, as is the case with the twelfth embodiment. Further, the signal amplitude of a response component in VOUT+, VOUT− to a change in common-mode components of VIN+, VIN− increases to approximately twice as much as the twelfth embodiment, thus improving the feedback response speed.
Fourteenth Embodiment
FIG. 33 is a circuit diagram showing the configuration of a fourteenth embodiment according to the present invention.
In this embodiment, p-mos transistor M3′ supplied with reference signal VY at a gate is provided between each gate of p-mos transistors M4A, M04A, M04B, M04B and the power supply in the circuit shown in FIG. 2B, and transistors M3A′, M3B′ supplied with reference voltage VY are removed in the circuit shown in FIG. 2b. 
In this embodiment configured as described above, an common-mode bias of outputs VOUT+, VOUT− is set to a predetermined bias by p-mos transistor M3′. In this way, three transistors are connected to each output node of the OTA, as is the case with the twelfth and thirteenth embodiments, making it possible to prevent a reduction in the output impedance of the OTA and a degradation in the characteristics as the OTA.
While each embodiment has been described on the assumption that the transistors which make up circuits comprise p-mos transistors and n-mos transistors, the circuits may be made up of JFETs and bipolar transistors. Also, p-mos transistors may be replaced with n-mos transistors, and n-mos transistors may be replaced with p-mos transistors.
Alternatively, a well separation type, which is effective in reducing noise, can be used for the n-mos transistors.
Fifteenth Embodiment
FIG. 34 is a diagram showing a fifteenth embodiment. In this embodiment, the transconductance amplifiers of the twelfth to fourteenth embodiments are used in filter circuits. As shown in FIG. 34a, this embodiment comprises first-order filter 241 connected in series with fourth-order filters 242, 243.
Each filter is a Gm-C filter which comprises which comprises a transconductance amplifier, in any of the configurations of the twelfth to fourteenth embodiments, and a capacitance. First-order filter 241 comprises transconductance amplifiers 244, 245 and a capacitance as shown in FIG. 34b, while fourth-order filters 242, 243 each comprise four transconductance amplifiers 246-249 and a capacitance as shown in FIG. 34c. 
Transconductance amplifier 244 which forms part of first-order filter 241 has an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of transconductance amplifier 245, respectively, and is grounded through capacitances as well. Transconductance amplifier 245 in turn has an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of transconductance amplifier 245, and is thus applied with negative feedback. Also, VX (preceding stage) of transconductance amplifier 245 is connected to VX (next stage) of transconductance amplifier 244.
Transconductance amplifier 246 which forms part of fourth-order filter 242 or 243 has an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of transconductance amplifier 248, respectively, and is grounded through capacitances as well. Transconductance amplifier 248 has an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of transconductance amplifier 249, respectively, and is grounded through capacitances as well. Transconductance amplifier 249 has an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of transconductance amplifier 249, and is thus applied with negative feedback. Transconductance amplifier 247 has an input terminal and an inverting input terminal connected to the output terminal and inverting output terminal of transconductance amplifier 248, and transconductance amplifier 247 has an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of transconductance amplifier 248. Also, the VX (preceding stage) of transconductance amplifier 248 is connected to the VX (next stage) of transconductance amplifiers 246, 247, and the VX (next stage) of transconductance amplifier 248 is connected to the VX (preceding stage) of transconductance amplifiers 248, 249.
By configuring first-order filter 241 and fourth-order filters 242, 243 using the transconductance amplifiers of the first to third embodiments and capacitances, the filters can be configured with the common-mode bias being set at a predetermined value such that there is limited degradation in characteristics. Also, it is not essential to combine first-order filter 241 with fourth-order filters 242, 243, but they may be used as discrete filters, as a matter of course.
Sixteenth Embodiment
FIG. 35 is a diagram showing a sixteenth embodiment. In this embodiment, a Gm-C type current controlled oscillator is configured using the transconductance amplifier of the twelfth to fourteenth embodiments, and is applied to a frequency control loop to configure a PLL circuit.
FIG. 35a shows the configuration of a PLL circuit which uses a frequency control loop. The PLL circuit of this embodiment comprises phase detector 251, charge pump circuit 252, loop filter 253, voltage/current converter 254, current controlled oscillator 255, and core filter 256.
Phase detector 251 receives reference frequency signal S1 from the outside and current controlled oscillator 255 to generate a signal in accordance with a phase difference therebetween. The output signal of phase detector 251 is amplified by charge pump circuit 252, converted to a current in voltage/current converter 254 after high frequency components thereof are removed by loop filter 253, and is supplied to current controlled oscillator 255 and core filter 256 as current control signal S2.
Current controlled oscillator 255 has its oscillation frequency controlled in accordance with the value of current control signal S2, while core filter 256 changes the frequency response characteristics in accordance with the value of current control signal S2.
FIG. 35b is a circuit diagram showing the configuration of current controlled oscillator 255.
Current controlled oscillator 255 shown in FIG. 35b comprises comparison voltage generating circuit 257, comparators 2581, 2582, RS flip-flop 259, resistors R2, R1, R2 provided between a power supply and a ground, and a switch whose open/close state of which is controlled by RS flip-flop 259, for selectively supplying comparison voltage generating circuit 257 with a voltage divided by each resistor. Comparison voltage generating circuit 257 is made up of transconductance amplifier gmm and capacitance Cm.
Comparators 2581, 2582, provided in front of RF flip-flop 259, compare output voltage Vgm of comparison voltage generating circuit 257 with Vh and Vl, and switch the stage of RS flip-flop 259 in accordance with the result. RS flip-flop 259 is set and reset to cause a change in its output, to change an input voltage to signal generating bias circuit 257, charging and discharging capacitance Cm to cause a change in output voltage Vgm of comparison voltage generating circuit 257. This operation is repeated every half period of the oscillation frequency of current controlled oscillator 255, and the output of RS flip-flop 259 is supplied to phase detector 251 as the output of current controlled oscillator 255.
Oscillation frequency tOSC of current controlled oscillator 255 is estimated by:

tOSC=2×(1/(gmu/Cm)×(R1/(R1+2×R2))+td)

where gmu represents mutual conductance of transconductance amplifier gmm, and td represents a delay on a switching path indicated by the broken arrow in FIG. 35b. Oscillation frequency tOSC of current controlled oscillator 255 is dominated by the ratio gmu/Cm of the mutual transconductance to the capacitance, and by delay td on the switching path. The ratio of the resistances R1/(R1+2×R2) determines the ratio of input and output voltages to comparison voltage generating circuit 257, and does not directly relate to oscillation frequency tOSC of current controlled oscillator 255. Stated another way, current controlled oscillator 255 will never be affected by processing steps, temperature, or supplied voltage. This means that an adjusted oscillation accuracy is ideal.

In this embodiment, the transconductance amplifier of the first to third embodiments is used for comparison voltage generating circuit 257, and current control signal S2 is converted to a voltage by a resistor (not shown) and supplied to VX (next stage) which is a feedback signal input terminal. By applying a negative feedback as described above, a current flowing through the output stage is controlled in accordance with the value of current control signal S2 to control the common-mode bias of the output. As a result of controlling the common-mode bias, the mutual conductance changes to cause a change in gmu/Cm which is the ratio of the mutual conductance to the capacitance, dominating oscillation frequency tOSC of current controlled oscillator 255, resulting in a change in oscillation frequency tOSC of current controlled oscillator 255.

## Claims

1. A transconductance amplifier for generating a first output voltage signal and a second output voltage signal proportional to a difference between a first input voltage signal and a second input voltage signal applied thereto from a first and a second output stage, respectively, said transconductance amplifier characterized by comprising:
a feedback signal output terminal for outputting common-mode components of the first output voltage signal and second output voltage signal;
a feedback signal input terminal;
a reference signal input terminal; and
feedback signal conveying means for controlling the first output voltage signal or second output voltage signal in accordance with an input signal to said feedback signal input terminal and an input signal to said reference signal input terminal,
wherein said feedback signal input terminal, said reference signal input terminal and said feedback signal conveying means are provided in said first and second output stages, and said feedback signal conveying means is connected to each output stage, and said feedback signal conveying means comprises:
a current mirror circuit having an output part connected to said output stage;
a first transistor of a first conductivity type having a control terminal connected to said feedback signal input terminal; and
a second transistor of a second conductivity type having a control terminal connected to said reference signal input terminal for determining a reference current for said current mirror circuit together with said first transistor.

2. A transconductance amplifier for generating a first output voltage signal and a second output voltage signal proportional to a difference between a first input voltage signal and a second input voltage signal applied thereto from a first and a second output stage, respectively, said transconductance amplifier characterized by comprising:
a feedback signal output terminal for outputting common-mode components of the first output voltage signal and second output voltage signal;
a reference signal input terminal for receiving a reference signal for bringing each of said first and second output stages into a predetermined bias state;
a feedback signal input terminal; and
feedback signal conveying means for controlling the first output voltage signal or second output voltage signal in accordance with an input signal to said feedback signal input terminal and an input signal to said reference signal input terminal,
wherein said feedback signal input terminal and said feedback signal conveying means are provided in said first and second output stages, and said feedback signal conveying means are connected to each output stage, and
said feedback signal conveying means comprises:
a current mirror circuit having an output part connected to said output stage;
a first transistor of a first conductivity type having a control terminal connected to said feedback signal input terminal; and
a second transistor of a second conductivity type for receiving the first input voltage signal or the first input voltage signal at a control terminal to determine a reference current for said current mirror circuit together with said first transistor.

3. A transconductance amplifier for generating a first output voltage signal and a second output voltage signal proportional to a difference between a first input voltage signal and a second input voltage signal applied thereto from a first and a second output stage, respectively, said transconductance amplifier characterized by comprising:
a feedback signal output terminal for outputting common-mode components of the first output voltage signal and second output voltage signal;
a reference signal input terminal for receiving a reference signal for bringing each of said first and second output states into a predetermined bias state;
a feedback signal input terminal; and
feedback signal conveying means for controlling the first output voltage signal or second output voltage signal in accordance with an input signal to said feedback signal input terminal and an input signal to said reference signal input terminal,
wherein said feedback signal input terminal and said feedback signal conveying means are provided in said first and second output stages, and said feedback signal conveying means are connected to each output stage, and
said feedback signal conveying means is a transistor which has a control terminal connected to said feedback signal input terminal and an output part connected to said output stage.

4. A transconductance amplifier for generating a first output voltage signal and a second output voltage signal proportional to a difference between a first input voltage signal and a second input voltage signal applied thereto from a first and a second output stage, respectively, said transconductance amplifier characterized by comprising:
a feedback signal output terminal for outputting common-mode components of the first output voltage signal and second output voltage signal;
a feedback signal input terminal;
a reference signal input terminal; and
feedback signal conveying means for controlling the first output voltage signal or second output voltage signal in accordance with an input signal to said feedback signal input terminal and an input signal to said reference signal input terminal,
wherein said feedback signal input terminal, said reference signal input terminal and said feedback signal conveying means are provided in said first and second output stages, and said feedback signal conveying means is connected to each output stage, and
said filter circuit comprises said transconductance amplifier and a capacitance, and is made up of a first and a second transconductance amplifier, said first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said second transconductance amplifier, respectively, and grounded through capacitances, said second transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said second transconductance amplifier.

5. A transconductance amplifier for generating a first output voltage signal and a second output voltage signal proportional to a difference between a first input voltage signal and a second input voltage signal applied thereto from a first and a second output stage, respectively, said transconductance amplifier characterized by comprising:
a feedback signal output terminal for outputting common-mode components of the first output voltage signal and second output voltage signal;
a feedback signal input terminal;
a reference signal input terminal; and
feedback signal conveying means for controlling the first output voltage signal or second output voltage signal in accordance with an input signal to said feedback signal input terminal and an input signal to said reference signal input terminal,
wherein said feedback signal input terminal, said reference signal input terminal and said feedback signal conveying means are provided in said first and second output stages, and said feedback signal conveying means is connected to each output stage, and
said filter circuit comprises a first to a fourth transconductance amplifier, said first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said second transconductance amplifier and grounded through capacitances, said second transconductance amplifier having an output terminal and an inverting output terminal connected to the input terminal and inverting input terminal of said second transconductance amplifier and grounded through capacitances, said third transconductance amplifier having an output terminal and an inverting output terminal connected to an inverting input terminal and an input terminal of said third transconductance amplifier, said fourth transconductance amplifier having an input terminal and an inverting input terminal connected to the output terminal and inverting output terminal of said second transconductance amplifier, said fourth transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said second transconductance amplifier.

6. A filter circuit comprising:
a first-order filter circuit comprising first and second transconductance amplifiers, wherein:
said first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said second transconductance amplifier, respectively, and grounded through capacitances, said second transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said second transconductance amplifier, and
two fourth order filter circuits connected in series to said first-order filter circuit, each of said fourth-order filter circuits comprising third to sixth transconductance amplifiers
said third transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said fourth transconductance amplifier and grounded through capacitances, said fourth transconductance amplifier having an output terminal and an inverting output terminal connected to the input terminal and inverting input terminal of said fourth transconductance amplifier and grounded through capacitances, said fifth transconductance amplifier having an output terminal and an inverting output terminal connected to an inverting input terminal and an input terminal of said fifth transconductance amplifier, said sixth transconductance amplifier having an input terminal and an inverting input terminal connected to the output terminal and inverting output terminal of said fourth transconductance amplifier, said sixth transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said fourth transconductance amplifier,
wherein each of said transconductance amplifiers comprises a transconductance amplifier for generating a first output voltage signal and a second output voltage signal proportional to a difference between a first input voltage signal and a second input voltage signal applied thereto from a first and a second output stage, respectively, said transconductance amplifier characterized by comprising:
a feedback signal output terminal for outputting common-mode components of the first output voltage signal and second output voltage signal;
a feedback signal input terminal;
a reference signal input terminal; and
feedback signal conveying means for controlling the first output voltage signal or second output voltage signal in accordance with an input signal to said feedback signal input terminal and an input signal to said reference signal input terminal,
wherein said feedback signal input terminal, said reference signal input terminal and said feedback signal conveying means are provided in said first and second output stages, and said feedback signal conveying means is connected to each output stage.

7. A voltage generating circuit configured using the transconductance amplifier for generating a first output voltage signal and a second output voltage signal proportional to a difference between a first input voltage signal and a second input voltage signal applied thereto from a first and a second output stage, respectively, said transconductance amplifier characterized by comprising:
a feedback signal output terminal for outputting common-mode components of the first output voltage signal and second output voltage signal;
a feedback signal input terminal;
a reference signal input terminal; and
feedback signal conveying means for controlling the first output voltage signal or second output voltage signal in accordance with an input signal to said feedback signal input terminal and an input signal to said reference signal input terminal,
wherein said feedback signal input terminal, said reference signal input terminal and said feedback signal conveying means are provided in said first and second output stages, and said feedback signal conveying means is connected to each output stage, characterized in that:
a feedback signal input terminal is used as a control signal input terminal for generating a bias current to change mutual conductance, and
said voltage generating circuit comprises a capacitance for alternatingly grounding an output current.

8. A current controlled oscillator configured using the voltage generating circuit according to claim 7, comprising:
a plurality of resistors provided in series between a power supply and a ground;
a switch group provided between said plurality of resistors and an input of said voltage generating circuit for selectively applying a voltage divided by said plurality of resistors to said voltage generating circuit;
a first and a second comparator for comparing terminal voltages of said plurality of resistors provided in series with an output of said voltage generating circuit; and
a flip-flop whose state changes in state in accordance with outputs of said first and second comparators and generates an output which defines an oscillation frequency and is used as a switching control signal for said switch group.

9. A PLL circuit configured using the current controlled oscillator according to claim 8, comprising:
a current controlled oscillator, whose oscillation frequency is controlled by a current control signal;
a phase detector for receiving a reference frequency signal and an output of said current controlled oscillator to generate a signal in accordance with a phase difference therebetween; and
a voltage/current converter for converting an output of said phase detector to a current, and supplying the same to the control signal input terminal of said current controlled oscillator.

10. A first-order filter circuit configured using the transconductance amplifier for generating a first output voltage signal and a second output voltage signal proportional to a difference between a first input voltage signal and a second input voltage signal applied thereto from a first and a second output stage, respectively, said transconductance amplifier characterized by comprising:
a feedback signal output terminal for outputting common-mode components of the first output voltage signal and second output voltage signal;
a reference signal input terminal for receiving a reference signal for bringing each of said first and second output stages into a predetermined bias state;
a feedback signal input terminal; and
feedback signal conveying means for controlling the first output voltage signal or second output voltage signal in accordance with an input signal to said feedback signal input terminal and an input signal to said reference signal input terminal,
wherein said feedback signal input terminal and said feedback signal conveying means are provided in said first and second output stages, and said feedback signal conveying means are connected to each output stage, wherein:
said filter circuit comprises said transconductance amplifier and a capacitance, and is made up of a first and a second transconductance amplifier, said first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said second transconductance amplifier, respectively, and grounded through capacitances, said second transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said second transconductance amplifier.

11. A first-order filter circuit configured using the transconductance amplifier according to claim 1, wherein:
said filter circuit comprises said transconductance amplifier and a capacitance, and is made up of a first and a second transconductance amplifier, said first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said second transconductance amplifier, respectively, and grounded through capacitances, said second transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said second transconductance amplifier.

12. A first-order filter circuit configured using the transconductance amplifier according to claim 2, wherein:
said filter circuit comprises said transconductance amplifier and a capacitance, and is made up of a first and a second transconductance amplifier, said first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said second transconductance amplifier, respectively, and grounded through capacitances, said second transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said second transconductance amplifier.

13. A first-order filter circuit configured using the transconductance amplifier according to claim 3, wherein:
said filter circuit comprises said transconductance amplifier and a capacitance, and is made up of a first and a second transconductance amplifier, said first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said second transconductance amplifier, respectively, and grounded through capacitances, said second transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said second transconductance amplifier.

14. A filter circuit comprising:
a first-order filter circuit comprising first and second transconductance amplifiers, wherein:
said first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said second transconductance amplifier, respectively, and grounded through capacitances, said second transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said second transconductance amplifier, and
two fourth order filter circuits connected in series to said first-order filter circuit, each of said fourth-order filter circuits comprising third to sixth transconductance amplifiers
said third transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said fourth transconductance amplifier and grounded through capacitances, said fourth transconductance amplifier having an output terminal and an inverting output terminal connected to the input terminal and inverting input terminal of said fourth transconductance amplifier and grounded through capacitances, said fifth transconductance amplifier having an output terminal and an inverting output terminal connected to an inverting input terminal and an input terminal of said fifth transconductance amplifier, said sixth transconductance amplifier having an input terminal and an inverting input terminal connected to the output terminal and inverting output terminal of said fourth transconductance amplifier, said sixth transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said fourth transconductance amplifier,
wherein each of said transconductance amplifiers comprises a transconductance amplifier for generating a first output voltage signal and a second output voltage signal proportional to a difference between a first input voltage signal and a second input voltage signal applied thereto from a first and a second output stage, respectively, said transconductance amplifier characterized by comprising:
a feedback signal output terminal for outputting common-mode components of the first output voltage signal and second output voltage signal;
a reference signal input terminal for receiving a reference signal for bringing each of said first and second output stages into a predetermined bias state;
a feedback signal input terminal; and
feedback signal conveying means for controlling the first output voltage signal or second output voltage signal in accordance with an input signal to said feedback signal input terminal and an input signal to said reference signal input terminal,
wherein said feedback signal input terminal and said feedback signal conveying means are provided in said first and second output stages, and said feedback signal conveying means are connected to each output stage.

15. A filter circuit comprising:
a first-order filter circuit comprising first and second transconductance amplifiers, wherein:
said first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said second transconductance amplifier, respectively, and grounded through capacitances, said second transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said second transconductance amplifier, and
two fourth order filter circuits connected in series to said first-order filter circuit, each of said fourth-order filter circuits comprising third to sixth transconductance amplifiers
said third transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said fourth transconductance amplifier and grounded through capacitances, said fourth transconductance amplifier having an output terminal and an inverting output terminal connected to the input terminal and inverting input terminal of said fourth transconductance amplifier and grounded through capacitances, said fifth transconductance amplifier having an output terminal and an inverting output terminal connected to an inverting input terminal and an input terminal of said fifth transconductance amplifier, said sixth transconductance amplifier having an input terminal and an inverting input terminal connected to the output terminal and inverting output terminal of said fourth transconductance amplifier, said sixth transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said fourth transconductance amplifier,
wherein each of said transconductance amplifiers comprises a transconductance amplifier according to claim 1.

16. A filter circuit comprising:
a first-order filter circuit comprising first and second transconductance amplifiers, wherein:
said first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said second transconductance amplifier, respectively, and grounded through capacitances, said second transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said second transconductance amplifier, and
two fourth order filter circuits connected in series to said first-order filter circuit, each of said fourth-order filter circuits comprising third to sixth transconductance amplifiers
said third transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said fourth transconductance amplifier and grounded through capacitances, said fourth transconductance amplifier having an output terminal and an inverting output terminal connected to the input terminal and inverting input terminal of said fourth transconductance amplifier and grounded through capacitances, said fifth transconductance amplifier having an output terminal and an inverting output terminal connected to an inverting input terminal and an input terminal of said fifth transconductance amplifier, said sixth transconductance amplifier having an input terminal and an inverting input terminal connected to the output terminal and inverting output terminal of said fourth transconductance amplifier, said sixth transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said fourth transconductance amplifier,
wherein each of said transconductance amplifiers comprises a transconductance amplifier according to claim 2.

17. A filter circuit comprising:
a first-order filter circuit comprising first and second transconductance amplifiers, wherein:
said first transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said second transconductance amplifier, respectively, and grounded through capacitances, said second transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said second transconductance amplifier, and
two fourth order filter circuits connected in series to said first-order filter circuit, each of said fourth-order filter circuits comprising third to sixth transconductance amplifiers
said third transconductance amplifier having an output terminal and an inverting output terminal connected to an input terminal and an inverting input terminal of said fourth transconductance amplifier and grounded through capacitances, said fourth transconductance amplifier having an output terminal and an inverting output terminal connected to the input terminal and inverting input terminal of said fourth transconductance amplifier and grounded through capacitances, said fifth transconductance amplifier having an output terminal and an inverting output terminal connected to an inverting input terminal and an input terminal of said fifth transconductance amplifier, said sixth transconductance amplifier having an input terminal and an inverting input terminal connected to the output terminal and inverting output terminal of said fourth transconductance amplifier, said sixth transconductance amplifier having an output terminal and an inverting output terminal connected to the inverting input terminal and input terminal of said fourth transconductance amplifier,
wherein each of said transconductance amplifiers comprises a transconductance amplifier according to claim 3.