# Patent

## Title
Switched capacitor voltage converters

## Abstract

An on-chip voltage conversion apparatus for integrated circuits includes a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.

## Background
BACKGROUND
The present invention relates generally to voltage conversion techniques and, more particularly, to switched capacitor voltage converters and methods for integrated circuit devices.
Power management has become a critical component for advanced computing architectures, including both high-end microprocessor systems and mobile electronic devices. However, existing on-chip solutions have limited success in simultaneously achieving high output current and high power conversion efficiency.
In particular, nominal power supply voltage (VDD) values for CMOS (complementary metal oxide semiconductor) technology have been gradually reduced over the past years due to performance and power scaling. In turn, maintaining efficiency in power delivery systems has become more difficult as VDD is scaled down. At VDD=1 Volt (V), the energy loss from an external power source to the circuits operated at VDD is significant. Since the power loss on the delivery grid is inversely proportional to the square of the voltage (V2), the efficiency issue on power delivery is further exacerbated for so-called “low” VDD circuits (e.g., about 300-500 millivolts (mV)).
Additionally, multiple supply voltages are required for logic circuits, SRAM, and embedded DRAM on the same IC chip. These voltages are generated using a linear series voltage regulator or an inductive buck converter. An on-chip linear regulator uses resistive elements to reduce the voltage and thus is not energy efficient. Traditionally, buck converters require discrete off-chip inductors to achieve high power conversion efficiency. However, due to the difficulty in integrating high quality inductors on silicon substrates, an on-chip integrated buck converter has poor power conversion efficiency.
Accordingly, it would be desirable to be able to provide improved voltage conversion systems for integrated circuit devices and systems having multiple voltage domains.
BRIEF SUMMARY
In an exemplary embodiment, an on-chip voltage conversion apparatus for integrated circuits includes a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
In another embodiment, an on-chip voltage conversion system for integrated circuits includes a clock source having a plurality of clock phases; a plurality of actuating signals corresponding to one of a plurality of phases; and a plurality of voltage converters controlled by the actuating signals, with each voltage converter including a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
In another embodiment, an on-chip voltage conversion system for integrated circuits includes a clock source having a plurality of clock phases; a plurality of actuating signals corresponding to one of a plurality of phases; and a plurality of voltage converters controlled by the actuating signals, with each voltage converter including a first capacitor; a first pair of NFET and PFET devices associated with a first voltage domain, with a first NFET of the first pair configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of the first voltage domain, and a first PFET of the first pair configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second pair of NFET and PFET devices associated with a second voltage domain, with a second NFET of the second pair configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of the second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain, and a second PFET of the second voltage domain configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain; and one or more additional capacitors in series with the first capacitor; one or more additional pairs of NFET and PFET devices associated with one or more additional voltage domains for each one or more additional capacitors so as to define a multiple level converter that nominally converts a voltage level of N voltage units to a voltage level of M voltage units and vice versa; wherein N also represents the total number of pairs of switching devices, N−1 represents the total number of capacitors, and 1≦M≦N−1.
In still another embodiment, a method of implementing on-chip voltage conversion for integrated circuits includes using a first NFET device to selectively couple a first electrode of a first capacitor to a low side voltage rail of a first voltage domain; using a first PFET device to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; using a second NFET device to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and using a second PFET device to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.



BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
FIG. 1 is a schematic diagram of a conventional 2-to-1 switched capacitor voltage converter;
FIG. 2 is a schematic diagram of a 2-to-1 switched capacitor voltage converter, in accordance with an embodiment of the invention;
FIG. 3 is a voltage and timing diagram illustrating the operation of the voltage converter of FIG. 2;
FIG. 4 is a of a 3-to-1 switched capacitor voltage converter and associated timing diagram, in accordance with a further embodiment of the invention;
FIG. 5 is a schematic diagram illustrating the general circuit topology of the converter of FIG. 4;
FIG. 6 is a schematic diagram of an exemplary, multi-phase voltage conversion system using the disclosed switched capacitor voltage converter embodiments, in accordance with a further embodiment of the invention.
FIG. 7 is a schematic diagram of a general switched capacitor voltage converter with N+1 voltage levels, in accordance with a further embodiment of the invention;
FIG. 8 is a schematic diagram of an exemplary multi-level voltage converter system using a total of k switched capacitor voltage converters shown in FIG. 8, in accordance with a further embodiment of the invention;
FIG. 9 is a schematic diagram of an exemplary N-to-M voltage down-converter system using the multi-phase voltage conversion system of FIG. 8;
FIG. 10 is a schematic diagram of an exemplary M-to-N voltage up-converter system using the multi-phase voltage conversion system of FIG. 8; and
FIG. 11 is a schematic diagram of a multi-level voltage conversion system using the system of FIG. 8, with multiple input and output voltages; and
FIG. 12 is a schematic diagram of an exemplary switched capacitor implemented using a deep trench capacitor array.



DETAILED DESCRIPTION
Disclosed herein are improved circuits and methods related to switched capacitor voltage converters and regulator techniques. Briefly stated, the embodiments presented herein utilize on-chip deep trench (DT) capacitors and silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) field effect transistor (FET) switches. In one embodiment for a 2-to-1 converter, two SOI, p-type FETs (PFETs) and two SOI, n-type FETs (NFETs) are used to accomplish the voltage conversion. In another embodiment for a 3-to-1 converter, three SOI PFETs and three SOI NFETs are used. A general architecture and methodology disclosed herein allows for voltage conversion between two voltages with an integer ratio. The disclosed system does not require high breakdown voltage switches. In addition, the disclosed system embodiments are reversible and may be used as a down-converter, an up-converter, or a negative voltage generator. In addition, an alternative embodiment contemplates utilizing bulk CMOS switches with triple well technology.
Further, the scalability of the disclosed system allows the integration of a very large number of individual voltage converters of multiple phases for smooth voltage output. As another aspect of the invention, voltage regulation is realized by changing the switching frequency.
Switched capacitor converters are discussed in a number of texts, for example, see Kiyoo Itoh, Masashi Horiguchi, and Hitoshi Tanaka, “Ultra-Low Voltage Nano-Scale Memories”, Springer, New York, 2007. Referring initially to FIG. 1, there is shown a schematic diagram illustrating the general topology of a conventional switched capacitor voltage converter 100 that performs either a voltage down-conversion from V2 to V1, or a voltage up-conversion from V1 to V2, wherein the voltage ratio of V2 to V1 is approximately equal to 2. In operation, a first pair of switches SW1 and SW2 is configured to couple a capacitor C1 between V1 and ground (as controlled by phase signal φ). A second pair of switches SW3 and SW4 is also configured to couple the capacitor C1 between V2 and V1 (as controlled by phase signal φ). In voltage down-conversion, V2>2*V1. By the closing of SW3 and SW4, the capacitor C1 is charged toward a level of the voltage difference across C1 of the value (V2−V1). By the closing of SW1 and SW2, the capacitor C1 is charged toward a level of the voltage difference across C1 of the value (V1−GND). Therefore, the voltage difference across C1 has changed over a relatively small range that corresponds to the difference between the value of V1 and the value (V2−V1), which leads to high voltage conversion efficiency. For example, if V1 is 0.95 volts (V) and V2 is 2.0 V, then the voltage across C1 switches between 0.95 V and 1.05 V, leading to an intrinsic conversion efficiency of 95%.
Conventionally, there are number of ways to implement the specific switching elements and capacitors for the converter of FIG. 1. For example, the switches and capacitor may simply be provided off-chip. Alternatively, if the switches are implemented as MOSFETs on a bulk semiconductor substrate, there is typically a PFET switching device coupled to the upper voltage rail (e.g., V2 in a 2-to-1 converter) and NFET devices for the remaining switches. However, these transistor switches are typically subjected to relatively large gate voltage swings, which leads to significant energy loss and thus reduced energy conversion efficiency.
Also, the conventional on-chip capacitor solutions limit both the output current and energy conversion efficiency of the on-chip voltage converters. Due to the lack of high-density capacitors, the on-chip switched capacitor voltage converters are useful only for low current applications. The stray capacitance of conventional on-chip capacitors reduces the energy conversion efficiency.
To improve the output current and energy efficiency of the on-chip switched capacitor voltage converter, the disclosed system uses on-chip deep trench (DT) capacitors and silicon-on-insulator (SOI) complimentary metal oxide semiconductor (CMOS) field effect transistor (FET) switches. Accordingly, FIG. 2 is a schematic diagram of a 2-to-1 switched capacitor voltage converter 200, in accordance with an embodiment of the invention, wherein the switches are implemented using SOI CMOS technology. More specifically, the 2-to-1 voltage converter 200 of FIG. 2 uses two PFETs, P1 and P2, and two NFETs, N1 and N2. P1 selectively couples a first capacitor electrode to the V1 rail, while P2 selectively couples the second capacitor electrode to the V2 rail. N1 selectively couples the first capacitor electrode to the ground rail while N2 selectively couples the second capacitor electrode to the V1 rail. In a down-conversion mode, V2 is the input voltage and V1 is the output voltage, where V2>2*V1. By way of a specific example, a down converter may operate with V2=2.0 V and V1=0.95 V. In an up-conversion mode, V1 is the input voltage and V2 is the output voltage, where V2<2*V1. By way of another specific example, an up converter may operate with V2=2.0 V and V1=1.05 V.
The actuating (clock) signals applied to the gates of P2 and N2 (φp2-1 and φn2-1) swing between V1 and V2. Conversely, the actuating signals applied to the gates of P1 and N1 (φp1-0 and φn1-0) swing between V0 (GND) and V1. A voltage and timing diagram 300 for these gate signals is shown in FIG. 3, together with the resulting voltage difference VC across the capacitor C. Non-overlap clocks are used to avoid a transient condition of creating a direct path from V2 to GND (i.e., preventing all four FETs from being simultaneously conductive). An advantageous aspect of this embodiment is that each transistor switch is only subjected to relatively small voltage swings. For example, the gate terminals of P2 and N2 in FIG. 2 are within the voltage domain between V2 and V1, while the gate terminals of P1 and N1 in FIG. 2 are within the voltage domain between V1 and V0.
The operation of the converter 200 of FIG. 2 in a down-conversion mode will be understood as follows. During the “P-cycle” where both PFETs, P1, P2 are conductive while both NFETs, N1, N2 are off, the capacitor C is charged from a lower voltage value (V1−V0) towards an upper value (V2−V1). During the “N-cycle” where both the PFETs are off while both the NFETs are on, the capacitor C is discharged from (V2−V1) to (V1−V0). In the limiting case of the cycle time being much greater than RC time constant, where R is the serial on-resistance of the switches, the charge output at V1 is 2*C*(V2+V0−2V1). Therefore, at the switching frequency f, the current output at V1 is given by the following expression:

Ī=2fC(V2+V0−2V1)  Eq. (1)

Assuming V0=0, the intrinsic energy efficiency is given by:




  
    
      
        
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In the general case, a more complete solution is given by the following expression:




  
    
      
        
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where tp and tn are the times when the PFETs and NFETs are on, respectively, td is the dead time that all FETs are off, and Rp1, Rp2, Rn1, and Rn2 are the on-resistance of the corresponding FETs.
Embodiments of the disclosed system use SOI CMOS transistors. Due to dielectric isolation of SOI transistors and their floating bodies, the small gate voltage swings as shown in FIG. 3 (e.g., the gate actuating signal for N2 swings between V1 and V2) allows the switches to be completely turned on and off. Because of the common body contact, operating in this configuration with dual-well bulk technology would generally problematic. Alternatively, at the cost of some additional silicon layout area, this circuit topology and voltage configuration is completely functional with bulk CMOS switches with triple well technology, where the wells for each transistor are isolated; and the well for N1 is tied to V0, the well for P1 is tied to V1, the well for N2 is tied to V1, and the well for P2 is tied to V2, respectively.
It will also be noted that the exemplary converter embodiment presented in FIG. 2 also utilizes on-chip, deep trench (DT) capacitors. This technology enables on-chip implementation of high density capacitors. The stray capacitance of the DT capacitor is very low, thereby minimizing the energy loss in charging the stray capacitor. Because of the scalability of both the DT capacitors and MOSFETs, the proposed voltage converter may be implemented with very fine granularity. Furthermore, a system using many converters operating on many different clock phases leads to a smooth output current and system stability.
Referring now to FIG. 4, there is shown a schematic diagram of a 3-to-1 switched capacitor voltage converter 400, in accordance with a further embodiment of the invention. As will be seen, the converter 400 is implemented with three PFETs and three NFETs embodied in SOI CMOS technology. Further, an intermediate voltage node V2 is available for multiple-phased converters. Whereas a conventional 3-to-1 converter generally requires high breakdown voltage devices (and is not compatible with high performance CMOS switches) the topology as presented in FIG. 4 advantageously uses only devices that are subjected to approximately Vdd. That is, as shown in the voltage and timing diagram in FIG. 4, the gate terminals of devices N1 and P1 operate in a voltage domain between V0 and V1; the gate terminals of devices N2 and P2 operate in a voltage domain between V1 and V2; and the gate terminals of devices N3 and P3 operate in a voltage domain between V2 and V3. As an exemplary 3-to-1 down converter, V0=0, V1=1 V, and V3=3.3 V. V2 is an internal node at approximately 2.1 V. As shown in FIG. 4, a capacitor CA is connected to V2 for keeping V2 stable; however, this additional capacitor CA is optional in multi-phased configuration. In an exemplary embodiment, the voltage conversion is done with many converters on different phases, where the V2 nodes are connected together. This method naturally forms a large capacitive charge reservoir for V2 that is stable, therefore the additional physical capacitor CA is not necessary.
The operation of the converter 400 of FIG. 4 in a down-conversion mode will be understood as follows. During the “P-cycle” where all PFETs, P1, P2, P3 are conductive while all NFETs, N1, N2, N3 are off, capacitor C1 is charged from a lower voltage value (V1−V0) towards an upper value (V2−V1) while capacitor C2 is charged from a lower voltage value (V2−V1) towards an upper value (V3−V2). During the “N-cycle” where all PFETs are off while all the NFETs are on, capacitor C1 is discharged from (V2−V1) to (V1−V0) while capacitor C2 is discharged from (V3−V2) to (V2−V1).
FIG. 5 is a schematic diagram illustrating the general circuit topology of the 4-ports, reversible 3-to-1 voltage converter. In addition to the 3-to-1 down converter shown in FIG. 4, this topology can be used as a 3-to-2 down-converter, a 1-to-3 up-converter, or a 2-to-3 up-converter. In a 3-to-1 down-conversion mode, V3 is the input voltage and V1 is the output voltage, where V3>3*V1. In a 3-to-2 down-conversion mode, V3 is the input voltage and V2 is the output voltage, where V3>(3*V2)/2. In a 1-to-3 up-conversion mode, V1 is the input voltage and V3 is the output voltage, where V3<3*V1. In a 2-to-3 up-conversion mode, V2 is the input voltage and V3 is the output voltage, where V3<(3*V2)/2. In addition to using the combination of 3 PFET/3 NFET devices, the voltages across the capacitors C1 and C2 as well as the drain-to-source voltages of the FET switches are limited to a value that does not significantly larger than Vdd. A key advantage of the topology shown in FIG. 5 is that the gate voltages of switches are operating in smaller voltage domains. For example, as shown in FIG. 5, the gate voltages of P3 and N3 operate in a voltage domain between V3 and V2; the gate voltage of P2 and N2 operate in a voltage domain between V2 and V1; and the gate voltage of P1 and N1 operate in a voltage domain between V1 and V0. Moreover, the topology illustrated in FIG. 5 may be generalized to implement an N to M voltage conversion shown in FIG. 7, where N and M are integers.
Further disclosed herein a method to regulate the output voltage by varying the clock frequency. As indicated Eq. (1) above, the output current increases when V1 decreases. Conversely, the output current increases when f increases. Therefore, for a given relation of load current versus voltage, V1 regulation can be realized by a feedback loop control on the switching frequency f.
An exemplary system-level implementation is illustrated in FIG. 6. The system 600 has power grids for V2 (e.g., input voltage), V1 (e.g., output voltage or Vdd for microprocessor cores), and V0 (e.g., ground plane). A clock generator 602 is implemented with frequencies controlled by a bias voltage. A clock divider and clock phase generator 604 receives an input clock signal from the clock generator 602, and generates output clock signals with multiple phases. In the exemplary embodiment depicted, four phases are generated in FIG. 6, which are designated as φ1, φ2, φ3, and φ4. Assuming these original clock signals from the clock generator and clock dividers swings between V1 and ground, then level shifters 606 are used to generate clock signals operating between V1 and V2, together with matching delays for the original clock signals operating between the ground and V1. These regenerated clock signals (for example, the signals φp2-1, φn2-1, φp1-0, φn1-0 for phase φ1) are then coupled to the voltage converters 608, such as illustrated in FIG. 2 described above. Again, this exemplary system may be extended for 3-to-1 voltage conversion, or more generally, N-to-M voltage conversions where the power grids for intermediate voltage levels can be used. It is also extendable to as many clock phases as needed.
FIG. 7 is a schematic diagram illustrating an overall general circuit topology of the disclosed voltage converter system. This system includes N+1 voltage levels, denoted as V0, V1, V2, . . . , VN, wherein V0 represents the lowest voltage level and VN represents the highest voltage level. V0 can also be referred to as a reference level, where all other voltage levels have a nominal value of integer ratio to V0. The nominal value of the voltage levels may be expressed as follows:

V1−V0=(V1−V0)

V2−V0=2(V1−V0)

V3−V0=3(V1−V0)

. . .

VM−V0=M(V1−V0)

. . .

VN−V0=N(V1−V0)  Eq. (4)

As shown in FIG. 7, for a system of N+1 voltage levels, there are a total of N−1 capacitors, denoted as C1, C2, . . . and CN-1. There are also N pairs of PMOS and NMOS switches, operated on two non-overlap clock phases, denoted by φp and φn. In the “N-cycle”, the lower switch (NFET) of each switch pair is on while the upper switch (PFET) is off. Therefore, the lower electrode of the capacitor C1 is connected to V0 while the lower electrode of the capacitor C2 is connected to V1, and so on, such that the lower electrode of the capacitor CN-1 is connected to VN-2, and the upper electrode of the capacitor CN-1 is connected to VN-1. In the “P-cycle”, the upper switch (PFET) of each switch pair is on while the lower switch (NFET) is off. Therefore, the lower electrode of the capacitor C1 is connected to V1, the lower electrode of the capacitor C2 is connected to V2, and so on, such that the lower electrode of the capacitor CN-1 is connected to VN-1, and the upper electrode of the capacitor CN-1 is connected to VN. Again, since φp and φn are non-overlapping clock signals, all switches are off during the phase that both φp and φn are off. Excluding the energy needed to operate the switches, this system has an equilibrium position at the nominal voltage levels given by Eq. (4). Away from the equilibrium, electrical charge will flow out from the system on the voltage levels that are lower than the nominal values, and electrical charge will flow into the system on the voltage levels that are higher than the nominal values. This is the physical basis for the voltage conversion.
FIG. 8 is a schematic diagram of an exemplary multi-level voltage converter system 800 using a total of k switched capacitor voltage converters of FIG. 7. These k switched capacitor voltage converters are operated on a set of clock phases, with the total number of different phases in the set to be less than or equal to the number N. There are N+1 internal voltage planes, as denoted by V1, V1, . . . , VN. All or a subset of the internal voltage planes may be externally connected with respect to the converter circuit. In the system 800 depicted in FIG. 8, V0, VM, and VN are input and output voltages. As will be appreciated, the system may be used for up-conversion, down-conversion, or a combination of both, as well as for multiple input and multiple output voltage levels. FIGS. 9 through 11 depict some exemplary conversion implementations in this regard.
For example, FIG. 9 is a schematic diagram of an exemplary N-to-M voltage down-converter configuration using the multi-phase voltage conversion system 800 of FIG. 8. In this example, V0 is the reference level, VN is the input voltage level and VM is the output voltage level. By way of comparison, FIG. 10 is a schematic diagram of an exemplary M-to-N voltage up-converter system using the multi-phase voltage conversion system 800 of FIG. 8. Here, V0 is the reference level, VM is the input voltage level and VN is the output voltage level. FIG. 11 is a schematic diagram of an exemplary multi-level voltage conversion configuration using the system of FIG. 8. Again, V0 is the reference level, with a plurality of input voltages designated as Vx1,Vx2, etc., and a plurality of output voltages designated as Vy1,Vy2, etc.
Finally, FIG. 12 is a schematic of an exemplary switched capacitor 1200 implemented using deep trench capacitor arrays. It is made available using high density embedded DRAM technology. The capacitor 1200 includes capacitive deep trench arrays 1202 formed in silicon-on-insulator (SOI) embedded DRAM technology, where the deep trench is formed through the SOI and buried oxide (BOX) layers and into the silicon substrate. After the oxidation (which forms the insulating layer for the capacitor), the trench is filled with polysilicon. The parasitic capacitance of deep trench structure (comes from the boundary of p-substrate and n-dopant diffusion area) is very low, estimated to be less than 0.1% of the total capacitance. This leads to high energy efficiency, as the loss due to the parasitic capacitance is reduced. Such capacitor arrays also provide extremely high density and granularity, to fit into many applications. As an example, a load current of 50 A (amperes) for a high performance microprocessor can be supplied by 10,000 voltage converters each generating 5 milliamps (mA) of output current with a 100 picofarad (pF) switched capacitor. The 100 pF capacitor may be formed using 5000 deep trenches, each contributing about 20 fF of capacitance. The 10,000 voltage converters could operate on multiple (for example, 8 or 16) phases to provide a smooth total current output.
The disclosed system is fully functional with any forms of capacitors. In particular, an alternative technology for high density on-chip capacitors is using the stacked capacitor method. The stacked capacitor method is developed in DRAM technology as alternative to the deep trench capacitor, wherein the capacitor is stacked above the surface of silicon rather than trenching it down into the silicon.
While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.

## Claims

1. An on-chip voltage conversion apparatus for integrated circuits, comprising:
a first capacitor;
a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain;
a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain;
a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and
a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain;
wherein actuating signals for the first NFET device and first PFET device are decoupled from one another, and actuating signals for the second NFET device and second PFET device are decoupled from one another;
one or more additional capacitors in series with the first capacitor; and
one or more pairs of additional NFET and PFET devices associated with one or more additional voltage domains for each one or more additional capacitors so as to define a voltage converter that nominally converts a voltage level of N voltage units to a voltage level of M voltage units and vice versa;
wherein N represents the total number of pairs of NFET and PFET devices, N−1 represents the total number of capacitors, and 1≦M≦N−1.

2. The apparatus of claim 1, wherein the pairs of NFET and PFET devices in each voltage domain are controlled in a manner so as to charge and discharge the associated capacitor between a first magnitude and a second magnitude, wherein for the Xth capacitor of the apparatus, the first magnitude corresponds to the voltage difference across the Xth voltage domain and the second magnitude corresponds to the voltage difference across the (X+1)th voltage domain.

3. The apparatus of claim 2, wherein the NFET and PFET devices are operated in a manner so as to prevent simultaneous conduction of any NFET device and any PFET device.

4. The apparatus of claim 1, wherein for a down-converter mode of operation, the converter serves an N-to-M down-converter.

5. The apparatus of claim 1, wherein for an up-converter mode of operation, the converter serves an M-to-N up-converter.

6. The apparatus of claim 1, wherein a first plurality of voltage levels are converted to a second plurality of voltage levels.

7. An on-chip voltage conversion system for integrated circuits, comprising:
a clock source having a plurality of clock phases;
a plurality of actuating signals corresponding to one of a plurality of phases; and
a plurality of voltage converters controlled by the actuating signals, with each voltage converter comprising:
a first capacitor;
a first pair of NFET and PFET devices associated with a first voltage domain, with a first NFET of the first pair configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of the first voltage domain, and a first PFET of the first pair configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain;
a second pair of NFET and PFET devices associated with a second voltage domain, with a second NFET of the second pair configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of the second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain, and a second PFET of the second voltage domain configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain, wherein actuating signals for the first NFET device and first PFET device are decoupled from one another, and actuating signals for the second NFET device and second PFET device are decoupled from one another; and
one or more additional capacitors in series with the first capacitor;
one or more additional pairs of NFET and PFET devices associated with one or more additional voltage domains for each one or more additional capacitors so as to define a multiple level converter that nominally converts a voltage level of N voltage units to a voltage level of M voltage units and vice versa;
wherein N represents the total number of pairs of switching devices, N−1 represents the total number of capacitors, and 1≦M≦N−1.

8. The system of claim 7, wherein actuating signals to the pairs of NFET and PFET devices in each voltage domain are applied so as to charge and discharge the associated capacitor between a first magnitude and a second magnitude, wherein for the Xth capacitor of the apparatus, the first magnitude corresponds to the voltage difference across the Xth voltage domain and the second magnitude corresponds to the voltage difference across the (X+1)th voltage domain.

9. The system of claim 8, wherein the actuating signals to the NFET and PFET devices in each pair are applied in a manner so as to prevent simultaneous conduction of the NFET and PFET devices.