# Patent

## Title
SIMD code generation for loops with mixed data lengths

## Abstract

Generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop operates on datatypes having different lengths, is disclosed. Further, a preferred embodiment of the present invention includes a novel technique to efficiently realign or shift arbitrary streams to an arbitrary offset, regardless whether the alignments or offsets are known at the compile time or not. This technique enables the application of advanced alignment optimizations to runtime alignment. Length conversion operations, for packing and unpacking data values, are included in the alignment handling framework. These operations are formally defined in terms of standard SIMD instructions that are readily available on various SIMD platforms. This allows sequential loop code operating on datatypes of disparate length to be transformed (“simdized”) into optimized SIMD code through a fully automated process.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation application of U.S. Non-Provisional patent application Ser. No. 10/919,131, entitled “SIMD Code Generation for Loops with Mixed Data Lengths,” filed on Aug. 16, 2004, and issued as U.S. Pat. No. 7,475,392 on Jan. 6, 2009, which is a continuation-in-part of commonly assigned, U.S. Non-Provisional patent application Ser. No. 10/862,483, entitled “System And Method For Efficient Data Reorganization To Satisfy Data Alignment Constraints,” filed on Jun. 7, 2004, and issued as U.S. Pat. No. 7,386,842 on Jun. 10, 2008.


BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to a system and method for vectorizing loop code for execution on Single Instruction Multiple Datapath (SIMD) architectures that impose strict alignment constraints on the data.
2. Description of the Related Art
Multimedia extensions (MMEs) have become one of the most popular additions to general-purpose microprocessors. Existing multimedia extensions can be characterized as Single Instruction Multiple Datapath (SIMD) units that support packed fixed-length vectors. The traditional programming model for multimedia extensions has been explicit vector programming using either (in-line) assembly or intrinsic functions embedded in a high-level programming language. Explicit vector programming is time-consuming and error-prone. A promising alternative is to exploit vectorization technology to automatically generate SIMD codes from programs written in standard high-level languages.
Although vectorization has been studied extensively for traditional vector processors decades ago, vectorization for SIMD architectures has raised new issues due to several fundamental differences between the two architectures. See, e.g., Ren, Gang, et al. A Preliminary Study on the Vectorization of Multimedia Applications. In 16th International Workshop of Languages and Compilers for Parallel Computing. October 2003. To distinguish between the two types of vectorization, we refer to the latter as simdization. One such fundamental difference comes from the memory unit. The memory unit of a typical SIMD processor bears more resemblance to that of a wide scalar processor than to that of a traditional vector processor. In the VMX instruction set found on certain POWERPC microprocessors (produced by International Business Machines Corporation and Motorola, Inc.), for example, a load instruction loads 16-byte contiguous memory from 16-byte aligned memory, ignoring the last 4 bits of the memory address in the instruction. The same applies to store instructions. In this paper, architectures with alignment constraints refer to machines that support only loads and stores of register-length aligned memory.
There has been a recent spike of interest in compiler techniques to automatically extract SIMD parallelism from programs. See, e.g., LARSEN, Samuel, et al. Exploiting Superword Level Parallelism with Multimedia Instruction Sets. In Proceedings of SIGPLAN Conference on Programming Language Design and Implementation. June 2000, pp. 145-156; BIK, Aart, et al. Automatic Intra-Register Vectorization for the Intel Architecture. Int. J. of Parallel Programming. April 2002, vol. 30, no. 2, pp. 65-98; KRALL, Andreas, et al. Compilation Techniques for Multimedia Processors. Int. J. of Parallel Programming. August 2000, vol. 28, no. 4, pp. 347-361; SRERAMAN, N., et al. A Vectorizing Compiler for Multimedia Extensions. Int. J. of Parallel Programming, August 2000, vol. 28, no. 4, pp. 363-400; LEE, Corinna G., et al. Simple Vector Microprocessors for Multimedia Applications. In Proceedings of International Symposium on Microarchitecture. 1998, pp. 25-36; and NAISHLOS, Dorit, et al. Vectorizing for a SIMD DSP Architecture. In Proceedings of International Conference on Compilers, Architectures, and Synthesis for Embedded Systems. October 2003, pp. 2-11. This upsurge was driven by the increasing prevalence of SIMD architectures in multimedia processors. Two principal techniques have been used, the traditional loop-based vectorization pioneered for vector supercomputers (e.g., ALLEN, John Randal, et al. Automatic Translation of Fortran Programs to Vector Form. ACM Transactions on Programming Languages and Systems. October 1987, vol. 4, pp. 491-542; and ZIMA, Hans, et al. Supercompilers for Parallel and Vector Computers. Reading, Mass.: Addison-Wesley/ACM Press, 1990. ISBN 0201175606) and the unroll-and-pack approach first proposed by Larsen and Amarasinghe in LARSEN, Samuel, et al. Exploiting Superword Level Parallelism with Multimedia Instruction Sets. In Proceedings of SIGPLAN Conference on Programming Language Design and Implementation. June 2000, pp. 145-156.
The alignment constraints of SIMD memory units present a great challenge to automatic simdization. Consider the code fragment in FIG. 1 where integer arrays a, b, and c are aligned (An aligned reference means that the desired data reside at an address that is a multiple of the vector register size). Although this loop is easily vectorizable for traditional vector processors, it is non-trivial to simdize it for SIMD architectures with alignment constraints. Hence, the most commonly used policy today is to simdize a loop only if all memory references in the loop are aligned.
A very extensive discussion of alignment considerations is provided by LARSON, Samuel, et al. Increasing and Detecting Memory Address Congruence. In Proceedings of 11th International Conference on Parallel Architectures and Compilation Techniques. September 2002. However, LARSON is concerned with the detection of memory alignments and with techniques to increase the number of aligned references in a loop, whereas our work focuses on generating optimized SIMD codes in the presence of misaligned references. The two approaches are complementary. The use of loop peeling to align accesses was discussed in LARSON as well as in the aforementioned BIK reference. The loop peeling scheme is equivalent to the eager-shift policy with the restriction that all memory references in the loop must have the same misalignment. Even under this condition, our scheme has the advantage of generating simdized prologue and epilogue, which is the by-product of peeling from the simdized loop.
Direct code generation for misaligned references have been discussed by several prior works. The vectorization of misaligned loads and stores using the VIS instruction set is described in CHEONG, Gerald, et al. An Optimizer for Multimedia Instruction Sets. In Second SUIF Compiler Workshop. August 1997. The aforementioned BIK, et al. reference described a specific code sequence of aligned loads and shuffle to load memory references that cross cache line boundaries, which is implemented in Intel's compiler for SSE2. However, their method is not discussed in the context of general misalignment handling.
The VAST compiler, a commercial product by Crescent Bay Software, has some limited ability to simdize loops with multiple misaligned references, unknown loop bounds, and runtime alignments, and exploit the reuse when aligning a steam of contiguous memory. The VAST compiler, however, produces less than optimal simdized code, as its highly generalized scheme for handling mis-alignment can produce additional compilation overhead.
An interesting simdization scheme using indirect register accesses is discussed in the aforementioned NAISHLOS, et al. reference. However, their method is specific to the eLite processor, which supports more advanced vector operations (such as gather and scatter operations) than are available on typical MME processors. In SHIN, Jaewook, et al. Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures. In Proceedings of International Conference on Parallel Architectures and Compilation Techniques. September 2002, register packing and shifting instructions were used to exploit temporal and spatial reuse in vector registers. However, their work does not address alignment handling.
Another work that is of note, but which is in the area of compiling for distributed memory systems as opposed to SIMD architectures, is CHATTERJEE, Siddhartha, et al. Modeling Data-Parallel Programs with the Alignment-Distribution Graph. J. of Programming Languages. 1994, vol. 2, no. 3, pp. 227-258.
In U.S. patent application Ser. No. 10/862,483 (hereinafter EICHENBERGER) a generic alignment handling framework that simdizes loops with arbitrary misalignments is disclosed. According to this framework, contiguous data accessed in a loop is viewed as streams, and aligning data to satisfy alignment constraints is modeled as shifting streams. Consider, for example, the (C-language) loop in FIG. 1 where the base of arrays a, b, and c are aligned (An aligned reference means that the desired data reside at an address that is a multiple of the vector register size). The grey boxes in FIG. 2A highlight the three memory streams represented by references a[i+2], b[i+1], and c[i+3] over the lifetime of the loop. Focusing on the first value of each stream, i.e., data accessed by the i=0 loop iteration, one can see from FIG. 2A that the a[2], b[1], and c[3] values are all misaligned with respect to each others. A valid simdization requires streams involved in a computation to have matching alignments. This condition can be satisfied by realigning misaligned streams using stream shift operations. FIG. 2B shows a minimum cost simdization of the loop in FIG. 1 that involves two shifts that respectively shifts the b[i+1] and c[i+3] memory streams to the alignment of the a[i+2] memory stream. The three streams have then the same alignment, satisfying the alignment constraints of the vadd and vstore operations.
Although runtime alignment is handled in the framework of EICHENBERGER, it is not as efficient as the handling of compile time alignment. Due to code generation issues, stream shifts must be implemented as either stream shift left or stream shift right. In the presence of runtime alignment, the relative alignment of 2 streams is clearly unknown at compile time. In such cases, the approach taken in EICHENBERGER is to shift left each input memory stream to the leftmost position (register offset 0), perform the computation, and shift right the result to the store memory alignment. For example, in the loop in FIG. 1, this runtime shift policy is equivalent to the simdization shown in FIG. 2C where 3 shifts are required instead of 2, increasing the alignment overhead by 50%.
In addition, existing technologies fail to adequately address the issue of data-length conversion in the generation of vectorized code for SIMD processors, where the source or destination data streams are misaligned with respect to each other. For example, one may write a loop that adds a vector of 16-bit “short” integers to a vector of 32-bit “long” integers to obtain a result that is a vector of 32-bit integer values (e.g., the case where b is an array of short integers and a and c are arrays of long integers in the loop of FIG. 1).
Thus, what is needed is a method for automatically simdizing sequential program code into parallelized SIMD code in the presence of vector misalignments that are undefined at compile-time and where a conversion between datatypes of different lengths is needed. The present invention provides a solution to these and other problems, and offers other advantages over previous solutions.
SUMMARY
A preferred embodiment of the present invention provides for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop operates on datatypes having different lengths. A preferred embodiment of the present invention includes a novel technique to efficiently realign or shift arbitrary streams to an arbitrary offset, regardless whether the alignments or offsets are known at the compile time or not. This technique enables the application of advanced alignment optimizations to runtime alignment. Length conversion operations, for packing and unpacking data values, are included in the alignment handling framework. These operations are formally defined in terms of standard SIMD instructions that are readily available on various SIMD platforms. This allows sequential loop code operating on datatypes of disparate length to be transformed (“simdized”) into optimized SIMD code through a fully automated process.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations, and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
FIG. 1 is a diagram of a loop in a C-like programming language that may be simdized/vectorized in accordance with a preferred embodiment of the present invention;
FIG. 2A is a diagram depicting a memory-misaligned set of data streams involved in a loop;
FIG. 2B is a data reorganization graph representing a set of operations performed in simdized loop code generated according to the teachings of the incorporated EICHENBERGER reference using an eager-shift realignment policy;
FIG. 2C is a data reorganization graph representing a set of operations performed in simdized loop code generated according to the teachings of the incorporated EICHENBERGER reference using an zero-shift realignment policy;
FIG. 3A is a diagram depicting a stream shift operation according to the manner described in the incorporated EICHENBERGER reference, wherein the stream shift operation shifts a data stream to the right;
FIG. 3B is a diagram depicting a stream shift operation according to the manner described in the incorporated EICHENBERGER reference, wherein the stream shift operation shifts a data stream to the left;
FIG. 3C is a diagram depicting a stream shift operation corresponding to the shift depicted in FIG. 3A, but in accordance with a preferred embodiment of the present invention, in which prepended values are utilized to ensure that the resulting generated code performs a left shift operation;
FIG. 3D is a diagram depicting a stream shift operation corresponding to the shift depicted in FIG. 3B, but in accordance with a preferred embodiment of the present invention, in which prepended values are utilized to ensure that the resulting generated code performs a left shift operation;
FIG. 4 is a diagram depicting an algorithm in which a data reorganization graph is recursively traversed and all stream shift operations are normalized such that the resulting generated code performs only left shift operations;
FIG. 5 is a diagram depicting a simdized loop in accordance with a preferred embodiment of the present invention, in which a type conversion between data types of different lengths is performed;
FIG. 6 is a flowchart representation of a process of vectorizing/simdizing a loop in accordance with a preferred embodiment of the present invention; and
FIG. 7 is a block diagram of a computing device capable of implementing the present invention.



DETAILED DESCRIPTION
1. Preliminary Matters
In this section, an overview of the alignment handling framework of the incorporated EICHENBERGER application is provided, some of the key concepts that a preferred embodiment of the present invention is built upon are highlighted.
1.1. Alignment Constraints of a Valid Simdization
A valid vectorization for traditional vector units is only constrained by dependencies. This is no longer sufficient when simdizing for architectures with alignment constraints. Consider the loop a[i+2]=b[i+1]+c[i+3] in FIG. 1. Since there is no loop-carried dependence, a straightforward vectorization simply involves replacing scalar operations by corresponding vector operations. The generated code, however, will execute incorrectly if the hardware has alignment constraints. For example, in the VMX instruction set, due to the address truncation effect, a vector load from address of b[1] (i.e., vload b[1]) actually loads b[0] . . . b[3], instead of the desired b[1] . . . b[4]. Similarly, vload c[3] loads c[0] . . . c[3], instead of the desired c[3] . . . c[6]. Adding the two vectors yields b[0]+c[0] . . . b[3]+c[3], which is clearly not the result specified by the original b[i+1]+c[i+3] computation. Therefore, for hardware platforms with strict alignment requirements, a valid simdization must satisfy additional alignment constraints:
When simdizing a store operation, the byte offset of the data to be stored in the vector register must match the memory alignment of the original store address.
When simdizing a binary operation, data involved in the original computation must reside at the same byte offset in their respective vector registers.
1.2. Stream and Stream Offset
The byte offset of data in a vector register is the key to expressing alignment constraints of a valid simdization. To capture the byte offset property within a loop, the abstraction of stream is introduced. There are two types of streams, a memory stream that represents the sequence of contiguous memory locations accessed by a memory reference over the lifetime of a loop, and a register stream that represents the sequence of consecutive registers produced by a SIMD operation over the lifetime of a loop.
Vector operations in a loop can be viewed as operations over streams. A vector load consumes a memory stream and produces a register stream. As data is read from memory in discrete chunks of 16 bytes, extra values may be introduced at the beginning and the end of a register stream. To indicate the boundaries of a register stream, the concept of a stream offset is introduced. The stream offset is defined as the byte offset of the first desired value in the first register of a register stream. Note that the stream offset of a register stream generated by of a vector load is dictated by the alignment of the input memory stream. The alignment of a memory stream is the alignment of the first element of the memory stream, namely the byte memory address of the first element modulo the byte width of the SIMD unit. For example, in FIG. 2B, the stream offset of vload b[i+1] (vload operation 210) is 4. Conversely, a vector store consumes a register stream and produces a memory stream where the offset of the input register stream must match the alignment of the memory stream. Finally, all other vector operations consume register streams with matching offsets and produce a register stream with the same offset.
1.3. Stream Shift and Alignment Policies
A valid simdization requires the offsets of register streams involved in the computation to satisfy alignment constraints. In the presence of misalignments, this property is only achievable by judiciously inserting data reorganization operations to enforce the desired stream offset. The stream shift operation, vshiftstream(S, c), is introduced for this purpose. vshiftstream(S, c) shifts all values of a register stream S across consecutive registers of the stream to an offset of c. Note that, once the first element of a stream satisfies the alignment constraints, the rest of the stream also satisfies the alignment constraints. There are several policies to generate a valid simdization, each of which is discussed in greater detail in the incorporated EICHENBERGER application.
Zero-Shift Policy This policy shifts each misaligned load stream to 0, and shifts the register stream to be stored to the alignment of the store address. The simdization in FIG. 2C uses the zero-shift policy. It is the least optimized as it inserts a stream shift for each misaligned memory stream. Left shift operation 218 shifts the “b” stream left by one value (4 bytes) to offset 0, and left shift operation 220 shifts the “c” stream left by three values (12 bytes) to offset 0. After addition operation 221, the result is shifted right two values (8 bytes) by right shift operation 222 from offset 0 to offset 8, for storage (store operation 223).
Eager-Shift Policy This policy shifts each load directly to the alignment of the store. The simdization in FIG. 2B uses this policy. In a preferred embodiment, eager-shift is the default policy for compile time alignment. Right shift operation 206 shifts the “b” stream right 4 bytes to place the “b” stream in at the proper alignment for storing the result (in “a”). Likewise, left shift operation 208 shifts the “c” stream left 4 bytes to place the “c” stream in at the proper alignment for storing the result (in “a”). The result of addition operation 214 can then be directly stored into memory for array “a” (store operation 216).
Lazy-Shift Policy This policy is based on the eager-shift policy but pushes the shift as close to the root of the expression tree as possible. Consider the example of a[i+3]=b[i+1]+c[i+1]. This policy exploits the fact that b[i+1] and c[i+1] are relatively aligned, and thus can be safely operated on as is. Therefore, only the result of the add needs to be shifted so as to match the alignment of the store.
Dominant-Shift Policy This policy further reduces the number of stream shifts by shifting register streams to the most dominant stream offset in an expression tree.
2. Efficient Runtime Alignment Handling
In this section, an intuitive explanation of the approach applied in a preferred embodiment of the present invention is provided in Section 2.1. Then, the overall simdization framework in described in Section 2.2. Section 2.3 describes an algorithm to transform an arbitrary stream shift to a shift left, and the correctness of this algorithm is proved in Section 2.4.
Note that all examples in this section have compile-time alignments, for simplicity. It will be demonstrated, however, that the code generation algorithm employed in a preferred embodiment of the present invention never uses specific properties of their values. Thus, this algorithm is suitable for runtime alignment as well.
2.1. An Intuitive Example
Consider the initial example of a[i+2]=b[i+1]+c[i+3]. Given the data layout in FIG. 2A, memory streams a[i+2] (data stream 204), b[i+1] (data stream 200), and c[i+3] (data stream 202) have three distinct alignments, 8, 4, and, 12, respectively. Using the eager-shift policy, a minimum cost simdization of the loop involves two shifts, i.e., a shift stream of vload b[i+1] from its original offset of 4 to 8, as depicted in FIG. 3A, and a shift stream of vload c[i+3] from offset 12 to 8, as shown in FIG. 3B.
While this approach works well for stream offsets known at compile time, it does not work for runtime alignment for the following reason. Generally, shifting a stream from offset x to offset y corresponds to a right shift when x≦y and a left shift when x≧y. When generating codes for a right shift (as in FIG. 3A), one must combine values from the current register (e.g., vload b[1] operation 300) with values from the previous register (e.g., vload b[−3] operation 302). Contrasting this to the algorithm for a left shift (as in FIG. 3B), one must combine the values from the current register (e.g., vload c[3] operation 304) with values from the next register (e.g., vload c[7] operation 306). Thus, when a stream offset is known only at runtime, the compiler cannot determine whether to generate codes that shift a stream left or right.
A key insight is to realize that this issue occurs because one is focusing on the first value of a stream. Consider, then, the case in which one focuses instead on a value before the first element, specifically on the value that is at offset zero of the register containing the first element after the shifting. For example, in FIG. 3A, the first value of the stream is b[1] (value 307), so b[−1] (value 308) is the value that will be at offset zero after shifting the stream to offset 8. Similarly in FIG. 3B, the first value of the stream is c[3] (value 312), so c[1] (value 314) will land at offset zero in the shifted register stream. It should be noted that the new values can be mechanically derived from the original first values. They are simply the values that are 8 bytes (i.e., precisely the destination offset of the stream shift) before the original first values.
Suppose one focuses, now, on two new streams that are constructed by prepending a few values to the original b[i+1] and c[i+3] streams so that the new streams start at, respectively, b[−1] (value 316) and c[1] (value 318). These new streams are shown in FIGS. 3C and 3D with the prepended values in light grey. Using the same definition of the stream offset as before, the offsets of the new streams are 12 and 4 bytes, respectively.
By definition, the newly prepended streams will be shifted to offset zero. The shifted new streams yield the same sequence of registers as that produced by shifting the original stream (highlighted with dark grey box with light grey circle), as confirmed by visual inspection of the outcome of FIGS. 3A and 3C as well as FIGS. 3B and 3D. This holds because the initial values of the new streams were selected precisely as the ones that will land at offset zero in the shifted version of the original streams. Since shifting any stream to offset zero is a left shift, this prepending and shifting operation effectively transforms an arbitrary stream shift into a shift left, as shown in FIGS. 3C and 3D.
2.2. Overview of the Simdization Framework
Now an overview of the overall simdization framework that the stream shift algorithm is based upon is provided. The framework that contains three phases:
Data reorganization phase. This phase takes, as input, an expression tree and generate a tree with generic SIMD operations as well as stream shifts that are inserted to satisfy the alignment constraints of the simdized operations. The augmented expression tree is called a data reorganization graph, such as the ones shown in FIGS. 2B and 2C. Different shift placement policies can be applied to minimize the number of shifts generated.
Shift normalization phase. This phase transforms all stream shifts in a data reorganization graph to stream left shifts. The output is still a data reorganization graph.
Code generation phase. This phase takes a data reorganization graph as input and maps generic SIMD operations and left shift operations to machine instructions. Specifically, the algorithm maps vshiftleft to native permutation instructions that “shifts” across a pair of vector registers, e.g., vec_perm on VMX. This phase also addresses issues such as resulting loads when shifting a stream, handling unknown loop counts and multiple statements, and efficient prologue/epilogue generation.
Of primary importance to a preferred embodiment of the present invention is the shift normalization phase that converts arbitrary stream shifts to stream shift left. The other two phases function essentially as described in the incorporated EICHENBERGER reference. Therefore, the rest of the section will focus on the shift normalization algorithm.
2.3. Transforming a Stream Shift to Shift Left
As illustrated in Section 2.1, an arbitrary stream shift, vshiftstream(S, x), can be converted to a stream shift left by shifting a derived stream, one that starts exactly x bytes before the first value of S, to offset zero. For the ease of description, introduce two operators are introduced: Prepend(S, x), which prepends x bytes at the beginning of stream S, and Skip(S, x), which skips the first x bytes of stream S. Using these two new operators, the above statement can be restated as,

vshiftstream(S,y)Skip(vshiftstream(Prepend(S,y),0),y).  (1)

Consider now the Skip operation in Equation (1). In this equation, one always skips y<V bytes from a register stream with offset zero. (By definition, vshiftstream(Prepend(S,y),0) has an offset of zero.) Since a register stream is a sequence of V byte wide registers, skipping strictly less than V bytes from offset 0 never skips a whole register and thus has no effect on which registers to produce in a register stream. It only serves for bookkeeping purposes to maintain that the transformed stream has the same offset and length properties as the original stream. Thus, it can be safely ignored during the code generation phase.
For the Prepend operation in Equation (1), there are two cases to consider. When prepending to a memory stream, one simply subtracts x bytes from the memory address. Directly prepending to a register stream is not feasible. However, one can propagate Prepend operations to the leaves of an expression tree until memory streams are reached. Below we describe how to perform Prepend for each type of nodes in a data reorganization graph.
VLOAD(addr(i)) This node represents a vector load from a stride-one accesses addr(i). Therefore,

Prepend(VLOAD(addr(i)),x)VLOAD(addr(i)−x)  (2)

VOP(src1, . . . , srcn) This node represents a generic operation that takes as input register streams associated with nodes src1, . . . , srcn and produces one output register stream. (Generic operations represent all vectorizable operations except for the ones that shuffle values inside vector registers or the ones that convert data of different data sizes.) Thus,

Prepend(VOP(src1, . . . , srcn),x)VOP(Prepend(src1,x), . . . , Prepend(srcn,x))  (3)

VSHIFTSTREAM(src,to) This node shifts the register stream associated with the input node src to offset to, producing a register stream with a stream offset to. Thus,

Prepend(VSHIFTSTREAM(src,to),x)VSHIFTSTREAM(Prepend(src,x),(to−x)mod V)  (4)

In FIG. 4, pseudocode for a shift normalization routine is depicted, where the function NormalizeStream recursively traverses the tree from the root of a data reorganization graph until all vshiftstream are normalized. Through an application of the routine depicted in FIG. 4, a data reorganization graph of the type described in EICHENBERGER may be transformed into a normalized graph in which all stream shifts have been replaced with left shifts. In this way, code may be generated in which the actual degree of misalignment between the data streams is not known until runtime.
2.4. Proof of Correctness
In this section, the correctness of two important equations in Section 2.3 is proved. The first theorem demonstrates the validity of sinking a prepend past a stream shift, i.e., Equation (4).
Theorem 1. The following equality holds for an arbitrary stream S and V-byte wide SIMD unit:

Prepend(VSHIFTSTREAM(S,to),x)≡VSHIFTSTREAM((S,x),(to−x)mod V)

Proof. As a preliminary step, the properties of Prepend(S,x) are first defined as functions of those of S. As x bytes are added at the head of the stream, the offset and length of the prepended stream becomes (Offset(S)−x)mod V and Length(S)+x, respectively. Similarly, the offset and length properties of VSHIFTSTREAM(S,to) becomes to and Length(S), respectively.
The equality of the two streams is now proven by demonstrating that they derive from the same register stream and have the same offset and length properties.




  
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Using Theorem 1, the validity of transforming arbitrary stream shift to stream shift left, i.e., Equation (1), can be demonstrated.
Theorem 2. A register stream S with arbitrary offset can be shifted to an arbitrary target offset to by (1) prepending to bytes to S, (2) shifting the resulting stream to offset zero, and (3) skipping the first to values of the resulting stream.
Proof. Since Skip is a reciprocal of Prepend, the following S1≡Skip(Prepend(S1,x),x) holds for any stream S1 Let S1 be VSHIFTSTREAM(S,to), it can be stated that

VSHIFTSTREAM(S,to)≡Skip(Prepend(VSHIFTSTREAM(S,to),to),to).

Using Theorem 1 to permute Prepend and VSHIFTSTREAM, one obtains,

VSHIFTSTREAM(S,to)≡Skip(VSHIFTSTREAM(Prepend(S,to),0)to).

3. Alignment Handling for Length Conversion
For the purpose of describing a preferred embodiment of the present invention, the term “length conversion operation” is defined as any operation that converts a stream into a stream of a different length. The most common length conversion operations are type conversions between data of different sizes. When processing typecasts (as in the C programming language, which supports long and short “int” types, for example), the primary focus is on the data reorganization aspect of type conversion. Further data processing beyond data reorganization, such as sign extensions or floating point conversions, for example, can be handled by additional non-length-conversion vector operations.
Two types of length conversion operations are defined.
VPACK(S,f). This operation packs a stream S by a factor f, e.g., a conversion from 4 to 2 byte data types is a vpack with a factor of 2. The length of the packed stream is divided by f and its offset is represented as,

Offset(VPACK(S,f))=Offset(S)/f.  (5)

VUNPACK(S,f). This operation unpacks stream S by a factor f, e.g., conversion from 4 to 8 byte data types is a vunpack with a factor of 2. The of the unpacked stream is multiplied by f and its offset is,

Offset(VUNPACK(S,f))=Offset(S)*f.  (6)

Length conversions have a significant impact on the simdization framework. The rest of the section explains how to incorporate them into the three phases of the framework.
3.1. Data Reorganization Phase
The scaling effect of length conversion on stream offsets affects all but the least optimized Zero-shift alignment policy. The Zero-shift policy is not affected by length conversions because the scaling impact on an offset of value 0 still results in an offset of 0. As defined in Section 1.3 and the incorporated EICHENBERGER application (in the absence of length conversions), the Eager-shift policy shifts each misaligned load stream directly to the alignment of the store. In the presence of length conversions, the store alignment is still propagated to load nodes, but its alignment value is scaled up/down by the packing/unpacking factors when traversing length conversion nodes. (Since stream offsets are propagated from the store to the loads, in the reverse direction of the data flow, Equations (5) and (6) are used in the reverse direction.) Similarly in the Lazy-shift policy, the target shift offset is also scaled when moving stream shifts past a pack/unpack node, i.e.,

VPACK(VSHIFTSTREAM(S,to),f)≡VSHIFTSTREAM(VPACK(S,f),to/f)

VUNPACK(VSHIFTSTREAM(S,to),f)≡VSHIFTSTREAM(VUNPACK(S,f),to*f)

3.2. Stream Shift Normalization Phase
In the normalization phase, the implementation of Prepend is augmented to accommodate length conversions. Consider the example of a[i+5]=(short)b[i+3] where a is an array of short and b is an array of integer. FIG. 5 illustrates the streams of a valid simdization of the loop. Using the Prepend algorithm described in Section 2.3, the original b[i+3] memory stream (dark grey) starting at b[3] (value 500) is prepended by 20 bytes so as to start at b[−2] (value 502) (prepended values being displayed in light grey). When loading b[−2] (load operation 508) from memory, the SIMD load unit truncates the address at 16 byte boundaries and loads b[−4] . . . b[−1] (values 506). However, as shown in FIG. 5, because of packing node (vpack operation 510) between the load and the stream shift, the b[−8] . . . b[−1] values (values 507) are what are needed. (For clarity, this discussion focuses on the generation of the first batch of values in FIG. 5 as an illustration of what happens in the steady state. When processing the first (or last) batch of values, it is sometime possible to eliminate some of the computations (e.g., vload b[−6] operation 550) that do not impact the final values that can legally be stored. However, no such elimination can occur in the steady state.)
The solution employed by a preferred embodiment of the present invention is to eliminate the dependence on address truncation that occurs at the memory operations by explicitly performing the desired truncation at the input stream of the stream shift operation. The solution is to further prepend the already prepended input stream of vshiftstream to the value that is at offset zero in the input register. For example, since the prepended input stream is b[−2] (values 502, 514), the stream is further prepended so that b[−8] (values 503, 516) is now the initial stream value. As can be visually seen from the figure by tracing the b[−8] value (value 516), the memory load truncation that used to occur at the load operation now occurs at the vicinity of shift stream operation 518, and is of the correct amount. The result may then be directly stored in the proper memory location for array “a” (store operation 520), with the result being truncated such that value 521 becomes the first value stored in array “a” (at value 522).
Theorem 3. In the presence of length conversion, a stream S can be shifted to an arbitrary target offset to by (1) prepending stream S by to+(Offset(S)−to)mod V bytes, (2) skipping the first (Offset(S)−to)mod V values of the resulting stream, (3) shifting the resulting stream to offset zero, and (4) skip to bytes of the shifted stream.
Note that, in Theorem 3, steps (1) and (3) produce streams of offset zero and in steps (2) and (4) the skip bytes are less than V. Therefore, the skips are only for bookkeeping purposes and can be safely ignored by code generation. Theorem 3 may be proved mathematically in a similar fashion to Theorem 2.
3.3. Code Generation Phase
During the code generation, vpack and vunpack are mapped to native permutation instructions. Some multimedia platforms even provide native packing and unpacking instructions to perform these operations, e.g., VMX. For machines where length conversions and stream shifts are both mapped to some sort of permutation instruction, the total number of extra permutation operations can be further reduced by merging together pairs of consecutive length conversion and stream shift.
4. Method Overview and Example Hardware Platform Description
FIG. 6 is a flowchart representation of a process of simdizing a loop in accordance with a preferred embodiment of the present invention. First, a naïve vectorized representation of the loop is obtained without regard for the alignment or misalignment of the various memory streams involved (block 600). Next, a data reorganization graph is generated from the naïve vectorization (block 602). Then, stream shift operations are applied to the data reorganization graph to satisfy the data-alignment constraints of the loop (block 604). The arbitrary-direction shift operation are then converted into left shifts, taking into account not only the shift operations, but also any pack or unpack operations needed to handle data-type conversion (block 606). (Note: this conversion to left shifts may be omitted if the alignment constraints are completely known at compile time or if the above-described “zero-shift” policy is used.) Finally, code is generated from the transformed data reorganization graph, including code for shift, pack, and unpack operations (block 608).
FIG. 7 illustrates information handling system 701 which is a simplified example of a computer system capable of performing the computing operations described herein. Computer system 701 includes processor 700 which is coupled to host bus 702. A level two (L2) cache memory 704 is also coupled to host bus 702. Host-to-PCI bridge 706 is coupled to main memory 708, includes cache memory and main memory control functions, and provides bus control to handle transfers among PCI bus 710, processor 700, L2 cache 704, main memory 708, and host bus 702. Main memory 708 is coupled to Host-to-PCI bridge 706 as well as host bus 702. Devices used solely by host processor(s) 700, such as LAN card 730, are coupled to PCI bus 710. Service Processor Interface and ISA Access Pass-through 712 provides an interface between PCI bus 710 and PCI bus 714. In this manner, PCI bus 714 is insulated from PCI bus 710. Devices, such as flash memory 718, are coupled to PCI bus 714. In one implementation, flash memory 718 includes BIOS code that incorporates the necessary processor executable code for a variety of low-level system functions and system boot functions.
PCI bus 714 provides an interface for a variety of devices that are shared by host processor(s) 700 and Service Processor 716 including, for example, flash memory 718. PCI-to-ISA bridge 735 provides bus control to handle transfers between PCI bus 714 and ISA bus 740, universal serial bus (USB) functionality 745, power management functionality 755, and can include other functional elements not shown, such as a real-time clock (RTC), DMA control, interrupt support, and system management bus support. Nonvolatile RAM 720 is attached to ISA Bus 740. Service Processor 716 includes JTAG and I2C buses 722 for communication with processor(s) 700 during initialization steps. JTAG/I2C buses 722 are also coupled to L2 cache 704, Host-to-PCI bridge 706, and main memory 708 providing a communications path between the processor, the Service Processor, the L2 cache, the Host-to-PCI bridge, and the main memory. Service Processor 716 also has access to system power resources for powering down information handling device 701.
Peripheral devices and input/output (I/O) devices can be attached to various interfaces (e.g., parallel interface 762, serial interface 764, keyboard interface 768, and mouse interface 770 coupled to ISA bus 740. Alternatively, many I/O devices can be accommodated by a super I/O controller (not shown) attached to ISA bus 740.
In order to attach computer system 701 to another computer system to copy files over a network, LAN card 730 is coupled to PCI bus 710. Similarly, to connect computer system 701 to an ISP to connect to the Internet using a telephone line connection, modem 775 is connected to serial port 764 and PCI-to-ISA Bridge 735.
While the computer system described in FIG. 7 is capable of executing the processes described herein, this computer system is simply one example of a computer system. Those skilled in the art will appreciate that many other computer system designs are capable of performing the processes described herein.
One of the preferred implementations of the invention is a client application, namely, a set of instructions (program code) or other functional descriptive material in a code module that may, for example, be resident in the random access memory of the computer. Until required by the computer, the set of instructions may be stored in another computer memory, e.g, computer storage media, for example, in a hard disk drive, or in a removable memory such as an optical disk (for eventual use in a CD ROM) or floppy disk (for eventual use in a floppy disk drive). In an alternative embodiment of the invention, the set of instructions may be downloaded via the Internet or other computer network. Thus, the present invention may be implemented as a computer program product for use in a computer. In addition, although the various methods described are conveniently implemented in a general purpose computer selectively activated or reconfigured by software, one of ordinary skill in the art would also recognize that such methods may be carried out in hardware, in firmware, or in more specialized apparatus constructed to perform the required method steps. Functional descriptive material is information that imparts functionality to a machine. Functional descriptive material includes, but is not limited to, computer programs, instructions, rules, facts, definitions of computable functions, objects, and data structures.
While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that, based upon the teachings herein, that changes and modifications may be made without departing from this invention and its broader aspects. Therefore, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of this invention. Furthermore, it is to be understood that the invention is solely defined by the appended claims. It will be understood by those with skill in the art that if a specific number of an introduced claim element is intended, such intent will be explicitly recited in the claim, and in the absence of such recitation no such limitation is present. For non-limiting example, as an aid to understanding, the following appended claims contain usage of the introductory phrases “at least one” and “one or more” to introduce claim elements. However, the use of such phrases should not be construed to imply that the introduction of a claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an”; the same holds true for the use in the claims of definite articles.

## Claims

1. A computer program product stored on a computer storage media, the computer storage media containing instructions for execution by a computer, which, when executed by the computer, cause the computer to implement a method comprising:
identifying a loop iterating over a plurality of continuous streams of memory in a stride-one fashion;
generating a data reorganization graph from the loop, wherein the data reorganization graph tracks stream offsets for the plurality of continuous streams of memory, wherein one of the stream offsets associated with a particular memory stream corresponds to a remainder of a byte memory address of a first element accessed by the particular memory stream divided by a byte width of a targeted Single-Instruction Multiple-Datapath unit;
selecting the particular memory stream from the plurality of continuous streams of memory, wherein the particular memory stream includes values of a datatype having a length that is different than a length of datatype contained within at least one other memory stream in the plurality of continuous streams of memory, and wherein the particular memory stream does not have the same stream offset in the data reorganization graph as with at least one other memory stream in the data reorganization graph;
in response to selecting the particular stream, interposing a data-length conversion operation into the data reorganization graph, wherein the data-length conversion operation allows alignment of the particular memory stream that has a given datatype length with at least one other stream that has a different datatype length; and
generating object code from the data reorganization graph.

2. The computer program product of claim 1, wherein the data-length conversion operation is a pack operation.

3. The computer program product of claim 1, wherein the data-length conversion operation is an unpack operation.

4. The computer program product of claim 1, wherein the method further comprises:
prepending a number of values to the particular memory stream to obtain a modified particular stream, such that the modified particular stream begins at a memory location that is at a zero memory offset.

5. The computer program product of claim 4, wherein the method further comprises:
truncating the prepended values from a computational result prior to storing the result in memory.

6. The computer program product of claim 1, wherein the method further comprises:
normalizing the data reorganization graph such that each of the one or more stream shift operations performs a left shift.

7. The computer program product of claim 6, wherein the normalizing further comprises:
prepending values to one of the one or more continuous streams of memory to convert a right shift operation into a left shift operation.

8. An information handling system comprising:
at least one processor;
one or more data storage units accessible by the at least one processor; and
functional descriptive material contained within the data storage units that, when executed by the at least one processor, directs the at least one processor to perform actions of:
identifying a loop iterating over a plurality of continuous streams of memory in a stride-one fashion;
generating a data reorganization graph from the loop, wherein the data reorganization graph tracks stream offsets for the plurality of continuous streams of memory, wherein one of the stream offsets associated with a particular memory stream corresponds to a remainder of a byte memory address of a first element accessed by the particular memory stream divided by a byte width of a targeted Single-Instruction Multiple-Datapath unit;
selecting the particular memory stream from the plurality of continuous streams of memory, wherein the particular memory stream includes values of a datatype having a length that is different than a length of datatype contained within at least one other memory stream in the plurality of continuous streams of memory, and wherein the particular memory stream does not have the same stream offset in the data reorganization graph as with at least one other memory stream in the data reorganization graph;
in response to selecting the particular stream, interposing a data-length conversion operation into the data reorganization graph, wherein the data-length conversion operation allows alignment of the particular memory stream that has a given datatype length with at least one other stream that has a different datatype length; and
generating object code from the data reorganization graph.

9. The information handling system of claim 8, wherein the data-length conversion operation is a pack operation.

10. The information handling system of claim 8, wherein the data-length conversion operation is an unpack operation.

11. The information handling system of claim 8, comprising additional functional descriptive material that, when executed by the at least one processor, directs the at least one processor to perform actions of:
prepending a number of values to the particular memory stream to obtain a modified particular stream, such that the modified particular stream begins at a memory location that is at a zero memory offset.

12. The information handling system of claim 11, comprising additional functional descriptive material that, when executed by the at least one processor, directs the at least one processor to perform actions of:
truncating the prepended values from a computational result prior to storing the result in memory.

13. The information handling system of claim 8, comprising additional functional descriptive material that, when executed by the at least one processor, directs the at least one processor to perform actions of:
normalizing the data reorganization graph such that each of the one or more stream shift operations performs a left shift.

14. The information handling system of claim 13, comprising additional functional descriptive material that, when executed by the at least one processor, directs the at least one processor to perform actions of:
prepending values to one of the one or more continuous streams of memory to convert a right shift operation into a left shift operation.