Intellectual Property Security Agreement



 Exhibit 10.2 
  
 INTELLECTUAL PROPERTY SECURITY AGREEMENT 
  
 This INTELLECTUAL PROPERTY SECURITY AGREEMENT, dated as of August 4, 2005, (the “Agreement”) between BRIDGE BANK, NATIONAL
ASSOCIATION (“Lender”) and Tripath Technology Inc., (“Grantor”) is made with reference to the Business Financing Agreement, dated as of August 4, 2005 (as amended from time to time, the “Financing Agreement”), between
Lender and Grantor. Terms defined in the Financing Agreement have the same meaning when used in this Agreement. 
  
 For good and valuable consideration, receipt of which is hereby acknowledged, Grantor hereby covenants and agrees as follows: 
  
 To secure the Obligations under the Financing Agreement, Grantor grants to Lender a security
interest in all right, title, and interest of Grantor in any of the following, whether now existing or hereafter acquired or created in any and all of the following property (collectively, the “Intellectual Property Collateral”):

  
 (a) copyright rights, copyright applications, copyright
registrations and like protections in each work or authorship and derivative work thereof, whether published or unpublished and whether or not the same also constitutes a trade secret, now or hereafter existing, created, acquired or held
(collectively, the “Copyrights”), including the Copyrights described in Exhibit A; 
  
 (b) trademark and servicemark rights, whether registered or not, applications to register and registrations of the same and like protections, and the entire goodwill of the business of Borrower connected with and
symbolized by such trademarks (collectively, the “Trademarks”), including the Trademarks described in Exhibit B; 
  
 (c) patents, patent applications and like protections including without limitation improvements, divisions, continuations, renewals, reissues, extensions
and continuations-in-part of the same (collectively, the “Patents”), including the Patents described in Exhibit C; 
  
 (d) mask work or similar rights available for the protection of semiconductor chips or other products (collectively, the “Mask Works”);

  
 (e) trade secrets, and any and all intellectual property
rights in computer software and computer software products; 
  
 (f) design rights; 
  
 (g) claims for damages by way of
past, present and future infringement of any of the rights included above, with the right, but not the obligation, to sue for and collect such damages for said use or infringement of the intellectual property rights identified above; 
  
 (h) licenses or other rights to use any of the Copyrights, Patents,
Trademarks, or Mask Works, and all license fees and royalties arising from such use to the extent permitted by such license or rights; 
  
 (i) amendments, renewals and extensions of any of the Copyrights, Trademarks, Patents, or Mask Works; and 
  
 (j) proceeds and products of the foregoing, including without limitation all
payments under insurance or any indemnity or warranty payable in respect of any of the foregoing. 
  
 The rights and remedies of Lender with respect to the security interests granted hereunder are in addition to those set forth in the Financing Agreement, and those which are now or hereafter available to Lender as a
matter of law or equity. Each right, power and remedy of Lender provided for herein or in the Financing Agreement, or now or hereafter existing at law or in equity shall be cumulative and concurrent and shall be in addition to every right, power or
remedy provided for herein, and the exercise by Lender of any one or more of such rights, powers or remedies does not preclude the simultaneous or later exercise by Lender of any other rights, powers or remedies. 







 IN WITNESS WHEREOF, the parties have executed this Agreement as of the date first written above. 
  

							
	GRANTOR:	 	 	 	LENDER:
			
	TRIPATH TECHNOLOGY INC.	 	 	 	BRIDGE BANK, NATIONAL ASSOCIATION
				
	By:	 	 /s/ Dr. Adya S. Tripathi

	 	By:	 	 /s/ Michael Lederman


	Name:	 	 Dr. Adya S. Tripathi
 President and Chief
Executive Officer,
 Chairman of the Board
	 	Name:	 	 Michael Lederman


	 	 	 	Title:	 	 Vice President



  

			
	Address for Notices:	  	Address for Notices:
		
	Attn: Jeffrey L. Garon	  	Attn: Lee Shodiss
	Vice President, Finance and Chief Financial Officer	  	2120 El Camino Real
	2560 Orchard Parkway	  	Santa Clara, CA 95050
	San Jose, CA 95131	  	Tel: (408) 556-6502
	Tel: (408) 750-3000	  	Fax: (408) 423-8510
	Fax: (408) 750-3001	  	 








 EXHIBIT A 
  
 COPYRIGHTS 
  

			
	Title:	 	A new technique for audio amplification and signal processing
	Claimant:	 	Dr Adya S. Tripathi
	Registered:	 	May 24, 1985

  
  
  
  







 EXHIBIT B 
  
 TRADEMARKS 
  

							
	 Country

	    	Status

	    	 Trademark

	  	Reg. No.


				
	Canada	    	Abandoned	    	 COMBINANT DIGITAL
	  	 
				
	Canada	    	Abandoned	    	 DESIGN (T)
	  	 
				
	Canada	    	Abandoned	    	 TRIPATH
	  	 
				
	China	    	Registered	    	 COMBINANT
	  	1513827
				
	China	    	Registered	    	 COMBINANT
	  	1445662
				
	China	    	Registered	    	 DESIGN (T)
	  	1505735
				
	China	    	Registered	    	 DESIGN (T)
	  	1436813
				
	China	    	Registered	    	 TRIPATH
	  	1654287
				
	China	    	Abandoned	    	 TRIPATH TECHNOLOGY
	  	 
				
	China	    	Abandoned	    	 TRIPATH TECHNOLOGY
	  	 
				
	China	    	Aband Inst	    	 TRIPATH TECHNOLOGY
	  	1538082
				
	European Community	    	Regd-DNR	    	 COMBINANT DIGITAL
	  	1089366
				
	European Community	    	Registered	    	 DESIGN (T)
	  	001089663
				
	European Community	    	Registered	    	 TRIPATH
	  	1812890
				
	European Community	    	Registered	    	 TRIPATH TECHNOLOGY
	  	1089028
				
	Hong Kong	    	Regd-DNR	    	 COMBINANT DIGITAL
	  	2011/2001
				
	Hong Kong	    	Abandoned	    	 COMBINANT DIGITAL
	  	 
				
	Hong Kong	    	Renewed	    	 DESIGN (T)
	  	200016783
				
	Hong Kong	    	Renewed	    	 DESIGN (T)
	  	4304/2002
				
	Hong Kong	    	Abandoned	    	 TRIPATH
	  	 
				
	Hong Kong	    	Abandoned	    	 TRIPATH
	  	 
				
	Japan	    	Regd-DNR	    	 COMBINANT DIGITAL
	  	4426096
				
	Japan	    	Registered	    	 DESIGN (T)
	  	4426095
				
	Japan	    	Registered	    	 TRIPATH
	  	4532845
				
	Japan	    	Registered	    	 TRIPATH TECHNOLOGY
	  	4434289
				
	Korea	    	Regd-DNR	    	 COMBINANT DIGITAL
	  	1293
				
	Korea	    	Registered	    	 DESIGN (T)
	  	1292
				
	Korea	    	Registered	    	 TRIPATH TECHNOLOGY
	  	1176
				
	Singapore	    	Abandoned	    	 COMBINANT DIGITAL
	  	 
				
	Singapore	    	Regd-DNR	    	 COMBINANT DIGITAL
	  	T99/01775D
				
	Singapore	    	Registered	    	 DESIGN (T)
	  	T99/01772Z
				
	Singapore	    	Registered	    	 DESIGN (T)
	  	T99/01773H
				
	Singapore	    	Registered	    	 TRIPATH
	  	T00/08697Z
				
	Singapore	    	Abandoned	    	 TRIPATH TECHNOLOGY
	  	 
				
	Singapore	    	Aband Inst	    	 TRIPATH TECHNOLOGY
	  	 
				
	Taiwan	    	Regd-DNR	    	 COMBINANT DIGITAL
	  	 
				
	Taiwan	    	Regd-DNR	    	 COMBINANT DIGITAL
	  	00133792
				
	Taiwan	    	Registered	    	 DESIGN (T)
	  	00903068
				
	Taiwan	    	Registered	    	 DESIGN (T)
	  	00130297
				
	Taiwan	    	Registered	    	 TRIPATH
	  	984786
				
	Taiwan	    	Registered	    	 TRIPATH TECHNOLOGY
	  	00915918
				
	Taiwan	    	Registered	    	 TRIPATH TECHNOLOGY
	  	00127054
				
	US	    	Registered	    	 CLASS-T
	  	2,809,670
				
	US	    	Abandoned	    	 COMBINANT DIGITAL
	  	 
				
	US	    	Abandoned	    	 DESIGN (T)
	  	 
				
	US	    	Registered	    	 DIGITAL POWER PROCESSING
	  	2,526,206
				
	US	    	Registered	    	 DPP
	  	2,453,669
				
	US	    	Abandoned	    	 TIO
	  	 
				
	US	    	Abandoned	    	 TIO AND DESIGN
	  	 
				
	US	    	Srch-INACT	    	 T-PATH
	  	 
				
	US	    	Registered	    	 TRIPATH
	  	2,398,029
				
	US	    	Registered	    	 TRIPATH AND DESIGN (T)
	  	2,685,346
				
	US	    	Abandoned	    	 TRIPATH TECHNOLOGY
	  	 








 EXHIBIT C 
  
 PATENTS 
  
 ISSUED U.S. PATENTS as of 6/30/05 
  

											
	 	  	Patent No.

	  	Issue Date

	  	 Title

	  	Inventors

	  	 
	 1. 
	  	5,974,089
	  	10/26/99
	  	METHOD AND APPARATUS FOR PERFORMANCE IMPROVEMENT BY QUALIFYING PULSES IN AN OVERSAMPLED NOISE-SHAPING SIGNAL PROCESSOR	  	Adya S. Tripathi
Cary L. Delano	  	TRIPP001
						
	 2. 
	  	5,909,153
	  	6/1/99 	  	METHOD AND APPARATUS FOR COMPENSATING FOR DELAYS IN MODULATOR LOOPS	  	Cary L. Delano
Adya S. Tripathi	  	TRIPP002
						
	 3. 
	  	6,107,844
	  	8/22/00 	  	METHODS AND APPARATUS FOR REDUCING MOSFET BODY DIODE CONDUCTION IN A HALF-BRIDGE CONFIGURATION	  	Steven K. Berg
Cary L. Delano	  	TRIPP003
						
	 4. 
	  	6,127,893
	  	10/3/00 	  	METHOD AND APPARATUS FOR CONTROLLING AN AUDIO SIGNAL LEVEL	  	William D. Llewellyn
Cary L. Delano	  	TRIPP004
						
	 5.
	  	6,246,283	  	6/12/01	  	POWER EFFICIENT LINE DRIVER	  	Bhupendra K. Ahuja
Cary L. Delano
Adya S. Tripathi	  	TRIPP005
						
	 6.
	  	6,281,747	  	8/28/01	  	POWER EFFICIENT LINE DRIVER	  	Bhupendra K. Ahuja
Cary L. Delano
Adya S. Tripathi	  	TRIPP005C1
						
	 7. 
	  	6,229,390
	  	5/8/01 	  	METHODS AND APPARATUS FOR NOISE SHAPING A MIXED SIGNAL POWER OUTPUT	  	Cary L. Delano 
Adya S. Tripathi	  	TRIPP006
						
	 8. 
	  	6,169,681
	  	1/2/01 	  	POWER SUPPLY TOPOLOGY TO REDUCE THE EFFECTS OF SUPPLY PUMPING	  	Alson R. Kemp
Richard Keller	  	TRIPP008
						
	 9. 
	  	5,777,512
	  	7/7/98 	  	METHOD AND APPARATUS FOR OVERSAMPLED, NOISE SHAPING, MIXED-SIGNAL PROCESSING	  	Adya S. Tripathi
Cary L. Delano	  	Townsend
						
	 10.
	  	5,808,491	  	9/15/98	  	METHOD AND APPARATUS FOR SENSING A COMMON MODE VOLTAGE	  	Cary L. Delano	  	Townsend
						
	 11. 
	  	5,754,079
	  	5/19/98 	  	METHOD AND APPARATUS FOR BIASING A DIFFERENTIAL CASCODECIRCUIT	  	Cary L. Delano 	  	Townsend
						
	 12. 
	  	6,297,697
	  	10/2/01 	  	METHODS AND APPARATUS FOR NOISE-SHAPING A MIXED SIGNAL POWER OUTPUT	  	Adya S. Tripathi
Cary L. Delano	  	TRIPP006C1
						
	 13. 
	  	6,316,992
	  	11/13/01
	  	DC OFFSET CALIBRATION FOR A DIGITAL SWITCHING AMPLIFIER	  	Guoqing Miao 
Cary L. Delano	  	TRIPP010 
						
	 14.
	  	6,329,876	  	12/11/01	  	NOISE REDUCTION SCHEME FOR OPERATIONAL AMPLIFIERS	  	William D. Llewellyn	  	TRIPP007X1
						
	 15. 
	  	6,348,836
	  	2/19/02 	  	DUAL INDEPENDENTLY CLOCKED ANALOG-TO-DIGITAL CONVERSION FOR A DIGITAL POWER AMPLIFIER	  	Cary L. Delano	  	TRIPP019
						
	 16.
	  	6,351,184	  	2/26/02	  	DYNAMIC SWITCHING FREQUENCY CONTROL FOR A DIGITAL SWITCHING AMPLIFIER	  	Cary L. Delano	  	TRIPP012
						
	 17.
	  	6,362,679	  	3/26/02	  	IMPROVED POWER FET DRIVER CIRCUIT	  	Donald T. Wile	  	TRIPP014
						
	 18. 
	  	6,362,683
	  	3/26/02	  	BREAK-BEFORE-MAKE DISTORTION COMPENSATION SYSTEM FOR THE DIGITAL POWER AMPLIFIER	  	Guoqing Miao
Cary L. Delano	  	TRIPP011
						
	 19. 
	  	6,411,165
	  	6/25/02 	  	ACTIVE COMMON MODE FEEDBACK	  	Cary L. Delano	  	TRIPP024
						
	 20.
	  	6,414,560	  	07/02/02
	  	LOOP DELAY COMPENSATION FOR A DIGITAL POWER AMPLIFIER	  	Cary L. Delano	  	TRIPP020
						
	 21.
	  	6,518,849	  	02/11/03	  	DYNAMICALLY DELAY COMPENSATION VERSUS AVERAGE SWITCHING FREQUENCY IN A MODULAR LOOP	  	Cary L. Delano	  	TRIPP023
						
	 22.
	  	6,515,604	  	02/04/03	  	DIGITAL SIGNAL PROCESSING UNIT WITH IMPROVED DISTORTION AND NOISE	  	Cary L. Delano	  	TRIPP027
						
	 23.
	  	6,549,069	  	04/15/03	  	SELF TIMED SWITCHING FOR A DIGITAL POWER AMPLIFIER	  	Cary L. Delano	  	TRIPP018
						
	 24. 
	  	6,566,946
	  	5/20/03 	  	NOISE REDUCTION SCHEME FOR OPERATIONAL AMPLIFIERS	  	Cary L. Delano	  	TRIPP007X1C1
						
	 25. 
	  	6,577,194
	  	6/10/03 	  	RESONANT GATE DRIVE TECHNIQUE FOR A DIGITAL POWER AMPLIFIER	  	Cary L. Delano	  	TRIPP017
						
	 26. 
	  	6,577,189
	  	6/10/03 	  	SCHEME FOR REDUCING TRANSMIT-BAND NOISE FLOOR AND ADJACENT CHANNEL POWER WITH POWER BACKOFF	  	Cary L. Delano
Arun Jayaraman	  	TRIPP031 
						
	 27. 
	  	6,580,322
	  	6/17/03 	  	DYNAMIC SWITCHING FREQUENCY CONTROL METHOD FOR A DIGITAL SWITCHING POWER AMPLIFIER	  	Cary L. Delano
Guoqing Miao	  	TRIPP012C1 
						
	 28. 
	  	6,603,355
	  	8/5/03 	  	ACTIVE COMMON MODE FEEDBACK FOR UNBALANCED INPUT AND FEEDBACK SIGNALS AND METHODS THEREOF	  	Cary L. Delano	  	TRIPP024C1
						
	 29.
	  	6,617,642	  	9/9/03	  	METHOD AND CIRCUIT TO OBTAIN HIGH FREQUENCY SWITCHING POWER FET STAGE FOR INDUCTIVE LOADS	  	Sorin Georgescu	  	TRIPP015
						
	 30. 
	  	6,621,339
	  	9/16/03 	  	METHODS AND APPARATUS FOR FACILITATING NEGATIVE FEEDBACK, PROVIDING LOOP STABILITY AND IMPROVING AMPLIFIER EFFICIENCY	  	Adya S. Tripathi 
Asit Tripathi	  	TRIPP038
						
	 31. 
	  	6,628,166
	  	9/30/03 	  	RF COMMUNICATION SYSTEM USING AN RF DIGITAL AMPLIFIER	  	Cary L. Delano	  	TRIPP016
						
	 32.
	  	6,630,899	  	10/7/03	  	SCHEME FOR MAXIMISING EFFICIENCY OF POWER AMPLIFIER UNDER POWER BACKOFF CONDITIONS	  	Arun Jayaraman	  	TRIPP032
						
	 33.
	  	6,693,491	  	2/17/04	  	METHOD AND APPARATUS FOR CONTROLLING AN AUDIO SIGNAL LEVEL	  	Cary L. Delano	  	TRIPP025
						
	 34. 
	  	6,724,248
	  	4/20/04 	  	AN IMPROVED DC OFFSET SELF-CALIBRATION SYSTEM FOR A DIGITAL SWITCHING AMPLIFIER	  	William Llewellyn	  	TRIPP036
						
	 35.
	  	6,737,713	  	5/13/04	  	SUBSTRATE CONNECTION IN INTEGRATED POWER CIRCUIT	  	Sorin Georgescu	  	TRIPP037
						
	 36.
	  	6,781,458	  	8/24/04	  	PROVIDING DC ISOLATION IN SWITCHING AMPLIFIERS	  	Babak Mazda	  	TRIPP039
						
	 37.
	  	6,785,392	  	8/31/04	  	A MUTE-IN-SILENCE SCHEME FOR AUDIO AMPLIFIERS	  	William Llewellyn	  	TRIPP029
						
	 38. 
	  	6,798,288
	  	9/28/04 	  	METHOD FOR OPTIMAL OPERATION OF LOOP STRUCTURE OF CLASS-T AMPLIFIERS FOR FDD SYSTEMS	  	Arun Jayaraman 
Cary Delano 	  	TRIPP033 

  
 ISSUED INTERNATIONAL PATENTS as of
6/30/05 
  

											
	 	  	Patent No.

	  	Issue Date

	  	 Title

	  	Country

	  	 
	1.	  	129936	  	8/1/01	  	METHOD AND APPARATUS FOR REDUCING MOSFET BODY DIODE CONDUCTION IN A HALF BRIDGE CONFIGURATION	  	Taiwan	  	TRIPP003.TW
						
	2.	  	130682 	  	8/16/01 	  	METHODS AND APPARATUS FOR CONTROLLING AN AUDIO SIGNAL LEVEL	  	Taiwan	  	TRIPP004.TW
						
	3.	  	60709	  	10/24/00	  	METHOD AND APPARATUS FOR OVERSAMPLED, NOISE SHAPING, MIXED SIGNAL PROCESSING	  	Singapore	  	Townsend
						
	4.	  	092983	  	6/17/98	  	METHOD AND APPARATUS FOR OVERSAMPLED, NOISE SHAPING, MIXED SIGNAL PROCESSING	  	Taiwan	  	Townsend
						
	5.	  	135600 	  	10/26/01
	  	METHOD AND APPARATUS FOR COMPENSATING FOR DELAYS IN MODULAR LOOP	  	Taiwan	  	TRIPP002.TW
						
	6.	  	70509 	  	2/27/02 	  	METHOD AND APPARATUS FOR PERFORMANCE IMPROVEMENT BY QUALIFYING PULSES IN AN OVERSAMPLED NOISE-SHAPING SIGNAL PROCESSOR	  	Singapore	  	TRIPP001.SG
						
	7.	  	89103715
	  	4/10/02 	  	POWER SUPPLY TOPOLOGY TO REDUCE THE EFFECTS OF SUPPLY PUMPING	  	Taiwan	  	TRIPP008.TW
						
	8.	  	148300 	  	5/1/02 	  	NOISE REDUCTION SCHEME FOR OPERATIONAL AMPLIFIERS	  	Taiwan	  	TRIPP007X1TW
						
	9.	  	148839	  	5/8/02	  	METHODS AND APPARATUS FOR NOISE SHAPING A MIXED SIGNAL POWER OUTPUT	  	Taiwan	  	TRIPP006.TW
						
	10.
	  	148925 	  	5/9/02 	  	BREAK-BEFORE-MAKE DISTORTION COMPENSATION SYSTEM FOR THE DIGITALPOWER AMPLIFIER	  	Taiwan	  	TRIPP011.TW
						
	11.
	  	74974 	  	8/16/02 	  	METHOD AND APPARATUS FOR COMPENSATING FOR DELAYS IN MODULATOR LOOPS	  	Singapore	  	TRIPP002.SG
						
	12.	  	157634	  	10/8/02	  	DYNAMIC SWITCHING FREQUENCY CONTROL FOR A DIGITAL SWITCHING AMPLIFIER	  	Taiwan	  	TRIPP012.TW
						
	13.	  	162267	  	12/23/02	  	POWER EFFICIENT LINE DRIVER	  	Taiwan	  	TRIPP005.TW
						
	14.
	  	163502 	  	2/7/03 	  	RF COMMUNICATION SYSTEM USING AN RF DIGITAL AMPLIFIER	  	Taiwan	  	TRIPP016.TW
						
	15.
	  	168866 	  	4/23/03 	  	METHOD AND CIRCUIT TO OBTAIN HIGH FREQUENCY SWITCHING POWER FET STAGE FOR INDUCTIVE LOADS	  	Taiwan	  	TRIPP015.TW
						
	16.	  	173026	  	7/2/03	  	IMPROVED POWER FET DRIVER CIRCUIT	  	Taiwan	  	TRIPP014.TW
						
	17.
	  	191538 	  	3/24/04 	  	DC OFFSET CALIBRATION FOR A DIGITAL SWITCHING AMPLIFIER	  	Taiwan	  	TRIPP010.TW