# Patent

## Title
Input/output (I/O) driver implementing dynamic gate biasing of buffer transistors

## Abstract

An input/output (I/O) driver that includes circuitry for over-voltage protection of first and second FETs coupled in series between a first rail and an output, and third and fourth FETs coupled between the output and a second rail. The circuitry is configured to generate a gate bias voltage for the second FET that transitions from high to low bias voltages state when the output voltage (VPAD) begins transitioning from low to high logic voltages, and transitions back to the high bias voltage while VPAD continues to transition towards the high logic voltage. Further, the circuitry is configured to generate a gate bias voltage for the third FET that transitions from low to high bias voltages when VPAD begins transitioning from high to low logic voltages, and transitions back to the low bias voltage while VPAD continues to transition towards the low logic voltage.

## Background
BACKGROUND
Field
Aspects of the present disclosure relate generally to input/output (I/O) drivers, and more particularly, to an I/O driver that implements dynamic gate biasing of buffer transistors for implementing the I/O driver using low-voltage transistors.
Background
An input/output (I/O) driver receives an input voltage that varies between a high logic voltage and a low logic voltage associated with a particular core voltage domain. In response to the input voltage, the I/O driver generates an output voltage that varies between a high logic voltage and a low logic voltage associated with an I/O voltage domain.
Generally, a difference between the high and low logic voltage of the I/O voltage domain is greater than a difference between the high and low logic voltage of the core voltage domain. This may be because the core circuitry of an integrated circuit (IC) operates with smaller voltages for higher processing speed and lower power consumption purposes.
When a voltage signal processed by the core circuitry is ready to be transmitted to another IC, the core circuitry provides the voltage signal as an input voltage to an I/O driver. As discussed above, the I/O driver generates an output voltage based on the input voltage, wherein the output voltage is in a higher voltage domain suitable for transmission of the signal to another IC or external device.
Generally, I/O drivers are implemented with field effect transistors (FETs) that are much larger than FETs implemented in core circuitry. This is because the FETs of I/O drivers need to be able to withstand the larger voltages associated with the I/O voltage domain. As a result, different masks and processes are needed to manufacture IC with relatively small FETs for the core circuitry and relatively large FETs for the I/O drivers. This produces higher costs and delays associated with the manufacture of such ICs.
SUMMARY
The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.
An aspect of the disclosure relates to an apparatus including a pull-up circuit including a first transistor and a second transistor coupled in series between a first voltage rail and an output, and a pull-down circuit including a third transistor and a fourth transistor coupled in series between the output and a second voltage rail.
The apparatus further includes a first voltage generator configured to generate a first bias voltage for a control input of the second transistor, the first bias voltage configured to transition from a first relatively high voltage to a first relatively low voltage approximately when a voltage at the output begins transitioning from a first low logic voltage towards a first high logic voltage due to the pull-up circuit coupling the first voltage rail to the output and the pull-down circuit decoupling the output from the second voltage rail, and the first bias voltage also configured to transition from the first relatively low voltage to the first relatively high voltage while the output voltage continues to transition from the first low logic voltage towards the first high logic voltage.
Additionally, the apparatus includes a second voltage generator configured to generate a second bias voltage for a control input of the third transistor, the second bias voltage configured to transition from a second relatively low voltage to a second relatively high voltage approximately when the output voltage begins transitioning from the first high logic voltage towards the first low logic voltage due to the pull-down circuit coupling the output to the second voltage rail and the pull-up circuit decoupling the first voltage rail from the output, and the second bias voltage also configured to transition from the second relatively high voltage to the second relatively low voltage while the output voltage continues to transition from the first high logic voltage towards the first low logic voltage.
Another aspect of the disclosure relates to a method including coupling a first voltage rail to an output by turning on a first transistor and a second transistor coupled in series between the first voltage rail and the output in response to an input voltage transitioning from a first low logic voltage to a first high logic voltage; and decoupling a second voltage rail from the output by turning off a third transistor and a fourth transistor coupled in series between the output and the second voltage rail in response to the input voltage transitioning from the first low logic voltage to the first high logic voltage, wherein a voltage at the output transitions from a second low logic voltage towards a second high logic voltage in response to the coupling of the first voltage rail to the output and the decoupling of the second voltage rail from the output.
The method further includes coupling the second voltage rail to the output by turning on the third transistor and the fourth transistor in response to the input signal transitioning from the first high logic voltage to the first low logic voltage; and decoupling the first voltage rail from the output by turning off the first transistor and the second transistor in response to the input signal transitioning from the first high logic voltage to the low logic voltage, wherein the output voltage transitions from the second high logic voltage towards the second low logic voltage in response to the coupling of the second voltage rail to the output and the decoupling of the first voltage rail from the output.
Additionally, the method includes transitioning a first bias voltage applied to a control input of the second transistor from a first relatively high voltage to a first relatively low voltage approximately when the output voltage begins transitioning from the second low logic voltage towards the second high logic voltage; transitioning a first bias voltage applied to a control input of the second transistor from a first relatively high voltage to a first relatively low voltage approximately when the output voltage begins transitioning from the second low logic voltage towards the second high logic voltage; transitioning a second bias voltage applied to a control input of the third transistor from a second relatively low voltage to a second relatively high voltage approximately when the output voltage begins transitioning from the second high logic voltage towards the low logic voltage; and transitioning the second bias voltage from the second relatively high voltage to the second relatively low voltage while the output voltage continues to transition from the second high logic voltage towards the second low logic voltage.
Another aspect of the disclosure relates to an apparatus including means for coupling a first voltage rail to an output by turning on a first transistor and a second transistor coupled in series between the first voltage rail and the output in response to an input voltage transitioning from a first low logic voltage to a first high logic voltage; and means for decoupling a second voltage rail from the output by turning off a third transistor and a fourth transistor coupled in series between the output and the second voltage rail in response to the input voltage transitioning from the first low logic voltage to the first high logic voltage, wherein a voltage at the output transitions from a second low logic voltage towards a second high logic voltage in response to the coupling of the first voltage rail to the output and the decoupling of the second voltage rail from the output.
The apparatus further includes means for coupling the second voltage rail to the output by turning on the third transistor and the fourth transistor in response to the input signal transitioning from the first high logic voltage to the first low logic voltage; and means for decoupling the first voltage rail from the output by turning off the first transistor and the second transistor in response to the input signal transitioning from the first high logic voltage to the first low logic voltage, wherein the output voltage transitions from the second high logic voltage towards the second low logic voltage in response to the coupling of the second voltage rail to the output and the decoupling of the first voltage rail from the output.
Additionally, the apparatus includes means for transitioning a first bias voltage applied to a control input of the second transistor from a first relatively high voltage to a first relatively low voltage approximately when the output voltage begins transitioning from the second low logic voltage towards the second high logic voltage; means for transitioning the first bias voltage from the first relatively low voltage to the first relatively high voltage while the output voltage continues to transition from the second low logic voltage towards the second high logic voltage; means for transitioning a second bias voltage applied to a control input of the third transistor from a second relatively low voltage to a second relatively high voltage approximately when the output voltage begins transitioning from the second high logic voltage to the second low logic voltage; and means for transitioning the second bias voltage from the second relatively high voltage to the second relatively low voltage while the output voltage continues to transition from the second high logic voltage towards the second low logic voltage.
To the accomplishment of the foregoing and related ends, the one or more embodiments include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more embodiments. These aspects are indicative, however, of but a few of the various ways in which the principles of various embodiments may be employed and the description embodiments are intended to include all such aspects and their equivalents.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A illustrates a schematic diagram of an exemplary input/output (I/O) driver in accordance with an aspect of the disclosure.
FIG. 1B illustrates a timing diagram of exemplary signals relevant to the operation of the I/O driver of FIG. 1A in accordance with another aspect of the disclosure.
FIG. 1C illustrates a graph of exemplary drain-to-source voltages (VDS) across respective buffer devices used in the I/O driver of FIG. 1A in accordance with another aspect of the disclosure.
FIG. 2A illustrates a schematic diagram of another exemplary input/output (I/O) driver in accordance with another aspect of the disclosure.
FIG. 2B illustrates a timing diagram associated with an exemplary operation of the I/O driver of FIG. 2A in accordance with another aspect of the disclosure.
FIG. 2C illustrates a timing diagram associated with another exemplary operation of the I/O driver of FIG. 2A in accordance with another aspect of the disclosure.
FIG. 3A illustrates a schematic diagram of an exemplary gate bias voltage generator in accordance with another aspect of the disclosure.
FIG. 3B illustrates a timing diagram related to an exemplary operation of the gate bias voltage generator of FIG. 3A in accordance with another aspect of the disclosure.
FIG. 4 illustrates a schematic diagram of an exemplary voltage generator in accordance with another aspect of the disclosure.
FIGS. 5A-5D illustrate schematic diagrams of exemplary first PMOS predriver, second PMOS predriver, first NMOS predriver, and second NMOS predriver in accordance with another aspect of the disclosure.
FIG. 6 illustrates a flow diagram of an exemplary method of generating an output voltage based on an input voltage in accordance with another aspect of the disclosure.



DETAILED DESCRIPTION
The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.
FIG. 1A illustrates a schematic diagram of an exemplary input/output (I/O) driver 100 in accordance with an aspect of the disclosure. The I/O driver 100 is configured to receive an input voltage VIN from, for example, a core circuit of an integrated circuit (IC). The input voltage VIN may swing between a high logic voltage and a low logic voltage according to a first or core voltage domain.
In response to the high and low voltages of the input voltage VIN, the I/O driver 100 generates an output voltage VPAD that swings between a high logic voltage and a low logic voltage according to a second or I/O voltage domain, respectively. As discussed in more detail below, the high and low logic voltages of the I/O voltage domain may swing substantially between VDDPX (applied to a first voltage rail) and VSS (applied to a second voltage rail). The I/O driver 100 provides the output voltage VPAD to a load coupled between the output and the second voltage rail (VSS). The load may have a capacitance CLOAD.
In this example, the I/O driver 100 includes a pull-up circuit situated between a first voltage rail (VDDPX) and an output (VPAD). The pull-up circuit is configured to couple the first voltage rail to the output to cause the output voltage VPAD at the output of the I/O device 100 to transition to and settle at a high logic voltage, such as substantially the voltage VDDPX at the first rail voltage (e.g., 3.6V).
The pull-up circuit is also configured to isolate or decouple the first voltage rail from the output of the I/O device 100 to allow the output voltage VPAD to transition to and settle at a low logic voltage, such as substantially a voltage VSS at a second rail voltage (e.g., 0V or ground). In this example, the pull-up circuit includes a pair of p-channel complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) (hereinafter “PMOS”) MP11 and MP12, and resistor RP. The PMOS MP11 is responsive to a control signal VPCTL for turning on and off the PMOS MP11 in order to pull-up and isolate the output voltage VPAD to and from the first rail voltage VDDPX, respectively.
The PMOS MP12 of the pull-up circuit may be biased with a substantially constant gate voltage VPBIAS, which may be set to VDDPX/2 (e.g., 1.8V). Configured as such, the PMOS MP12 turns on and off in response to the turning on and off of PMOS MP11, respectively. For instance, when control voltage VPCTL is substantially at a low logic voltage, such as VDDPX/2 (e.g., 1.8V), the PMOS MP11 is turned on because its gate-to-source voltage (VGS) (e.g., 3.6V−1.8V=1.8V) is greater than the threshold voltage VT (e.g., 0.4V) of the device. The turning on of PMOS MP11 causes VDDPX to be substantially applied to the source of PMOS MP12. Accordingly, PMOS MP12 turns on because its VGS (e.g., 3.6V−1.8V=1.8V) is greater than its threshold voltage VT (e.g., 0.4V). Both PMOS MP11 and MP12 being turned on causes VDDPX to be applied substantially to the output of the I/O driver 100 by way of resistor RP, which causes the output voltage VPAD to transition to and settle substantially at VDDPX (e.g.,  ̃3.6V). The resistor RP limits the current flow through the FETs MP11 and MP12 to prevent overstressing or damaging of these devices.
Similarly, when control voltage VPCTL is at a high logic voltage, such as substantially at VDDPX (e.g., +3.6V), the PMOS MP11 is turned off because its VGS (e.g., 3.6V−3.6V=0V) is less than its threshold voltage VT (e.g., 0.4V). The PMOS MP11 being turned off isolates VDDPX from the source of PMOS MP12, which causes the voltage at the source of PMOS MP12 to decrease and settle at a voltage VPI no greater than a threshold voltage above VPBIAS (e.g., <2.2V). Thus, PMOS MP12 is turned off because its VGS does not exceed its threshold voltage VT. With both PMOS MP11 and MP12 turned off, the output of the I/O driver 100 is substantially isolated from VDDPX, allowing a pull-down circuit of the I/O driver 100 to pull-down the output voltage VPAD so that it transitions to and settles at substantially VSS (e.g., 0V).
When the output voltage VPAD is substantially at VSS, the PMOS MP12 prevents the entire voltage difference between VDDPX and VSS to be applied across PMOS MP11, thereby preventing overstressing or damage to device MP11. Instead, the voltage difference (VDDPX−VSS) is split, albeit unequally, across both PMOS MP11 and MP12. Thus, PMOS MP12 acts as a buffering device for PMOS MP11.
The I/O driver 100 further includes a pull-down circuit situated between the output of the I/O driver 100 and the second voltage rail (VSS). The pull-down circuit is configured to couple the output to the second voltage rail to cause the output voltage VPAD to transition to and settle at a low logic voltage, such as substantially the steady-state second rail voltage VSS (e.g., ground). The pull-down circuit is also configured to isolate or decouple the output of the I/O device 100 from the second voltage rail to allow the output voltage VPAD to transition to and settle at a high logic voltage, such as substantially the first rail voltage VDDPX. In this example, the pull-down circuit includes a pair of n-channel CMOS devices (hereinafter “NMOS”) MN11 and MN12, and resistor RN. The NMOS MN11 is responsive to a control signal VNCTL for turning on and off the NMOS MN11 in order to couple and isolate the output to and from the second voltage rail, respectively.
The NMOS MN12 of the pull-down circuit may be biased with a substantially constant gate voltage VNBIAS, which may be set to VDPPX/2 (e.g., 1.8V). Configured as such, the NMOS MN12 turns on and off in response to the turning on and off of NMOS MN11, respectively. For instance, when control voltage VNCTL is at a high logic voltage, such as VDPPX/2 (e.g., 1.8V), the NMOS MN11 is turned on because its VGS (e.g., 1.8V−0V=1.8V) is greater than its threshold voltage VT (e.g., 0.4V). The turning on of NMOS MN11 causes VSS to be substantially applied to the source of NMOS MN12. In response, NMOS MN12 turns on because its VGS (e.g., 1.8V−0V=1.8V) is greater than its threshold voltage VT (e.g., 0.4V). Both NMOS MN11 and MN12 being turned on causes VSS to be applied substantially to the output of the I/O driver 100 by way of resistor RN, which results in the output voltage VPAD to transition to and settle substantially at the second rail voltage VSS (e.g., 0V). The resistor RN limits the current flow through the devices MN11 and MN12 to prevent overstressing or damaging of the devices.
Similarly, when control voltage VNCTL is at a low logic voltage, such as VSS (e.g., 0V), the NMOS MN11 is turned off because its VGS (e.g., 0V−0V=0V) is less than its threshold voltage VT (e.g., 0.4V). The device NMOS MN11 being turned off isolates VSS from the source of NMOS MN12, which causes the source of NMOS MN12 to decrease and settle to no more than a threshold voltage below VNBIAS (e.g., >1.4V). Accordingly, NMOS MN12 is turned off because its VGS does not exceed its threshold voltage VT. Both NMOS MN11 and MN12 being turned off decouple the output from the second voltage rail, thereby allowing the pull-up circuit to cause the output voltage VPAD to transition to and settle at the high logic voltage, such as substantially at the first rail voltage VDDPX (e.g., +3.6V).
When the output voltage VPAD is at VDDPX, the NMOS MN12 prevents the entire voltage difference between VDDPX and VSS to be applied across NMOS MN11, thereby preventing overstressing or damage to device MN11. Instead, the voltage difference (VDDPX−VSS) is split, albeit unequally, across both NMOS MP12 and MN11. Thus, NMOS MN12 acts as a buffering device for NMOS MN11.
Note that the respective logic voltages pertaining to the output voltage VPAD, the control VPCTL voltage, and the VNCTL gate voltage are in different voltage domains. For instance, the high and low logic voltages pertaining to the VPAD voltage domain vary between substantially VDDPX (e.g., 3.6V) and VSS (e.g., 0V). The high and low logic voltages pertaining to the VPCTL voltage domain vary between substantially VDDPX (e.g., 3.6V) and VDDIX (e.g., 1.8V). And, the high and low logic voltages pertaining to the VNCTL voltage domain vary between substantially VDDIX (e.g., 1.8V) and VSS (e.g., 0V).
FIG. 1B illustrates a timing diagram of exemplary signals relevant to the operation of the exemplary I/O driver 100 in accordance with another aspect of the disclosure. The x- or horizontal axis of the timing diagram represents time, and is divided into four states or time intervals: (1) when the output voltage VPAD of the I/O driver 100 is at a steady-state high logic voltage VDDPX, which is indicated in the left-most and right-most columns of the timing diagram; (2) when the output voltage VPAD is transitioning from the high logic voltage VDDPX to a low logic voltage VSS, which is indicated in the second column from the left; (3) when the output voltage VPAD is at a steady-state low logic voltage VSS, which is indicated in the third column from the left; and (4) when the output voltage VPAD is transitioning from the low logic voltage VSS to the high logic voltage VDDPX, which is indicated in the fourth column from the left.
The y- or vertical axis of the timing diagram represents the various voltages of the I/O driver 100. For instance, from top to bottom, the voltages are: (1) the control voltage VPCTL for PMOS MP11; (2) the gate bias voltage VPBIAS for PMOS MP12; (3) the voltage VPI at the source of PMOS MP12; (4) the output voltage VPAD of the I/O driver 100; (5) the gate bias voltage VNBIAS for NMOS MN12; (6) the voltage VNI at the source of NMOS MN12; and (7) the control voltage VNCTL for NMOS MN11.
In operation, during the state or time interval where the output voltage VPAD of the I/O driver 100 is at a steady-state high logic voltage VDDPX as indicated in the left-most column of the timing diagram, the control voltage VPCTL is at a low logic voltage VDDIX (e.g., 1.8V) and the gate bias voltage VPBIAS is at a constant VDDPX/2 voltage (e.g., 1.8V) in order to turn on both PMOS MP11 and MP12, respectively. The turning on of both PMOS MP11 and MP12 results in substantially applying VDDPX to the output of the I/O driver 100, thereby causing the output voltage VPAD to be at the high logic voltage VDDPX (e.g., 3.6V). Also, the voltage VPI at the source of PMOS MP12 is substantially at VDDPX (e.g., 3.6V). Further, during this state or time interval, the control voltage VNCTL is at a low logic voltage VSS (e.g., 0V) to turn off NMOS MN11. The gate bias voltage VNBIAS for NMOS MN12 is at the constant VDDPX/2 voltage (e.g., 1.8V). With NMOS MN11 being turned off, the voltage VNI at the source of NMOS MN12 settles to no more than a threshold voltage below VNBIAS, for example, to VNBIAS−VT (e.g., 1.4V). Thus, both NMOS MN11 and MN12 are turned off to isolate or decouple the output of the I/O driver 100 from VSS.
During the state or time interval where the output voltage VPAD of the I/O driver 100 is transitioning from the high logic voltage VDDPX to the low logic voltage VSS as indicated in the second column from the left, the control voltage VPCTL for PMOS MP11 is raised to the high logic voltage VDDPX (e.g., 3.6V) to turn off PMOS MP11. The gate bias voltage VPBIAS of PMOS MP12 remains at the constant VDDPX/2 (e.g., 1.8V). Thus, the voltage VPI at the source of PMOS MP12 decreases and settles to no more than a threshold voltage above VPBIAS, for example, to VPBIAS+VT (e.g., 2.2V). Thus, both PMOS MP11 and MP12 are turned off to isolate or decouple the output of the I/O driver 100 from VDDPX. Also, during this state or time interval, the control voltage VNCTL is raised to a high logic voltage VDDIX (e.g., 1.8V) to turn on NMOS MN11. The turning on of NMOS MN11 causes the voltage VNI at the source of NMOS MN12 to decrease to substantially VSS (e.g., 0V). The gate bias voltage of NMOS MN12 remains at VDDPX/2 (e.g., 1.8V). Thus, the gate-to-source voltage VGS of NMOS MN12 is greater than its threshold voltage VT, thereby causing NMOS MN12 to turn on. Both NMOS MN11 and MN12 being turned on cause the output voltage VPAD to transition to and settle substantially at VSS (e.g., 0V).
Once the voltages have transitioned, they will remain substantially constant during the state or time interval where the output voltage VPAD is at substantially VSS, as indicated in the third column from the left. That is, the voltage VPCTL is at the high logic voltage VDDPX and VNBIAS is at VDDPX/2 to keep devices MP11 and MP12 turned off to isolate or decouple the output from the first voltage rail (VDDPX). The voltage VPI at the source of PMOS MP12 remains substantially constant at no more than a threshold voltage VT above VNBIAS (e.g., 2.2V). The voltage VNCTL is at the high logic voltage VDDIX and voltage VNBIAS is at the constant VDDPX/2 to keep both devices MN11 and MN12 turned on to cause the output voltage VPAD to be at the low logic voltage VSS. Both devices MN11 and MN12 being turned on cause the voltage VNI at the source of NMOS MN12 to be at VSS (e.g., 0V).
During the state or time interval where the output voltage VPAD of the I/O driver 100 is transitioning from the low logic voltage VSS to the high logic voltage VDDPX as indicated in the fourth column from the left, the control voltage VPCTL for PMOS MP11 is lowered to the low logic voltage VDDIX (e.g., 1.8V) to turn on PMOS MP11. The gate bias voltage VPBIAS for PMOS MP12 remains at the constant VDDPX/2 (e.g., 1.8V). Thus, both PMOS MP11 and MP12 turn on. Accordingly, the voltage VPI at the source of PMOS MP12 as well as the output voltage VPAD transition to the high logic voltage VDDPX (e.g., 3.6 V). Also, during this state or time interval, the control voltage VNCTL is lowered to the low logic voltage VSS (e.g., 0V) to turn off NMOS MN11. The gate bias voltage VNBIAS of NMOS MN12 remains at the constant VDPPX/2 (e.g., 1.8V). Accordingly, the voltage VNI at the source of NMOS MN12 increases to at least a threshold voltage below VNBIAS, to, for example, 1.4V. Thus, the gate-to-source voltage VGS of NMOS MN12 does not exceed its threshold voltage VT, thereby causing NMOS MN12 to turn off. Both NMOS MN11 and MN12 being turned off isolate or decouple the output voltage VPAD from VSS (e.g., 0V). Once the voltages have transitioned, they will remain substantially constant during the state or time interval where the output voltage VPAD is at the high logic voltage VDDPX, as indicated in the right-most column.
There are a couple of issues with the I/O driver 100. For instance, if the devices MP11, MP12, MN11, and MN12 used in I/O driver 100 are manufactured in accordance with 45 nm, 40 nm or 28 nm technology (e.g., to use the same technology for all other non-I/O devices (e.g., core devices) in an integrated circuit), the maximum reliability voltage across any terminals (VGS, VGD, and VDS) of these devices is about 2.0V. If the devices are exposed to voltages above the reliable limit of 2.0V and for an extended period of time (e.g., a few picoseconds or more), recoverable or unrecoverable damage to these devices may result. Such damage may be due to negative bias temperature instability (NBTI) or hot carrier injection (HCI). As a consequence, the performance and functionality of the devices may degrade or completely fail.
With reference again to FIG. 1B, when the output voltage VPAD is at the high logic voltage VDDPX as indicated in the left-most and right-most columns of the timing diagram, the voltage at the drain of NMOS MN12 is substantially at VDDPX (e.g., 3.6V) and the voltage at the source of NMOS MN12 is at 1.4V. Thus, the voltage difference (e.g., VDS) across the drain and source of NMOS MN12 is 2.2V. As previously discussed, this voltage differential of 2.2V across NMOS MN12 exceeds the reliability limit of +2.0V if this device is manufactured in accordance with a particular implementation.
Further, during the state or time interval where the output voltage VPAD is transitioning from VDDPX to VSS as indicated in the second column from the left, the voltage VNI at the source of NMOS MN12 decreases from 1.4V to 0V at a rate much faster than the output voltage VPAD decreases from 3.6V to 0V, due to generally a larger load present at the output of the I/O driver 100. As a result, the voltage difference VDS across the drain and source of NMOS MN12 increases up to about 2.8V during the transition of the output voltage VPAD from VDDPX to VSS, again exceeding the reliability limit of 2.0V if the device is manufactured in accordance with a particular implementation.
Similarly, when the output voltage VPAD is at the low logic voltage VSS as indicated in the third column from the left, the voltage at the drain of the PMOS MP12 is substantially at VSS (e.g., 0V) and the voltage at the source of the PMOS MP12 is at 2.2V. Thus, the voltage difference (e.g., VDS) across the drain and source of PMOS MP12 is 2.2V. As previously discussed, this voltage differential of 2.2V across PMOS MP12 exceeds the reliability limit of 2.0V if this device is manufactured in accordance with a particular implementation.
Also, similarly, during the state or time interval where the output voltage VPAD is transitioning from VSS to VDDPX as indicated in the fourth column from the left, the voltage VPI at the source of PMOS MP12 increases from 2.2V to 3.6V at a rate much faster than the output voltage VPAD increases from 0V to 3.6V due to generally a larger load present at the output of the I/O driver 100. As a result, the voltage differential VDS across the drain and source of PMOS MP12 increases up to about 2.8V during the transition of the output voltage VPAD from VSS to VDDPX, again exceeding the reliability limit of 2.0V if the device is manufactured in accordance with a particular implementation.
FIG. 1C illustrates a graph of exemplary voltages (VDS) across respective devices MP12 and MN12 used in the exemplary I/O driver 100 in accordance with another aspect of the disclosure. When the output voltage VPAD is substantially at steady-state VDDPX (e.g., 3.6V), which occurs in this graph between 6 nanoseconds (ns) and 10 ns, the voltage difference (VDS) across the drain and source of NMOS MN12 is approximately at 2.2V, which exceeds the reliability limit of 2.0V for a 45 nm, 40 nm or 28 nm technology device. Also, during the transition of the output voltage VPAD from VDDPX to VSS (e.g., from 3.6V to 0V), which occurs in this graph between 10 ns and 11 ns, the voltage difference (VDS) across the drain and source of NMOS MN12 spikes up to approximately 2.8V, which substantially exceeds the reliability limit of 2.0V for a device manufactured with a particular implementation.
Similarly, when the output voltage VPAD is substantially at steady-state VSS (e.g., 0V), which occurs in this graph between 11 ns and 15 ns, the voltage difference (VDS) across the drain and source of PMOS MP12 is approximately at 2.2V, which exceeds the reliability limit of 2.0V for a 45 nm, 40 nm or 28 nm technology device. Also, during the transition of the output voltage VPAD from VSS to VDDPX, which occurs in this graph between 15 ns and 16 ns, the voltage difference (VDS) across the drain and source of PMOS MP12 spikes up to approximately 2.8V, which substantially exceeds the reliability limit of 2.0V for a device manufactured with a particular implementation.
Thus, there is a need to implement lower voltage devices, such as those manufactured in accordance with 45 nm, 40 nm or 28 nm technology, for I/O driver operations, while controlling the voltages across the devices so as to not exceed their reliability limits. A discussion of an exemplary I/O driver that achieves at least this end is provided below.
FIG. 2A illustrates a schematic diagram of an input/output (I/O) driver 200 in accordance with another aspect of the disclosure. One of the differences between I/O driver 200 and I/O driver 100 is that the bias voltages VNBIAS and VPBIAS are not constant, but change during transitions of the output voltage VPAD from high-to-low logic voltages and from low-to-high logic voltages, respectively. This is done to reduce the maximum voltages across the buffer devices MN22 and MP22 to below their reliability limits during transitions of the output voltage VPAD, respectively. Additionally, the I/O driver 200 applies bias voltages to the sources of MN22 and MP22 to prevent over-voltage of such devices when the output voltage VPAD is at steady-state high and low logic voltages, respectively.
As an overview, the I/O driver 200 is configured to receive an input voltage VIN from, for example, a core circuit of an IC. The input voltage VIN may swing between high and low logic voltages according to a first (e.g., core) voltage domain. In response to the high and low voltages of the input voltage VIN, the I/O driver 200 generates an output voltage VPAD that swings between high and low logic voltages according to a second (e.g., “I/O”) voltage domain, respectively. The high and low logic voltages of the second voltage domain may coincide substantially with VDDPX and VSS. The I/O driver 200 provides the output voltage VPAD to a load having a capacitance CLOAD.
More specifically, the I/O driver 200 includes a pull-up circuit having PMOS MP21 and MP22 coupled in series between a first voltage rail (VDDPX) and the output (VPAD) of the I/O driver. Similarly, the I/O driver 200 includes a pull-down circuit including NMOS MN22 and MN21 coupled in series between the output (VPAD) and a second voltage rail (VSS).
The I/O driver 200 further includes a first PMOS predriver 210 configured to generate a voltage signal VPCTL_HV in response to an input signal VIN. The voltage domain for VPCTL_HV varies between a low logic voltage VDDIX (e.g., VDDPX/2) and a high logic voltage VDDPX. The I/O driver 200 further includes a second PMOS predriver 211 configured to generate a voltage signal VPCTL_LV in response to an input signal VIN. The voltage domain for VPCTL_LV varies between a low logic voltage VSS and a high logic voltage VDDIX. Thus, when the input voltage VIN is low, VPCTL_HV is at VDDPX and VPCTL_LV is at VDDIX. When the input voltage VIN is high, VPCTL_HV is at VDDIX and VPCTL_LV is at VSS.
Similarly, the I/O driver 200 further includes a first NMOS predriver 220 configured to generate a voltage signal VNCTL_LV in response to the input signal VIN. The voltage domain for VNCTL_LV varies between a low logic voltage VSS and a high logic voltage VDDIX. The I/O driver 200 further includes a second NMOS predriver 221 configured to generate a voltage signal VNCTL_HV in response to the input signal VIN. The voltage domain for VNCTL_HV varies between a low logic voltage VDDIX and a high logic voltage VDDPX. Thus, when the input voltage VIN is low, VNCTL_LV is at VDDIX and VNCTL_HV is at VDDPX. When the input voltage VIN is high, VNCTL_LV is at VSS and VNCTL_HV is at VDDIX.
The signal VPCTL_HV generated by the first PMOS predriver 210 is applied to the gate of PMOS MP21 and to a VPI voltage generator 214. The signal VPCTL_LV generated by the second PMOS predriver 211 is applied to a VPBIAS voltage generator 212. Similarly, the signal VNCTL_LV generated by the first NMOS driver 220 is applied to the gate of NMOS MN21 and to a VNI voltage generator 224. The signal VNCTL_HV generated by the second NMOS predriver 221 is applied to a VNBIAS voltage generator 222.
The VPBIAS voltage generator 212 is configured to generate a bias voltage VPBIAS based on VPCTL_LV and VPAD. The bias voltage VPBIAS is applied to the gate of PMOS MP22. Similarly, the VNBIAS voltage generator 222 is configured to generate a bias voltage VNBIAS based on VNCTL_HV and VPAD. The bias voltage VNBIAS is applied to the gate of NMOS MN22.
The VPI voltage generator 214 is configured to generate a defined voltage VPI based on VPCTL_HV and VPAD. The defined voltage VPI is applied to the source of PMOS MP22. The defined voltage VPI protects the PMOS MP22 from over-voltage when the output voltage VPAD is at a steady-state low logic voltage. For example, when the output voltage VPAD is at the steady-state low logic voltage VSS (e.g., 0V), the defined voltage VPI is substantially at VDDIX (e.g., 1.8V). Due to the defined voltage VPI, the drain-to-source voltage VDS of PMOS MP22 is, for example, 1.8V, below a reliability maximum voltage of 2.0V for certain device technology.
Similarly, the VNI voltage generator 224 is configured to generate a defined voltage VNI based on VNCTL_LV and VPAD. The defined voltage VNI is applied to the source of NMOS MN22. The defined voltage VNI protects the NMOS MN22 from over-voltage when the output voltage VPAD is at a steady-state high logic voltage. For example, when the output voltage VPAD is at the steady-state high logic voltage VDDPX (e.g., 3.6V), the defined voltage VNI is substantially at VDDIX (e.g., 1.8V). Due to the defined voltage VNI, the drain-to-source voltage VDS of NMOS MN22 is, for example, 1.8V, below a reliability maximum voltage of 2.0V for certain device technology.
FIG. 2B illustrates a timing diagram associated with an exemplary operation of the I/O driver 200 in accordance with another aspect of the disclosure. For explanation purposes, VDDPX is 3.6V, VDDIX is 1.8V, and VSS is 0V. Also, for explanation purposes, the maximum reliability voltage for VDS, VGS, and VDG of devices MP21, MP22, MN22, and MN21 is 2.0V. It shall be understood that such voltages and maximum reliability voltages may be different in various implementations based on the type of devices and applications used for the I/O driver 200.
Similar to the graph of FIG. 1B, the x- or horizontal axis of the timing diagram represents time, and is divided into four states or time intervals: (1) when the output voltage VPAD of the I/O driver 200 is at a steady-state high logic voltage VDDPX, which is indicated in the right-most and left-most columns of the timing diagram; (2) when the output voltage VPAD is transitioning from the high logic voltage VDDPX to a low logic voltage VSS, which is indicated in the second column from the left; (3) when the output voltage VPAD is at a steady-state low logic voltage VSS, which is indicated in the third column from the left; and (4) when the output voltage VPAD is transitioning from the low logic voltage VSS to the high logic voltage VDDPX, which is indicated in the fourth column from the left.
The y- or vertical axis of the timing diagram represents the various voltages of the I/O driver 200. For instance, from top to bottom, the voltages are: (1) the control voltage VPCTL_HV for PMOS MP11; (2) the defined voltage VPI at the source of PMOS MP12; (3) the gate bias voltage VPBIAS for PMOS MP12; (4) the output voltage VPAD, (5) the gate bias voltage VNBIAS for NMOS MN12; (6) the defined voltage VNI at the source of NMOS MN12; and (7) the control voltage VNCTL_LV for NMOS MN11.
When the output voltage VPAD is at a high logic voltage VDDPX (3.6V) as indicated by the left-most and right-most columns, the control voltage VPCTL_HV is at a low logic voltage VDDIX (1.8V) to turn on PMOS MP21, the defined voltage VPI at the source of PMOS MP22 is at VDDPX (3.6V), and the bias voltage VPBIAS is at a relatively high voltage VDDIX (1.8V), which causes PMOS MP22 to turn on in response to PMOS MP21 turning on. Accordingly, the output voltage VPAD is at a high logic voltage VDDPX (3.6V) due to the first voltage rail being coupled to the output via the turned-on PMOS MP21 and MP22.
Also, when the output voltage VPAD is at the high logic voltage VDDPX (3.6V), the control voltage VNCTL_LV is at a low logic voltage VSS (0V) to turn off NMOS MN21, the defined voltage VNI is at VDDIX (1.8V) to maintain the VDS of NMOS MN22 below its reliability limit, and the bias voltage VNBIAS is at a relatively low voltage VDDIX (1.8V) to turn off NMOS MN22. Accordingly, the output is decoupled from the second voltage rail (VSS) due to the turned-off NMOS MN22 and MN21.
To transition the output voltage VPAD from the high logic voltage VDDPX (3.6V) towards the low logic voltage VSS (0V) as indicated in the second column from the left, the control voltage VNCTL_HV is changed from the low logic voltage VSS (0V) to the high logic voltage VDDIX (1.8V) to turn on NMOS MN21. Simultaneous with VNCTL_LV changing from low to high, the bias voltage VNBIAS is raised from a relatively low bias voltage (e.g.,  ̃VDDIX (1.8V)) to a relatively high bias voltage (e.g.,  ̃VDDPX (3.6V)). This is done to configure the respective turn-on resistances of NMOS MN21 and MN22 to be more equalized (e.g., substantially the same) when the output voltage VPAD initially transitions from high-to-low. This causes the 3.6V voltage drop between VPAD and VSS to be equally divided among NMOS MN22 and MN21; thus, causing the devices to each see a voltage drop of substantially 1.8V, which is below the 2.0V reliability limit.
When the output voltage VPAD has decreased to a defined voltage level, the bias voltage VNBIAS is brought back to the relatively low bias voltage (e.g.,  ̃VDDIX (1.8V)). The time interval in which the VNBIAS is at the relatively high bias voltage (e.g.,  ̃VDDPX (3.6V)) should be controlled to prevent over-voltage of NMOS MN22. For instance, if the time interval is too short, then NMOS MN22 may be subjected to over-voltage due to its VDS being above the reliability limit. If, on the other hand, the time interval is too long, then the device MN22 may be subjected to over-voltage due to its gate-to-source voltage (VGS) and/or gate-to-drain voltage (VGD) being above the reliability limit.
The time interval depends on the rate at which the output voltage VPAD decreases from VDDPX to VSS. Such rate depends on the capacitive load CLOAD coupled to the output of the I/O driver 200. If the capacitance CLOAD of the load is relatively small, then the time interval should be relatively short because the rate at which output voltage VPAD is decreasing is relatively high. If the capacitance CLOAD of the load is relatively large, then the time interval should be relatively long because the rate at which output voltage VPAD is decreasing is relatively low. Accordingly, the VNBIAS voltage generator 222 generates the raised VNBIAS voltage based on the rate at which output voltage VPAD transitions from high-to-low.
Further, to facilitate the transition of the output voltage VPAD from the high logic voltage VDDPX (3.6V) towards the low logic voltage VSS (0V), the control voltage VPCTL_HV is changed from the low logic voltage VDDIX (1.8V) to the high logic voltage VDDPX (3.6V) to turn off PMOS MP21. In response to the output voltage VPAD decreasing to a defined voltage level, the VPI voltage generator 214 generates a defined voltage VPI substantially at VDDIX (1.8V). As the bias voltage VPBIAS applied to gate of PMOS MP22 is maintained constant at VDDIX (1.8V) during the transition of the output voltage VPAD from high-to-low, PMOS MP22 turns off because its VGS is substantially at 0V. Accordingly, during the transition of the output voltage VPAD from high-to-low, the pull-up circuit decouples the output from the first voltage rail (VDDPX) due to the turned off PMOS MP21 and MP22.
When the output voltage VPAD is at a steady-state low logic voltage VSS (0V) as indicated in the third column from the left, the control voltage VNCTL_LV is at the high logic voltage VDDIX (1.8V) to maintain NMOS MN21 turned on, the bias voltage VNBIAS is at a low bias voltage VDDIX (1.8V) (relative compared to VDDPX), which maintains NMOS MN22 turned on. Thus, output voltage VPAD receives VSS (0V) from the second voltage rail via the turned-on NMOS MN21 and MN22. It follows that the defined voltage VNI is also at VSS (0V).
Also, when the output voltage VPAD is at the steady-state low logic voltage VSS (0V), the bias voltage VPCTL_HV is at a high logic voltage VDDPX (3.6V) to maintain PMOS MP21 turned off, the defined voltage VPI is at VDDIX (1.8V) to protect PMOS MP22 from over-voltage as discussed, and the bias voltage VPBIAS is at a high bias voltage VDDIX (1.8V) (compared to VSS), which maintains PMOS MP22 turned off. Thus, the output of the I/O driver 200 is decoupled from the first voltage rail (VDDPX) via the turned-off PMOS MP21 and MP22.
To transition the output voltage VPAD from the low logic voltage VSS (0V) towards the high logic voltage VDDPX (3.6V) as indicated in the fourth column from the left, the control voltage VPCTL_HV is changed from the high logic voltage VDDPX (3.6V) to the low logic voltage VDDIX (1.8V) to turn on PMOS MP21. Simultaneous with VPCTL_HV changing from high to low, the bias voltage VPBIAS is lowered from the relatively high bias voltage (e.g.,  ̃VDDIX (1.8V)) to a relatively low bias voltage (e.g., VSS (0V)). This is done to configure the respective turn-on resistances of PMOS MP21 and MP22 to be more equalized (e.g., substantially the same) when the output voltage VPAD initially transitions from low-to-high. This causes the 3.6V voltage drop between VDDPX and VPAD to be divided equally among PMOS MP22 and MP21; thus, causing the devices to each see a voltage drop of substantially 1.8V, which is below the 2.0V reliability limit.
When the output voltage VPAD has increased to a defined voltage level, the bias voltage VPBIAS is brought back to the relatively high bias voltage (e.g.,  ̃VDDIX (1.8V)). The time interval in which the VPBIAS is at the relatively low bias voltage (e.g.,  ̃VSS (0V)) should be controlled to prevent over-voltage of PMOS MP22. For instance, if the time interval is too short, then PMOS MP22 may be subjected to over-voltage due to its VDS being above the reliability limit. If, on the other hand, the time interval is too long, then the device MP22 may be subjected to over-voltage due to its gate-to-source voltage (VGS) and/or gate-to-drain (VGD) being above the reliability limit.
The time interval depends on the rate at which the output voltage VPAD increases from VSS to VDDPX. Such rate depends on the capacitive load CLOAD coupled to the output of the I/O driver 200. If the capacitance CLOAD of the load is relatively small, then the time interval should be relatively short because the rate at which output voltage VPAD is increasing is relatively high. If the capacitance CLOAD of the load is relatively large, then the time interval should be relatively long because the rate at which output voltage VPAD is increasing is relatively low. Accordingly, the VPBIAS voltage generator 212 generates the lowered VPBIAS voltage based on the rate at which output voltage VPAD transitions from low-to-high.
Further, to facilitate the transition the output voltage VPAD from the low logic voltage VSS (0V) towards the high logic voltage VSS (3.6V), the control voltage VNCTL_LV is changed from the high logic voltage VDDIX (1.8V) to the low logic voltage VSS (0V) to turn off NMOS MN21. In response to the output voltage VPAD increasing to a defined voltage level, the VNI voltage generator 224 generates a defined voltage VNI substantially at VDDIX (1.8V). As the bias voltage VNBIAS applied to gate of NMOS MN22 is maintained constant at VDDIX (1.8V) during the transition of the output voltage VPAD from low-to-high, NMOS MN22 turns off because its VGS is substantially at 0V. Accordingly, during the transition of the output voltage VPAD from low-to-high, the pull-down circuit decouples the output from the second voltage rail (VSS) due to the turned off NMOS MN21 and MN22.
FIG. 2C illustrates a timing diagram associated with another exemplary operation of the I/O driver 200 in accordance with another aspect of the disclosure. The I/O driver 200 may be configured as a tristate device, where the I/O driver may produce a high logic voltage, a low logic voltage, or high impedance at its output. Accordingly, the timing diagram depicted in FIG. 2C relates to the operation of the I/O driver 200 when it produces a high impedance at its output.
As illustrated in FIG. 2A, the first and second PMOS predrivers 210 and 211, and the first and second NMOS predrivers 220 and 221 each receive an enable (EN) signal. When the EN signal is asserted, the I/O driver 200 operates to output a high logic voltage or low logic voltage based on the input voltage VIN, as previously discussed. When the EN signal is not asserted, the I/O driver 200 is configured to produce high impedance at the output to allow other one or more external devices to drive a transmission line or load coupled to the output. The I/O driver 200 produces the high impedance at its output by turning off the pull-up circuit (e.g., turning off PMOS MP21 and MP22) and the pull-down circuit (e.g., turning off NMOS MN22 and MN21).
More specifically, when the EN signal is not asserted, the first PMOS predriver 210 generates the control voltage VPCTL_HV at the high logic voltage VDDPX (3.6V) and the second PMOS predriver 211 generates the control voltage VPCTL_LV at the high logic voltage VDDIX (1.8V) regardless of the logic state of the input voltage VIN and the output voltage VPAD. The control voltage VPCTL_HV being maintained at the high logic voltage VDDPX (3.6V) maintains PMOS MP21 turned off while the I/O driver 200 is operated to produce high impedance at the output. The control voltage VPCTL_HV being at the high logic voltage VDDIX (1.8V) causes the VPBIAS voltage generator 212 to generate the bias voltage VPBIAS at a constant relatively high bias voltage VDDIX (1.8V). The timing diagram of FIG. 2C depicts VPCTL_HV and VPCTL_LV at constant voltages VDDPX (3.6V) and VDDIX (1.8V) while the I/O driver 200 is configured to output a high impedance.
Similarly, when the EN signal is not asserted, the first NMOS predriver 220 generates the control voltage VNCTL_LV at the low logic voltage VSS (0V) and the second NMOS predriver 221 generates the control voltage VNCTL_HV at the low logic voltage VDDIX (1.8V) regardless of the logic state of the input voltage VIN and the output voltage VPAD. The control voltage VNCTL_LV being maintained at the low logic voltage VSS (0V) maintains NMOS MN21 turned off while the I/O driver 200 is operated to produce a high impedance at the output. The control voltage VNCTL_HV being at the low logic voltage VDDIX (1.8V) causes the VNBIAS voltage generator 212 to generate the bias voltage VNBIAS at a constant relatively low bias voltage VDDIX (1.8V). The timing diagram of FIG. 2C depicts both VNCTL_LV and VNCTL_HV at constant voltages VSS (0V) and VDDIX (1.8V) while the I/O driver 200 is configured to output a high impedance.
The control voltage VPCTL_HV being at the constant high logic voltage VDDPX (3.6V) causes the VPI voltage generator 214 to generate the defined voltage VPI to maintain PMOS MP22 turned off and protected from over-voltage while the I/O driver 200 is configured to output a high impedance. For instance, when the output voltage VPAD is driven to a high logic voltage VDDPX (3.6V) by another device, the VPI voltage generator 214 generates the defined voltage VPI at VDDPX (3.6V), as illustrated in the timing diagram of FIG. 2C. Thus, PMOS MP22 is effectively turned off as its VDS is 0V and the maximum voltage across PMOS MP22 is VGS and VGD at 1.8V, which is below the reliability limit of 2.0V for certain device technology. When the output voltage VPAD is driven to a low logic voltage VSS (0V) by another device, the VPI voltage generator 214 generates the defined voltage VPI at VDDIX (1.8V), as illustrated in the timing diagram of FIG. 2C. Thus, the maximum voltage across PMOS MP22 is VDS 1.8V, which is also below the reliability limit of 2.0V for certain device technology.
The control voltage VNCTL_LV being at the constant low logic voltage VSS (0V) causes the VNI voltage generator 224 to generate the defined voltage VNI to maintain NMOS MN22 turned off and protected from over-voltage while the I/O driver 200 is configured to output a high impedance. For instance, when the output voltage VPAD is driven to a low logic voltage VSS (0V) by another device, the VNI voltage generator 224 generates the defined voltage VNI at VSS (0V), as illustrated in the timing diagram of FIG. 2C. Thus, NMOS MP22 is effectively turned off as its VDS is 0V and the maximum voltage across NMOS MN22 is VGS and VGD at 1.8V, which is below the reliability limit of 2.0V for certain device technology. When the output voltage VPAD is driven to a high logic voltage VDDPX (3.6V) by another device, the VNI voltage generator 224 generates the defined voltage VNI at VDDIX (1.8V), as illustrated in the timing diagram of FIG. 2C. Thus, the maximum voltage across NMOS MN22 is VDS 1.8V, which is also below the reliability limit of 2.0V for certain device technology.
FIG. 3A illustrates a schematic diagram of an exemplary bias voltage generator 300 including a VNBIAS voltage generator 310 and a VPBIAS voltage generator 320. The VNBIAS voltage generator 310 and the VPBIAS voltage generator 320 may be one exemplary detailed implementation of VNBIAS voltage generator 222 and VPBIAS voltage generator 212 of I/O driver 200, respectively.
In particular, the VNBIAS voltage generator 310 includes a PMOS MP31, a PMOS MP32, a NAND gate 312, and an inverter 314. The PMOS MP31 includes source and drain coupled between the output (VPAD) of the I/O driver 200 and a first input of the NAND gate 312. The gate of PMOS MP31 is configured to receive the constant bias voltage VDDIX. The PMOS MP32 includes source and drain coupled between a source of the constant bias voltage VDDIX and the first input of the NAND gate 312. The gate of MP32 is coupled to the output (VPAD) of the I/O driver 200. The control voltage VNCTL_HV is applied to a second input of the NAND gate 312. The output of the NAND gate 312 is coupled to an input of the inverter 314. The bias voltage VNBIAS is generated at the output of the inverter 314.
The VPBIAS voltage generator 320 includes an NMOS MN31, an NMOS MN32, a NOR gate 322, and an inverter 324. The NMOS MN31 includes drain and source coupled between the output (VPAD) of the I/O driver 200 and a first input of the NOR gate 322. The gate of NMOS MN31 is configured to receive the constant bias voltage VDDIX. The NMOS MN32 includes source and drain coupled between the source of the constant bias voltage VDDIX and the first input of the NOR gate 322. The gate of MN32 is coupled to the output (VPAD) of the I/O driver 200. The control voltage VPCTL_LV is applied to a second input of the NOR gate 322. The output of the NOR gate 322 is coupled to an input of the inverter 324. The bias voltage VPBIAS is generated at the output of the inverter 324.
The circuit including PMOS MP31 and MP32 and NMOS MN31 and MN32 operate as a waveform splitter. That is, as discussed, the voltage domain for the output voltage VPAD has high and low logic voltages at VDDPX and VSS, respectively. The portion of the waveform splitter having PMOS MP31 and MP32 generates the signal VPAD_HV that tracks the high and low logic voltages of the output voltage VPAD but in a different voltage domain having high and low voltages at VDDPX and VDDIX, respectively. Similarly, the portion of the waveform splitter having NMOS MN31 and MN32 generates the signal VPAD_LV that tracks the high and low logic voltages of the output voltage VPAD but in a different voltage domain having high and low voltages at VDDIX and VSS, respectively.
FIG. 3B illustrates a timing diagram related to exemplary operations of the I/O driver 200, VNBIAS voltage generator 310, and VPBIAS voltage generator 320 in accordance with another aspect of the disclosure. The x- or horizontal axis of the timing diagram represents time, and is divided into four primary time intervals: (1) when the output voltage VPAD of the I/O driver 200 is substantially at a steady-state high logic voltage VDDPX (3.6V), which is indicated in the left-most and right-most columns of the timing diagram; (2) when the output voltage VPAD is transitioning from the high logic voltage VDDPX (3.6V) to a low logic voltage VSS (0V), which is indicated in the second column from the left; (3) when the output voltage VPAD of the I/O driver 200 is substantially at a steady-state low logic voltage VSS (0V), which is indicated in the third column from the left; and (4) when the output voltage VPAD is transitioning from the low logic voltage VSS (0V) to the high logic voltage VDDPX (3.6V), which is indicated in the fourth column from the left.
The y- or vertical axis of the timing diagram represents the various voltages of the I/O driver 200, VNBIAS voltage generator 310, and VPBIAS voltage generator 320. For instance, from top to bottom, the voltages are: (1) the output voltage VPAD at the output of the I/O driver 200; (2) the voltage VPAD_HV at the first input of the NAND gate 312; (3) the voltage VPAD_LV at the first input of the NOR gate 322; (4) the control voltage VPCTL_LV at the second input of the NOR gate 322 (generated by the second PMOS predriver 211); (5) the gate bias voltage VPBIAS for PMOS MP22; (6) the control voltage VNCTL_HV at the second input of the NAND gate 312 (generated by the second NMOS predriver 221); and (7) the gate bias voltage VNBIAS for NMOS MN22.
In operation, when the output voltage VPAD of the I/O driver 200 is at the steady-state high logic voltage VDDPX (3.6V), PMOS MP31 is turned on because its source is at VDDPX (3.6V) and its gate is at VDDIX (1.8V); thus, PMOS MP31 has a VGS of 1.8V, which is greater than its threshold voltage VT of 0.4V. Additionally, PMOS MP32 is turned off because its source is at VDDPX (3.6V) and its gate is at VDDPX (3.6V); thus, PMOS MP32 has a VGS of 0V, which is less than its threshold voltage VT of 0.4V. Accordingly, the voltage VPAD_HV at the first input of the NAND gate 312 is at a high logic voltage VDDPX (3.6V). The voltage VNCTL_HV is at a low logic voltage of VDDIX (1.8V). Thus, since the inputs to the NAND gate 312 are high and low logic voltages, the NAND gate 312 generates a high logic voltage, and the inverter 314 outputs VNBIAS as a relatively low bias voltage VDDIX (1.8V), as indicated in the timing diagram of FIG. 3B.
Also, when the output voltage VPAD of the I/O driver 200 is the steady-state high logic voltage VDDPX (3.6V), NMOS MN32 is turned on because its gate is at VDDPX (3.6V) and its source is at VDDIX (1.8V); thus, NMOS MN32 has a VGS of 1.8V, which is greater than its threshold voltage VT of 0.4V. Thus, since MN32 is turned on, the voltage VPAD_LV at the first input of the NOR gate 322 is at a high logic voltage VDDIX (1.8V). NMOS MN31 is turned off since its gate is at VDDIX (1.8V) and its source is at VDDIX (1.8V); thus, NMOS MN32 has a VGS of 0V, which is less than its threshold voltage VT of 0.4V. The voltage VPCTL_LV is at a low logic voltage of VSS (0V). Thus, since the inputs to the NOR gate 322 are high and low logic voltages, the NOR gate 322 generates a low logic voltage, and the inverter 324 outputs VPBIAS as a relatively high bias voltage VDDIX (1.8V), as indicated in the timing diagram of FIG. 3B.
When the output voltage VPAD is to be transitioned from the high logic voltage VDDPX (3.6V) to a low logic voltage VSS (0V), the control voltage VNCTL_HV is raised to a logic high voltage VDDPX (3.6V) and VPCTL_LV is raised to a high logic voltage VDDIX (1.8V). Accordingly, the inputs to the NAND gate 312 are both at high logic voltages; and thus, the NAND gate 312 outputs a low logic voltage and the inverter 314 outputs VNBIAS as a relatively high bias voltage VDDPX (3.6V). As previously discussed, VNBIAS being high configures the NMOS MN22 of I/O driver 200 to have similar resistance as the resistance of NMOS MN21 so that the voltages across the devices MN21 and MN22 are substantially equal to prevent an over-voltage of the devices.
When the output voltage VPAD has decreased to a defined voltage where VPAD_HV is interpreted by the NAND gate 312 as a low logic voltage, the inputs to the NAND gate 312 are at low and high logic voltages; and accordingly, the NAND gate 312 generates a high logic voltage, and the inverter 314 outputs VNBIAS as a relatively low bias voltage VDDIX (1.8V). At such time, the output voltage VPAD has sufficiently decreased to prevent over-voltage of NMOS MN22 and MN21 of I/O driver 200. PMOS MP32 turns on when the output voltage VPAD has decreased to substantially VDDIX−VT (threshold of MP32) and PMOS MP31 turns off when the output voltage VPAD has decreased to VDDIX+VT (threshold of MP31).
Thus, as indicated in the timing diagram of FIG. 3B, the bias voltage VNBIAS is temporarily raised during an initial portion or discharge subinterval of the transition of the output voltage VPAD from high-to-low to prevent an over-voltage condition of NMOS MN22 and MN21. The time interval in which VNBIAS is at the raised state depends on when the voltage VPAD_HV becomes a low logic voltage as interpreted by the NAND gate 312. The output voltage VPAD decreases at a rate that depends on the capacitive load CLOAD; e.g., small capacitive load CLOAD, faster rate of decrease for VPAD, larger capacitive load CLOAD, slower rate of decrease for VPAD. Thus, the bias voltage VNBIAS is held at the raised state for sufficient amount of time to prevent an over-voltage NMOS MN22 due to VDS being above the reliability limit if VNBIAS is otherwise brought to a lower bias voltage too early, and prevent an over-voltage of NMOS MN22 due to VGS and/or VGD being above the reliability limit if VNBIAS is otherwise kept at the higher bias voltage for too long.
As indicated in the timing diagram of FIG. 3B, during the transition of the output voltage VPAD from high-to-low, the bias voltage VPBIAS remains at the relatively high bias voltage VDDIX (1.8V). This is because the control voltage VPCTL_LV is raised to a high logic voltage VDDIX (1.8V) during the transition of the output voltage VPAD from high-to-low. In response to the high logic voltage VPCTL_LV; the NOR gate 322 generates a low logic voltage, and the inverter 324 maintains VPBIAS at the relatively high bias voltage VDDIX (1.8V).
When the output voltage VPAD is to be transitioned from the low logic voltage VSS (0V) to a high logic voltage VDDPX (3.6V), the control voltage VPCTL_LV is lowered to a low logic voltage VSS (0V) and control voltage VNCTL_HV is lowered to a low logic voltage VDDIX (1.8V). Accordingly, the inputs to the NOR gate 322 are both at low logic voltages; and thus, the NOR gate 322 outputs a high logic voltage and the inverter 324 outputs VPBIAS as a relatively low bias voltage VSS (0V). As previously discussed, VPBIAS being low configures the PMOS MP22 of I/O driver 200 to have similar resistance as the resistance of PMOS MP21 so that the voltages across the devices MP21 and MP22 are substantially equal to prevent an over-voltage of the devices.
When the output voltage VPAD has increased to a defined voltage where VPAD_LV is interpreted by the NOR gate 322 as a high logic voltage, the NOR gate 322 generates a low logic voltage, and the inverter 324 outputs VPBIAS as a relatively high bias voltage VDDIX (1.8V). At such time, the output voltage VPAD has sufficiently increased to prevent over-voltage of PMOS MP22 and MP21 of I/O driver 200. NMOS MN31 turns off when the output voltage VPAD has increased to substantially VDDIX−VT (threshold of MN31) and NMOS MP32 turns on when the output voltage VPAD has increased to VDDIX+VT (threshold of MN32).
Thus, as indicated in the timing diagram of FIG. 3B, the bias voltage VPBIAS is temporarily lowered during an initial portion or charge subinterval of the transition of the output voltage VPAD from low-to-high to prevent an over-voltage condition of PMOS MP22 and MP21. The time interval in which VPBIAS is at the lowered state depends on when the voltage VPAD_LV becomes a high logic voltage as interpreted by the NOR gate 322. The output voltage VPAD increases at a rate that depends on the capacitive load CLOAD; e.g., small capacitive load CLOAD, faster rate of increase for VPAD; larger capacitive load CLOAD, slower rate of increase for VPAD. Thus, the bias voltage VPBIAS is held at the raised state for sufficient amount of time to prevent an over-voltage PMOS MP22 due to VDS being above the reliability limit if VPBIAS is otherwise brought to a high bias voltage too early, and prevent an over-voltage of PMOS MP22 due to VGS and/or VGD being above the reliability limit if VPBIAS is otherwise kept at the low bias voltage for too long.
As indicated in the timing diagram of FIG. 3B, during the transition of the output voltage VPAD from low-to-high, the bias voltage VNBIAS remains at the relatively low bias voltage VDDIX (1.8V). This is because the control voltage VNCTL_HV is lowered to a low logic voltage VSS (0V) during the transition of the output voltage VPAD from low-to-high. In response to the logic high voltage VNCTL_HV, the NAND gate 312 generates a high logic voltage, and the inverter 314 maintains VNBIAS at the relatively low bias voltage VDDIX (1.8V).
FIG. 4 illustrates a schematic diagram of an exemplary bias voltage generator 400 including VPI voltage generator 410 and VNI voltage generator 420. The VPI and VNI voltage generators 410 and 420 may be one exemplary detailed implementation of the VPI and VNI voltage generators 214 and 224 of I/O driver 200, respectively. As previously discussed, the VPI voltage generator 410 is configured to generate a defined voltage VPI at VDDIX (1.8V) when the output voltage VPAD is at steady-state low logic voltage VSS (0V). This is to protect PMOS MP22 from an over-voltage condition. Similarly, the VNI voltage generator 420 is configured to generate a defined voltage VNI at VDDIX (1.8V) when the output voltage VPAD is at steady-state high logic voltage VDDPX (3.6V). This is to protect NMOS MN22 from an over-voltage condition. This applies to both situations: (1) when the I/O driver 200 is driving the output voltage VPAD, and (2) when the I/O driver 200 is presenting high impedance at the output and another device is driving the output voltage VPAD.
In particular, the VPI voltage generator 410 includes a PMOS MP41, a PMOS MP42, and an NMOS MN43. The PMOS MP41 includes source and drain coupled between the output (VPAD) of the I/O driver 200 and a drain of NMOS MN43. The gate of PMOS MP41 is configured to receive the constant bias voltage VDDIX. The PMOS MP42 includes source and drain coupled between a source of the constant bias voltage VDDIX and the drain of NMOS MN43. The gate of PMOS MP42 is coupled to the output (VPAD) of the I/O driver 200. The gate of NMOS MN43 is configured to receive the control voltage VPCTL_HV. The defined voltage VPI is generated at the source of MN43.
The VNI voltage generator 420 includes an NMOS MN41, an NMOS MN42, and a PMOS MP43. The NMOS MN41 includes drain and source coupled between the output (VPAD) of the I/O driver 200 and a drain of PMOS MP43. The gate of MN41 is configured to receive the constant bias voltage VDDIX. The NMOS MN42 includes source and drain coupled between the source of the constant bias voltage VDDIX and the drain of PMOS MP43. The gate of NMOS MN42 is coupled to the output (VPAD) of the I/O driver 200. The gate of PMOS MP43 is configured to receive the control voltage VNCTL_LV. The bias voltage VNI is generated at the source of MP43.
The circuit including PMOS MP41 and MP42 and NMOS MN41 and MN42 operate as a waveform splitter. That is, as discussed, the voltage domain for the output voltage VPAD has high and low logic voltages at VDDPX and VSS, respectively. The portion of the waveform splitter having PMOS MP41 and MP42 generates the signal VPAD_HV that tracks the high and low logic voltages of the output voltage VPAD but in a different voltage domain having high and low voltages at VDDPX and VDDIX, respectively. Similarly, the portion of the waveform splitter having NMOS MN41 and MN42 generates the signal VPAD_LV that tracks the high and low logic voltages of the output voltage VPAD but in a different voltage domain having high and low voltages at VDDIX and VSS, respectively.
Considering first the case where the I/O driver 200 is driving the output voltage VPAD to a high logic voltage VDDPX (3.6V). In such case, the control voltages VPCTL_HV and VNCTL_LV are at low logic voltages VDDIX (1.8V) and VSS (0V), respectively. With regard to VPI voltage generator 410, PMOS MP41 is turned on, PMOS MP42 is turned off, and NMOS MN43 is effectively turned off. Thus, the defined voltage VPI is at VDDPX (3.6V) due to the turned on PMOS MP11 and MP22 of the pull-up circuit. With regard to VNI voltage generator 420, NMOS MN42 is turned on, NMOS MN41 is turned off, and PMOS MP43 is turned on. Thus, the defined voltage VNI is at VDDIX (1.8V) via the turned on MN42 and MP43. The defined voltage VNI (1.8V) at the source of NMOS MN22 protects the device from over-voltage when the output voltage VPAD is driven to a high logic voltage VDDPX (3.6V) by the I/O driver 200.
Considering next the case where the I/O driver 200 is driving the output voltage VPAD to a low logic voltage VSS (0V). In such case, the control voltages VPCTL_HV and VNCTL_LV are at high logic voltages VDDPX (3.6V) and VDDIX (1.8V), respectively. With regard to VNI voltage generator 420, NMOS MN42 is turned off, NMOS MN41 is turned on, and PMOS MP43 is effectively turned off. Thus, the defined voltage VNI is at 0V (VPAD) via the turned on MN21 and MN22 of the pull-down circuit. With regard to VPI voltage generator 410, PMOS MP41 is turned off, PMOS MP42 is turned on, and NMOS MN43 is turned on. Thus, the voltage VPI is at VDDIX (1.8V) via the turned on MP42 and MN43. The defined voltage VPI (1.8V) at the source of PMOS MP22 protects the device from over-voltage when the output voltage VPAD driven to a low logic voltage VSS (0V) by the I/O driver 200.
Considering next the case where the I/O driver 200 is providing high impedance at the output and another device is driving the output voltage VPAD to a high logic voltage VDDPX (3.6V). In such case, the control voltages VPCTL_HV and VNCTL_LV are at a high logic voltage VDDPX (3.6V) and a low logic voltage VSS (0V), respectively. With regard to VPI voltage generator 410, PMOS MP41 is turned on, PMOS MP42 is turned off, and NMOS MN43 is turned on. Thus, the defined voltage VPI is at VDDPX (3.6V) via the turned on MP41 and MN43. With regard to VNI voltage generator 420, NMOS MN42 is turned on, NMOS MN41 is turned off, and PMOS MP43 is turned on. Thus, the defined voltage VNI is at VDDIX (1.8V) via the turned on MN42 and MP43. The defined voltage VNI (1.8V) at the source of NMOS MN22 protects the device from over-voltage when the output voltage VPAD driven to VDDPX (3.6V) by another device.
Considering next the case where the I/O driver 200 is providing a high impedance at the output and another device is driving the output voltage VPAD to a low logic voltage VSS (0V). In such case, the voltages VPCTL_HV and VNCTL_LV are at high logic voltage VDDPX (3.6V) and low logic voltage VDDIX (1.8V), respectively. With regard to VNI voltage generator 420, NMOS MN42 is turned off, NMOS MN41 is turned on, and PMOS MP43 is turned on. Thus, the voltage VNI is at VSS (0V) via turned on MN41 and MP43. With regard to VPI voltage generator 410, PMOS MP41 is turned off, PMOS MP42 is turned on, and NMOS MN43 is turned on. Thus, the defined voltage VPI is at VDDIX (1.8V) via the turned on MP42 and MN43. The defined voltage VPI (1.8V) at the source of PMOS MP22 protects the device from over-voltage when the output voltage VPAD driven to a low logic voltage VSS (0V) by another device.
FIG. 5A illustrates a schematic diagram of an exemplary predriver 500 in accordance with another aspect of the disclosure. The predriver 500 may be an exemplary detailed implementation of the first PMOS predriver 210 previously discussed.
In summary, the predriver 500 generates the control signal VPCTL_HV based on an input signal VIN. That is, based on an enable signal EN being asserted, the predriver 500 generates the control signal VPCTL_HV at a high logic voltage (VDDPX) in a first voltage domain in response to the input signal VIN being at a low logic voltage in a second voltage domain. Similarly, based on the enable signal EN being asserted, the predriver 500 generates the control signal VPCTL_HV at a low logic voltage (VDDIX) in the first voltage domain in response to the input signal VIN being at a high logic voltage in the second voltage domain. Based on the enable signal EN not being asserted, the predriver 500 generates the control signal VPCTL_HV at the high logic voltage (VDDPX) regardless of the logic state of the input signal VIN.
In particular, the predriver 500 includes a level shifter 505 and an inverter 510. The inverter 510, in turn, includes a first transistor (e.g., PMOS) MP51 and a second transistor (e.g., NMOS) MN51 coupled in series between a first voltage rail (VDDPX) and a second voltage rail (VDDIX). The control terminals (e.g., gates) of the PMOS MP51 and NMOS MN51 are coupled together, and to an output of the level shifter 505. The predriver 500 is configured to generate the control signal VPCTL_HV at a node between (e.g., drains of) the PMOS MP51 and NMOS MN51. The level shifter 505 includes a signal input configured to receive the input signal VIN and a control input configured to receive the enable signal EN. As previously discussed, the level shifter 505 includes a signal output coupled to the gates of PMOS MP51 and NMOS MN51.
In operation, when the enable signal EN is asserted, the level shifter 505 generates an output signal to turn on PMOS MP51 and turn off NMOS MN51 in response to the input signal VIN being at a low logic voltage. This causes the control signal VPCTL_HV to be substantially at the high logic voltage of VDDPX. Also, when the enable signal EN is asserted, the level shifter 505 generates an output signal to turn off PMOS MP51 and turn on NMOS MN51 in response to the input signal VIN being at a high logic voltage. This causes the control signal VPCTL_HV to be substantially at the low logic voltage of VDDIX. When the enable signal EN is not asserted, the level shifter 505 generates an output signal to turn on PMOS MP51 and turn off NMOS MN51 regardless of the logic state of the input signal VIN. This causes the control signal VPCTL_HV to be maintained substantially at the high logic voltage of VDDPX when the enable signal EN is not asserted.
FIG. 5B illustrates a schematic diagram of another exemplary predriver 520 in accordance with another aspect of the disclosure. The predriver 520 may be an exemplary detailed implementation of the second PMOS predriver 211 previously discussed.
In summary, the predriver 520 generates the control signal VPCTL_LV based on an input signal VIN. That is, based on an enable signal EN being asserted, the predriver 520 generates the control signal VPCTL_HV at a high logic voltage (VDDIX) in a third voltage domain in response to the input signal VIN being at a low logic voltage in the second voltage domain. Similarly, based on the enable signal EN being asserted, the predriver 520 generates the control signal VPCTL_LV at a low logic voltage (VSS) in the third voltage domain in response to the input signal VIN being at a high logic voltage in the second voltage domain. Based on the enable signal EN not being asserted, the predriver 520 generates the control signal VPCTL_LV at the high logic voltage (VDDIX) regardless of the logic state of the input signal VIN.
In particular, the predriver 520 includes a level shifter 525 and an inverter 530. The inverter 530, in turn, includes a first transistor (e.g., PMOS) MP52 and a second transistor (e.g., NMOS) MN52 coupled in series between a first voltage rail (VDDIX) and a second voltage rail (VSS). The control terminals (e.g., gates) of the PMOS MP52 and NMOS MN52 are coupled together, and to an output of the level shifter 525. The predriver 520 is configured to generate the control signal VPCTL_LV at a node between (e.g., drains of) the PMOS MP52 and NMOS MN52. The level shifter 525 includes a signal input configured to receive the input signal VIN and a control input configured to receive the enable signal EN. As previously discussed, the level shifter 525 includes a signal output coupled to the gates of PMOS MP52 and NMOS MN52.
In operation, when the enable signal EN is asserted, the level shifter 525 generates an output signal to turn on PMOS MP52 and turn off NMOS MN52 in response to the input signal VIN being at a low logic voltage. This causes the control signal VPCTL_LV to be substantially at the high logic voltage of VDDIX. Also, when the enable signal EN is asserted, the level shifter 525 generates an output signal to turn off PMOS MP52 and turn on NMOS MN52 in response to the input signal VIN being at a high logic voltage. This causes the control signal VPCTL_LV to be substantially at the low logic voltage of VSS. When the enable signal EN is not asserted, the level shifter 525 generates an output signal to turn on PMOS MP52 and turn off NMOS MN52 regardless of the logic state of the input signal VIN. This causes the control signal VPCTL_LV to be maintained substantially at the high logic voltage of VDDIX when the enable signal EN is not asserted.
FIG. 5C illustrates a schematic diagram of another exemplary predriver 540 in accordance with another aspect of the disclosure. The predriver 540 may be an exemplary detailed implementation of the first NMOS predriver 220 previously discussed.
In summary, the predriver 540 generates the control signal VNCTL_LV based on an input signal VIN. That is, based on an enable signal EN being asserted, the predriver 540 generates the control signal VNCTL_LV at a high logic voltage (VDDIX) in the third voltage domain in response to the input signal VIN being at a low logic voltage in the second voltage domain. Similarly, based on the enable signal EN being asserted, the predriver 540 generates the control signal VNCTL_LV at a low logic voltage (VSS) in the third voltage domain in response to the input signal VIN being at a high logic voltage in the second voltage domain. Based on the enable signal EN not being asserted, the predriver 540 generates the control signal VNCTL_LV at the low logic voltage (VSS) regardless of the logic state of the input signal VIN.
In particular, the predriver 540 includes a level shifter 545 and an inverter 550. The inverter 550, in turn, includes a first transistor (e.g., PMOS) MP53 and a second transistor (e.g., NMOS) MN53 coupled in series between a first voltage rail (VDDIX) and a second voltage rail (VSS). The control terminals (e.g., gates) of the PMOS MP53 and NMOS MN53 are coupled together, and to an output of the level shifter 545. The predriver 540 is configured to generate the control signal VNCTL_LV at a node between (e.g., drains of) the PMOS MP53 and NMOS MN53. The level shifter 545 includes a signal input configured to receive the input signal VIN and a control input configured to receive the enable signal EN. As previously discussed, the level shifter 545 includes a signal output coupled to the gates of PMOS MP53 and NMOS MN53.
In operation, when the enable signal EN is asserted, the level shifter 545 generates an output signal to turn on PMOS MP53 and turn off NMOS MN53 in response to the input signal VIN being at a low logic voltage. This causes the control signal VNCTL_LV to be substantially at the high logic voltage of VDDIX. Also, when the enable signal EN is asserted, the level shifter 545 generates an output signal to turn off PMOS MP53 and turn on NMOS MN53 in response to the input signal VIN being at a high logic voltage. This causes the control signal VNCTL_LV to be substantially at the low logic voltage of VSS. When the enable signal EN is not asserted, the level shifter 545 generates an output signal to turn off PMOS MP53 and turn on NMOS MN53 regardless of the logic state of the input signal VIN. This causes the control signal VNCTL_LV to be maintained substantially at the low logic voltage of VSS when the enable signal EN is not asserted.
FIG. 5D illustrates a schematic diagram of an exemplary predriver 560 in accordance with another aspect of the disclosure. The predriver 560 may be an exemplary detailed implementation of the second NMOS predriver 221 previously discussed.
In summary, the predriver 560 generates the control signal VNCTL_HV based on an input signal VIN. That is, based on an enable signal EN being asserted, the predriver 560 generates the control signal VNCTL_HV at a high logic voltage (VDDPX) in the first voltage domain in response to the input signal VIN being at a low logic voltage in the second voltage domain. Similarly, based on the enable signal EN being asserted, the predriver 560 generates the control signal VNCTL_HV at a low logic voltage (VDDIX) in the first voltage domain in response to the input signal VIN being at a high logic voltage in the second voltage domain. Based on the enable signal EN not being asserted, the predriver 560 generates the control signal VNCTL_HV at the low logic voltage (VDDIX) regardless of the logic state of the input signal VIN.
In particular, the predriver 560 includes a level shifter 565 and an inverter 570. The inverter 570, in turn, includes a first transistor (e.g., PMOS) MP54 and a second transistor (e.g., NMOS) MN54 coupled in series between a first voltage rail (VDDPX) and a second voltage rail (VDDIX). The control terminals (e.g., gates) of the PMOS MP54 and NMOS MN54 are coupled together, and to an output of the level shifter 565. The predriver 560 is configured to generate the control signal VNCTL_HV at a node between (e.g., drains of) the PMOS MP54 and NMOS MN54. The level shifter 565 includes a signal input configured to receive the input signal VIN and a control input configured to receive the enable signal EN. As previously discussed, the level shifter 565 includes a signal output coupled to the gates of PMOS MP54 and NMOS MN54.
In operation, when the enable signal EN is asserted, the level shifter 565 generates an output signal to turn on PMOS MP54 and turn off NMOS MN54 in response to the input signal VIN being at a low logic voltage. This causes the control signal VNCTL_HV to be substantially at the high logic voltage of VDDPX. Also, when the enable signal EN is asserted, the level shifter 565 generates an output signal to turn off PMOS MP54 and turn on NMOS MN54 in response to the input signal VIN being at a high logic voltage. This causes the control signal VNCTL_HV to be substantially at the low logic voltage of VDDIX. When the enable signal EN is not asserted, the level shifter 565 generates an output signal to turn off PMOS MP54 and turn on NMOS MN54 regardless of the logic state of the input signal VIN. This causes the control signal VNCTL_HV to be maintained substantially at the low logic voltage of VDDIX when the enable signal EN is not asserted.
FIG. 6 illustrates a flow diagram of an exemplary method 600 of generating an output voltage based on an input voltage in accordance with another aspect of the disclosure. The method 600 includes coupling a first voltage rail to an output by turning on a first transistor and a second transistor coupled in series between the first voltage rail and the output in response to an input voltage transitioning from a first low logic voltage to a first high logic voltage (block 602). An examples of means for coupling the first voltage rail to the output include the pull-up circuit with PMOS MP21 and MP22 coupled in series between the voltage rail (VDDPX) and the output (VPAD) in I/O driver 200 depicted in FIG. 2A.
The method 600 further includes decoupling a second voltage rail from the output by turning off a third transistor and a fourth transistor coupled in series between the output and the second voltage rail in response to the input voltage transitioning from the first low logic voltage to the first high logic voltage, wherein a voltage at the output transitions from a second low logic voltage towards a second high logic voltage in response to the coupling of the first voltage rail to the output and the decoupling of the second voltage rail from the output (block 604). An example of means for decoupling a second voltage rail from the output include the pull-down circuit with NMOS MN22 and MN21 coupled in series between the output (VPAD) and the voltage rail (VSS) in I/O driver 200 depicted in FIG. 2A.
Additionally, the method 600 includes coupling the second voltage rail to the output by turning on the third transistor and the fourth transistor in response to the input signal transitioning from the first high logic voltage to the first low logic voltage (block 606). An example of means for coupling the second voltage rail to the output include the pull-down circuit with NMOS MN22 and MN21 coupled in series between the output (VPAD) and the voltage rail (VSS) in I/O driver 200 depicted in FIG. 2A.
Further, the method 600 includes decoupling the first voltage rail from the output by turning off the first transistor and the second transistor in response to the input signal transitioning from the first high logic voltage to the low logic voltage, wherein the output voltage transitions from the second high logic voltage towards the second low logic voltage in response to the coupling of the second voltage rail to the output and the decoupling of the first voltage rail from the output (block 608). An examples of means for decoupling the first voltage rail from the output include the pull-up circuit with PMOS MP21 and MP22 coupled in series between the voltage rail (VDDPX) and the output (VPAD) in I/O driver 200 depicted in FIG. 2A.
The method 600 also includes transitioning a first bias voltage applied to a control input of the second transistor from a first relatively high voltage to a first relatively low voltage approximately when the output voltage begins transitioning from the second low logic voltage towards the second high logic voltage (block 610). Examples of such means for transitioning a first bias voltage include the VPBIAS voltage generators 212 and 320 depicted in FIGS. 2A and 3A, respectively.
The method 600 further includes transitioning the first bias voltage from the first relatively low voltage to the first relatively high voltage while the output voltage continues to transition from the second low logic voltage towards the second high logic voltage (block 612). Examples of such means for transitioning the first bias voltage include the VPBIAS voltage generators 212 and 320 depicted in FIGS. 2A and 3A, respectively.
In addition, the method 600 includes transitioning a second bias voltage applied to a control input of the third transistor from a second relatively low voltage to a second relatively high voltage approximately when the output voltage begins transitioning from the second high logic voltage towards the low logic voltage (block 614). Examples of such means for transitioning a second bias voltage include the VNBIAS voltage generators 222 and 310 depicted in FIGS. 2A and 3A, respectively.
The method 600 also includes transitioning the second bias voltage from the second relatively high voltage to the second relatively low voltage while the output voltage continues to transition from the second high logic voltage towards the second low logic voltage (block 616). Examples of such means for transitioning the second bias voltage include the VNBIAS voltage generators 222 and 310 depicted in FIGS. 2A and 3A, respectively.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

## Claims

1. An apparatus, comprising:
a pull-up circuit including a first transistor and a second transistor coupled in series between a first voltage rail and an output;
a pull-down circuit including a third transistor and a fourth transistor coupled in series between the output and a second voltage rail;
a first voltage generator configured to generate a first bias voltage responsive to a voltage at the output, wherein a control input of the second transistor is configured to receive the first bias voltage, the first bias voltage configured to transition from a first relatively high voltage to a first relatively low voltage approximately when the voltage at the output begins transitioning from a first low logic voltage towards a first high logic voltage due to the pull-up circuit coupling the first voltage rail to the output and the pull-down circuit decoupling the output from the second voltage rail, and the first bias voltage also configured to transition from the first relatively low voltage to the first relatively high voltage while the output voltage continues to transition from the first low logic voltage towards the first high logic voltage; and
a second voltage generator configured to generate a second bias voltage responsive to the voltage at the output, wherein a control input of the third transistor is configured to receive the second bias voltage, the second bias voltage configured to transition from a second relatively low voltage to a second relatively high voltage approximately when the output voltage begins transitioning from the first high logic voltage towards the first low logic voltage due to the pull-down circuit coupling the output to the second voltage rail and the pull-up circuit decoupling the first voltage rail from the output, and the second bias voltage also configured to transition from the second relatively high voltage to the second relatively low voltage while the output voltage continues to transition from the first high logic voltage towards the first low logic voltage.

2. The apparatus of claim 1, wherein a time interval beginning with the first bias voltage transitioning from the first relatively high voltage to the first relatively low voltage and ending with the first bias voltage transitioning from the first relatively low voltage to the first relatively high voltage is a function of a rate at which the output voltage transitions from the first low logic voltage towards the first high logic voltage.

3. The apparatus of claim 1, wherein a time interval beginning with the second bias voltage transitioning from the second relatively low voltage to the second relatively high voltage and ending with the second bias voltage transitioning from the second relatively high voltage to the second relatively low voltage is a function of a rate at which the output voltage transitions from the first high logic voltage towards the first low logic voltage.

4. The apparatus of claim 1, wherein the first bias voltage is configured to transition from the first relatively low voltage to the first relatively high voltage in response to the output voltage increasing to a defined voltage level.

5. The apparatus of claim 1, wherein the second bias voltage is configured to transition from the second relatively high voltage to the second relatively low voltage in response to the output voltage decreasing to a defined voltage level.

6. The apparatus of claim 1, further comprising a predriver configured to generate a third voltage, the third voltage configured to transition from a second high logic voltage to a second low logic voltage in response to an input voltage transitioning from a third low logic voltage to a third high logic voltage, wherein the first bias voltage is configured to transition from the first relatively high voltage to the first relatively low voltage in response to the third voltage transitioning from the second high logic voltage to the second low logic voltage.

7. The apparatus of claim 1, further comprising a predriver configured to generate a third voltage, the third voltage configured to transition from a second low logic voltage to a second high logic voltage in response to an input voltage transitioning from a third high logic voltage to a third low logic voltage, wherein the second bias voltage is configured to transition from the second relatively low voltage to the second relatively high voltage in response to the third voltage transitioning from the second low logic voltage to the second low logic voltage.

8. The apparatus of claim 1, wherein the first relatively high voltage is different than the second relatively high voltage, and wherein the first relatively low voltage is different than the second relatively low voltage.

9. The apparatus of claim 1, further comprising a third voltage generator configured to generate a third voltage applied to a node between the first transistor and the second transistor in response to the output voltage transitioning to or being at the first low logic voltage, wherein the third voltage is substantially halfway between the first high logic voltage and the first low logic voltage.

10. The apparatus of claim 1, further comprising a third voltage generator configured to generate a third voltage applied to a node between the third transistor and the fourth transistor in response to the output voltage transitioning to or being at the first high logic voltage, wherein the third voltage is substantially halfway between the first high logic voltage and the first low logic voltage.

11. A method, comprising:
coupling a first voltage rail to an output by turning on a first transistor and a second transistor coupled in series between the first voltage rail and the output in response to an input voltage transitioning from a first low logic voltage to a first high logic voltage;
decoupling a second voltage rail from the output by turning off a third transistor and a fourth transistor coupled in series between the output and the second voltage rail in response to the input voltage transitioning from the first low logic voltage to the first high logic voltage, wherein a voltage at the output transitions from a second low logic voltage towards a second high logic voltage in response to the coupling of the first voltage rail to the output and the decoupling of the second voltage rail from the output;
coupling the second voltage rail to the output by turning on the third transistor and the fourth transistor in response to the input signal transitioning from the first high logic voltage to the first low logic voltage;
decoupling the first voltage rail from the output by turning off the first transistor and the second transistor in response to the input signal transitioning from the first high logic voltage to the low logic voltage, wherein the output voltage transitions from the second high logic voltage towards the second low logic voltage in response to the coupling of the second voltage rail to the output and the decoupling of the first voltage rail from the output;
transitioning a first bias voltage applied to a control input of the second transistor from a first relatively high voltage to a first relatively low voltage approximately when the output voltage begins transitioning from the second low logic voltage towards the second high logic voltage;
transitioning the first bias voltage, responsive to the voltage at the output, from the first relatively low voltage to the first relatively high voltage while the output voltage continues to transition from the second low logic voltage towards the second high logic voltage;
transitioning a second bias voltage applied to a control input of the third transistor from a second relatively low voltage to a second relatively high voltage approximately when the output voltage begins transitioning from the second high logic voltage towards the low logic voltage; and
transitioning the second bias voltage, responsive to the voltage at the output, from the second relatively high voltage to the second relatively low voltage while the output voltage continues to transition from the second high logic voltage towards the second low logic voltage.

12. The method of claim 11, wherein a time interval beginning with the first bias voltage transitioning from the first relatively high voltage to the first relatively low voltage and ending with the first bias voltage transitioning from the first relatively low voltage to the first relatively high voltage is a function of a rate at which the output voltage transitions from the second low logic voltage towards the second high logic voltage.

13. The method of claim 11, wherein a time interval beginning with the second bias voltage transitioning from the second relatively low voltage to the second relatively high voltage and ending with the second bias voltage transitioning from the second relatively high voltage to the second relatively low voltage is a function of a rate at which the output voltage transitions from the second high logic voltage towards the second low logic voltage.

14. The method of claim 11, wherein the first bias voltage is configured to transition from the first relatively low voltage to the first relatively high voltage in response to the output voltage increasing to a defined voltage level.

15. The method of claim 11, wherein the second bias voltage is configured to transition from the second relatively high voltage to the second relatively low voltage in response to the output voltage decreasing to a defined voltage level.

16. The method of claim 11, further comprising transitioning a third voltage from a third high logic voltage to a third low logic voltage in response to the input voltage transitioning from the first low logic voltage to the first high logic voltage, wherein the first bias voltage is configured to transition from the first relatively high voltage to the first relatively low voltage in response to the third voltage transitioning from the third high logic voltage to the third low logic voltage.

17. The method of claim 11, further comprising transitioning a third voltage from a third low logic voltage to a third high logic voltage in response to the input voltage transitioning from the first high logic voltage to the first low logic voltage, wherein the second bias voltage is configured to transition from the second relatively low voltage to the second relatively high voltage in response to the third voltage transitioning from the third high logic voltage to the third low logic voltage.

18. The method of claim 11, wherein the first relatively high voltage is different than the second relatively high voltage, and wherein the first relatively low voltage is different than the second relatively low voltage.

19. The method of claim 11, further comprising generating a third voltage applied to a node between the first transistor and the second transistor in response to the output voltage transitioning to or being at the second low logic voltage, wherein the third voltage is substantially halfway between the second high logic voltage and the second low logic voltage.

20. The method of claim 11, further comprising generating a third voltage applied to a node between the third transistor and the fourth transistor in response to the output voltage transitioning to or being at the second high logic voltage, wherein the third voltage is substantially halfway between the second high logic voltage and the second low logic voltage.

21. An apparatus, comprising:
means for coupling a first voltage rail to an output by turning on a first transistor and a second transistor coupled in series between the first voltage rail and the output in response to an input voltage transitioning from a first low logic voltage to a first high logic voltage;
means for decoupling a second voltage rail from the output by turning off a third transistor and a fourth transistor coupled in series between the output and the second voltage rail in response to the input voltage transitioning from the first low logic voltage to the first high logic voltage, wherein a voltage at the output transitions from a second low logic voltage towards a second high logic voltage in response to the coupling of the first voltage rail to the output and the decoupling of the second voltage rail from the output;
means for coupling the second voltage rail to the output by turning on the third transistor and the fourth transistor in response to the input signal transitioning from the first high logic voltage to the first low logic voltage;
means for decoupling the first voltage rail from the output by turning off the first transistor and the second transistor in response to the input signal transitioning from the first high logic voltage to the first low logic voltage, wherein the output voltage transitions from the second high logic voltage towards the second low logic voltage in response to the coupling of the second voltage rail to the output and the decoupling of the first voltage rail from the output;
means for transitioning a first bias voltage applied to a control input of the second transistor from a first relatively high voltage to a first relatively low voltage approximately when the output voltage begins transitioning from the second low logic voltage towards the second high logic voltage;
means for transitioning the first bias voltage, responsive to the voltage at the output, from the first relatively low voltage to the first relatively high voltage while the output voltage continues to transition from the second low logic voltage towards the second high logic voltage;
means for transitioning a second bias voltage applied to a control input of the third transistor from a second relatively low voltage to a second relatively high voltage approximately when the output voltage begins transitioning from the second high logic voltage to the second low logic voltage; and
means for transitioning the second bias voltage, responsive to the voltage at the output, from the second relatively high voltage to the second relatively low voltage while the output voltage continues to transition from the second high logic voltage towards the second low logic voltage.

22. The apparatus of claim 21, wherein a time interval beginning with the first bias voltage transitioning from the first relatively high voltage to the first relatively low voltage and ending with the first bias voltage transitioning from the first relatively low voltage to the first relatively high voltage is a function of a rate at which the output voltage transitions from the second low logic voltage towards the second high logic voltage.

23. The apparatus of claim 21, wherein a time interval beginning with the second bias voltage transitioning from the second relatively low voltage to the second relatively high voltage and ending with the second bias voltage transitioning from the second relatively high voltage to the second relatively low voltage is a function of a rate at which the output voltage transitions from the second high logic voltage towards the second low logic voltage.

24. The apparatus of claim 21, wherein the first bias voltage is configured to transition from the first relatively low voltage to the first relatively high voltage in response to the output voltage increasing to a defined voltage level.

25. The apparatus of claim 21, wherein the second bias voltage is configured to transition from the second relatively high voltage to the second relatively low voltage in response to the output voltage decreasing to a defined voltage level.

26. The apparatus of claim 21, further comprising means for transitioning a third voltage from a third high logic voltage to a third low logic voltage in response to the input voltage transitioning from the first low logic voltage to the first high logic voltage, wherein the first bias voltage is configured to transition from the first relatively high voltage to the first relatively low voltage in response to the third voltage transitioning from the third high logic voltage to the third low logic voltage.

27. The apparatus of claim 21, further comprising means for transitioning a third voltage from a third low logic voltage to a third high logic voltage in response to the input voltage transitioning from the first high logic voltage to the first low logic voltage, wherein the second bias voltage is configured to transition from the second relatively low voltage to the second relatively high voltage in response to the third voltage transitioning from the third high logic voltage to the third low logic voltage.

28. The apparatus of claim 21, wherein the first relatively high voltage is different than the second relatively high voltage, and wherein the first relatively low voltage is different than the second relatively low voltage.

29. The apparatus of claim 21, further comprising means for generating a third voltage applied to a node between the first transistor and the second transistor in response to the output voltage transitioning to or being at the second low logic voltage, wherein the third voltage is substantially halfway between the second high logic voltage and the second low logic voltage.

30. The apparatus of claim 21, further comprising means for generating a third voltage applied to a node between the third transistor and the fourth transistor in response to the output voltage transitioning to or being at the second high logic voltage, wherein the third voltage is substantially halfway between the second high logic voltage and the second low logic voltage.