# Patent

## Title
Self-aligned metal oxide TFT with reduced number of masks and with reduced power consumption

## Abstract

A method of fabricating MO TFTs includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Depositing etch stop material on the semiconductor material. Positioning photoresist defining an isolation area in the semiconductor material, the etch stop material and the photoresist being selectively removable. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional application of currently pending U.S. application Ser. No. 14/071,644, filed 5 Nov. 2013, which is a continuation in part of U.S. application Ser. No. 13/564,746, filed 2 Aug. 2012, now issued as U.S. Pat. No. 8,592,817, issue date 26 Nov. 2013.


FIELD OF THE INVENTION
This invention generally relates to a self-alignment fabrication of metal oxide TFTs to remove critical alignment tools and a reduction in masks during manufacturing. The resulting MOTET array enables higher pixel density and lower power consumption.
BACKGROUND OF THE INVENTION
Metal oxide thin film transistors (MOTET) are gaining interest as high performance TFT backplanes for large area applications such as active matrix organic light emitting diodes (AMOLED). MOTFTs have gained popularity because of their high mobility in amorphous and/or nano-crystalline states and low fabrication temperature. The high mobility enables applications that require high performance such as integrated drivers, driving OLED displays. See for example the U.S. Pat. No. 7,977,868 entitled “Active Matrix Light Emitting Display”, and incorporated herein by reference. The amorphous and/or nano-crystalline nature enables short range uniformity which plagues poly-Si TFTs. The low fabrication temperature makes the MOTFTs attractive for large area flat panel displays (FPD) because they can be fabricated on low cost substrates and even achieve flexible FPDs.
Some remaining challenges are to reduce the parasitic gate-to-source and gate-to-drain capacitances. These capacitances become important with display frame rate, when the number of pixels in a row increase along with information content. Overlap between the gate and the source/drain regions leads to the parasitic gate-to-source and gate-to-drain capacitances. The overlap is necessary to insure that the channel is fully controlled by the gate. But an excessive overlap leads to the large parasitic capacitances. The degree of overlapping is determined by the alignment capability between the patterning of the gate layer, the channel layer, and the source/drain metal layer. There will be some degree of misalignment due to tool capability, which can also be eliminated by the present method. The other major misalignment, and that which is also addressed here, is due to substrate deformation (i.e. deformation of substrates in processing such as in glass substrates due to high temperature treatment or in plastic substrates due to an increase in moisture, chemical and heat treatment). Basically, the overlap is designed so that under the worst circumstance there will be overlap between the gate and the source/drain metal. For low cost FPDs the area of the substrates is large and the size of exposure field is also large. The misalignment is going to be relatively large over large substrates and thus large exposure fields. Large overlap designs are needed to compensate for all potential misalignments, thereby leading to large parasitic overlap capacitances.
Typically, misalignment due to deformation increases with the size of the exposure field. One way to compensate for the deformation is to reduce the exposure field by performing multiple exposures on the substrate and then stitching the multiple patterns together. However, this approach substantially increases the manufacturing cost due to lower through put and the high cost of stitching. Many of the large area applications use either glass or plastic substrates. To produce TFTs on large areas at low cost, it is advantageous to use low cost lithographic tools such as proximity/projection aligners/scanners rather than the more expensive stepper tools.
The large parasitic capacitances lead to slower waveforms (and thus limited number of pixels for a given frame time) and more power consumption. It is important therefore to reduce the parasitic capacitances while maintaining the minimum overlap between the gate and the source/drain to ensure that the channel is fully controlled by the gate. Also, these conditions have to be met over the large substrate areas regardless of substrate deformations and tool alignment capabilities.
Another item to be addressed herein is the cost of manufacturing the TFTs. Primarily, the cost of manufacturing TFTs depends on the number of masks used during the manufacturing process. Lithography is a big part of the fabrication cost. Therefore, a reduction in the number of masks (e.g. from four masks to three masks), while still achieving the self-alignment between the gate and the source/drain, or between the gate and the etch-stop, or between the S/D electrodes and the pixel electrode pad, can result in a major reduction in the overall cost.
It would be highly advantageous to have a self-aligned process in which there are no or fewer critical alignment steps.
Accordingly, it is an object of the present invention to provide new and improved methods of fabricating self-aligned metal oxide TFTs and thin film backpanel circuit.
It is another object of the present invention to provide new and improved methods of fabricating metal oxide TFTs and thin film backpanel circuit including no critical alignment tools or steps and using a minimum of process steps.
It is another object of the present invention to provide new and improved methods of fabricating self-aligned metal oxide TFTs and thin film backpanel circuit using a reduced number of masks.
It is another object of the present invention to provide new and improved methods of fabricating self-aligned metal oxide TFTs and thin film backpanel circuit with reduced inter-electrode capacitance.
It is another object of the present invention to provide a new and improved metal oxide TFT and thin film backpanel circuit with reduced inter-electrode capacitance.
It is another object of the present invention to provide a new and improved metal oxide TFT and thin film backpanel circuit with reduced alignment error and thus smaller channel length.
It is another object of the present invention to provide a new and improved method of making display backpanels with self-aligned metal oxide TFT with reduced inter-electrode capacitance.
It is another object of the present invention to provide a method of making high uniformity over large display area with phototools with low alignment accuracy.
SUMMARY OF THE INVENTION
Briefly, to achieve the desired objects of the instant invention in accordance with a preferred embodiment thereof, provided is a method of fabricating metal oxide TFTs on transparent substrates including the steps of providing a transparent substrate having a front surface and a rear surface, positioning opaque gate metal on the front surface of the substrate defining a gate area for a TFT, depositing a layer of transparent gate dielectric material on the front surface of the substrate overlying the gate metal and a surrounding area and a layer of transparent metal oxide semiconductor material on the surface of the layer of transparent gate dielectric.
The method further includes depositing a layer of etch stop material on the layer of metal oxide semiconductor material and positioning photoresist material on the layer of etch stop material. The etch stop material and the photoresist material are selectively removable and the photoresist material is one of patterned and selectively removed to define an isolation area in the layer of transparent metal oxide semiconductor material.
The method then includes removing uncovered portions of the layer of etch stop material, remaining portions of the layer of etch stop material forming a metal oxide semiconductor material etch mask and a step of exposing the photoresist material from the rear surface of the substrate using the opaque gate metal on the front surface of the substrate as a mask and removing exposed portions of the photoresist material so as to leave the layer of etch stop material uncovered except for a portion overlying and aligned with the gate metal.
Using the metal oxide semiconductor material etch mask, etching uncovered portions of the metal oxide semiconductor material so as to isolate the TFT and using the portion of the photoresist material directly overlying and aligned with the gate metal, selectively etching uncovered portions of the etch stop layer leaving a portion of the etch stop layer overlying and aligned with the gate metal. The portion of the etch stop layer defines a channel area in the layer of metal oxide semiconductor material and serves as a passivation layer for the metal oxide. The final step of the method is depositing and patterning conductive material on the portion of the etch stop layer overlying and aligned with the gate metal and on the layer of metal oxide semiconductor material to form source and drain areas on opposed sides of the channel area.
The metal oxide TFT has reduced inter-electrode capacitance generally because of the alignment of the etch stop layer with the gate metal substantially without regard to deformation of the substrate. Further, the metal oxide TFT has reduced inter-electrode capacitance generally because the etch stop layer is substantially thicker than the gate dielectric layer and the dielectric constant is substantially lower.
The desired objects of the instant invention are further realized in accordance with a preferred embodiment thereof, which provides a metal oxide TFT with reduced inter-electrode capacitance. The TFT includes a transparent substrate having a front surface and a rear surface, an opaque gate metal positioned on the front surface of the substrate and defining a gate area for a TFT, a layer of transparent gate dielectric material positioned on the front surface of the substrate overlying the gate metal and a surrounding area, and a layer of transparent metal oxide semiconductor material positioned on the surface of the layer of transparent gate dielectric. A layer of etch stop material is positioned on the layer of metal oxide semiconductor material overlying and aligned with the gate metal. The layer of the etch stop material defines a channel area in the layer of metal oxide semiconductor material. Conductive material is patterned on the portion of the etch stop layer overlying and aligned with the gate metal and on the layer of metal oxide semiconductor material to form source and drain areas on opposed sides of the channel area.
In a preferred embodiment the layer of etch stop material has a thickness greater than the thickness of the layer of transparent gate dielectric material and a lower dielectric constant than a dielectric constant of the transparent gate dielectric material to substantially reduce inter-electrode capacitance.



BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and further and more specific objects and advantages of the instant invention will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the drawings, in which:
FIG. 1 illustrates a first stage or phase in the fabrication of TFTs in accordance with the present invention; and
FIG. 2 illustrates an enlarged final stage or phase in the fabrication of TFTs in accordance with the present invention;
FIGS. 3 through 9 illustrate several stages or phases in another fabrication process of TFTs in accordance with the present invention; and
FIGS. 10 through 12 each illustrate a different pixel layer-out with self-aligned MOTFT in sequential steps designated (a) through (e) and (a) through (g) respectively, in accordance with the present invention.



DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
Turning now to the drawings, attention is first directed to FIG. 2, for the purpose of briefly explaining prior art problems. The device illustrated in FIG. 2 is a bottom gate and top source/drain metal oxide TFT, designated 10. TFT 10 includes a substrate 12 with gate metal 14 patterned thereon. A gate dielectric layer 16 is deposited over gate metal 14 and a semiconductor active layer 18 is deposited over dielectric layer 16 so as to insulate active layer 18 from gate metal 14. An etch stop/passivation area 20 is patterned on active layer 18 and source/drain areas 22 are formed on opposite sides of etch stop/passivation area 20 on the upper surface of active layer 18. The space between the source and drain, i.e. etch stop/passivation area 20, defines the conduction channel, designated 24, for TFT 10. It will be understood by the artisan that the terms “etch stop” and “passivation” are used throughout this disclosure to describe the primary purpose of specific layers but that they are generally interchangeable and the title provide is not intended to limit the purpose or use of the layer. For example, area 20 has the dual function of an etch stop layer and a passivation layer.
In the prior art process of fabricating TFT 10, two critical alignment steps are prevalent. The first critical alignment step is between passivation area 20 (channel protection layer) and gate metal 14. Gate metal 14 should be slightly larger than passivation area 20, indicated as overlap area d1 where d1>0. The second critical alignment is between the pattern for source/drain 22 and passivation area 20. There should be a slight overlap between source/drain areas 22 and passivation area 20, indicated as overlap area d2 where d2>0, so that the etching of the source/drain conductor in the formation of source/drain areas 22 (i.e. the channel space between source/drain 22) will not affect active layer 18. That is the possibility that an etchant can pass around the edges of passivation area 20 and reach active layer 18 is prevented by overlap d2. It will be understood that any alignment patterning includes some tolerance and that the fabrication process includes some deformation tolerance.
Therefore to make a channel length of L (generally the horizontal width of passivation area 20), the distance between the source and drain should be smaller than (L−2×d2). In this relationship or description of L, d2 includes any alignment and deformation tolerance. Further, horizontal width of gate metal 14 should be larger than (L+2×d1). In this relationship or description of L, d1 includes any alignment and deformation tolerance. Thus, the value of overlaps d1 and d2 depends on the alignment tool (i.e. the alignment tolerance) and the amount of substrate deformation during the fabrication process. For low cost tools, overlaps d1 and d2 are relative large, around 5 microns without the added contribution from substrate deformation. For 10 ppm substrate deformation, a field size of 50 cm can contribute another 5 microns to the tolerance. It is desirable at present to fabricate TFTs with channel lengths as small, or smaller, than 10 microns. However, using the prior art fabrication methods described above with low cost tools and large field sizes, forming a channel length of 10 microns is not possible, or alternatively a source/drain spacing of 10 microns, will result in L equaling 30 microns because of the alignment/deformation tolerances included in overlaps d1 and d2.
To understand the self-alignment procedure of the present invention, FIGS. 1 and 2 illustrate sequential steps in an embodiment fabricated in accordance with the present invention. Turning specifically to FIG. 1, a transparent substrate 12 is illustrated, which may be any convenient material transparent to radiation (i.e. self-alignment exposure) wavelength used in the self-alignment procedure, such as glass, plastic, etc. Throughout this disclosure the terms “transparent” and “opaque” mean that the material being discussed or described is transparent or opaque to radiation (i.e. exposure) wavelengths used in the self-alignment procedure. Gate metal layer 14 is patterned on the upper surface of substrate 12 by any convenient means. Since the position of gate metal layer 14 is not critical virtually any non-critical patterning technique can be used.
It will be understood by those of skill in the art that in addition to or instead of forming gate metal layer 14 with a proximity or a projection photolithography tool, the gate layer can be formed with any of the various printing processes known to experts in the field, including ink jetting, imprinting or off-set printing methods, layer 14 can also be patterned with laser writing lithography. Also, gate metal 14 is an opaque conductive metal that will not transmit the radiation wavelengths used in the self-alignment procedure. While a single gate metal 14 is illustrated for convenience in understanding, it will be understood that this might represent one or more (even all) of the TFTs used in a backplane or other large area applications.
A thin layer 16 of gate dielectric material is formed over gate metal 14 and the surrounding area. For purposes of this disclosure the term “surrounding area” refers to the gate dielectric covering the patterned gate metal completely so that no leakage in TFT channel area occurs. Again, layer 16 may be a blanket layer covering the entire large area application and no alignment is required. The gate dielectric material may be any convenient material that provides the desired dielectric constant for TFT operation and is transparent to the radiation wavelengths used in the self-alignment procedure. Examples include SiN, SiO2, SiON, Al2O3, ZrO2, Ta2O5, TiO2 in single layer or in multiple stack form.
The self-aligned TFT and backpanel process disclosed in this invention enables the fabrication of TFTs with low inter-electrode capacitance even for a gate dielectric with high dielectric constant. It should also be pointed out specifically that, other than methods known in the a-Si TFT industry (such as PECVD, sputter, atomic layer deposition, ALD), the metal-oxide type gate dielectrics listed above can also be made with a surface chemical reaction process on top of a mating metal including oxidation under high temperature, plasma oxidation, anodization and their combinations. It should also be specifically understood that with such surface reaction methods, one could achieve higher gate dielectric constant and lower leakage current than SiO2, SiON and SiN achieved by PECVD for a given process temperature. For example, 100 nm thin amorphous Al2O3 film processed by 80V anodization under 5-20° C. environmental temperature, Al2O3 film with dielectric constant beyond 8 (areal capacitance >70 nF/cm2), and leakage current below 1 nA/cm2 under 1 MV/cm electric field bias has been achieved. The RC constant is thus more than 700 Sec. Such high K dielectric film is ideal for high mobility MOTFTs, as discussed in copending U.S. patent application Ser. No. 13/902,514, one could achieve a MOTFT with mobility beyond 50 cm2/Vsec. The MOTFT and backpanel design disclosed in this invention enables such high mobility MOTFTs to be used for high speed, large pixel content displays such as 8000×4000 displays with 480 Hz frame rate. The low process temperatures in anodization avoid substrate vamping, and dimension change, and improves alignment accuracy between the gate metal layer and post gate insulator layers. In contrast, SiO2, SiON and SiN gate insulator layers have to be processed at temperature above 300° C. for the needed film quality.
A layer 18 of semiconductor metal oxide is deposited over the upper surface of layer 16. Metal oxide layer 18 is transparent to the radiation wavelengths used in the self-alignment procedure. Some typical examples of transparent metal oxide semiconductor materials include ZnO, InO, SnO, GaO, AlSnO, GaInO, GaZnO, ZnInO, InAlZnO, InGaSnO, InAlSnO, InGaZnO, ZnSnO, GaSnO, InGaCuO, InCuO, AlSnO, AlCuO, etc. As explained in the above described copending patent application (now, issued as U.S. Pat. No. 7,977,868), the metal oxide semiconductor may be amorphous or polycrystalline, however, amorphous and/or nano-crystalline is preferred. Layer 18 may be a blanket layer or it may optionally be patterned, depending primarily on the final product.
A passivation layer transparent to the radiation wavelengths used in the self-alignment procedure is then deposited over layer 18. Preferably, the constraint on the passivation layer is that the passivation layer should have very little chemical interaction with the underlying semiconductor metal oxide layer 18. For examples and explanations of this feature see the U.S. Pat. No. 7,812,346 entitled “Metal Oxide TFT with Improved Carrier Mobility”, and incorporated herein by reference. Examples of passivation material that can be processed by a coating process (such as spin coating, slot coating, spray coating, etc.) include polymer PMGI, polystyrene (PS), Poly(methyl methacrylate)(PMMA), polyimide (PI), polyethylene (PE), poly-acrylics and spin on glass. Examples of passivation material that can be processed by vacuum deposition (such as thermal evaporation, sputter, PECVD, MOCVD or ALD) include MgF2, Ta2O5, TiO2, ZrO2, V2O5, W2O3, SiO2, SiN, SiON, Al2O3, AlN, etc.
Once the passivation layer is deposited, a positive working photoresist layer 30 is positioned thereon, for example by spin coating, slot coating, spray coating, or the like. Photoresist layer 30 is then exposed from the back (rear surface, below substrate 12 in FIG. 1, represented by arrows 32). Since all of the materials except the gate metal are transparent to the exposing light, gate metal 14 will act as a mask for the alignment of the passivation area 20. Thus, photoresist layer 30 is exposed and developed to form a mask for the etching of the passivation layer into passivation area 20 overlying gate metal 14. As illustrated in FIG. 1, all exposed portions of photoresist layer 30 are removed because the exposed portions of the positive photoresist decompose or disassociate (change relative to the unexposed portion) to allow the exposed areas to be relatively easily removed in the developing stage. The passivation material over the exposed areas can be etched away using the first photoresist as a mask, generally with a light etchant or other dissolving material, with no effect on the lower surface.
Regardless which method or process for patterning passivation area 20 is used, the method should not destroy or adversely affect semiconductor active layer 18. Some extra mask pattern may be needed or used to pattern other parts of the product outside of TFT 10 and the critical gate area. A description of such parts of the product outside of TFT 10 is provided in a U.S. Pat. No. 7,605,029 entitled “Self-Aligned Transparent Metal Oxide TFT on Flexible Substrate”, and incorporated herein by reference. The pattern in such non-critical areas can also be formed by one of several printing methods (such as imprinting, inkjet printing, solution dispensing, laser printing, etc.) known to artisans in the printing field.
Some photo-patternable polymers can be used directly as the passivation/etch-stop layer. In such a case, layers 20 and 30 in FIG. 1 are simplified into single layers. Examples of such material include photosensitive polyimides from Toray Industries, Inc. (DL-1000 series and SL-4100 series), DuPont (PI2555), and HD Microsystem (HD8820). Photo-patternable acrylics such as PMGI from Microchem can also be used.
It will be understood that substantially complete control is possible for the size of overlap d1 during the masking and etching stages without requiring additional steps or materials. For example, referring to the first masking step illustrated in FIG. 1, by changing the exposure time or intensity (e.g. increasing or decreasing either one) the amount of remaining photoresist can be decreased or increased, thus altering the width of overlap d1. Also, the etchant used in conjunction with either of the patterns in FIGS. 1 and 3 can be increased to increase overlap d1. These features and how to adjust them are well known in the self-alignment field and are included in the term ‘self-align” or “self-alignment” when used to describe the process.
It can be seen that no critical masking step is performed in which expensive tools are required. Also, because of the substantially complete control of the overlap or critical areas, any overlap can be provided from substantially zero to any desired amount without the necessity of sacrificing small channel lengths. Further, no expensive masks or tools are required and larger areas can be exposed during the process so that expensive stepping and stitching or the like are not required.
Several stages or phases in another fabrication process of TFTs is illustrated in FIGS. 3 through 9 in accordance with the present invention. Turning specifically to FIG. 3, a transparent substrate 52 is illustrated, which may be any convenient material transparent to radiation (i.e. self-alignment exposure) wavelength used in the self-alignment procedure, such as glass, plastic, etc. Gate metal layer 54 is patterned on/in the upper surface of substrate 52 by any convenient means. Since the position of gate metal layer 54 is not critical virtually any non-critical patterning technique can be used. It will be understood by those of skill in the art that in addition to or instead of forming gate metal layer 54 with a proximity or a projection tool, the gate layer can be formed with any of the various printing processes mentioned above, including imprinting or off-set printing methods. Also, gate metal 54 is an opaque conductive metal that will not transmit the radiation wavelengths used in the self-alignment procedure. While a single gate metal 54 is illustrated for convenience in understanding, it will be understood that this might represent one or more (even all) of the TFTs used in a backplane or other large area applications. The patterning of gate metal 54 is considered in this procedure as the first of three masking or alignment steps.
A thin layer 56 of gate dielectric material is formed over gate metal 54 and the surrounding area. Again, layer 56 may be a blanket layer covering the entire TFT array, or by a surface reaction method or process self-aligned to the gate metal layer and covering the gate metal completely, no alignment is required. The gate dielectric material may be any convenient material that provides the desired dielectric constant for TFT operation and is transparent to the radiation wavelengths used in the self-alignment procedure. A layer 58 of semiconductor amorphous/nano-crystalline metal oxide is deposited over the upper surface of layer 56. Metal oxide layer 58 is transparent to the radiation wavelengths used in the self-alignment procedure. Some typical examples of transparent metal oxides include ZnO, InO, SnO, GaO, AlZnO, GaInO, GaZnO, ZnInO, InAlZnO, InGaZnO, ZnSnO, GaSnO, InGaCuO, InCuO, AlCuO, etc. As explained in the above described copending patent application, the metal oxide semiconductor may be amorphous or polycrystalline, however, amorphous and/or nano-crystalline is preferred. Layer 58 may be a blanket layer or it may optionally be patterned, depending primarily on the final product. However, since the patterning would be, at the most very large, and since it is optional this is not considered a masking step of the present process.
A layer 60 of etch stop material is deposited in a blanket layer over metal oxide semiconductor layer 58. It will be understood from the following description that layer 60, while referred to as an “etch stop material”, actually has the dual function of an etch stop material during S/D and following processes and a passivation material (during final device operation and the title is not intended to in any way limit the scope of the invention. Generally, etch stop layer 60 is selected to be etchable by a process that does not use or generate UV light, such as a standard wet etch process. Also, etch stop layer 60 can be thinner or thicker than gate dielectric layer 56 and the dielectric constant is much lower than the dielectric constant of the gate dielectric. As an example, etch stop layer 60 is generally greater than twice as thick as gate dielectric layer 56 or at least 500 nm thick while dielectric layer 56 is generally in a range of 100 nm to 200 nm thick. It will be understood that the etch stop material can be any material that fulfills these requirements. A layer 62 of photo-patternable material, preferably a positive photoresist material, is coated or deposited in a blanket layer over etch stop layer 60. Photo resist layer 62 can be deposited, for example by spin coating, slot coating, spray coating, or the like. Generally, photoresist layer 62 is a standard material that is exposed by typical UV sources in a normal lithographic process and is not affected by the wet etch process used to remove portions of etch stop layer 60. In a second masking step, outer portions 64 of layer 62 are exposed and developed (removed) using a typical UV source (>350 nm) in conjunction with an isolation mask (not shown). It will be understood that layers 60 and 62 are specifically selected to be individually or selectively removable. For a better understanding in this process the term “non-UV etch” is any etch process that does not have or include any UV generation source.
Turning specifically to FIG. 4, with portions 64 of layer 62 removed, outer uncovered portions of etch stop layer 60 can be removed using a non-UV etch, generally a wet etch. Referring additionally to FIG. 5A, in the preferred process photoresist layer 62 is then exposed from the back (rear surface, below substrate 52 in FIG. 5A). Since all of the materials except gate metal 54 are transparent to the exposing light, gate metal 54 will act as a mask for the ultimate alignment of etch stop layer 60. Thus, photoresist layer 62 is exposed and developed to form a mask for the subsequent etching of etch stop layer 60. Referring additionally to FIG. 6, etch stop layer 60 is used as a mask to etch metal oxide semiconductor layer 58 to isolate or define the limits of the TFT active layer. Because photoresist layer 62 has already been exposed and developed, it is not necessary to limit the etch process used for etching semiconductor layer 58 to a non-UV etch at this point and a simple dry etch or any other convenient etch can be used.
It will be understood that the step of exposing photoresist layer 62 from the rear surface and developing or removing the material and the step of etching metal oxide semiconductor layer 58 can be performed in any convenient order and neither of the steps is considered a masking step of the present process. For example and referring to FIG. 5B, it can be seen that metal oxide semiconductor layer 58 can be etched prior to exposing and developing photoresist layer 62. However, when using these process steps a non-UV etch process must be used in etching metal oxide semiconductor layer 58 so as not to affect photoresist layer 62. Photoresist layer 62 is then exposed from the back (rear surface, below substrate 52 in FIG. 5B) to arrive at the structure illustrated in FIG. 6.
Referring specifically to FIG. 7, etch stop layer 60 is etched using some convenient etch and using the remaining portion of photoresist layer 62 as a mask. Since the remaining portion of photoresist layer 62 is accurately aligned with gate metal 54 by the rear exposure process and is not affected by substrate deformation, the remaining portion of etch stop layer 60 will be accurately aligned with gate metal 54.
Referring additionally to FIG. 8, the remaining portion of photoresist layer 62 is simply and easily stripped to leave the portion of etch stop layer 60 overlying the active layer 58 of metal oxide semiconductor material. As illustrated in FIG. 9, a layer 64 of source/drain metal is deposited and patterned using the remaining portion of etch stop layer 60 to define a channel in layer 58 of metal oxide semiconductor material. The patterning of metal layer 64 into spaced apart source and drain contacts 66 is the third and final masking step of the present process.
In a preferred embodiment, source/drain metal layer 60 consists of two layers. A top layer can be any metal that can provide good conductivity, such as Al, and can be selectively etched over a bottom layer. The bottom layer is a metal that can be patterned without etching the metal oxide of layer 58, such as Mo, Ti, Ta, W etc. or a metal alloy including any such metal. In the preferred process the top layer is etched first and the chemistry is changed to etch the bottom layer. Source/drain metal 66 is defined in the traditional way by allowing a large overlap with gate 54 but the overlap capacitance is greatly reduced by the thickness and low dielectric constant of etch stop layer 60.
In a variation of the processes described in FIG. 3-9, etch stop layer 60 can be printed with an isolation mask pattern (much larger than the etch stop pattern and therefore feasible). The result is basically the etch stop formation illustrated in FIG. 5A, without the overlying layer 62 of photoresist. The printed etch stop layer 60 is used as a mask to etch metal oxide layer 58 for isolation. After metal oxide layer 58 is etched, a layer of regular positive photoresist is blanket coated and exposed from the backside of substrate 52 without masking. The coating can be accomplished using any one of a variety of methods including for example by spin coating, dip coating, inkjet printing, screen printing, Gravure printing, and the like. The developed photoresist (generally as illustrated in FIGS. 6 and 7) is used as a mask to pattern etch stop layer 60. The photoresist is removed and source/drain metal deposited and patterned as described above.
FIG. 10-12 illustrate several pixel circuit designs and corresponding processes for low-parasitic capacitance, self-aligned MOTFTs to be used for display pixels with large aperture ratio. Each FIG. 10-12 illustrates a different embodiment of a MOTFT in accordance with the present invention and the step-by-step process of fabrication in top plan views (a) through (e) and (a) through (g), respectively. It should be understood that the various layers described are the same as layers previously described above and will appear the same in side views (not shown here for simplicity of understanding).
FIG. 10(a) shows the gate line pattern in a display pixel area. The gate metal layer is first deposited onto a transparent supporting substrate (depicted by the paper surface), and then patterned with a standard photolithograph process. Two holes are left in areas corresponding to via-holes in the etch stop layer (see description below) and for forming S/D contact electrodes. A gate dielectric layer is than formed by means of a deposition method, a coating method or a surface chemical reaction method discussed previously. Again, it is pointed out specifically that surface reaction methods or processes such as anodization provide a self-aligned gate dielectric material on top and side walls of the gate metal layer. A metal oxide channel layer is then blanket deposited on the gate insulator layer by means of a deposition or a coating method, described previously. The channel layer can be in either single layer form, or in multiple layer form with the composition variation in a vertical direction. Examples of bilayer MOTFTs with high mobility and high operation stability under current and under back-light illumination were disclosed in a co-pending US patent application entitled “STABLE HIGH MOBILITY MOTFT AND FABRICATION AT LOW TEMPERATURE”, bearing Ser. No. 13/502,914, filed on May 24, 2013, and incorporated herein by reference.
The transparent metal-oxide channel layer is than patterned in the form showing in FIG. 10(b) with a standard lithograph patterning method. It will be understood that the location accuracy for the metal-oxide layer is less critical than other layers, as long as the edge covers most of the two holes on the gate layer and the area in between. The etch-stop layer is then blanket deposited onto the patterned channel layer. A positive photoresist is then coated onto the etch-stop layer and patterned by means of the built-in mask as formed by the opaque gate metal layer by exposing UV light from the other side of the transparent substrate (as shown in FIG. 10(C)). With this process, a patterned etch-stop layer is formed overlaying the gate line with via-holes opened for source/drain contacts. The source drain metal layer, including source/drain contacts and data lines, is then formed by means of a blanket deposition and patterned into the shape shown in FIG. 10(d). For applications requiring a high conductance data line, Mo/M/Mo, Ti/M/Ti, W/M/W (in which M=Al or Cu, W=tungsten) can be used. The pixel electrode can then be formed with shape and location shown in FIG. 10(e). Although only a single pixel is illustrated in FIG. 10(e), the entire backpanel can be envisioned by tiling the pixel in vertical and horizontal directions. The entire TFT array can be form with just a 4 mask process and can be used for driving TN type or VA type LCD.
A similar process can also be used for the fabrication of a pixel driver array for AMOLED, with one more mask for via-hole forming on the gate insulator layer. The same flow used for fabricating AMOLED can also be used for fabricating gate and data drivers in peripheral areas outside the display array. In addition, image sensor arrays with active sensing pixels with local gain (typically three TFTs and one capacitor or beyond) can also be made with the same flow. For in-plane switching (IPS) type of AMLCD, two more mask steps are needed after forming the transparent pixel electrode in FIG. 10(e): (1) depositing an interlayer on top of the pixel electrode and forming via holes at contact pad areas out of the display area, and (2) forming a transparent common electrode on top of the interlayer with electrode patterns formed following a requirement for the specific liquid crystal cell arrangement. An example of a 6 mask structure and process for IPS-LCD is disclosed in a copending U.S. patent application entitled “Mask level reduction in MOTFT”, bearing Ser. No. 13/481,781, filed on May 26, 2012. More details on the interlayer forming and the top and bottom electrodes forming process are provided in that application.
In certain portable applications with high pixel density (small pixel pitch), and high aperture ratio, one would like to form a planarization layer between the S/D formation (FIG. 10(d)) and the bottom electrode formation (FIG. 10(e)). One more mask is needed to open a via hole on top of the drain metal electrode. The pixel electrode can then be extended to that hole, filling the entire transparent area defined within the gate and data lines.
FIG. 11 illustrates another embodiment, with a finger pattern in the area corresponding to the drain contact (as shown in FIG. 11(a)). The gate insulator and the metal-oxide channel layer are then formed on top of the patterned gate metal. The metal oxide channel layer is then patterned into the shape shown in FIG. 11(b). The etch-stop layer is then blanket coated on top of the channel and patterned into the shape of the gate layer by means of a self-aligned process with the gate metal serving as the built-in mask (as shown in FIG. 11(c)). The source/drain layer and the data line are then formed on the etch-stop layer with a standard lithography process. In this case, an S/D bilayer is used with a thin transparent conducting oxide (or a thin, semitransparent Mo layer) and a thick Al or Cu layer. When a half-tone photolithograph is used, the photoresist over the drain electrode area can be removed and the opaque Al (or Cu) layer can be removed (as shown in FIG. 11(e)). A blanket planarization layer is then coated over and a via hole is opened up on top of the drain area (as shown in FIG. 11e). The transparent pixel electrode can then be deposited and patterned with the 2nd self-aligned process within the area defined by the opaque gate and date metal lines. A MOTFT pixel driver array is then formed with a high aperture ratio using only 4 mask steps.
In certain LCD applications, it may be convenient to form a hole at locations for the liquid crystal spacer post from the color filter side of the substrate, such location anchors can be formed at designated areas in the pixel, as shown in FIG. 12. FIG. 12(a) shows a hole at the location for the LCD spacer post. A via hole is formed in the etch-stop layer (as shown in FIG. 11(c)) and used as the spacer anchor in the final MOTFT backpanel (as shown in FIG. 12(g)) The rest of the process steps are similar to that shown in FIG. 12 below.
It should be noted that other components in a flat panel circuit can also be made concurrently during the TFT process, including capacitors and contact pads for connecting wafer based drivers in peripheral areas surrounding the display area. The self-aligned etch-stop over the gate pattern guarantees TFT performance uniformity over the entire substrate area. With the TFT structure and process described in FIGS. 10-12, high uniformity TFT backpanel circuits over large active areas can thus be made with phototools having low alignment accuracy.
The other components are easily included in the process with no need for additional masks or other steps. Thus, the process disclosed in this invention can be conveniently used to make entire backpanels for displays or other applications (such as image sensor arrays, chemical and/or bio-sensor arrays) with a substantial reduction in process steps and labor.
Thus, mask reduced processes are described for fabricating MOTFTs and display backpanels comprising such MOTFTs with substantially reduced electrode overlap and with reduced masking steps over the prior art. Also, the etch stop layer can be formed thicker than the gate dielectric layer and with a much lower dielectric constant. Thus, in addition to the substantially reduced overlap, the dielectric in the overlap has a substantially increased thickness and lower dielectric constant so that the capacitance is substantially reduced. Therefore, a reduction in the number of masks (i.e. from four masks to three masks), while still achieving the self-alignment between the gate and the source/drain, results in a major reduction in the overall cost. Such designs also enable high pixel density applications with low power consumption (due to both improved aperture ratio and reduced power loss associating with coupling capacitances. It should further be noted that other components in a flat panel circuit can also be made concurrently during the TFT process, including capacitors and contact pads for connecting wafer based drivers in peripheral areas surrounding the display area. The process disclosed in this invention can thus be used to make entire backpanels for displays or other applications.
Various changes and modifications to the embodiments herein chosen for purposes of illustration will readily occur to those skilled in the art. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.

## Claims

1. An active matrix backpanel including an array of metal oxide TFTs with reduced inter-electrode capacitance, each TFT of the array of TFTs comprising:
a transparent substrate having a front surface and a rear surface;
an opaque gate metal positioned on the front surface of the substrate and defining a gate area for the TFT and gate selection bus-lines of the active matrix;
a layer of transparent gate dielectric material positioned on the front surface of the substrate overlying the gate metal and a surrounding area;
a layer of transparent metal oxide semiconductor material positioned on the surface of the layer of transparent gate dielectric;
a layer of etch stop material positioned on the layer of metal oxide semiconductor material overlying and aligned with the gate metal, the layer of the etch stop material defining a channel area in the layer of metal oxide semiconductor material; and
conductive material patterned to form data lines of the active matrix crossing over the gate/selection lines and source/drain electrodes on opposed sides of the channel area of each TFT, wherein the source/drain contacts are aligned on a portion of the etch stop layer overlying and aligned with the gate metal and on the layer of metal oxide semiconductor material.

2. The active matrix backpanel as claimed in claim 1 further including a transparent pixel electrode patterned within a transparent zone defined by the data lines and gate/selection lines in each TFT of the array of TFTs.

3. The active matrix backpanel as claimed in claim 1 wherein the transparent substrate is a glass or a plastic sheet, or combination thereof in stack form.

4. The active matrix backpanel as claimed in claim 1 wherein the transparent gate dielectric layer comprises SiN, SiO2, SiON, Al2O3, ZrO2, Ta2O5, TiO2 in single layer or in multiple stack form.

5. The active matrix backpanel as claimed in claim 1 wherein the gate dielectric layer is a self-aligned surface chemical reaction material overlying top and side walls of the gate metal layer.

6. The active matrix backpanel as claimed in claim 1 wherein the gate dielectric layer includes a thermal oxidation material, plasma oxidation material, anodization material and their combinations.

7. The active matrix backpanel as claimed in claim 1 wherein the layer of transparent metal oxide semiconductor material includes ZnO, InO, SnO, GaO, AlZnO, GaInO, GaZnO, ZnInO, InAlZnO, InGaSnO, InAlSnO, InGaZnO, ZnSnO, GaSnO, InGaCuO, InCuO, AlSnO, and AlCuO in single layer with uniform composition or in blend or multiple stack form.

8. The active matrix backpanel as claimed in claim 1 wherein the layer of etch stop material comprises a transparent inorganic dielectric layer, or a transparent organic dielectric layer, or combinations thereof in multiple stack or in blend form.

9. The active matrix backpanel as claimed in claim 8 wherein the transparent etch-stop layer comprises PMGI, polystyrene (PS), Poly(methyl methacrylate)(PMMA), polyimide (PI), polyethylene (PE), spin on glass, poly-acrylics, MgF2, Ta2O5, TiO2, ZrO2, V2O5, W2O3, SiO2, SiN, SiON, Al2O3, AlN in single or multiple-stack form.

10. The active matrix backpanel as claimed in claim 1 wherein the layer of etch stop material includes a layer with a thickness greater than the thickness of the layer of transparent gate dielectric material.

11. An active matrix backpanel as claimed in claim 1 wherein the layer of etch stop material has a thickness greater than twice as thick as the thickness of the gate dielectric material.

12. An active matrix backpanel as claimed in claim 1 wherein the layer of etch stop material has a thickness of at least 500 nm.

13. An active matrix backpanel as claimed in claim 1 wherein the layer of etch stop material includes a material with a lower dielectric constant than a dielectric constant of the transparent gate dielectric material.

14. The active matrix backpanel of claim 1 incorporated in a thin film electronic device.

15. The active matrix backpanel as claimed in claim 14 wherein thin film electronic device is an active matrix display, an active matrix image array, a chemical sensor array or a bio-sensor array.