# Patent

## Title
MOS devices with ultra-high dielectric constants and methods of forming the same

## Abstract

An integrated circuit structure includes a semiconductor substrate, and a gate stack over the semiconductor substrate. The gate stack includes a high-k gate dielectric over the semiconductor substrate, and a magnetic compound over and in contact with the high-k gate dielectric. A source region and a drain region are on opposite sides of the gate stack. The gate stack, the source region, and the drain region are portions of a Metal-Oxide-Semiconductor (MOS) device.

## Background
BACKGROUND
Metal Oxide-Semiconductor (MOS) devices are key components of integrated circuits. A MOS device includes a gate stack, which further includes a gate dielectric over a semiconductor substrate, and a gate electrode over the gate dielectric. A source region and a drain region are disposed on the opposite sides of the gate stack. The MOS device may be turned on and off by controlling the voltage applied on the gate electrode, so that the source region and the drain region are either electrically disconnected or electrically interconnected.
Conventionally, silicon dioxide was used to form the gate dielectrics. With the evolving of integrated circuits, dielectric materials with high dielectric constants (high-k values) are increasingly used to form the gate dielectrics. The high-k dielectrics may improve the short channel control of the MOS devices. The high-k dielectrics may also reduce gate leakage currents. Hafnium oxide and aluminum oxide are among known high-k dielectric materials.
It is desirable to have high-k materials with the k values higher than the currently used high-k dielectric materials in order to further improve the performance of the MOS devices. However, higher k values also result in problems. For example, with the further increase in the k values, the band-gaps of the high-k dielectric materials reduce, which results in the gate leakage currents of the respective MOS devices to be increased. Therefore, tradeoff has to be made to choose between higher k values accompanied by higher leakage currents and lower k-values accompanied by lower leakage currents.



BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIGS. 1 through 12 illustrate the cross-sectional views of intermediate stages in the formation of a Metal-Oxide-Semiconductor (MOS) device in accordance with some exemplary embodiments.



DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
A Metal-Oxide-Semiconductor (MOS) device and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the MOS device are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In the illustrated embodiments, a gate-last approach is used to form the replacement gate stack of the MOS device. It is appreciated that teaching regarding the materials and the formation methods of the gate stack is readily applicable to forming a MOS device using a gate-first approach, in which the gate stack is formed before the formation of source and drain regions of the MOS device.
FIGS. 1 through 12 are cross-sectional views of intermediate stages in the formation of a MOS device in accordance with some exemplary embodiments. Referring to FIG. 1, wafer 10, which includes substrate 20, is provided. Substrate 20 may be formed of a semiconductor material such as silicon, silicon carbon (SiC), silicon germanium (SiGe), a III-V compound semiconductor, or the like. Isolation regions such as Shallow Trench Isolation (STI) regions 21 are formed in substrate 20, and are used to define the active regions of MOS devices.
Dummy gate stack 22 is formed over substrate 20. Dummy gate stack 22 includes dummy gate dielectric 24 and dummy gate electrode 26. Dummy gate dielectric 24 includes silicon oxide in some exemplary embodiments. In alternative embodiments, other materials such as silicon nitride, silicon carbide, or the like, are also used. Dummy gate electrode 26 may include polysilicon. In some embodiments, dummy gate stacks 22 further includes hard mask 28 over dummy gate electrode 26. Hard mask 28 may comprise silicon nitride, for example, while other materials such as silicon carbide, silicon oxynitride, and the like may also be used. In alternative embodiments, hard mask 28 is not formed.
Lightly-Doped Drain/source (LDD) regions 30 are formed, for example, by implanting a p-type impurity (such as boron and/or indium) or an n-type impurity (such as phosphorous and/or arsenic) into substrate 20, depending on the conductivity type of the resulting MOS device 100 (FIG. 10). For example, when MOS device 100 is a pMOS device, LDD regions 30 are p-type regions. When the MOS device 100 is an nMOS device, LDD regions 30 are n-type regions. Dummy gate stacks 22 acts as an implantation mask, so that the edges of LDD regions 30 are substantially aligned with the edges of gate stacks 22.
Referring to FIG. 2, gate spacers 34 are formed on the sidewalls of dummy gate stack 22. In some embodiments, each of gate spacers 34 includes silicon oxynitride layer 34A and silicon oxide layer 34B. In alternative embodiments, gate spacers 34 include one or more layers, each comprising silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials. The available formation methods include Plasma Enhanced Chemical Vapor Deposition (PECVD), Low-Pressure Chemical Vapor Deposition (LPCVD), Sub-Atmospheric Chemical Vapor Deposition (SACVD), and other deposition methods.
Source and drain regions (referred to as source/drain regions hereinafter) 38 are formed in semiconductor substrate 20. In the embodiments wherein MOS device 100 (FIG. 10) is a pMOS device, source/drain regions 38 are of p-type. In the embodiments wherein MOS device 100 is an nMOS device, source/drain regions 38 are of n-type. In some embodiments, source/drain stressors (also marked as 38) are formed in semiconductor substrate 20. The source/drain stressors form at least parts of source and drain regions 38. FIG. 2 illustrates the embodiments in which source/drain regions 38 fully overlap the respective source/drain stressors. In alternative embodiments, source/drain regions 38 and the source/drain stressors are partially overlapped.
Furthermore, in the embodiments in which MOS device 100 (FIG. 10) is an nMOS device, source/drain stressors 38 may comprise silicon phosphorous (SiP), silicon carbon (SiC), or the like. In the embodiments in which MOS device 100 is a pMOS device, source/drain stressors 38 may comprise silicon germanium (SiGe). The formation of source/drain stressors 38 may be achieved by etching semiconductor substrate 20 to form recesses therein, and then performing an epitaxy to grow source/drain stressors 38 in the recesses.
Referring to FIG. 3, Contact Etch Stop Layer (CESL) 40 is formed over gate stack 22 and source/drain regions 38. In some embodiments, CESL 40 comprises silicon nitride, silicon carbide, or other dielectric materials. Inter-Layer Dielectric (ILD) 42 is form over CESL 40. ILD 42 is blanket formed to a height higher than the top surface of dummy gate stack 22. ILD 42 may comprise Flowable oxide formed using, for example, Flowable Chemical Vapor Deposition (FCVD). ILD 42 may also be a spin-on glass formed using spin-on coating. For example, ILD 42 may comprise Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), Tetraethyl Orthosilicate (TEOS) oxide, TiN, SiOC, or other low-k non-porous dielectric materials.
FIG. 4 illustrates a planarization step, which is performed using, for example, Chemical Mechanical Polish (CMP). The CMP is performed to remove excess portions of ILD 42 and CESL 40, wherein the excess portions are over the top surface of hard mask 28. Accordingly, dummy gate stack 22 is exposed. In alternative embodiments, hard mask 28 is removed during the CMP, wherein the CMP stops on the top surface of dummy gate electrode 26.
Next, dummy gate stack 22 is removed. Recess 44 is formed as a result of the removal of dummy gate stack 22, wherein the resulting structure is shown in FIG. 5. In some embodiment, the width W1 of recess 44 is smaller than about 25 nm, and may be in the range between about 18 nm and about 22 nm. It is appreciated, however, that the values recited throughout the description are merely examples, and may be changed to different values. Furthermore, depth D1 of recess 44 may be greater than about 10 nm. The aspect ratio D1/W1 of recess 44 may be higher than about 5, higher than about 7, or higher than about 10. Such high aspect ratio, small width W1, and great depth D1 demand the subsequently formed metal layers to be conformal in order to achieve the required performance.
FIGS. 6 through 11 illustrate the formation of a replacement gate stack. Referring to FIG. 6, gate dielectric layer 46 is formed. In some embodiments, gate dielectric layer 46 may have a k value greater than 3.9, and hence is a high-k dielectric layer. The k value of high-k gate dielectric layer 46 may further be higher than about 20. In alternative embodiments, gate dielectric layer 46 may be a low-k dielectric layer having a k value lower than 3.9. In these embodiments, however, the k value of gate dielectric layer 46 will be propelled to be high-k by the overlying magnetic layer as shown in FIG. 7. In some embodiments, before the formation of high-k gate dielectric layer 46, an Interfacial Layer (IL, not shown) may be formed at the top surface of semiconductor substrate 20, wherein the IL layer is in recess 44. The IL layer may include an oxide layer such as a silicon oxide layer, which may be formed through the thermal oxidation of substrate 20, a chemical oxidation, or a deposition step.
In some embodiments, gate dielectric layer 46 is formed of a high-k dielectric material, which is formed of BaTiO3, CoFe2O4, YFeO3, CdCr2S4, TbMnO3, BiFeO3, or the like. In yet alternative embodiments, gate dielectric layer 46 is formed of HfO2, Al2O3, or the like. In yet alternative embodiments, gate dielectric layer 46 is formed of a low-k dielectric material such as HgCr2S4, which has a k value lower than 1 (such as about 0.54). The thickness T1 of gate dielectric layer 46 is preferably small, for example, smaller than about 10 Å. In some embodiments, thickness T1 is in the range between about 5 Å and about 10 Å. The formation of gate dielectric layer 46 may be performed using, for example, Atomic Layer Deposition (ALD). Other methods may also be used. Gate dielectric layer 46 may have a high k value. For example, BaTiO3 may have a k value equal to about 300.
As also shown in FIG. 6, magnetic layer 48 is formed over, and may or may not be in contact with, gate dielectric layer 46. Magnetic layer 48 may be formed of a magnetic compound, which generates magnetic field 49. Magnetic layer 48 may be electrically conductive. In some embodiments, magnetic material 48 comprises iron (Fe) and platinum (Pt). The formation process and the composition of magnetic material 48 are adjusted to increase the magnetic field generated by magnetic material 48. FIG. 6 schematically illustrates the magnetic fields (represented by arrows 49) that are generated by magnetic layer 48. Magnetic fields 49 have directions perpendicular to the major surface planes of magnetic layer 48. For example, the bottom portion of magnetic layer 48, with the bottom portion extending horizontally, generates a magnetic field 49 penetrating through the underlying horizontal portion of gate dielectric layer 46, wherein the respective magnetic field 49 is in the vertical direction. The respective magnetic field 49 is also perpendicular to a major top surface 20A (FIG. 1) or bottom surface of substrate 20.
On the other hand, the sidewall portions of magnetic layer 48, which extend vertically, generate magnetic fields 49 penetrating through the respective contacting portions of gate dielectric layer 46, wherein the respective portions of magnetic fields 49 are in the horizontal directions in FIG. 6. In the embodiments in which BaTiO3 is used, the magnetic field 49 may have directions as illustrated. In alternative embodiments in which different magnetic materials are used, the magnetic field 49 may have directions opposite to the illustrated directions.
In some embodiments, magnetic layer 48 has a thickness T2 in the range between about 10 nm and about 500 m. Thickness T2 may also be in the range between about 100 nm and about 300 nm. The formation of magnetic layer 48 may be performed using, for example, sputtering (Physical Vapor Deposition (PVD)). The formation conditions affect the magnitude of the magnetic field 49, and without the proper formation conditions, magnetic field may not be generated. In some embodiments, to induce and increase magnetic field 49, the chamber for forming magnetic layer 48 may have a pressure lower than about 10−7 torr. The formation temperature is higher than about 500° C. After the formation, a post-anneal is performed on wafer 10, with the temperature being higher than about 1,000° C. The optimum conditions for inducing and increasing magnetic field 49 are affected by various factors, and may be found through experiments.
In some embodiments, magnetic layer 48 is formed of (or comprises) FePt. An exemplary atomic percentage of Pt in FePt is in the range between about 20 percent and about 80 percent, and the atomic percentage of Fe in FePt is in the range between about 80 percent and about 20 percent accordingly. Experiment results indicated that when the atomic percent of Fe and the atomic percent of Pt are close to each other, the magnetic field 49 generated by magnetic layer 48 is high. In some exemplary embodiments, an atomic percentage of Pt in FePt is in the range between about 40 percent and about 60 percent, and the atomic percentage of Fe in FePt is in the range between about 60 percent and about 40 percent accordingly. In alternative embodiments, magnetic layer 48 comprises NiFe, wherein the atomic percentage of Fe in NiFe is in the range between about 20 percent and about 80 percent, and the atomic percentage of Ni in NiFe is in the range between about 80 percent and about 20 percent accordingly.
By adjusting the formation process conditions and the composition of magnetic layer 48 in combination, magnetic field 49 may be higher than about 0.1 Tesla, which is applied on gate dielectric layer 46. The dipoles in gate dielectric layer 46 are affected by magnetic field 49, and are more oriented in the direction parallel to (or anti-parallel to) the direction of magnetic field 49 than if no magnetic field 49 is applied. The dipoles may be induced when the respective MOS device is applied with voltages. This results in the capacitance that is caused by gate dielectric layer 46 to be increased. This is equivalent to that the effective k value of gate dielectric layer 46 is increased. In some embodiments, depending on the materials of gate dielectric layer 46 and magnetic layer 48, and the formation processes, the effective k value of gate dielectric layer 46 may be increased by between about 10 percent and about 10,000 percent (100 times). For example, when gate dielectric layer 46 is formed of BaTiO3, and magnetic layer 48 is formed of FePt, the effective k-value of gate dielectric layer 46 may be increased by about 3 times, and the effective k value of gate dielectric layer 46 may be about 1,250 to about 10,000. On the other hand, when gate dielectric layer 46 is formed of HgCr2S4, and magnetic layer 48 is formed of FePt, the effective k-value of gate dielectric layer 46 may be increased by about 120 times, and the effective k-value may be about 65.
Next, as shown in FIG. 7, diffusion barrier layer 50 is formed over magnetic layer 48. In some embodiments, diffusion barrier layer 50 includes TiN, TaN, or composite layers thereof. For example, diffusion barrier layer 50 may include a TiN layer (the lower part of diffusion barrier layer 50), and a TaN layer (the upper part of diffusion barrier layer 50) over the TiN layer.
Referring to FIG. 8, metal layer 52 is formed. In the embodiments in which the resulting MOS device 100 (FIG. 12) is an N-type MOS (NMOS) device, metal layer 52 is in contact with diffusion barrier layer 50. For example, in the embodiments in which diffusion barrier layer 50 comprises a TiN layer and a TaN layer, metal layer 52 may be in physical contact with the TaN layer. Metal layer 52 provides the work function suitable for NMOS devices, which work function is lower than the mid-gap work function. The work function lower than the mid-gap work function is referred to as an n-work function, and the respective metal having the n-work function is referred to as an n-metal. In some embodiments, metal layer 52 is an n-metal having a work function lower than about 4.4 eV. The work function of metal layer 52 may also be in the range between about 4.1 eV and about 4.4 eV. Metal layer 52 may comprise titanium aluminum (TiAl) (which may include, or free from or substantially free from other elements) in accordance with some embodiments. The formation of metal layer 52 may be achieved through Physical Vapor Deposition (PVD).
In alternative embodiments in which the resulting MOS device 100 (FIG. 12) is a P-type MOS (PMOS) device, an additional TiN layer (not shown) is formed between, and in contact with, the TaN layer (in diffusion barrier layer 50) and the overlaying metal layer 52. The additional TiN layer provides the work function suitable for PMOS devices, which work function is higher than the mid-gap work function (about 4.5 eV) that is in the middle of the valance band and the conduction band of silicon. The work function higher than the mid-gap work function is referred to as a p-work function, and the respective metal having the p-work function is referred to as a p-metal.
Next, as shown in FIG. 9, layer(s) 54 are formed. In some embodiments, layers 54 include a block layer, which may comprise TiN in some embodiments. Block layer 52 may be formed using Chemical Vapor Deposition (CVD). Layers 54 may also include a wetting layer, which has a good ability to adhere (and wet) the subsequently formed filling metal 56 (FIG. 12) during the reflow of filling metal 56. In some embodiments, the wetting layer is a cobalt layer, which may be formed using CVD.
FIG. 10 illustrates the formation of filling metal 56 to fill the remaining portions of recess 44 (FIG. 9). Filling metal 56 may comprise aluminum or an aluminum alloy, which may also be formed using PVD, CVD, or the like. Filling metal 56 may be reflowed to fully fill the remaining recess 44 as in FIG. 9. The formation of wetting layer 54 improves the wetting of filling metal 56 to the underlying layers.
FIG. 11 illustrates a planarization step (for example, a CMP) for removing excess portions of layers 46, 48, 50, 52, 54, and 56, wherein the excess portions are over ILD 42. The remaining portions of layers 46, 48, 50, 52, 54, and 56 form replacement gate stack 58. Each of the remaining portions of layers 46, 48, 50, 52, 54, and 56 may include a bottom portion, and sidewall portions over and connected to the bottom portion.
Referring to FIG. 12, source/drain silicide regions 60 and contact plugs 62 are formed. The formation process may include forming contact plug openings in ILD 42 to expose source/drain regions 38, forming a metal layer (not shown) to extend into the contact plug openings, performing an annealing to form the source/drain silicide regions 60, removing the unreacted portions of the metal layer, and filling the contact plug openings to form contact plugs 62. MOS device 100 is thus formed.
When the gate-first approach is used, the structure of MOS device 100 is similar to what is shown in FIG. 12, except that that the layers, such as 46, 48, 50, 52, 54, and 56, in gate stack 58 are horizontal without including the vertical portions. One of ordinary skill in the art will realize the formation details of the respective MOS device by applying the teaching of the present disclosure.
The embodiments of the present disclosure have some advantageous features. By forming a magnetic layer over the high-k dielectric layer, the effective k value of the high-k dielectric layer, affected by the magnetic field, is increased. On the other hand, the increase in the k value of the high-k dielectric layer does not result in the reduction in the bandgap of the high-k dielectric layer. Accordingly, the gate leakage current is not increased.
In accordance with some embodiments of the present disclosure, a MOS device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a magnetic layer over the gate dielectric.
In accordance with alternative embodiments of the present disclosure, an integrated circuit structure includes a semiconductor substrate, and a gate stack over the semiconductor substrate. The gate stack includes a high-k gate dielectric over the semiconductor substrate, and a magnetic compound over and in contact with the high-k gate dielectric. A source region and a drain region are on opposite sides of the gate stack. The gate stack, the source region, and the drain region are portions of a MOS device.
In accordance with yet alternative embodiments of the present disclosure, a method includes forming a gate stack over a semiconductor substrate. The formation of the gate stack includes forming a high-k gate dielectric over the semiconductor substrate, and forming a magnetic compound over the high-k gate dielectric. A source region and a drain region are formed on opposite sides of the gate stack, wherein the gate stack, the source region, and the drain region are portions of a MOS device.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

## Claims

1. An integrated circuit structure comprising:
a semiconductor substrate;
a Metal-Oxide-Semiconductor (MOS) device comprising:
a gate stack over the semiconductor substrate, the gate stack having two substantially vertical outer sidewalls opposing to each other, wherein the gate stack comprises:
a gate dielectric over the semiconductor substrate; and
a magnetic layer over the gate dielectric, wherein the magnetic layer is between the two substantially vertical outer sidewalls.

2. The integrated circuit structure of claim 1, wherein the magnetic layer is configured to generate a magnetic field penetrating through the gate dielectric in a direction perpendicular to a major surface plane of the gate dielectric.

3. The integrated circuit structure of claim 1, wherein the magnetic layer comprises FePt or NiFe.

4. The integrated circuit structure of claim 3, wherein the magnetic layer comprises FePt.

5. The integrated circuit structure of claim 1, wherein the magnetic layer comprises a first substantially vertical portion and a second substantially vertical portion having magnetic fields opposing to each other.

6. The integrated circuit structure of claim 1, wherein the gate dielectric comprises a high-k dielectric material comprising BaTiO3, CoFe2O4, YFeO3, CdCr2S4, TbMnO3, or BiFeO3.

7. The integrated circuit structure of claim 1, wherein the gate dielectric is in physical contact with the magnetic layer.

8. An integrated circuit structure comprising:
a semiconductor substrate;
a gate stack over the semiconductor substrate, wherein the gate stack comprises:
a gate dielectric over the semiconductor substrate; and
a magnetic compound over the gate dielectric, wherein the magnetic compound is configured to generate a magnetic field perpendicular to a planar surface of the gate dielectric; and
a gate electrode, wherein the magnetic compound is between the gate electrode and the gate dielectric; and

a source region and a drain region on opposite sides of the gate stack.

9. The integrated circuit structure of claim 8, wherein the gate dielectric comprises:
a bottom portion parallel to a top surface of the semiconductor substrate, wherein the magnetic field comprises a first portion perpendicular to and penetrating through the bottom portion of the gate dielectric; and
a sidewall portion perpendicular to the top surface of the semiconductor substrate, wherein the magnetic field comprises a second portion perpendicular to and penetrating through the sidewall portion of the gate dielectric.

10. The integrated circuit structure of claim 8, wherein the magnetic compound comprises FePt or NiFe.

11. The integrated circuit structure of claim 10, wherein the magnetic compound comprises FePt, and wherein an atomic percentage of platinum in the magnetic compound is in a range between about 20 percent and about 80 percent.

12. The integrated circuit structure of claim 1 further comprising:
a source region extending into the semiconductor substrate; and
a drain region extending into the semiconductor substrate.

13. The integrated circuit structure of claim 12, wherein the gate dielectric and the magnetic layer overlaps a portion of the semiconductor substrate, and the source region and the drain region are on opposite sides of, and do not extend into, the portion of the semiconductor substrate.

14. The integrated circuit structure of claim 8, wherein the source region and the drain region extend into the semiconductor substrate.

15. The integrated circuit structure of claim 8, wherein the source region, the drain region, and the gate stack are parts of a transistor, and the transistor is configured to have a current flowing between the source region and the drain region, and in the semiconductor substrate.