# Patent

## Title
Ultralow power carbon nanotube logic circuits and method of making same

## Abstract

In one embodiment, a complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs) includes: at least one p-type metal-oxide-semiconductor (PMOS) thin-film transistor (TFT) formed with the SWCNTs, and at least one n-type metal-oxide-semiconductor (NMOS) TFT formed with the SWCNTs, where each of the at least one PMOS TFT and the at least one NMOS TFT has a gate, a source and a drain. The gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage, and respectively includes a local metallic gate structure formed of a metal. At least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage VOUT.

## Background
CROSS-REFERENCE TO RELATED PATENT APPLICATION
This application claims priority to and the benefit of, pursuant to 35 U.S.C. §119(e), U.S. provisional patent application Ser. No. 61/889,841, filed Oct. 11, 2013, entitled “ULTRALOW POWER CARBON NANOTUBE LOGIC CIRCUITS,” by Mark C. Hersam, Michael L. Geier, Pradyumna L. Prabhumirashi, Weichao Xu and Hyungil Kim, which is incorporated herein in its entirety by reference.
Some references, which may include patents, patent applications and various publications, are cited and discussed in the description of this invention. The citation and/or discussion of such references is provided merely to clarify the description of the present invention and is not an admission that any such reference is “prior art” to the invention described herein. All references cited and discussed in this specification are incorporated herein by reference in their entireties and to the same extent as if each reference was individually incorporated by reference. In terms of notation, hereinafter, superscript “n” represents the nth reference cited in the reference list. For example, superscript6 represents the 6th reference cited in the reference list, namely, Hersam, M. C. Nature Nanotech. 2008, 3, 387-394.


STATEMENT AS TO RIGHTS UNDER FEDERALLY-SPONSORED RESEARCH
This invention was made with government support under grant numbers DMR-1006391 and DMR-1121262 awarded by the National Science Foundation and under grant number N00014-11-1-0690 awarded by the Office of Naval Research. The government has certain rights in the invention.


FIELD OF THE INVENTION
The present invention relates generally to complementary metal-oxide-semiconductor (CMOS) and carbon nanotube (CNT) technology, and more particularly to ultralow power CMOS logic circuits and devices using CNTs, methods of making the same, and applications of the same.
BACKGROUND OF THE INVENTION
A transistor is a semiconductor device used to amplify and switch electronic signals and electrical power, which is composed of semiconductor material with at least three terminals for connection to an external circuit. Transistors are commonly used logical circuits and devices. However, power consumption during operation of the transistors is a significant issue. In order to reduce the power consumption, various types of transistors and materials used for the transistors have been discussed. However, previous studies have not addressed any transistors or logic circuits with satisfactory ultralow power consumption.
Therefore, a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies.
SUMMARY OF THE INVENTION
One aspect of the disclosure provides a complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs). In certain embodiments, the CMOS logic device includes: at least one p-type metal-oxide-semiconductor (PMOS) thin-film transistor (TFT) formed with the SWCNTs, where each of the at least one PMOS TFT has a gate, a source and a drain; and at least one n-type metal-oxide-semiconductor (NMOS) TFT formed with the SWCNTs, where each of the at least one NMOS TFT has a gate, a source and a drain. The gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage. At least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage VOUT. In certain embodiments, the gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT respectively includes a local metallic gate structure formed of a metal.
In one embodiment, a linear tube density of the SWCNTs in the at least one PMOS TFT and the at least one NMOS TFT is about 18 nanotubes/μm.
In certain embodiments, each of the at least one NMOS TFT is chemically doped with benzyl viologen.
In one embodiment, the metal of the local metal gate structure is nickel (Ni).
In certain embodiments, the CMOS logic device has a static power consumption of less than about 0.1 nW in a static state, and a peak power consumption of about 10 nW in a transfer state.
In one embodiment, the CMOS logic device is a logic inverter. In certain embodiment, the at least one PMOS TFT includes a first PMOS TFT; the at least one NMOS TFT includes a first NMOS TFT; and the at least one input voltage includes a common input voltage VIN. In certain embodiments, the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a common input voltage line for alternatively receiving the common input voltage VIN; the drain of the first PMOS TFT and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for alternatively outputting the output voltage VOUT; the source of the first PMOS TFT is connected to a power supply VDD; and the source of the first NMOS TFT is connected to ground. In one embodiment, the CMOS logic device has a low noise margin (NM) of about 0.32 VDD, and a high NM of about 0.54 VDD.
In one embodiment, the CMOS logic device is a logic NAND gate. In certain embodiment, the at least one PMOS TFT includes a first PMOS TFT and a second PMOS TFT; the at least one NMOS TFT includes a first NMOS TFT and a second NMOS TFT; and the at least one input voltage includes a first input voltage VA and a second input voltage VB. In certain embodiments, the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage VA; the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage VB; the drain of the first PMOS TFT, the drain of the second PMOS TFT, and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for outputting the output voltage VOUT; the source of the first PMOS TFT and the source of the second PMOS TFT are respectively electrically connected to a power supply VDD; the source of the first NMOS TFT is electrically connected to the drain of the second NMOS TFT; and the source of the second NMOS TFT is electrically connected to ground.
In one embodiment, the CMOS logic device is a logic NOR gate. In certain embodiment, the at least one PMOS TFT includes a first PMOS TFT and a second PMOS TFT; the at least one NMOS TFT includes a first NMOS TFT and a second NMOS TFT; and the at least one input voltage includes a first input voltage VA and a second input voltage VB. In certain embodiments, the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage VA; the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage VB; the drain of the first PMOS TFT, the drain of the first NMOS TFT, and the drain of the second NMOS TFT are respectively electrically connected to a common output voltage line for outputting the output voltage VOUT; the source of the second PMOS TFT is electrically connected to a power supply VDD; the source of the first PMOS TFT is electrically connected to the drain of the second PMOS TFT; and the source of the first NMOS TFT and the source of the second NMOS TFT are respectively electrically connected to ground.
In certain embodiments, the CMOS logic device further includes: a first encapsulation layer covering the at least one PMOS TFT; and a second encapsulation layer covering the at least one NMOS TFT and the first encapsulation layer. In one embodiment, the first encapsulation layer is formed by a photoresist, and the second encapsulation layer is formed by Al2O3.
In another aspect of the disclosure, a CMOS logic device formed with carbon nanotubes (CNTs) is provided. In one embodiment, the CMOS logic device includes: at least one PMOS transistor formed with the CNTs, where each of the at least one PMOS transistor has a gate, a source and a drain; and at least one NMOS transistor formed with the CNTs, where each of the at least one NMOS transistor has a gate, a source and a drain. The gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor is configured to alternatively receive at least one input voltage. At least one of the drain of the at least one PMOS transistor and the drain of the at least one NMOS transistor is configured to output an output voltage VOUT. The gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor respectively comprises a local metallic gate structure formed of a metal.
In certain embodiments, each of the at least one PMOS transistor and each of the at least one NMOS transistor is a TFT.
In one embodiment, the metal of the local metal gate structure is nickel (Ni).
In certain embodiments, the CMOS logic device has a static power consumption of less than about 0.1 nW in a static state, and a peak power consumption of about 10 nW in a transfer state.
In certain embodiments, the CNTs are SWCNTs. In one embodiment, a linear tube density of the SWCNTs in the at least one PMOS transistor and the at least one NMOS transistor is about 18 nanotubes/μm. In certain embodiments, each of the at least one NMOS transistor is chemically doped with benzyl viologen.
In one embodiment, the CMOS logic device is a logic inverter. In certain embodiment, the at least one PMOS transistor includes a first PMOS TFT; the at least one NMOS transistor includes a first NMOS TFT; and the at least one input voltage includes a common input voltage VIN. In certain embodiments, the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a common input voltage line for alternatively receiving the common input voltage VIN; the drain of the first PMOS TFT and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for alternatively outputting the output voltage VOUT; the source of the first PMOS TFT is connected to a power supply VDD; and the source of the first NMOS TFT is connected to ground. In one embodiment, the CMOS logic device has a low NM) of about 0.32 VDD, and a high NM of about 0.54 VDD.
In one embodiment, the CMOS logic device is a logic NAND gate. In certain embodiment, the at least one PMOS transistor includes a first PMOS TFT and a second PMOS TFT; the at least one NMOS transistor includes a first NMOS TFT and a second NMOS TFT; and the at least one input voltage includes a first input voltage VA and a second input voltage VB. In certain embodiments, the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage VA; the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage VB; the drain of the first PMOS TFT, the drain of the second PMOS TFT, and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for outputting the output voltage VOUT; the source of the first PMOS TFT and the source of the second PMOS TFT are respectively electrically connected to a power supply VDD; the source of the first NMOS TFT is electrically connected to the drain of the second NMOS TFT; and the source of the second NMOS TFT is electrically connected to ground.
In one embodiment, the CMOS logic device is a logic NOR gate. In certain embodiment, the at least one PMOS transistor includes a first PMOS TFT and a second PMOS TFT; the at least one NMOS transistor includes a first NMOS TFT and a second NMOS TFT; and the at least one input voltage includes a first input voltage VA and a second input voltage VB. In certain embodiments, the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage VA; the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage VB; the drain of the first PMOS TFT, the drain of the first NMOS TFT, and the drain of the second NMOS TFT are respectively electrically connected to a common output voltage line for outputting the output voltage VOUT; the source of the second PMOS TFT is electrically connected to a power supply VDD; the source of the first PMOS TFT is electrically connected to the drain of the second PMOS TFT; and the source of the first NMOS TFT and the source of the second NMOS TFT are respectively electrically connected to ground.
In certain embodiments, the CMOS logic device further includes: a first encapsulation layer covering the at least one PMOS transistor; and a second encapsulation layer covering the at least one NMOS transistor and the first encapsulation layer. In one embodiment, the first encapsulation layer is formed by a photoresist, and the second encapsulation layer is formed by Al2O3.
A further aspect of the disclosure relates to a method of fabricating a CMOS logic device with SWCNTs, including: forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor, wherein each of the at least one NMOS transistor and each of the at least one PMOS transistor has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor is configured to alternatively receive at least one input voltage. At least one of the drain of the at least one PMOS transistor and the drain of the at least one NMOS transistor is configured to output an output voltage VOUT.
In certain embodiments, each of the at least one PMOS transistor and each of the at least one NMOS transistor is a TFT.
In one embodiment, the metal of each of the local metal gate structures is nickel (Ni). In a further embodiment, the method further includes: depositing a layer of Al2O3 over the substrate to cover the Ni of each of the local metal gate structures.
In certain embodiments, the method further includes: depositing a first encapsulation layer on the substrate to cover the at least one PMOS transistor and the at least one NMOS transistor, where the first encapsulation layer is formed by a photoresist; removing a part of the first encapsulation layer to expose the at least one NMOS transistor, such that the remaining first encapsulation layer covers the at least one PMOS transistor; and coating a second encapsulation layer to cover the exposed at least one NMOS TFT and the remaining first encapsulation layer, wherein the second encapsulation layer is formed by Al2O3.
In certain embodiments, the step of forming a plurality of contacts on the substrate includes: patterning the contacts on the substrate by photolithography.
In certain embodiments, the step of depositing the SWCNTs on the substrate includes: depositing the SWCNTs on a membrane; stamping the membrane with the SWCNTs on the substrate; and submerging the substrate with the membrane and the SWCNTs thereon in a solvent to dissolve the membrane. In one embodiment, the solvent is acetone. In certain embodiments, the step of depositing the SWCNTs on the substrate further includes: covering a plurality of channel areas of the SWCNTs on the substrate with a photoresist; and etching the SWCNTs outside the channel areas by reactive ion etching.
In certain embodiments, the step of doping a certain area of the SWCNTs includes: annealing the substrate in vacuum at an annealing temperature for a period of time; and depositing a benzyl viologen solution onto the certain area of the SWCNTs to form the at least one NMOS transistor. In one embodiment, the annealing temperature is about 200° C., and the period of time is about 1 hour.
In one embodiment, the CMOS logic device is a logic inverter. In certain embodiment, the at least one PMOS transistor includes a first PMOS TFT; the at least one NMOS transistor includes a first NMOS TFT; and the at least one input voltage includes a common input voltage VIN. In certain embodiments, the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a common input voltage line for alternatively receiving the common input voltage VIN; the drain of the first PMOS TFT and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for alternatively outputting the output voltage VOUT; the source of the first PMOS TFT is connected to a power supply VDD; and the source of the first NMOS TFT is connected to ground. In one embodiment, the CMOS logic device has a low NM of about 0.32 VDD, and a high NM of about 0.54 VDD.
In one embodiment, the CMOS logic device is a logic NAND gate. In certain embodiment, the at least one PMOS transistor includes a first PMOS TFT and a second PMOS TFT; the at least one NMOS transistor includes a first NMOS TFT and a second NMOS TFT; and the at least one input voltage includes a first input voltage VA and a second input voltage VB. In certain embodiments, the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage VA; the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage VB; the drain of the first PMOS TFT, the drain of the second PMOS TFT, and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for outputting the output voltage VOUT; the source of the first PMOS TFT and the source of the second PMOS TFT are respectively electrically connected to a power supply VDD; the source of the first NMOS TFT is electrically connected to the drain of the second NMOS TFT; and the source of the second NMOS TFT is electrically connected to ground.
In one embodiment, the CMOS logic device is a logic NOR gate. In certain embodiment, the at least one PMOS transistor includes a first PMOS TFT and a second PMOS TFT; the at least one NMOS transistor includes a first NMOS TFT and a second NMOS TFT; and the at least one input voltage includes a first input voltage VA and a second input voltage VB. In certain embodiments, the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage VA; the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage VB; the drain of the first PMOS TFT, the drain of the first NMOS TFT, and the drain of the second NMOS TFT are respectively electrically connected to a common output voltage line for outputting the output voltage VOUT; the source of the second PMOS TFT is electrically connected to a power supply VDD; the source of the first PMOS TFT is electrically connected to the drain of the second PMOS TFT; and the source of the first NMOS TFT and the source of the second NMOS TFT are respectively electrically connected to ground.
A further aspect of the disclosure may relate to a CMOS logic device formed by any of the methods as described above.
The CMOS logic device as described above may be applicable in an apparatus, which may include one or more of the CMOS logic device as described above.
These and other aspects of the present invention will become apparent from the following description of the preferred embodiment taken in conjunction with the following drawings, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure.



BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings illustrate one or more embodiments of the invention and together with the written description, serve to explain the principles of the invention. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like elements of an embodiment.
FIG. 1 shows schematically a circuit diagram of a CMOS logic inverter according to certain embodiments of the disclosure.
FIG. 2 shows schematically a SWCNT CMOS logic inverter structure according to certain embodiments of the disclosure, where (a) shows the SWCNT CMOS inverter including the unencapsulated p-type TFT and benzyl viologen doped n-type TFT; (b) shows a cross-section of an individual SWCNT TFT, and (c) shows an atomic force microscopy image of the SWCNT film morphology in the TFT channel region.
FIG. 3 shows the n-type dopant benzyl viologen in toluene and its chemical structure according to certain embodiments of the disclosure.
FIG. 4 shows UV-vis-NIR optical absorbance spectra of both sorted and unsorted SWCNTs according to certain embodiments of the disclosure.
FIG. 5 shows SWCNT TFT electrical characteristics according to certain embodiments of the disclosure, where (a) shows the Log-linear transfer characteristics (IDS vs. VGS) of a p-type TFT (blue) at VDS=−1 V and n-type TFT (green) at VDS=1 V; (b) shows the output characteristics (IDS vs. VDS) of a p-type TFT (left axis) from VGS=−1 V to 0 V in 0.25 V steps and n-type TFT (right axis) from VGS=1 V to 0 V in 0.25 V steps; (c) shows the linear-linear transfer characteristics for PMOS (blue) at VDS=−1 V and for NMOS (green) at VDS=1 V with the linear region fit shown for VT extraction; and (d) shows the statistical distribution of VT for 30 p-type TFTs (blue) and 30 n-type TFTs (green).
FIG. 6 shows a diagram of gate leakage current vs. VGS according to certain embodiments of the disclosure.
FIG. 7 shows a diagram of capacitance-voltage profile of 10 nm thick ALD Al2O3 on Ni diagram according to certain embodiments of the disclosure.
FIG. 8 shows SWCNT CMOS inverter electrical characteristics according to certain embodiments of the disclosure, where (a) shows the voltage transfer curves for VDD=0.8 V, 1 V, and 1.25 V; (b) shows power; (c) shows gain characteristics of the CMOS inverter at the same values of VDD; and (d) shows linear dependence of peak gain as function of VDD.
FIG. 9 shows the two-input CMOS NAND and NOR gate electrical characteristics according to certain embodiments of the disclosure, where (a) shows a CMOS logic NAND circuit diagram and associated truth table; (b) shows a CMOS logic NOR circuit diagram and associated truth table; (c) shows the output voltages (VOUT) for each possible two input state for the NAND circuit; (d) shows the output voltages (VOUT) for each possible two input state for the NOR circuit; (e) shows NAND power consumption for each possible two input state; and (f) shows NOR power consumption for each possible two input state.
FIG. 10 shows NAND transfer characteristics according to certain embodiments of the disclosure, where (a) shows the transfer schematic, in which inputs A and B are simultaneously swept from a logic “0” state (GND) to a logic “1” state (VDD); (b) shows the transfer characteristics at different supply voltages (VDD); (c) shows power consumption at different supply voltages (VDD) vs. VIN; and (d) shows gain at different supply voltages (VDD) vs. VIN.
FIG. 11 shows NOR transfer characteristics according to certain embodiments of the disclosure, where (a) shows the transfer schematic, input A is held at logic “0” (GND) while input B is swept from a logic “0” state (GND) to a logic “1” state (VDD); (b) shows the transfer characteristics at different supply voltages (VDD); (c) shows power consumption at different supply voltages (VDD) vs. VIN; and (d) shows gain at different supply voltages (VDD) vs. VIN.
FIG. 12 shows voltage transfer curves (at VDD=1 V) for an SWCNT CMOS inverter taken 3 weeks apart according to certain embodiments of the disclosure.
FIG. 13 shows hysteresis and representative IDS-VGS curves for n-type SWCNT TFTs according to certain embodiments of the disclosure, where typical transfer plots (taken at VDS=0.5 V) for 4 different n-type SWCNT TFTs, and the arrows indicate the direction of the voltage sweep.
FIG. 14 shows variability of n-type SWCNT TFTs according to certain embodiments of the disclosure, where histograms of 20 representative n-type SWCNT TFTs are used, and (a) shows ION/IOFF ratio, (b) shows electron mobility, and (c) shows channel width normalized ON current (ION/W), measured at VDS=0.1 V. All devices have a channel width of 100 μm and a channel length of 20 μm.
FIG. 15 shows array of p-type and n-type SWCNT TFTs according to certain embodiments of the disclosure, where (a) shows optical micrographs of the fabricated SWCNT TFT device (inset) and array of SWCNT TFTs (Scale bar: inset: 200 μm, a: 1 mm); (b) shows atomic force micrograph of the random network SWCNT morphology in the TFT channel; and (c) shows schematic cross-sections of both p-type SWCNT TFT and n-type SWCNT TFT. TFTs are fabricated using SiO2 (300 nm) on a Si substrate, a local Ni (25 nm) gate, Al2O3 (10 nm) gate dielectric deposited by atomic layer deposition (ALD), gate via channel through the dielectric by reactive ion etching, Cr/Au (1 nm/50 nm) source/drain contacts, >98% semiconducting SWCNTs deposited by vacuum filtration film transfer method, p-type encapsulant ( ̃1.3 μm 51813 photoresist), n-type dopant benzyl viologen ( ̃100 nm), and final top encapsulant (50 nm ALD Al2O3).
FIG. 16 shows time stability of p-type and n-type SWCNT TFTs electrical properties according to certain embodiments of the disclosure, where (a) shows the log-linear transfer (IDS-VGS) curves for final encapsulated p-type (solid) and n-type (dashed) SWCNT TFTs measured initially after exposure to atmosphere (blue) and after 7 hours of atmospheric exposure (green) at VDS=1 V; (b) shows the log-linear transfer (IDS-VGS) curves for unencapsulated SWCNT TFTs p-type (solid) and n-type (dashed) TFTs measured initially after exposure to atmosphere (blue) and after 5 hours of atmospheric exposure (red); (c) shows the log(ION/IOFF) of p-type TFTs vs. atmospheric exposure time for repeated transfer measurements of a single encapsulated (purple) and unencapsulated (black) SWCNT TFT; and (d) shows the log(ION/IOFF) of n-type TFTs vs. atmospheric exposure time for repeated transfer measurements of a single encapsulated (purple) and unencapsulated (black) SWCNT TFT.
FIG. 17 shows histograms for large sample statistics of SWCNT TFT electronic properties according to certain embodiments of the disclosure, where (a)-(b) show the log(ION/IOFF) of p-type and n-type TFTs for encapsulated (purple) and unencapsulated (black) where each device is measured once; (c) shows subthreshold swing for encapsulated (purple) and unencapsulated (black) p-type SWCNT TFTs; (d) shows log(IDS) values when VGS=0V for encapsulated (purple) and unencapsulated (black) n-type TFTs; and (e) shows the threshold voltage distributions for encapsulated (purple) and unencapsulated (black) p-type (solid) and n-type (striped) TFTs.



DETAILED DESCRIPTION OF THE INVENTION
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.
Definitions
The terms used in this specification generally have their ordinary meanings in the art, within the context of the invention, and in the specific context where each term is used. Certain terms that are used to describe the invention are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner regarding the description of the invention. For convenience, certain terms may be highlighted, for example using italics and/or quotation marks. The use of highlighting has no influence on the scope and meaning of a term; the scope and meaning of a term is the same, in the same context, whether or not it is highlighted. It will be appreciated that same thing can be said in more than one way. Consequently, alternative language and synonyms may be used for any one or more of the terms discussed herein, nor is any special significance to be placed upon whether or not a term is elaborated or discussed herein. Synonyms for certain terms are provided. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms discussed herein is illustrative only, and in no way limits the scope and meaning of the invention or of any exemplified term. Likewise, the invention is not limited to various embodiments given in this specification.
It will be understood that, as used in the description herein and throughout the claims that follow, the meaning of “a”, “an”, and “the” includes plural reference unless the context clearly dictates otherwise. Also, it will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can therefore, encompasses both an orientation of “lower” and “upper,” depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” or “has” and/or “having” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, “around”, “about” or “approximately” shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around”, “about” or “approximately” can be inferred if not expressly stated.
As used herein, the terms “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to.
As used herein, if any, the term “scanning electron microscope” or its abbreviation “SEM” refers to a type of electron microscope that images the sample surface by scanning it with a high-energy beam of electrons in a raster scan pattern. The electrons interact with the atoms that make up the sample producing signals that contain information about the sample's surface topography, composition and other properties such as electrical conductivity.
As used herein, a “nanostructure” refers to an object of intermediate size between molecular and microscopic (micrometer-sized) structures. In describing nanostructures, the sizes of the nanostructures refer to the number of dimensions on the nanoscale. For example, nanotextured surfaces have one dimension on the nanoscale, i.e., only the thickness of the surface of an object is between 0.1 and 1000 nm. Sphere-like nanoparticles have three dimensions on the nanoscale, i.e., the particle is between 0.1 and 1000 nm in each spatial dimension. A list of nanostructures includes, but not limited to, nanoparticle, nanocomposite, quantum dot, nanofilm, nanoshell, nanofiber, nanoring, nanorod, nanowire, nanotube, and so on.
Overview of the Invention
Certain aspect of the present invention relates to, among other things, single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics as required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, sub-nanowatt static power consumption, high gain, and excellent noise immunity. This invention provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.
SWCNTs possess exceptional electronic characteristics and have been explored for applications in solution processable, flexible, high performance electronics.1-5 In particular, advances in semiconducting SWCNT sorting6-10 and integration techniques11-13 have enabled the fabrication of random network unipolar14-20 and ambipolar21-23 logic devices ranging from transistors to 4-bit row decoders.24 However, as SWCNT electronics moves from individual device demonstrations to highly integrated circuits, unipolar/ambipolar transistors present significant issues, most notably high power consumption. Although there have been demonstrations25-27 of random network SWCNT-based complementary metal-oxide-semiconductor (CMOS) circuits, these early works did not realize the principal advantage of CMOS logic, namely low power consumption, due to suboptimal threshold voltage control. In this disclosure, SWCNT-based CMOS logic circuits are provided with sub-nanowatt static power consumption via threshold voltage tuning of the constituent p-type and n-type SWCNT transistors. The resulting ultralow power SWCNT CMOS logic circuits possess symmetric voltage transfer curves, high gain, and wide noise margins that are suitable for logic gate cascading and large-scale integration.
The development of solution-processed semiconducting SWCNTs has allowed large-area deposition of random network SWCNT films, leading to extensive studies of SWCNT thin-film transistors (TFTs) in a variety of device structures.15,16,21 Due to adventitious atmospheric doping of SWCNT TFTs under ambient conditions, p-type unipolar devices have dominated prior efforts that have primarily focused on optimizing the tradeoff between mobility and current on/off ratio (ION/IOFF).13,14,17 However, when implemented in logic circuits, unipolar devices sustain high steady-state currents, which lead to significant steady-state power consumption during operation. In contrast, CMOS logic is the backbone of modern microelectronics since either the constituent p-type or n-type transistor is turned off in each logic gate, resulting in intrinsically low power consumption and thus the ability to be implemented in efficient large-scale integrated circuits.28 Moreover, CMOS logic offers large noise margins, which allows robust and reliable operation in highly complex circuitry that inevitably encounters large parametric shifts. These enabling advantages of CMOS technology not only require the realization and integration of p-type and n-type transistors, but also precisely tuned, well-separated threshold voltages to ensure that the complementary devices are not concurrently passing on-current and thus not dissipating high steady-state power. This critical issue has not been addressed in previous SWCNT TFT studies,14-23 and thus stands as the key challenge limiting the realization of highly integrated SWCNT-based CMOS electronics.
One aspect of the disclosure provides a CMOS logic device formed with SWCNTs. In certain embodiments, the CMOS logic device includes: at least one PMOS TFT formed with the SWCNTs, where each of the at least one PMOS TFT has a gate, a source and a drain; and at least one NMOS TFT formed with the SWCNTs, where each of the at least one NMOS TFT has a gate, a source and a drain. The gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage. At least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage VOUT. In certain embodiments, the gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT respectively includes a local metallic gate structure formed of a metal.
In another aspect of the disclosure, a CMOS logic device formed with carbon nanotubes (CNTs) is provided. In one embodiment, the CMOS logic device includes: at least one PMOS transistor formed with the CNTs, where each of the at least one PMOS transistor has a gate, a source and a drain; and at least one NMOS transistor formed with the CNTs, where each of the at least one NMOS transistor has a gate, a source and a drain. The gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor is configured to alternatively receive at least one input voltage. At least one of the drain of the at least one PMOS transistor and the drain of the at least one NMOS transistor is configured to output an output voltage VOUT. The gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor respectively comprises a local metallic gate structure formed of a metal.
A further aspect of the disclosure relates to a method of fabricating a CMOS logic device with SWCNTs, including: forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor, wherein each of the at least one NMOS transistor and each of the at least one PMOS transistor has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor is configured to alternatively receive at least one input voltage. At least one of the drain of the at least one PMOS transistor and the drain of the at least one NMOS transistor is configured to output an output voltage VOUT.
In certain embodiments, the CMOS logic device as described above and/or formed by the method as described may be a logic inverter, a logic NAND gate, or a logic NOR gate.
These and other aspects of the present invention are further described below.
Implementations and Examples of the Invention
Without intent to limit the scope of the invention, exemplary instruments, apparatus, methods and their related results according to the embodiments of the present invention are given below. Note that titles or subtitles may be used in the examples for convenience of a reader, which in no way should limit the scope of the invention. Moreover, certain theories are proposed and disclosed herein; however, in no way they, whether they are right or wrong, should limit the scope of the invention so long as the invention is practiced according to the invention without regard for any particular theory or scheme of action.
Example One
In one embodiment, threshold voltage control is demonstrated for both p-type and n-type SWCNT TFTs via a local Ni gate structure, which enables ultralow power complementary device operation. For example, a high-performance SWCNT CMOS inverter (logic NOT gate) is provided with reference to FIG. 1 as an initial illustration of this device architecture.
FIG. 1 shows schematically a circuit diagram of a CMOS logic inverter according to certain embodiments of the disclosure. As shown in FIG. 1, the CMOS logic inverter includes a p-type MOS (PMOS) transistor and an n-type MOS (NMOS) transistor. Each of the PMOS and NMOS transistors has a gate, a source and a drain. As shown in FIG. 1, the gate of the PMOS transistor and the gate of the NMOS transistor are respectively electrically connected to a common input voltage line for alternatively receiving a common input voltage VIN. The drain of the first PMOS transistor and the drain of the NMOS transistor are respectively electrically connected to a common output voltage line for alternatively outputting the output voltage VOUT. The source of the PMOS transistor is connected to a power supply VDD, and the source of the NMOS transistor is connected to ground. In other words, the PMOS transistor and the NMOS transistor are connected in series.
FIG. 2 shows schematically a SWCNT CMOS logic inverter structure according to certain embodiments of the disclosure, where (a) shows the SWCNT CMOS inverter including the unencapsulated p-type TFT and benzyl viologen doped n-type TFT; (b) shows a cross-section of an individual SWCNT TFT, and (c) shows an atomic force microscopy image of the SWCNT film morphology in the TFT channel region. FIG. 3 shows the n-type dopant benzyl viologen in toluene and its chemical structure according to certain embodiments of the disclosure. FIG. 4 shows a UV-vis-NIR optical absorbance spectra of both sorted and unsorted SWCNTs according to certain embodiments of the disclosure. As shown in FIG. 2(a), the inverter structure includes an unencapsulated SWCNT p-type TFT and a SWCNT n-type TFT that is chemically doped with benzyl viologen (as shown in FIG. 3).29 The p-type and n-type TFTs share a common input voltage (VIN) at their gates and a common output voltage (VOUT) at their drains. In addition, the p-type TFT source is connected to the power supply (VDD), and the n-type TFT source is connected to ground (GND). FIG. 2(b) shows the cross-section of an individual SWCNT TFT structure with further details. As shown in FIG. 2(b), the SWCNT TFT includes a 300 nm SiO2 on Si substrate, a local Ni (25 nm thick) gate patterned by photolithography, a conformal 10 nm Al2O3 layer deposited via atomic layer deposition (ALD), >99% semiconductor purity SWCNTs deposited by vacuum filtration film transfer, and Cr/Au (2 nm/50 nm) source/drain contacts. In addition, the atomic force microscope (AFM) image as shown in FIG. 2(c) illustrates the uniformity of the SWCNT network in the TFT channel region with a linear tube density of  ̃18 nanotubes/μm ( ̃99% semiconducting purity SWCNTs; see also FIG. 4), which will be described in detail later.
FIG. 5 shows SWCNT TFT electrical characteristics according to certain embodiments of the disclosure. FIG. 6 shows a diagram of gate leakage current vs. VGS according to certain embodiments of the disclosure. FIG. 7 shows a diagram of capacitance-voltage profile of 10 nm thick ALD Al2O3 on Ni diagram according to certain embodiments of the disclosure. Specifically, FIG. 5(a) shows the log-linear transfer characteristics of the constituent p-type and n-type TFTs with channel lengths of 20 μm and widths of 100 μm. The individual transistors have ION/IOFF of  ̃105 and subthreshold slopes of  ̃125 mV/decade (p-type) and  ̃175 mV/decade (n-type) over the CMOS operating voltage range of each device, namely VGS of the p-type TFT is between −VDD and GND, and VGS of the n-type TFT is between GND and VDD. The gate dielectric (10 nm Al2O3) has a leakage current of less than 100 pA (as shown in FIG. 6) in the operational voltage window (−1 V to 1 V) and a capacitance of  ̃850 nF/cm2 (as shown in FIG. 7). FIG. 5(b) shows well-balanced output characteristics for the p-type TFT (VGS varied from 0 V to −1 V in 0.25 V steps) and n-type TFT (VGS varied from 0 V to 1 V in 0.25 V steps). VT for both the p-type and n-type TFTs is determined by extrapolation from the linear transfer characteristics as shown in FIG. 5(c). The use of the local metallic (Ni) gate structure is critical to obtaining a negative VT for p-type SWCNT TFTs as demonstrated previously.15 Upon conversion of the p-type TFTs to n-type TFTs via benzyl viologen doping, the VT for the n-type TFT becomes analogously positive, thus achieving the symmetric VT separation required for ultralow power CMOS. In particular, FIG. 5(d) shows a histogram of extracted VT for the p-type and n-type TFTs, demonstrating clearly separated and symmetric VT with negative VT for the p-type TFTs and positive VT for the n-type TFTs.
FIG. 8 shows SWCNT CMOS inverter electrical characteristics according to certain embodiments of the disclosure, where (a) shows the voltage transfer curves for VDD=0.8 V, 1 V, and 1.25 V; (b) shows power; (c) shows voltage gain characteristics of the CMOS inverter at the same values of VDD; and (d) shows linear dependence of peak gain as function of VDD.
As shown in the inset of FIG. 8(a), the CMOS inverter performance is investigated using the device geometry as shown in FIG. 1. FIG. 8(a) shows the inverter voltage transfer characteristics for different supply voltages (VDD=0.8 V, 1.0 V, and 1.25 V). At low input voltage (VIN=GND), equivalent to logic “0”, VOUT is pulled up to VDD, equivalent to logic “1”. Similarly, at high input voltage (VIN=VDD), equivalent to logic “1”, VOUT is pulled down to GND, equivalent to logic “0”. Thus, the SWCNT CMOS inverter demonstrates a full rail-to-rail (VDD to GND) transfer curve in a symmetric operating voltage window. The noise margins (NM) for this device are NMLOW=0.32 VDD and NMHIGH=0.54 VDD for all VDD, thereby providing excellent tolerance against incoming signal variation and suitability for inverter cascading as well as further device integration.
FIG. 8(b) shows the power consumption (P=VDD×IGND) of the CMOS inverter during transfer at different supply voltages. The power consumption is less than 0.1 nW in the static states of VIN=VDD and VIN=GND. The peak power consumption is less than 10 nW (for all VDD) and occurs approximately at the midpoint of the transfer state (VIN=VOUT) when the p-type and n-type TFTs are simultaneously in the ON-state. The ultralow power consumption demonstrated by these devices, representing the lowest reported value by 3 orders of magnitude for random network SWCNT-based CMOS logic,25-27 is enabled by the symmetric and well-separated threshold voltages for the p-type and n-type TFTs. FIG. 8(c) shows the gain (dVOUT/dVIN) of the inverter, including a peak gain in excess of 25 at VDD=1.25 V. The peak gain shows a linearly increasing relationship, as shown in FIG. 8(d), with respect to VDD, and is likely due to VDD being comparable to the threshold voltages of the TFTs, allowing increasing transconductance with increasing VDD.
Example Two
To demonstrate the next level of CMOS integration, NAND and NOR logic gates were fabricated. FIG. 9 shows the two-input CMOS NAND and NOR gate electrical characteristics according to certain embodiments of the disclosure, where (a) shows a CMOS logic NAND circuit diagram and associated truth table; (b) shows a CMOS logic NOR circuit diagram and associated truth table; (c) shows the output voltages (VOUT) for each possible two input state for the NAND circuit; (d) shows the output voltages (VOUT) for each possible two input state for the NOR circuit; (e) shows NAND power consumption for each possible two input state; and (f) shows NOR power consumption for each possible two input state. The supply voltage (VDD) for the circuits is 0.8 V. Input voltages of 0 V (GND) and 0.8 V (VDD) are treated as logic “0” and “1”, respectively.
As shown in FIG. 9(a), a logic NAND gate is realized by connecting two n-type TFTs in series and two p-type TFTs in parallel. Specifically, the NAND gate includes a first PMOS TFT and a second PMOS TFT, and a first NMOS TFT and a second NMOS TFT. The gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage VA; the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage VB; the drain of the first PMOS TFT, the drain of the second PMOS TFT, and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for outputting the output voltage VOUT; the source of the first PMOS TFT and the source of the second PMOS TFT are respectively electrically connected to a power supply VDD; the source of the first NMOS TFT is electrically connected to the drain of the second NMOS TFT; and the source of the second NMOS TFT is electrically connected to ground.
As shown in FIG. 9(b), a logic NOR gate employs two n-type TFTs in parallel and two p-type TFTs in series. Specifically, the NAND gate includes a first PMOS TFT and a second PMOS TFT, and a first NMOS TFT and a second NMOS TFT. The gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage VA; the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage VB; the drain of the first PMOS TFT, the drain of the first NMOS TFT, and the drain of the second NMOS TFT are respectively electrically connected to a common output voltage line for outputting the output voltage VOUT; the source of the second PMOS TFT is electrically connected to a power supply VDD; the source of the first PMOS TFT is electrically connected to the drain of the second PMOS TFT; and the source of the first NMOS TFT and the source of the second NMOS TFT are respectively electrically connected to ground.
FIGS. 9(c) and 9(d) show VOUT for the four possible input states of A and B for NAND and NOR gates, respectively. In all cases, VIN (A and B) is set at VDD for the logic state “1”, and VIN is set at 0 V (GND) for the logic state of “0”. For the CMOS NAND logic gate, VOUT becomes logic “0” only when both A and B are in the logic “1” state. Conversely, for the CMOS NOR logic gate, VOUT is the logic “1” level only when both A and B are in the logic “0” state. These tests confirm that in both SWCNT CMOS NAND and NOR devices, the logic gates demonstrate ideal rail-to-rail output voltages for the appropriate two input state. In all static states, the power consumption is on the order of 0.1 nW as shown in FIG. 9(e) for the NAND gate and FIG. 9(f) for the NOR gate. In addition, during the transition between the output states of logic “1” (VOUT=VDD) and “0” (VOUT=GND), the NAND and NOR gates show a peak power of  ̃10 nW as expected from the earlier inverter discussion.
FIG. 10 shows NAND transfer characteristics according to certain embodiments of the disclosure, where (a) shows the transfer schematic, in which inputs A and B are simultaneously swept from a logic “0” state (GND) to a logic “1” state (VDD); (b) shows the transfer characteristics at different supply voltages (VDD); (c) shows power consumption at different supply voltages (VDD) vs. VIN; and (d) shows gain at different supply voltages (VDD) vs. VIN. FIG. 11 shows NOR transfer characteristics according to certain embodiments of the disclosure, where (a) shows the transfer schematic, input A is held at logic “0” (GND) while input B is swept from a logic “0” state (GND) to a logic “1” state (VDD); (b) shows the transfer characteristics at different supply voltages (VDD); (c) shows power consumption at different supply voltages (VDD) vs. VIN; and (d) shows gain at different supply voltages (VDD) vs. VIN. The gain behavior of NAND and NOR gates (as shown in FIGS. 10 and 11) is also similar to the inverter, showing a linear increase in peak gain with respect to applied voltage, VDD. Overall, these CMOS NAND and NOR logic gates are suitable for further integration into complex circuits due to their ideal input and output voltage behavior while concurrently possessing sub-nanowatt static power consumption.
Example Three
1. Preparation of Benzyl Viologen Solution for n-Type Single-Walled Carbon Nanotube Transistors
In certain embodiments, benzyl viologen dichloride (0.1 g; 97%, Aldrich) was dissolved in 5 mL of deionized water, after which 2 mL of toluene (>99.5%, Sigma Aldrich) was added on top of the water solution, creating a biphasic solution. Next, 1 mL of sodium borohydride (>98% Aldrich) in water (200 mM) was added as a catalytic reducing agent, causing the benzyl viologen solution to turn purple and evolve H2 gas. The biphasic solution was left standing overnight, and the toluene containing  ̃10 mM benzyl viologen was decanted (as shown in FIG. 3) and used for n-type doping for all n-type transistors.
2. Dispersion and Separation of SWCNTs
In certain embodiments, 45 mg of single-walled carbon nanotubes (SWCNTs) synthesized by the arc discharge method (P2, Carbon Solutions) were added to 6.6 mL of 1% w/v aqueous sodium cholate (SC) solution. This mixture was then sonicated for 60 min at 20% of the maximum tip amplitude using a horn ultrasonicator equipped with a 0.125′′ diameter probe (Fisher Scientific 500 Sonic Dismembrator). During sonication, the vial was chilled in an ice/water bath. After sonication, 1% w/v aqueous SC and sodium dodecyl sulfate (SDS) solutions containing 60% w/v iodixanol were added to the SWCNT dispersion to obtain the final iodixanol concentration of 32.5% w/v and surfactant ratio of 1:4 (SDS:SC). Prior to ultracentrifugation, the SWCNT dispersion was briefly centrifuged at 3000 rpm for 3 min to eliminate large SWCNT aggregates and carbonaceous impurities. Next, 6 mL of this SWCNT dispersion was carefully inserted below a 15 mL linear density gradient of 15-30% w/v iodixanol (1.08-1.16 g cm−3), and 0% w/v iodixanol solution was used to cap the remainder of the ultracentrifuge tube. All solutions contained a 1:4 ratio of 1% w/v SDS/SC. The linear density gradients were then ultracentrifuged for 18 h at 32 krpm in an SW 32 rotor (Beckman Coulter) at a temperature of 22° C. The resulting layer of semiconductor-enriched SWCNTs at the top of the gradient was extracted using a piston gradient fractionator (Biocomp Instruments).
3. Characterization of Semiconducting SWCNTs
In order to estimate the electronic purity of the sorted semiconducting SWCNTs, their optical absorbance spectra were measured with a Cary 5000 spectrophotometer (Agilent Technologies) operating in dual beam mode. Prior to the measurement, the extracted SWCNT fractions were diluted to 850 μL in disposable plastic cuvettes (Fisher Scientific). The baseline optical absorbance was measured with a reference aqueous solution containing 1% w/v of SDS and SC (1:4 ratio) and then subtracted from the sample spectrum. The electronic purity of the sorted semiconducting SWCNTs was determined by first subtracting out the linear background (with respect to energy) and π-plasmon resonance contributions from the measured absorbance spectra, followed by a comparison of the area of the S22 peak to that of the M11 peak. The semiconducting purity for the sorted SWCNTs was calculated to be  ̃99%, as shown in FIG. 4.
4. Device Fabrication
All CMOS circuits were fabricated on 300 nm SiO2/Si wafers purchased from Silicon Quest International. Metal gate contacts were patterned by photolithography, where 25 nm of Ni was deposited by thermal evaporation and subsequent liftoff in acetone. Atomic layer deposition (ALD) using trimethylaluminum (TMA) and water at 150° C. (Savannah, Cambridge NanoTech) was then used to deposit 10 nm of Al2O3 over the entire substrate. Source/drain contacts were then patterned by photolithography and 2 nm/50 nm of Cr/Au were deposited by thermal evaporation, followed by liftoff in acetone. Sorted semiconductor-enriched SWCNTs were then deposited on a cellulose membrane (Millipore VMWP, 0.05 μm pore size) by vacuum filtration. The cellulose membrane was wetted with isopropyl alcohol to attach the membrane by surface tension, gently stamped onto the entire substrate, and submerged in acetone to dissolve the filter membrane. Then, the substrate was patterned by photolithography, covering the SWCNT TFT channel areas with Shipley S1813 photoresist. Reactive ion etching in an oxygen plasma atmosphere (100 mW, 15 sec, 20 sccm O2) etched the nanotubes outside of the channel after which the substrate was soaked in acetone overnight to remove residual organic materials. The substrate was then transferred to a nitrogen atmosphere glove box and annealed in vacuum (50 mTorr) at 200° C. for 1 h. Inside the glove box, the benzyl viologen solution was deposited on the intended n-type TFTs and allowed to dry.
5. Electrical Testing Scheme
Output, transfer, and leakage characteristics of the TFTs and logic devices were measured using Keithley 2400 source meters and home-written LabView programs. For TFT measurements, the gate voltage was swept at a rate of 0.5 V/sec in steps of 0.05 V from 0 V to VDD. For the logic gate measurements, VIN was swept at a rate of 0.1 V/sec in steps of 0.01 V. For all measurements, the input voltages and currents were measured simultaneously for each contact.
6. Dielectric Characterization
As-fabricated substrates containing the Ni gate contact, ALD dielectric, and source/drain contacts were tested for dielectric leakage, with a typical leakage profile given in FIG. 6 (Keithley 2400 source meters). To measure the capacitance of the dielectric, a planar Ni electrode was thermally evaporated, followed by ALD processing and Cr/Au contact pad deposition. The capacitance of the resulting capacitors was measured at 10 kHz with an AC amplitude of 50 mV (Keithley Model 4200-SCS) as shown in FIG. 7.
7. Logic NAND Gate Characterization
The transfer characteristic of the NAND logic gate is shown in FIG. 10. FIG. 10(a) shows the schematic of the transfer states, where VIN=A=B, and both inputs are varied from logic “0” (GND) to logic “1” (VDD) at the same time. For the NAND gate, as the inputs are varied from a “0,0” state (both A and B are at GND) to a “1,1” state (both A and B are at VDD), the output voltage, VOUT, transitions from a logical “1” (VDD) to a logical “0” (GND) state. The transfer characteristics are shown in FIG. 10(b) for varying supply voltages VDD=0.6 V, 0.8 V, and 1 V. The corresponding power consumption at various VDD is shown in FIG. 10(c), where the static power consumption is less than 1 nW (occurring at the endpoints, i.e. at logic “0” and “1”) and the peak power is 10 nW (occurring at VIN=VOUT) for all VDD. FIG. 10(d) shows gain vs. VIN, where the peak gain shows a linear increase with VDD similar to the inverter as shown in FIG. 5.
8. Logic NOR Gate Characterization
The transfer characteristic of the NOR logic gate is shown in FIG. 11. FIG. 11(a) shows the schematic of the transfer states, where VIN=B and A is held at logic “0” (GND), while B is varied from logic “0” (GND) to logic “1” (VDD). For the NOR gate, as the inputs are varied from a “0,0” state (both A and B are at GND) to a “0,1” state (A is at GND and B is at VDD), the output voltage, VOUT, transitions from a logical “1” (VDD) to a logical “0” (GND) state. The transfer characteristics are shown in FIG. 11(b) for varying supply voltages VDD=0.6 V, 0.8 V, and 1 V. The corresponding power consumption at various VDD is shown in FIG. 11(c), where the static power consumption is about 0.1 nW (occurring at the endpoints, i.e. at logic “0” and “1”) and the peak power is 10 nW (occurring at VIN=VOUT) for all VDD. FIG. 11(d) shows gain vs. VIN, where the peak gain shows linear increase with VDD, which is similar to the inverter shown in FIG. 5.
9. Stability of n-Type SWCNT TFTs
The stability of the n-type SWCNT TFTs fabricated using benzyl viologen as a dopant molecule has been previously studied in the literature. Similarly, the inventors find that the individual n-type SWCNT TFTs as well as the CMOS logic circuits are environmentally stable when stored under inert conditions (i.e., in a glove box).
FIG. 12 shows voltage transfer curves (at VDD=1 V) for an SWCNT CMOS inverter taken 3 weeks apart according to certain embodiments of the disclosure. As shown in FIG. 12, a typical inverter shows minimal degradation in functionality, including maintaining a full rail-to-rail swing, when measured after 3 weeks.
10. Hysteresis of n-Type SWCNT TFTs
FIG. 13 shows hysteresis and representative IDS-VGS curves for n-type SWCNT TFTs according to certain embodiments of the disclosure, where typical transfer plots (taken at VDS=0.5 V) for 4 different n-type SWCNT TFTs, and the arrows indicate the direction of the voltage sweep. As shown in FIG. 13, the n-type SWCNT TFTs show a hysteresis of  ̃0.3 V in the appropriate CMOS voltage operation window (0<VGS<1.5 V).
11. Variability of n-Type SWCNT TFTs
FIG. 14 shows variability of n-type SWCNT TFTs according to certain embodiments of the disclosure, where histograms of 20 representative n-type SWCNT TFTs are used, and (a) shows ION/IOFF ratio, (b) shows electron mobility, and (c) shows channel width normalized ON current (ION/W), measured at VDS=0.1 V. All devices have a channel width of 100 μm and a channel length of 20 μm. The mean values and associated variations of these metrics are as follows: Log10(ION/IOFF): 3.32±0.6, Mobility: 2.6±2.2 cm2/Vs, ION/W: 4.1±3.25 μA/mm, VT: 1.36±0.47 V (VT histogram included in FIG. 5(d)).
In conclusion, SWCNT-based CMOS inverter, NOR, and NAND gates have been demonstrated, which constitute the fundamental building blocks of large-scale integrated digital logic circuits, with sub-nanowatt static power consumption, thereby realizing the primary benefit of the CMOS architecture. This enabling advance was accomplished through precise tuning of the p-type and n-type TFT threshold voltages to match the ideal conditions for an integrated CMOS device. The resulting logic gates exhibit symmetric rail-to-rail operation and excellent noise immunity, which will allow for cascaded multiple logic gates in highly integrated circuits. These results coupled with the many other unique attributes of SWCNTs (e.g., solution processability, mechanical flexibility, chemical and thermal stability, and high mobility) provide a direct pathway to large area, ultralow power nanoelectronic systems.
Example Four
Further expansion of the work has been performed in characterizing the air stability of single walled carbon nanotube (SWCNT) thin film transistors (TFTs) while preparing to further integrate logic circuits with increasing complexity/functionality. In certain embodiments, it is demonstrated that the electronic properties of both p-type and n-type SWCNT TFTs change during exposure to atmosphere leading to deterioration of TFT properties needed for proper circuit operation. A process is created for encapsulating p-type SWCNT TFTs and n-type SWCNT TFTs, which stabilizes advantageous electronic properties for complementary logic circuit operation. Further, it is demonstrated that these processes with hundreds of transistors over a large area giving the results unprecedented statistical significance for complementary SWCNT TFT characterization. The inventors performed simulating and designing of the first complementary static random access memory (SRAM) cells based on SWCNT TFTs for a demonstration of large area complementary logic circuits with integration levels and functionality not previously demonstrated.
1. Time Stability of p-Type and n-Type SWCNT TFTs
FIG. 15 shows array of p-type and n-type SWCNT TFTs according to certain embodiments of the disclosure, where (a) shows optical micrographs of the fabricated SWCNT TFT device (inset) and array of SWCNT TFTs (Scale bar: inset: 200 μm, a: 1 mm); (b) shows atomic force micrograph of the random network SWCNT morphology in the TFT channel; and (c) shows schematic cross-sections of both p-type SWCNT TFT and n-type SWCNT TFT. TFTs are fabricated using SiO2 (300 nm) on a Si substrate, a local Ni (25 nm) gate, Al2O3 (10 nm) gate dielectric deposited by atomic layer deposition (ALD), gate via channel through the dielectric by reactive ion etching, Cr/Au (1 nm/50 nm) source/drain contacts, >98% semiconducting SWCNTs deposited by vacuum filtration film transfer method, p-type encapsulant ( ̃1.3 μm S1813 photoresist), n-type dopant benzyl viologen ( ̃100 nm), and final top encapsulant (50 nm ALD Al2O3).
The electronic properties of SWCNT TFTs have not been thoroughly characterized for ambient stability and little to no work has been done previously to determine the time scale of electronic stability. One of the major barriers to the creation of large-scale integrated circuits based on complementary SWCNT TFTs is the lack of reproducible and stable electronic properties needed for proper CMOS circuit operation.
The fabrication of the stable SWCNT TFTs is the same as previous p-type and n-type SWCNT TFTs but with a modified final structure for the doping scheme and encapsulation as shown in FIG. 15. After the p-type TFTs are fabricated, they are vacuum annealed for 1 hour at 200° C. to remove atmospheric dopants. The device is then encapsulated with photoresist (Shipley S1813) without ever being exposed to atmosphere by spin coating the encapsulant in a nitrogen atmosphere glovebox. Photolithography is then performed to expose all areas except the p-type SWCNT TFT channel region. The remaining channels are converted to n-type TFTs by again vacuum annealing for 1 hour at 200° C., and then spin coating benzyl viologen n-type dopant in a nitrogen atmosphere glovebox without any exposure to atmosphere. Finally, 50 nm of Al2O3 are deposited by atomic layer deposition (ALD) for a final encapsulation top layer.
FIG. 16 shows time stability of p-type and n-type SWCNT TFTs electrical properties according to certain embodiments of the disclosure, where (a) shows the log-linear transfer (IDS-VGS) curves for final encapsulated p-type (solid) and n-type (dashed) SWCNT TFTs measured initially after exposure to atmosphere (blue) and after 7 hours of atmospheric exposure (green) at VDS=1 V; (b) shows the log-linear transfer (IDS-VGS) curves for unencapsulated SWCNT TFTs p-type (solid) and n-type (dashed) TFTs measured initially after exposure to atmosphere (blue) and after 5 hours of atmospheric exposure (red); (c) shows the log(ION/IOFF) of p-type TFTs vs. atmospheric exposure time for repeated transfer measurements of a single encapsulated (purple) and unencapsulated (black) SWCNT TFT; and (d) shows the log(ION/IOFF) of n-type TFTs vs. atmospheric exposure time for repeated transfer measurements of a single encapsulated (purple) and unencapsulated (black) SWCNT TFT.
TFTs with and without encapsulation are tested for their time stability both using individual TFTs repeatedly measured over several hours and over 800 TFTs measured once for a similar testing period. The VGS range is limited to the operating range of CMOS transistors, from VGS=0V to |VDD|, because this is the only relevant operating voltages within a CMOS circuit. The transfer curves for encapsulated TFTs are shown in FIG. 16(a) after initial exposure to air and after 7 hours of repeated testing in atmosphere. For both encapsulated p-type and n-type SWCNT TFTs, enhanced or stable electronic properties are observed over the 7-hour testing period. In contrast, FIG. 16(b) shows unencapsulated p-type SWCNT TFTs displaying significant deterioration of relevant metrics like the ION/IOFF current ratio. ION is defined as IDS at VGS=|VDD| and IOFF is defined as IDS at VGS=0 V. Over 5 hours, ION/IOFF current ratio for both unencapsulated p-type and n-type TFTs decreases by  ̃3 orders of magnitude. FIG. 16(c) and FIG. 16(d) show the time evolution of log(ION/IOFF) for p-type and n-type SWCNT TFTs, respectively. Clearly, encapsulated TFTs experience stable or enhanced ION/IOFF current ratio over time, while the unencapsulated SWCNT TFTs experience significant degradation of ION/IOFF current ratio over the same time period. This deterioration would cause CMOS circuits to no longer function properly.
2. Large-Scale Device Property Statistics
FIG. 17 shows histograms for large sample statistics of SWCNT TFT electronic properties according to certain embodiments of the disclosure, where (a)-(b) show the log(ION/IOFF) of p-type and n-type TFTs for encapsulated (purple) and unencapsulated (black) where each device is measured once; (c) shows subthreshold swing for encapsulated (purple) and unencapsulated (black) p-type SWCNT TFTs; (d) shows log(IDS) values when VGS=0V for encapsulated (purple) and unencapsulated (black) n-type TFTs; and (e) shows the threshold voltage distributions for encapsulated (purple) and unencapsulated (black) p-type (solid) and n-type (striped) TFTs.
The phenomenon is consistent over large numbers of TFTs as demonstrated in FIG. 17. Each TFT is only measured once within the operating voltages defined above, and do not include the enhancements achieved through repeated measurement. FIGS. 17 (a) and (b) show the log(ION/IOFF) values for both encapsulated and unencapsulated p-type and n-type SWCNT TFTs. Both encapsulated p-type and n-type SWCNT TFTs exhibit high log(ION/IOFF) current ratios, with both having an average of 3.5+/−0.15 (p-type)+/−0.53 (n-type) for over 800 TFTs. Unencapsulated TFTs have low log(ION/IOFF) current ratio averages of 1.82+/−0.38 (p-type) and 1.39+/−0.77 (n-type) with long tails for these distributions. The ION/IOFF current ratio for encapsulated TFTs are suitable for CMOS circuit operation, whereas unencapsulated TFTs are highly variable and thus not appropriate for large scale CMOS circuit integration.
The cause of the decreased ION/IOFF current ratio can be attributed to changes in electronic properties. For p-type SWCNT TFTs, the increase in subthreshold swing is the main reason for the deterioration in functionality. Encapsulated TFTs as shown in FIG. 17(c) have a uniformly low and narrow value of 236+/−13 mV/decade compared to unencapsulated TFTs having high values and a broad distribution of 483+/−146 mV/decade. For n-type TFTs, the increase in IDS at VGS=0 V is the main factor in the decreased ION/IOFF current ratio. FIG. 17(d) shows the values for log(IDS) at VGS=0 V, where encapsulated TFTs have an average log(IOFF) of −9.42+/−0.6, and unencapsulated TFTs have an average of −7.6+/−0.56. This increase of almost 2 orders of magnitude is the primary cause of decreased ION/IOFF current ratio.
Additionally, threshold voltage shifts also contribute to the deterioration of the ION/IOFF current ratios. For both p-type and n-type encapsulated TFTs shown in FIG. 17(e), the threshold voltages are consistently to the left of unencapsulated TFTs. These threshold voltages are more symmetric about VGS=0 V than the unencapsulated TFTs, leading to advantageous symmetric operating voltages required for CMOS circuit operation. VT for encapsulated p-type SWCNT TFTs is −0.93+/−0.046 V, while VT for unencapsulated p-type SWCNT TFTs is −0.62+/−0.18 V. Similarly, for encapsulated n-type TFTs VT is 1.01+/−0.1V and unencapsulated n-type TFTs have a VT of 1.26+/−0.057 V. The encapsulated TFTs both have threshold voltages near |1 V| while unencapsulated TFTs are shifted  ̃0.3 V in the positive direction, leading to unbalanced transfer characteristics in the given operating window of CMOS circuits, between VGS=0 V and VGS=|VDD|. All of the improvements in SWCNT TFT properties and stability will enable more complex TFTs to be created due to the predictability of fabricated SWCNT TFTs. These statistics are used to develop transistor models for circuit simulation enabling more complex circuits to be built. We are currently simulating and designing static random access memory (SRAM) cells on large scales that will demonstrate complex operation and functionality not yet demonstrated for CMOS SWCNT TFTs.
The foregoing description of the exemplary embodiments of the invention has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.
The embodiments were chosen and described in order to explain the principles of the invention and their practical application so as to enable others skilled in the art to utilize the invention and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present invention pertains without departing from its spirit and scope. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.
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## Claims

1. A complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs), comprising:
at least one p-type metal-oxide-semiconductor (PMOS) thin-film transistor (TFT) formed with the SWCNTs, wherein each of the at least one PMOS TFT has a gate, a source and a drain; and
at least one n-type metal-oxide-semiconductor (NMOS) TFT formed with the SWCNTs, wherein each of the at least one NMOS TFT has a gate, a source and a drain,
wherein the gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage;
wherein at least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage VOUT;
wherein the gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT respectively comprises a local metallic gate structure formed of a metal;
wherein a threshold voltage of the at least one PMOS TFT and a threshold voltage of the at least one NMOS TFT are symmetric; and
wherein each of the at least one NMOS TFT is chemically doped with benzyl viologen.

2. The CMOS logic device of claim 1, wherein a linear tube density of the SWCNTs in the at least one PMOS TFT and the at least one NMOS TFT is about 18 nanotubes/μm.

3. The CMOS logic device of claim 1, wherein the metal of the local metal gate structure is nickel (Ni).

4. The CMOS logic device of claim 1, having a static power consumption of less than about 0.1 nW in a static state, and a peak power consumption of about 10 nW in a transfer state.

5. The CMOS logic device of claim 1, being a logic inverter.

6. The CMOS logic device of claim 5, wherein
the at least one PMOS TFT comprises a first PMOS TFT;
the at least one NMOS TFT comprises a first NMOS TFT;
the at least one input voltage comprises a common input voltage VIN;
the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a common input voltage line for alternatively receiving the common input voltage VIN;
the drain of the first PMOS TFT and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for alternatively outputting the output voltage VOUT;
the source of the first PMOS TFT is connected to a power supply VDD; and
the source of the first NMOS TFT is connected to ground.

7. The CMOS logic device of claim 6, having a low noise margin (NM) of about 0.32 VDD, and a high NM of about 0.54 VDD.

8. The CMOS logic device of claim 1, being a logic NAND gate.

9. The CMOS logic device of claim 8, wherein
the at least one PMOS TFT comprises a first PMOS TFT and a second PMOS TFT;
the at least one NMOS TFT comprises a first NMOS TFT and a second NMOS TFT;
the at least one input voltage comprises a first input voltage VA and a second input voltage VB;
the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage VA;
the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage VB;
the drain of the first PMOS TFT, the drain of the second PMOS TFT, and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for outputting the output voltage VOUT;
the source of the first PMOS TFT and the source of the second PMOS TFT are respectively electrically connected to a power supply VDD;
the source of the first NMOS TFT is electrically connected to the drain of the second NMOS TFT; and
the source of the second NMOS TFT is electrically connected to ground.

10. The CMOS logic device of claim 1, being a logic NOR gate.

11. The CMOS logic device of claim 10, wherein
the at least one PMOS TFT comprises a first PMOS TFT and a second SWCNT PMOS TFT;
the at least one NMOS TFT comprises a first NMOS TFT and a second NMOS TFT;
the at least one input voltage comprises a first input voltage VA and a second input voltage VB;
the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage VA;
the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage VB;
the drain of the first PMOS TFT, the drain of the first NMOS TFT, and the drain of the second NMOS TFT are respectively electrically connected to a common output voltage line for outputting the output voltage VOUT;
the source of the second PMOS TFT is electrically connected to a power supply VDD;
the source of the first PMOS TFT is electrically connected to the drain of the second PMOS TFT; and
the source of the first NMOS TFT and the source of the second NMOS TFT are respectively electrically connected to ground.

12. The CMOS logic device of claim 1, further comprising:
a first encapsulation layer covering the at least one PMOS TFT;
a second encapsulation layer covering the at least one NMOS TFT and the first encapsulation layer.

13. The CMOS logic device of claim 12, wherein the first encapsulation layer is formed by a photoresist, and the second encapsulation layer is formed by Al2O3.

14. A complementary metal-oxide-semiconductor (CMOS) logic device formed with carbon nanotubes (CNTs), comprising:
at least one p-type metal-oxide-semiconductor (PMOS) transistor formed with the CNTs, wherein each of the at least one PMOS transistor has a gate, a source and a drain; and
at least one n-type metal-oxide-semiconductor (NMOS) transistor formed with the CNTs, wherein each of the at least one NMOS transistor has a gate, a source and a drain,
wherein the gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor is configured to alternatively receive at least one input voltage;
wherein at least one of the drain of the at least one PMOS transistor and the drain of the at least one NMOS transistor is configured to output an output voltage VOUT;
wherein the gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor respectively comprises a local metallic gate structure formed of a metal;
wherein a threshold voltage of the at least one PMOS TFT and a threshold voltage of the at least one NMOS TFT are symmetric; and
wherein each of the at least one NMOS TFT is chemically doped with benzyl viologen.

15. The CMOS logic device of claim 14, wherein each of the at least one PMOS transistor and each of the at least one NMOS transistor is a thin-film transistor (TFT).

16. The CMOS logic device of claim 14, wherein the metal of the local metal gate structure is nickel (Ni).

17. The CMOS logic device of claim 14, having a static power consumption of less than about 0.1 nW in a static state, and a peak power consumption of about 10 nW in a transfer state.

18. The CMOS logic device of claim 14, wherein the CNTs are single-walled CNTs (SWCNTs).

19. The CMOS logic device of claim 18, wherein a linear tube density of the SWCNTs in the at least one PMOS transistor and the at least one NMOS transistor is about 18 nanotubes/μm.

20. The CMOS logic device of claim 18, being a logic inverter.

21. The CMOS logic device of claim 20, wherein
the at least one PMOS transistor comprises a first PMOS thin-film transistor (TFT);
the at least one NMOS transistor comprises a first NMOS TFT;
the at least one input voltage comprises a common input voltage VIN;
the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a common input voltage line for alternatively receiving the common input voltage VIN;
the drain of the first PMOS TFT and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for alternatively outputting the output voltage VOUT;
the source of the first PMOS TFT is connected to a power supply VDD; and
the source of the first NMOS TFT is connected to ground.

22. The CMOS logic device of claim 21, having a low noise margin (NM) of about 0.32 VDD, and a high NM of about 0.54 VDD.

23. The CMOS logic device of claim 18, being a logic NAND gate.

24. The CMOS logic device of claim 23, wherein
the at least one PMOS transistor comprises a first PMOS thin-film transistor (TFT) and a second PMOS TFT;
the at least one NMOS transistor comprises a first NMOS TFT and a second NMOS TFT;
the at least one input voltage comprises a first input voltage VA and a second input voltage VB;
the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage VA;
the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage VB;
the drain of the first PMOS TFT, the drain of the second PMOS TFT, and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for outputting the output voltage VOUT;
the source of the first PMOS TFT and the source of the second PMOS TFT are respectively electrically connected to a power supply VDD;
the source of the first NMOS TFT is electrically connected to the drain of the second NMOS TFT; and
the source of the second NMOS TFT is electrically connected to ground.

25. The CMOS logic device of claim 18, being a logic NOR gate.

26. The CMOS logic device of claim 25, wherein
the at least one PMOS transistor comprises a first PMOS thin-film transistor (TFT) and a second PMOS TFT;
the at least one NMOS transistor comprises a first NMOS TFT and a second NMOS TFT;
the at least one input voltage comprises a first input voltage VA and a second input voltage VB;
the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage VA;
the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage VB;
the drain of the first PMOS TFT, the drain of the first NMOS TFT, and the drain of the second NMOS TFT are respectively electrically connected to a common output voltage line for outputting the output voltage VOUT;
the source of the second PMOS TFT is electrically connected to a power supply VDD;
the source of the first PMOS TFT is electrically connected to the drain of the second PMOS TFT; and
the source of the first NMOS TFT and the source of the second NMOS TFT are respectively electrically connected to ground.

27. The CMOS logic device of claim 14, further comprising:
a first encapsulation layer covering the at least one PMOS transistor; and
a second encapsulation layer covering the at least one NMOS transistor and the first encapsulation layer.

28. The CMOS logic device of claim 27, wherein the first encapsulation layer is formed by a photoresist, and the second encapsulation layer is formed by Al2O3.

29. An apparatus, having at least one of the complementary metal-oxide-semiconductor (CMOS) logic device of claim 1.

30. An apparatus, having at least one of the complementary metal-oxide-semiconductor (CMOS) logic device of claim 14.