# Patent

## Title
Apparatus and method for receiving signal in communication system

## Abstract

Disclosed is an apparatus for receiving a signal in a communication system, which receives the signal, and decodes the received signal in a non-binary Low Density Parity Check (LDPC) decoding scheme, in which elements of a Galois field are expressed by an exponent representation, thereby minimizing the memory capacity required for a check node operation when the non-binary LDPC code is decoded.

## Background
PRIORITY
This application claims priority to an application filed in the Korean Industrial Property Office on Feb. 22, 2006 and assigned Serial No. 2006-017363, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and a method for receiving a signal in a communication system, and more particularly to an apparatus and a method for receiving a signal in a communication system using a non-binary Low Density Parity Check (LDPC) code, which decodes the non-binary LDPC code while minimizing the memory capacity required for performing a check node operation.
2. Description of the Related Art
Next-generation communication systems have evolved from a packet service communication system for transmitting burst packet data to a plurality of Mobile Stations (MSs), with the packet service communication system being suitable for mass data transmission. Further, next-generation communication systems are considering a LDPC code, together with a turbo code, as a channel code. The LDPC code is known to have an excellent performance gain at high-speed data transmission, and advantageously enhances data transmission reliability by effectively correcting an error due to noise occurring in a transmission channel. Examples of next-generation communication systems positively considering the use of the LDPC code include the IEEE (Institute of Electrical and Electronics Engineers) 802.16e communication system, the IEEE 802.11n communication system, etc.
Reference will now be made to the structure of a signal transmission apparatus in a common communication system using a LDPC code, with reference to FIG. 1.
FIG. 1 is a block diagram illustrating the structure of a signal transmission apparatus in a common communication system using a LDPC code. Referring to FIG. 1, the signal transmission apparatus includes an encoder 111, a modulator 113 and a transmitter 115. First, if an information vector s to be transmitted occurs in the signal transmission apparatus, the information vector s is delivered to the encoder 111. The encoder 111 generates a codeword vector c, that is, a LDPC codeword by encoding the information vector s in a predetermined encoding scheme, and then outputs the generated codeword vector c to the modulator 113. Here, the predetermined encoding scheme corresponds to a LDPC encoding scheme. The modulator 113 generates a modulation vector m by modulating the codeword vector c in a predetermined modulation scheme, and then outputs the generated modulation vector m to the transmitter 115. The transmitter 115 inputs therein the modulation vector m output from the modulator 113, executes transmission signal processing for the input modulation vector m, and then transmits the processed modulation vector m to a signal reception apparatus through an antenna.
Next, reference will be made to the structure of a signal reception apparatus in a common communication system using a LDPC code, with reference to FIG. 2.
FIG. 2 is a block diagram illustrating the structure of a signal reception apparatus in a common communication system using a LDPC code. Referring to FIG. 2, the signal reception apparatus includes a receiver 211, a demodulator 213 and a decoder 215. First, a signal transmitted by a signal transmission apparatus is received through an antenna of the signal reception apparatus, and the received signal is delivered to the receiver 211. The receiver 211 executes reception signal processing for the received signal to thereby generate a reception vector r, and then outputs the processed and generated reception vector r to the demodulator 213. The demodulator 213 inputs therein the reception vector r output from the receiver 211, generates a demodulation vector x by demodulating the input reception vector r in a demodulation scheme corresponding to a modulation scheme applied to a modulator of the signal transmission apparatus, that is, the modulator 113, and then outputs the generated demodulation vector x to the decoder 215. The decoder 215 inputs therein the demodulation vector x output from the demodulator 213, decodes the input demodulation vector x in a decoding scheme corresponding to an encoding scheme applied to an encoder of the signal transmission apparatus, that is, the encoder 111, and then outputs the decoded demodulation vector x into a finally restored information vector s. Here, the decoding scheme, that is, a LDPC scheme, is a scheme using an iterative decoding algorithm based on a sum-product algorithm. The sum-product algorithm will be described below in detail.
A binary LDPC code is a code defined by a parity check matrix in which most elements have a value of 0, but a small minority of other elements have a non-zero value, for example, a value of 1. Thus, all the elements constituting the parity check matrix of the binary LDPC code have a value of 0 or 1. In contrast with this, all elements constituting the parity check matrix of a non-binary LDPC code are elements in a Galois Field of order q (hereinafter referred to as “GF(q)”). Here, “q” in GF(q) indicates the order of a GF, and q=2p. Thus, the non-binary LDPC code is a code defined by a parity check matrix in which most elements have a value of 0, but a small minority of other elements are non-zero elements, for example, elements of GF(q).
Further, a codeword of the non-binary LDPC code, C, is a vector having a length of N and including elements of GF(q), and satisfies Equation (1):




  
    
      
        
          
            
              ∑
              
                i
                =
                1
              
              N
            
            ⁢
            
              
            
            ⁢
            
              
                h
                ji
              
              ⁢
              
                c
                i
              
            
          
          =
          0
        
        ,
        
          ∀
          
            j
            ∈
            
              {
              
                1
                ,
                ⋯
                ⁢
                
                  
                
                ,
                M
              
              }
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




In Equation (1), hji denotes an element existing in a jth row and an ith column of the parity check matrix of the non-binary LDPC code, ci denotes an ith element of the codeword C, M denotes the number of rows of the parity check matrix, and N denotes the number of columns of the parity check matrix.
If it is assumed that a jth row of the parity check matrix includes three non-zero elements and the three non-zero elements are hji1, hji2, hji3, respectively, then a codeword C satisfies Equation (2):

(hji1{circle around (x)}ci1)⊕(hji2{circle around (x)}ci2)⊕(hji3{circle around (x)}ci3)=0   (2)

In Equation (2), ⊕ denotes an additive operation on GF(q), and {circle around (x)} denotes a multiplicative operation on GF(q).
In general, a polynomial representation is used as a scheme for expressing elements of GF(2p). Coefficients of GF(2p) are generated from a pth degree irreducible polynomial which is defined in GF(2), and all elements of GF(2p) are expressed by a (p−1)th degree polynomial whose coefficients are defined in GF(2). GF(2p) will now be described by exemplifying GF(24).
First, GF(24) is generated from a fourth-order irreducible polynomial p(x)=x4+x+1. Here, if it is assumed that a root of the fourth-order irreducible polynomial p(x)=x4+x+1 is α, all elements of GF(24) are equal to {0, 1, α, α2, α3, . . . , α14}. Further, all the elements of GF(24) can be expressed by at most a third-order polynomial α3x3+α2x2+α1x+α0, the coefficients of which are defined in GF(2).
All the elements {0, 1, α, α2, α3, . . . , α14} of GF(24), the polynomial coefficients {α3, α2, α1, α0}, and decimal expressions corresponding thereto are shown below in Table 1.













TABLE 1






element
a3
a2
a1
a0
decimal number






















0
0
0
0
0
0



1
0
0
0
1
1



α
0
0
1
0
2



α2
0
1
0
0
4



α3
1
0
0
0
8



α4
0
0
1
1
3



α5
0
1
1
0
6



α6
1
1
0
0
12



α7
1
0
1
1
11



α8
0
1
0
1
5



α9
1
0
1
0
10



α10
0
1
1
1
7



α11
1
1
1
0
14



α12
1
1
1
1
15



α13
1
1
0
1
13



α14
1
0
0
1
9









In addition, the LDPC code can be expressed using a bipartite graph which is represented by variable nodes, check nodes and edges connecting the variable nodes and the check nodes with each other.
Further, the LDPC code can be decoded on the bipartite graph by using an iterative decoding algorithm based on a sum-product algorithm. Here, the sum-product algorithm is a type of message passing algorithm, and the message passing algorithm refers to an algorithm in which messages are exchanged on the bipartite graph through the edges, and an output message is calculated and updated from messages input into the variable nodes or the check nodes. That is, since a decoder for decoding the LDPC code uses the iterative decoding algorithm based on the sum-product algorithm, it is less complex than a decoder for decoding a turbo code, and can be easily implemented as a parallel processing decoder.
In a bipartite graph of a non-binary LDPC code defined in GF(2p), a variable node is a random variable of GF(2p), and a message passed through an edge is a vector with a size of 2p. Each element included in the vector with a size of 2p indicates the probability that the random variable has each of a 2p number of elements of GF(2p).
Reference will now be made to the permutation of a message vector with the value of an edge in a non-binary LDPC code, with reference to FIG. 3.
FIG. 3 illustrates explains the permutation of a message vector with the value of edge in an ordinary non-binary LDPC code Referring to FIG. 3, variable node i and check node j are connected by an edge, and the edge connecting the variable node i and the check node j has a value of hji which is an element of GF(2p). To mention that the edge connecting the variable node i and the check node j has a value of hji implies that an element existing in a jth row and an ith column of a parity check matrix defined in GF(2p) is hji. Here, a message, which is passed through the edge connecting the variable node i and the check node j, is a vector with a size of 2p, and each element {P0, . . . , Pq−1} included in the message vector with a size of 2p indicates the probability that the variable node i has each element of GF(2p). The message vector is permuted with the edge's value hji, and elements included in the permuted message vector become {P0×hji, . . . P(q−1)×hji} in sequence. Here, a multiplicative operation is defined on GF(2p), and decimal numbers {0, 1, . . . , q−1} indicate elements of GF(2p), expressed by the polynomial representation as shown above in Table 1.
Reference will now be made to the inner structure of a decoder in the case of decoding a non-binary LDPC code by using a sum-product algorithm, with reference to FIG. 4.
FIG. 4 is a block diagram illustrating the inner structure of a decoder for decoding an ordinary non-binary LDPC code. Before explaining FIG. 4, it should be noted that although the decoder generally includes a check node processing unit and a variable node processing unit, only the structure of the check node processing unit of the decode is illustrated in FIG. 4. Referring to FIG. 4, a node processing unit within the decoder includes a first shuffle network processing unit 410, a check node processor 440 and a second shuffle network processing unit 470.
The first shuffle network processing unit 410 includes a plurality of multipliers, for example, a dc number of multipliers, that is, a multiplier 411-1 through multiplier 411-dc, and a plurality of FFT (Fast Fourier Transform) units, for example, a dc number of FFT units, that is, an FFT unit 413-1 through an FFT unit 413-dc.
The second shuffle network processing unit 470 includes a plurality of IFFT (Inverse Fast Fourier Transform) units, for example, a dc number of IFFT units, that is, an IFFT unit 471-1 through an IFFT unit 471-dc, and a plurality of multipliers, for example, a dc number of multipliers, that is, a multiplier 473-1 through a multiplier 473-dc.
The operation of the check node processing unit will now be described by exemplifying a jth check node in the parity check matrix of a non-binary LDPC code. Here, the degree of the jth check node is assumed to be dc.
First, if it is assumed that input messages input into the first shuffle network processing unit 410 are




  
    κ
    
      i
      1
    
  
  ,
  
    κ
    
      i
      2
    
  
  ,
  ⋯
  ⁢
  
    
  
  ,
  
    κ
    
      i
      
        d
        c
      
    
  
  ,




the input messages





  
    κ
    
      i
      1
    
  
  ,
  
    κ
    
      i
      2
    
  
  ,
  ⋯
  ⁢
  
    
  
  ,
  
    κ
    
      i
      
        d
        c
      
    
  




are messages passed from a variable node to a check node, and each input message





  
    κ
    
      i
      1
    
  
  ,
  
    κ
    
      i
      2
    
  
  ,
  ⋯
  ⁢
  
    
  
  ,
  
    κ
    
      i
      
        d
        c
      
    
  




is a vector with a size of 2p. The input messages





  
    κ
    
      i
      1
    
  
  ,
  
    κ
    
      i
      2
    
  
  ,
  ⋯
  ⁢
  
    
  
  ,
  
    κ
    
      i
      
        d
        c
      
    
  




are input into the multiplier 411-1, the multiplier 411-2, the multiplier 411-3, . . . and the multiplier 411-dc, respectively.

Each of multiplier 411-1 through multiplier 411-dc performs multiplication of each input message vector




  
    κ
    
      i
      1
    
  
  ,
  
    κ
    
      i
      2
    
  
  ,
  ⋯
  ⁢
  
    
  
  ,
  
    κ
    
      i
      
        d
        c
      
    
  




and each edge value





  
    h
    
      ji
      1
    
  
  ,
  
    h
    
      ji
      2
    
  
  ,
  ⋯
  ⁢
  
    
  
  ,
  
    h
    
      ji
      
        d
        c
      
    
  




of the parity check matrix on GF(2p). However, since the input messages are not elements on GF(2p), but indicate the probabilities of having the elements on GF(2p), each of multiplier 411-1 through multiplier 411-dc actually performs the permutation of each input message





  
    κ
    
      i
      1
    
  
  ,
  
    κ
    
      i
      2
    
  
  ,
  ⋯
  ⁢
  
    
  
  ,
  
    
      κ
      
        i
        
          d
          c
        
      
    
    .
  




Here, a 2p×2p number of unit memories are required for storing the permutation information. Further, since each unit memory consists of p bits, a memory capacity capable of storing total 2p×2p×p bits is consequently required for storing the permutation information.

After the permutation, each of multiplier 411-1 through multiplier 411-dc outputs each permuted input message




  
    κ
    
      i
      1
    
  
  ,
  
    κ
    
      i
      2
    
  
  ,
  ⋯
  ⁢
  
    
  
  ,
  
    κ
    
      i
      
        d
        c
      
    
  




to each of the FFT unit 413-1 through FFT unit 413-dc. Each of FFT unit 413-1 through FFT unit 413-dc inputs therein a signal output from each of multiplier 411-1 through multiplier 411-dc, performs FFT for the input signal, and then outputs the fast Fourier transformed signal to the check node processor 440. Here, the signal input into each of FFT unit 413-1 through and FFT unit 413-dc is the probability of each element expressed by the polynomial representation as defined above in Table 1. Further, the FFT performed in each of FFT unit 413-1 through FFT unit 413-dc means not ordinary FFT, but FFT performed on GF(2p), which is identical to Fast Hadamard Transform (“FHT”).

The check node processor 440 inputs therein a signal output from each of FFT unit 413-1 through FFT unit 413-dc, performs a check node operation, and then outputs a corresponding result to each of IFFT unit 471-1 through IFFT unit 471-dc. Each of IFFT unit 471-1 through IFFT unit 471-dc inputs therein a signal output from the check node processor 440, performs IFFT for the input signal, and outputs the inverse fast Fourier transformed signal to each of the multiplier 473-1, the multiplier 473-2, the multiplier 473-3, . . . and the multiplier 473-dc. Here, the IFFT performed in each of IFFT unit 471-1 through IFFT unit 471-dc means not ordinary IFFT, but IFFT performed on GF(2p). Further, each of IFFT unit 471-1 through IFFT unit 471-dc has the same structure as that of each of FFT unit 413-1 through FFT unit 413-dc, except that an output thereof is scaled by 1⁄2p.
Each of multiplier 473-1 through multiplier 473-dc inputs therein a signal output from each of IFFT unit 471-1 through IFFT unit 471-dc, and performs multiplication of the input signal and the multiplicative inverse element




  
    h
    
      ji
      1
    
    
      -
      1
    
  
  ,
  
    h
    
      ji
      2
    
    
      -
      1
    
  
  ,
  ⋯
  ⁢
  
    
  
  ,
  
    h
    
      ji
      
        d
        c
      
    
    
      -
      1
    
  




of each edge value





  
    h
    
      ji
      1
    
  
  ,
  
    h
    
      ji
      2
    
  
  ,
  ...
  ⁢
  
    
  
  ,
  
    h
    
      ji
      
        d
        c
      
    
  




of the parity check matrix on GF(2p). Here, each of multiplier 473-1 through multiplier 473-dc also actually performs the permutation of the signal output from each of IFFT unit 471-1 through IFFT unit 471-dc, and this permutation corresponds to the inverse of the permutation performed in each of multiplier 411-1 through multiplier 411-dc. Hereinafter, for the convenience of explanation, the permutation performed in each of multiplier 473-1 through multiplier 473-dc will be referred to as “inverse permutation”. Thus, a 2p×2p number of unit memories are required for storing the inverse permutation information. Further, since each unit memory consists of p bits, a memory capacity capable of storing total 2p×2p×p bits is consequently required for storing the inverse permutation information. Since it is possible to extract one of the permutation information and the inverse permutation information from the other, it does not matter if only one of them is stored.

As stated above, in order to perform a check node operation, a memory capacity capable of storing 2p×2p×p bits is required for storing permutation information or inverse permutation information. Therefore, there is a strong need for decoder which makes it possible to reduce the memory capacity required for the check node operation.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve at least the above-mentioned problems occurring in conventional systems, and an aspect of the present invention is to provide an apparatus and a method for receiving a signal in a communication system using a non-binary LDPC code.
A further aspect of the present invention is to provide an apparatus and a method for receiving a signal in a communication system using a non-binary LDPC code, which decodes the non-binary LDPC code while minimizing the memory capacity required for performing a check node operation.
In order to accomplish these aspects, in accordance with one aspect of the present invention, there is provided an apparatus for receiving a signal in a communication system, the apparatus includes a receiver for receiving the signal and a decoder for decoding the received signal in a non-binary Low Density Parity Check (LDPC) decoding scheme in which elements of a Galois field are expressed by an exponent representation.
In accordance with another aspect of the present invention, there is provided a method for receiving a signal in a communication system, the method includes receiving a signal and decoding the received signal in a non-binary Low Density Parity Check (LDPC) decoding scheme in which elements of a Galois field are expressed by an exponent representation.



BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a block diagram illustrating the structure of a signal transmission apparatus in a common communication system using an LDPC code;
FIG. 2 is a block diagram illustrating the structure of a signal reception apparatus in a common communication system using an LDPC code;
FIG. 3 explains the permutation of a message vector with the value of edge in an ordinary non-binary LDPC code;
FIG. 4 is a block diagram illustrating the inner structure of a decoder for decoding an ordinary non-binary LDPC code; and
FIG. 5 is a block diagram illustrating the inner structure of a decoder for decoding a non-binary LDPC code in accordance with the present invention.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that similar components are designated by similar reference numerals although they are illustrated in different drawings. Also, in the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may obscure the subject matter of the present invention. Further, it should be noted that only parts essential for understanding the operations according to the present invention will be described and a description of parts other than the essential parts will be omitted in order not to obscure the gist of the present invention.
The present invention provides an apparatus and a method for receiving a signal in a communication system using a non-binary Low Density Parity Check (LDPC) code, which decodes the non-binary LDPC code while minimizing the memory capacity required for performing a check node operation. The present invention further provides an apparatus and a method for receiving a signal in a communication system, which decodes a non-binary LDPC code while minimizing the memory capacity required for performing a check node operation by using an exponent representation as a scheme for expressing elements of a Galois field GF(q). “q” in GF(q) indicates the order of GF, and q=2p.
As mentioned above, a polynomial representation is used as a scheme for expressing elements of GF(2p) in a conventional communication system using a non-binary LPDC code. In this case, a memory capacity of 2p×2p×p bits is required for performing a check node operation when the non-binary LDPC code is decoded. Thus, in the present invention, elements of GF(2p) are expressed using not the polynomial representation, but an exponent representation in order to reduce the memory capacity required for the check node operation to below a memory capacity of 2p×2p×p bits. Reference will now be made to a scheme for expressing elements of GF(2p) by using the exponent representation proposed in the present invention.
First, all elements of GF(2p) are {0, 1, α, α2, . . . , αq−2}. In order to express all the elements of GF(2p) by using only their exponents, if we take the base-α logarithm (logα) of each element of GF(2p), {−∞, 0, 1, 2, . . . , q−2} can be obtained. The exponent representation is a representation scheme in which all the elements of GF(2p) are expressed by {−∞, 0, 1, 2, . . . , q−2} obtained in this way. The exponent representation of GF(2p) will now be described by exemplifying GF(24). Here, GF(24) is generated from a fourth-order irreducible polynomial p(x)=x4+x+1. Further, if it is assumed that a root of the fourth-order irreducible polynomial p(x)=x4+x+1 is α, all elements of GF(24) are equal to {0, 1, α, α2, α3, . . . , α14}. Further, all the elements of GF(24) can be expressed by at most a third-order polynomial α3x3+α2x2+α1x+α0, the coefficients of which are defined in GF(2). If we take the base-α logarithm (logα) of each element {0, 1, α, α2, α3, . . . , α14} of GF(24), {−∞, 0, 1, 2, . . . , 14} can be obtained. Here, if it is assumed that “−∞” is represented as “15”, all the elements {0, 1, α, α2, α3, . . . , α14} of GF(24), the polynomial coefficients {α3, α2, α1, α0}, and decimal expressions corresponding thereto are shown below in Table 2.













TABLE 2






element
a3
a2
a1
a0
decimal number








0
1
1
1
1
−∞ → 15



1
0
0
0
0
0



α
0
0
0
1
1



α2
0
0
1
0
2



α3
0
0
1
1
3



α4
0
1
0
0
4



α5
0
1
0
1
5



α6
0
1
1
0
6



α7
0
1
1
1
7



α8
1
0
0
0
8



α9
1
0
0
1
9



α10
1
0
1
0
10



α11
1
0
1
1
11



α12
1
1
0
0
12



α13
1
1
0
1
13



α14
1
1
1
0
14









In Table 2, {α3, α2, α1, α0} are values obtained by converting the integer values of the exponent representation into binary values.
As shown in Table 2, when elements of GF(2p) are expressed by the exponent representation, a multiplicative operation between two GF elements is transformed into a simple additive operation between integers, which can be expressed by Equation (3):

αi{circle around (x)}αj=αi+j→i {circle around (x)}j=i+j mod(q−1)   (3)

In Equation (3), “{circle around (x)}” denotes a multiplicative operation on GF(q), and “mod” denotes a modulo operation.

In this way, when elements of GF(q) are expressed by the exponent representation, the memory capacity required for a check node operation is minimized in decoding a non-binary LDPC code by using an iterative decoding algorithm based on a sum-product algorithm, as described above in FIG. 3. hereinafter, this will be described in detail with reference to FIG. 5.
FIG. 5 is a block diagram illustrating the inner structure of a decoder for decoding a non-binary LDPC code according to the present invention. Before explaining FIG. 5, it should be appreciated that although the decoder generally includes a check node processing unit and a variable node processing unit, only the structure of the check node processing unit of the decode is illustrated in FIG. 5. Referring to FIG. 5, a node processing unit within the decoder includes a first shuffle network processing unit 510, a check node processor 540 and a second shuffle network processing unit 570.
The first shuffle network processing unit 510 includes a plurality of multipliers, for example, a dc number of multipliers, that is, a multiplier 511-1, a multiplier 511-2, a multiplier 511-3, . . . and a multiplier 511-dc, a plurality of interleavers, for example, a dc number of interleavers, that is, an interleaver 513-1, an interleaver 513-2, an interleaver 513-3, . . . and an interleaver 513-dc, and a plurality of FFT (Fast Fourier Transform) units, for example, a dc number of FFT units, that is, an FFT unit 515-1, an FFT unit 515-2, an FFT unit 515-3, . . . and an FFT unit 515-dc.
The second shuffle network processing unit 570 includes a plurality of IFFT (Inverse Fast Fourier Transform) units, for example, a dc number of IFFT units, that is, an IFFT unit 571-1, an IFFT unit 571-2, an IFFT unit 571-3, . . . and an IFFT unit 571-dc, a plurality of deinterleavers, for example, a dc number of deinterleavers, that is, a deinterleaver 573-1, a deinterleaver 573-2, a deinterleaver 573-3, . . . and a deinterleaver 573-dc, and a plurality of multipliers, for example, a dc number of multipliers, that is, a multiplier 575-1, a multiplier 575-2, a multiplier 575-3, . . . and a multiplier 575-dc.
The operation of the check node processing unit will now be described by exemplifying a jth check node in the parity check matrix of a non-binary LDPC code. Here, the degree of the jth check node is assumed to be dc.
First, if it is assumed that input messages input into the first shuffle network processing unit 510 are




  
    x
    
      i
      1
    
  
  ,
  
    x
    
      i
      2
    
  
  ,
  ...
  ⁢
  
    
  
  ,
  
    x
    
      i
      
        d
        c
      
    
  
  ,




the input messages





  
    x
    
      i
      1
    
  
  ,
  
    x
    
      i
      2
    
  
  ,
  ...
  ⁢
  
    
  
  ,
  
    x
    
      i
      
        d
        c
      
    
  




are messages passed from a variable node to a check node, and each input message





  
    x
    
      i
      1
    
  
  ,
  
    x
    
      i
      2
    
  
  ,
  ...
  ⁢
  
    
  
  ,
  
    x
    
      i
      
        d
        c
      
    
  




is a vector with a size of 2p. The input messages





  
    x
    
      i
      1
    
  
  ,
  
    x
    
      i
      2
    
  
  ,
  ...
  ⁢
  
    
  
  ,
  
    x
    
      i
      
        d
        c
      
    
  




are input into the multiplier 511-1, the multiplier 511-2, the multiplier 511-3, . . . and the multiplier 511-dc, respectively.

Each of multiplier 511-1 through multiplier 511-dc performs multiplication of each input message vector




  
    x
    
      i
      1
    
  
  ,
  
    x
    
      i
      2
    
  
  ,
  ...
  ⁢
  
    
  
  ,
  
    x
    
      i
      
        d
        c
      
    
  




and each edge value





  
    h
    
      ji
      1
    
  
  ,
  
    h
    
      ji
      2
    
  
  ,
  ...
  ⁢
  
    
  
  ,
  
    h
    
      ji
      
        d
        c
      
    
  




of the parity check matrix on GF(2p). Here, the edge value hji represents an element of GF(2p), which has an edge connecting variable node i and check node j, and the mention that the edge connecting the variable node i and the check node j has a value of hji implies that an element existing in an jth row and an ith column of a parity check matrix defined in GF(2p) is hji. However, since the input messages are not elements on GF(2p), but indicate the probabilities of having the elements on GF(2p), each of the multiplier 511-1, the multiplier 511-2, the multiplier 511-3, . . . and the multiplier 511-dc actually performs the permutation of each input message





  
    x
    
      i
      1
    
  
  ,
  
    x
    
      i
      2
    
  
  ,
  ...
  ⁢
  
    
  
  ,
  
    
      x
      
        i
        
          d
          c
        
      
    
    .
  




Here, since, in the case of using the exponent representation, multiplication for elements on GF(2p) is implemented as mod(q−1) addition, as shown in Equation (3), the permutation is implemented by (q−1)-sized shift registers for elements on GF(2p).

After the permutation, each of multiplier 511-1 through multiplier 511-dc outputs each permuted input message




  
    x
    
      i
      1
    
  
  ,
  
    x
    
      i
      2
    
  
  ,
  ...
  ⁢
  
    
  
  ,
  
    x
    
      i
      
        d
        c
      
    
  




to each of interleaver 513-1 through interleaver 513-dc. Each of interleaver 513-1 through interleaver 513-dc inputs therein a signal output from each of multiplier 511-1 through multiplier 511-dc, interleaves the input signal in a predetermined interleaving scheme, and then outputs the interleaved signal to each of FFT unit 515-1 through FFT unit 515-dc. Here, since FFT performed in each of FFT unit 515-1 through FFT unit 515-dc is based on the assumption that elements of GF(2p) are expressed by the polynomial representation, each of interleaver 513-1 through interleaver 513-dc performs the interleaving operation in order to express the elements of GF(2p), which have been expressed by the exponent representation, again by the polynomial representation. Table 3 as presented below shows decimal numbers expressed by the polynomial representation (as shown in Table 1) and the exponent representation (as shown in Table 3), respectively.











TABLE 3







polynomial
exponent



element
representation
representation



















0
0
15



1
1
0



α
2
1



α2
4
2



α3
8
3



α4
3
4



α5
6
5



α6
12
6



α7
11
7



α8
5
8



α9
10
9



α10
7
10



α11
14
11



α12
15
12



α13
13
13



α14
9
14









As shown in Table 3, in the case of GF(2 4), 16 unit memories are required for storing information on interleaving performed by the interleavers. Further, since each unit memory consists of 4 bits, a memory capacity of total 16×4 bits is consequently required for storing the interleaving information. Thus, in the case of GF(2p), a 2p number of unit memories, each consisting of 4 bits, are required for storing information on interleaving performed by the interleavers, and consequently a memory capacity of total 2p×p bits is required for storing the interleaving information.
As a result of this, storing permutation information, for which a memory capacity of 2p×2p×p bits is required in a conventional check node processing unit, is implemented by the (q−1)-sized shift registers and the interleavers requiring a memory capacity of 2p×p bits in the node processing unit according to the present invention, so that the required memory capacity can be reduced.
Further, each of the FFT unit 515-1, the FFT unit 515-2, the FFT unit 515-3, . . . and the FFT unit 515-dc inputs therein a signal output from each of the interleaver 513-1, the interleaver 513-2, the interleaver 513-3, . . . and the interleaver 513-dc, performs FFT for the input signal, and then outputs the fast Fourier transformed signal to the check node processor 540. Here, the signal input into each of the FFT unit 515-1, the FFT unit 515-2, the FFT unit 515-3, . . . and the FFT unit 515-dc is the probability of elements expressed by the exponent representation as defined above in Table 2. Further, the FFT performed in each of the FFT unit 515-1, the FFT unit 515-2, the FFT unit 515-3, . . . and the FFT unit 515-dc means not ordinary FFT, but FFT performed on GF(2p), which is identical to FHT.
The check node processor 540 inputs therein a signal output from each of the FFT unit 515-1, the FFT unit 515-2, the FFT unit 515-3, . . . and the FFT unit 515-dc, performs a check node operation, and then outputs a corresponding result to each of the IFFT unit 571-1, the IFFT unit 571-2, the IFFT unit 571-3, . . . and the IFFT unit 571-dc. Each of the IFFT unit 571-1, the IFFT unit 571-2, the IFFT unit 571-3, . . . and the IFFT unit 571-dc inputs therein a signal output from the check node processor 540, performs IFFT for the input signal, and outputs the inverse fast Fourier transformed signal to each of the deinterleaver 573-1, the deinterleaver 573-2, the deinterleaver 573-3, . . . and the deinterleaver 573-dc. Here, the IFFT performed in each of the IFFT unit 571-1, the IFFT unit 571-2, the IFFT unit 571-3, . . . and the IFFT unit 571-dc means not ordinary IFFT, but IFFT performed on GF(2p). Further, each of the IFFT unit 571-1, the IFFT unit 571-2, the IFFT unit 571-3, . . . and the IFFT unit 571-dc has the same structure as that of each of the FFT unit 515-1, the FFT unit 515-2, the FFT unit 515-3, . . . and the FFT unit 515-dc, except that an output thereof is scaled by 1⁄2p.
Each of the deinterleaver 573-1, the deinterleaver 573-2, the deinterleaver 573-3, . . . and the deinterleaver 573-dc inputs therein a signal output from each of the IFFT unit 571-1, the IFFT unit 571-2, the IFFT unit 571-3, and the IFFT unit 571-dc, deinterleaves the input signal in a predetermined deinterleaving scheme, and then output the deinterleaved signal to each of the multiplier 575-1, the multiplier 575-2, the multiplier 575-3, . . . and the multiplier 575-dc. Here, the deinterleaving scheme used in each of the deinterleaver 573-1, the deinterleaver 573-2, the deinterleaver 573-3, . . . and the deinterleaver 573-dc is a deinterleaving scheme corresponding to the interleaving scheme used in each of the interleaver 513-1, the interleaver 513-2, the interleaver 513-3, . . . and the interleaver 513-dc. That is, since the signal output from each of the IFFT unit 571-1, the IFFT unit 571-2, the IFFT unit 571-3, and the IFFT unit 571-dc is expressed by the polynomial representation, each of the deinterleaver 573-1, the deinterleaver 573-2, the deinterleaver 573-3, . . . and the deinterleaver 573-dc performs the deinterleaving operation in order to express the signal again by the exponent representation.
Each of the multiplier 575-1, the multiplier 575-2, the multiplier 575-3, . . . and the multiplier 575-dc inputs therein a signal output from each of the deinterleaver 573-1, the deinterleaver 573-2, the deinterleaver 573-3, . . . and the deinterleaver 573-dc, and performs multiplication of the input signal and the multiplicative inverse element




  
    h
    
      ji
      1
    
    
      -
      1
    
  
  ,
  
    h
    
      ji
      2
    
    
      -
      1
    
  
  ,
  ...
  ⁢
  
    
  
  ,
  
    h
    
      ji
      
        d
        c
      
    
    
      -
      1
    
  




of each edge value





  
    h
    
      ji
      1
    
  
  ,
  
    h
    
      ji
      2
    
  
  ,
  ⋯
  ⁢
  
    
  
  ,
  
    h
    
      ji
      
        d
        c
      
    
  




of the parity check matrix on GF(2p). Here, each of the multiplier 575-1, the multiplier 575-2, the multiplier 575-3, . . . and the multiplier 575-dc also actually performs the permutation of the signal output from each of the deinterleaver 573-1, the deinterleaver 573-2, the deinterleaver 573-3, . . . and the deinterleaver 573-dc, and this permutation corresponds to the inverse of the permutation performed in each of the multiplier 511-1, the multiplier 511-2, the multiplier 511-3, . . . and the multiplier 511-dc. Hereinafter, for the convenience of explanation, the permutation performed in each of the multiplier 575-1, the multiplier 575-2, the multiplier 575-3, . . . and the multiplier 575-dc will be referred to as “inverse permutation”. Thus, the inverse permutation is also implemented by (q−1)-sized shift registers for elements on GF(2p). Since it is possible to extract one of the permutation information and the inverse permutation information from the other, it does not matter if only one of them is stored.

In the present invention, since storing permutation information, for which a memory capacity of 2p×2p×p bits is conventionally required, is implemented by the (q−1)-sized shift registers and the interleavers requiring a memory capacity of 2p×p bits, and storing inverse permutation information, for which a memory capacity of 2p33 2p×p bits is conventionally required, is implemented by the (q−1)-sized shift registers and the deinterleavers requiring a memory capacity of 2p×p bits, as described above, the memory capacity required for performing a check node operation can be minimized.
According to the present invention as described above, by expressing elements of GF(q) by an exponent representation in a communication system using a non-binary LDPC code, the memory capacity required for performing a check node operation in a decoder for decoding the non-binary LDPC code can be minimized.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention, as defined by the appended claims.

## Claims

1. A method for receiving a signal in a signal reception apparatus of a communication system, the method comprising:
receiving a signal; and
decoding the received signal in a non-binary Low Density Parity Check (LDPC) decoding scheme in which elements of a Galois field are expressed by an exponent representation.

2. The method as claimed in claim 1, wherein the non-binary LDPC decoding scheme includes a check node operation in which the elements of the Galois field are expressed by the exponent representation.

3. The method as claimed in claim 1, wherein decoding the received signal in the non-binary LDPC decoding scheme comprises:
expressing a plurality of messages input into any check node by the exponent representation and permuting the messages into permuted signals;
expressing the permuted signals by a polynomial representation and interleaving the signals;
fast Fourier transforming the interleaved signals on the Galois field;
performing a check node operation of the fast Fourier transformed signals;
inversely fast Fourier transforming the signals subjected to the check node operation;
expressing the inversely fast Fourier transformed signals by the exponent representation and deinterleaving the signals; and
inversely permuting the deinterleaved signals in a scheme corresponding to the permuting the messages.

4. The method as claimed in claim 3, wherein the exponent representation corresponds to a scheme in which only exponents of all elements of a Galois field GF(2p) are detected and all the elements of the Galois field GF(2p) are expressed using only the detected exponents.

5. The method as claimed in claim 4, wherein the Galois field GF(2p) is a Galois field GF(24), and when all elements of the Galois field GF(24) are expressed by at most a third-order polynomial α3x3+α2x2+α1x+α0, coefficients defined in GF(2), all the elements {0, 1, α, α2, α3, . . . , α14} of the Galois field GF(24), the polynomial coefficients {α3, α2, α1, α0} and decimal expressions corresponding thereto are represented as follows:

















element
a3
a2
a1
a0
decimal number








0
1
1
1
1
−∞ → 15



1
0
0
0
0
0



α
0
0
0
1
1



α2
0
0
1
0
2



α3
0
0
1
1
3



α4
0
1
0
0
4



α5
0
1
0
1
5



α6
0
1
1
0
6



α7
0
1
1
1
7



α8
1
0
0
0
8



α9
1
0
0
1
9



α10
1
0
1
0
10



α11
1
0
1
1
11



α12
1
1
0
0
12



α13
1
1
0
1
13



α14
1
1
1
0
14.

6. The method as claimed in claim 5, wherein expressing the permuted signals by the polynomial representation and interleaving the signals comprises expressing the permuted signals by the polynomial representation as shown in following table and interleaving the signals:















polynomial
exponent



element
representation
representation



















0
0
15



1
1
0



α
2
1



α2
4
2



α3
8
3



α4
3
4



α5
6
5



α6
12
6



α7
11
7



α8
5
8



α9
10
9



α10
7
10



α11
14
11



α12
15
12



α13
13
13



α14
9
14.

7. An apparatus for receiving a signal in a communication system, the apparatus comprising:
a receiver for receiving the signal; and
a decoder for decoding the received signal in a non-binary Low Density Parity Check (LDPC) decoding scheme in which elements of a Galois field are expressed by an exponent representation.

8. The apparatus as claimed in claim 7, wherein the non-binary LDPC decoding scheme includes a check node operation in which the elements of the Galois field are expressed by the exponent representation.

9. The apparatus as claimed in claim 8, wherein the decoder comprises:
a plurality of multipliers for expressing a plurality of messages input into any check node by the exponent representation and permuting the messages into permuted signals;
a plurality of interleavers for expressing the permuted signals by a polynomial representation and interleaving the signals;
a plurality of Fast Fourier Transform units for fast Fourier transforming the interleaved signals on the Galois field;
a check node processor for performing a check node operation of the fast Fourier transformed signals;
a plurality of inverse FFT units for inversely fast Fourier transforming the signals subjected to the check node operation;
a plurality of deinterleavers for expressing the inversely fast Fourier transformed signals by the exponent representation and deinterleaving the signals; and
a plurality of multipliers for inversely permuting the deinterleaved signals in a scheme corresponding to the permuting the messages.

10. The apparatus as claimed in claim 9, wherein the exponent representation corresponds to a scheme in which only exponents of all elements of a Galois field GF(2p) are detected and all the elements of the Galois field GF(2p) are expressed using only the detected exponents.

11. The apparatus as claimed in claim 10, wherein the Galois field GF(2p) is a Golois field GF(24), and when all the elements of the Galois field GF(24) are expressed by at most a third-order polynomial α3x3+α2x2+α1x+α0, coefficients of which are defined in GF(2), all the elements {0, 1, α, α2, α3, . . . , α14} of the Galois field GF(24), the polynomial coefficients {α3, α2, α1, α0} and decimal expressions corresponding thereto are presented as follows:

















element
a3
a2
a1
a0
decimal number








0
1
1
1
1
−∞ → 15



1
0
0
0
0
0



α
0
0
0
1
1



α2
0
0
1
0
2



α3
0
0
1
1
3



α4
0
1
0
0
4



α5
0
1
0
1
5



α6
0
1
1
0
6



α7
0
1
1
1
7



α8
1
0
0
0
8



α9
1
0
0
1
9



α10
1
0
1
0
10



α11
1
0
1
1
11



α12
1
1
0
0
12



α13
1
1
0
1
13



α14
1
1
1
0
14.

12. The apparatus as claimed in claim 11, wherein the plurality of interleavers express the permuted signals by the polynomial representation as shown in following table and interleave the signals:















polynomial
exponent



element
representation
representation



















0
0
15



1
1
0



α
2
1



α2
4
2



α3
8
3



α4
3
4



α5
6
5



α6
12
6



α7
11
7



α8
5
8



α9
10
9



α10
7
10



α11
14
11



α12
15
12



α13
13
13



α14
9
14.