# Patent

## Title
Method and apparatus to process dedicated physical control channel (DPCCH) in a transmit antenna diversity (TXDIV) rake finger

## Abstract

A method to process DP bits and TPC bits from multiple fingers within a WCDMA rake receiver is provided. DPCH symbols are received, quantized and channel compensated. Then processing operations for individual fingers for the channel compensated quantized despread DPCH symbols containing DP bits and TPC bits are chosen based on the DPCH slot format. The DPCH symbols are processed based on the DPCH slot format in order to produce processed DPCH pilot symbols in a common format. DP bits and TPC bits may be processed in parallel by separate processing branches or in series by applying timing control to common processing modules. These processed symbols may then be combined. Other embodiments may further allow for the computation of an SNR estimate based on the combined DPCH symbols.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE
This application makes reference to U.S. Provisional Patent Application Ser. No. 60/953,270. The above referenced application is hereby incorporated herein by reference in its entirety.


TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to cellular wireless communication systems, and more particularly to a method and apparatus for processing downlink Dedicated Physical Control Channel (DPCCH) Pilot and Transmit Power Control (TPC) bits in a wideband CDMA (WCDMA) network.
BACKGROUND OF THE INVENTION
Cellular wireless communication systems support wireless communication services in many populated areas of the world. While cellular wireless communication systems were initially constructed to service voice communications, they are now called upon to support data and video (multimedia) communications as well. The demand for video and data communication services has exploded with the acceptance and widespread use video capable wireless terminals and the Internet. Video and data communications have historically been serviced via wired connections; cellular wireless users now demand that their wireless units also support video and data communications. The demand for wireless communication system video and data communications will only increase with time. Thus, cellular wireless communication systems are currently being created/modified to service these burgeoning demands.
Cellular wireless networks include a “network infrastructure” that wirelessly communicates with wireless terminals within a respective service coverage area. The network infrastructure typically includes a plurality of base stations dispersed throughout the service coverage area, each of which supports wireless communications within a respective cell (or set of sectors). The base stations couple to controllers, with each controller serving a plurality of Node B's. Each controller couples to a mobile switching center (MSC). Each controller also typically directly or indirectly couples to the Internet. In the 3rd Generation Partnership Agreement (3GPP) these base stations may be referred to as “Node B's” and the wireless terminals may be referred to as user equipment (UE).
In operation, each Node B communicates with a plurality of wireless UEs operating in its cell/sectors. A controller coupled to the Node B routes voice, video, data or multimedia communications between the MSC and a serving base station. The MSC then routes these communications to another MSC or to the PSTN. Typically, controllers route data communications between a servicing Node B and a packet data network that may include or couple to the Internet. Transmissions from base stations to wireless terminals are referred to as “forward link” or “downlink” transmissions while transmissions from wireless terminals to base stations are referred to as “reverse link” or “uplink” transmissions. The volume of data transmitted on the forward link typically exceeds the volume of data transmitted on the reverse link. Such is the case because data users typically issue commands to request data from data sources, e.g., web servers, and the web servers provide the data to the wireless terminals. The great number of wireless terminals communicating with a single Node B forces the need to divide the forward and reverse link transmission resources (depending on the specific wireless standards, the resources could be frequency band, time slot, orthogonal code, and transmit power) amongst the various wireless terminals.
Wireless links between base stations and their serviced wireless terminals typically operate according to one (or more) of a plurality of operating standards. These operating standards define the manner in which the wireless link may be allocated, setup, serviced and torn down. One popular cellular standard is the Global System for Mobile telecommunications (GSM) standard. The GSM standard, or simply GSM, is predominant in Europe and is in use around the globe. The GSM standard has evolved in part into the 3rd Generation Partnership Agreement (3GPP). 3GPP provides Technical Specifications and Technical Reports for a 3rd Generation Mobile System based on evolved GSM core networks and the radio access technologies that they support (i.e., UMTS Terrestrial Radio Access (UTRA) both Frequency Division Duplex (FDD) and Time Division Duplex (TDD) modes). The scope also includes the maintenance and development of the Global System for Mobile communication (GSM) Technical Specifications and Technical Reports including evolved radio access technologies (e.g. General Packet Radio Service (GPRS) and Enhanced Data rates for GSM Evolution (EDGE)). While GSM originally serviced only voice communications, it has been modified to also service data communications. General Packet Radio Service (GPRS) operations and the Enhanced Data rates for GSM (or Global) Evolution (EDGE) operations coexist with GSM by sharing the channel bandwidth, slot structure, and slot timing of the GSM standard. GPRS operations and EDGE operations may also serve as migration paths for other standards as well, e.g., IS-136 and Pacific Digital Cellular (PDC).
Third generation (3G) cellular networks have been specifically designed to fulfill the future demands of the mobile Internet. As mobile Internet services grow in popularity and usage, factors such as cost efficient optimization of network capacity and quality of service (QoS) will become ever more essential to cellular operators. These factors may be achieved with careful network planning and operation, improvements in transmission methods, and advances in receiver techniques. To this end, carriers need technologies that will allow them to increase uplink and downlink throughput and, in turn, offer advanced QoS capabilities and speeds that rival those delivered by cable modem and/or DSL service providers. In this regard, networks based on wideband CDMA (WCDMA) technology can make the delivery of data to end users a more feasible option for today's wireless carriers. WCDMA has evolved continuously towards higher data rates and towards packet-switched IP-based services.
GPRS and EDGE technologies may be utilized for enhancing the data throughput of present second generation (2G) systems such as GSM. The GSM technology may support data rates of up to 14.4 kilobits per second (Kbps), while the GPRS technology may support data rates of up to 115 Kbps by allowing up to 8 data time slots per time division multiple access (TDMA) frame. The EDGE technology, a further enhancement to GPRS, may support data rates of up to 384 Kbps. The EDGE technology may utilizes 8 phase shift keying (8-PSK) modulation to provide higher data rates than those that may be achieved by GPRS technology. The GPRS and EDGE technologies may be referred to as “2.5G” technologies.
UMTS technology with theoretical data rates as high as 2 Mbps, is a 3G evolution of GSM, using wideband CDMA technology. UMTS may achieve higher data rates than GSM/EDGE due to many enhancements, including higher transmission bandwidth, adaptive higher order modulation and interference averaging due to a unity frequency reuse factor.
High-Speed Downlink Packet Access (HSDPA) technology is an Internet protocol (IP) based service, oriented towards data communications, which adapts WCDMA to support data transfer rates in the order of 14 megabits per second (Mbit/s). Developed by the 3G Partnership Project (3GPP) group, the HSDPA technology achieves higher data rates through a plurality of methods. In order to avoid excessive interference, 2G WCDMA may require fast power control to maintain a constant data rate. The HSDPA technology changes this paradigm and instead maintains a constant transmission power but may change the coding and modulation rate to adapt to changing channel conditions. Other methods that may be used to improve the data throughput are fast packet scheduling and a fast retransmission of lost packets by using Hybrid Automatic Repeat Request techniques.
Since processing of the data received to determine the need for retransmission takes place at the UE, these operations may be very sensitive to processing time. It is therefore important to devise methods that may lead to a minimum processing time for the determination of the need for a fast retransmission of lost packets without placing increasing demands on the processors and capacity of the UE. Unlike a desktop computer, the processors within the wireless terminal are assigned multiple processing duties. The addition of processing requirements within the wireless terminal requires new methods with which to balance data processing within the UE's while maintaining service.
BRIEF SUMMARY OF THE INVENTION
Embodiments of the present invention are directed to systems and methods that are further described in the following description and claims. Advantages and features of embodiments of the present invention may become apparent from the description, accompanying drawings and claims.



BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numerals indicate like features and wherein:
FIG. 1 shows the Frame structure for downlink DPCH in accordance with an embodiment of the present invention;
FIG. 2 is a system diagram illustrating a portion of a cellular wireless communication system that supports wireless terminals operating according to embodiments of the present invention;
FIG. 3 is a block diagram functionally illustrating the peripherals of a WCDMA processing block implemented as part of the WCDMA receiver constructed according to embodiments of the present invention;
FIGS. 4A and 4B provide top-level block diagrams of the ‘WCDMA Processing’ block of FIG. 3 in accordance with embodiments of the present invention;
FIG. 5 provides a lower level block diagram of the WCDMA DPCCH downlink processing block in FIG. 3 in accordance with embodiments of the present invention;
FIG. 6 provides a block diagram of finger Dedicated Physical Channel (DPCH) processing in accordance with an embodiment of the present invention;
FIG. 7 provides a block diagram of finger DPCH processing in accordance with an embodiment of the present invention;
FIG. 8 provides a detailed block diagram of the Space Time Transmit Diversity (STTD) decoding block in accordance with embodiments of the present invention.
FIG. 9 provides a detailed block diagram of the pair STTD decoding block in accordance with embodiments of the present invention.
FIG. 10 provides a detailed block diagram of the pair STTD decoding compressed mode block in accordance with embodiments of the present invention.
FIG. 11 provides a detailed block diagram of the quartet STTD decoding compressed mode block in accordance with embodiments of the present invention.
FIGS. 12 and 13 show the combiner blocks for DP processing.
FIG. 14 provides a logic flow diagram in accordance with embodiments of the present invention that describes a method to process Dedicated Pilot (DP) bits for multiple fingers within a WCDMA rake receiver; in accordance with embodiments of the present invention; and



DETAILED DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the present invention are illustrated in the FIGs., like numerals being used to refer to like and corresponding parts of the various drawings.
Embodiments of the present invention provide a method to process DP and TPC bits from multiple fingers within a WCDMA rake receiver. DPCH symbols are received, quantized and channel compensated. Then processing operations for individual fingers for the channel compensated quantized despread DPCH symbols are chosen based on the DPCH slot format associated with the despread DPCH symbols and on the transmit diversity mode used at the transmitter. The DPCH symbols are processed based on the DPCH slot format in order to produce processed DPCH symbols in a common format. These processed symbols may then be combined across fingers. Other embodiments may further allow for the computation of a signal to noise (SNR) estimate based on the combined DPCH symbols. The downlink DPCH can be seen as a time multiplex of a downlink DPDCH and a downlink DPCCH. FIG. 1 shows the frame structure of the downlink DPCH. Each frame of length 10 ms is split into 15 slots, each of length Tslot=2560 chips. The parameter k in FIG. 1 determines the total number of bits per downlink DPCH slot. It is related to the spreading factor SF of the physical channel as SF=512/2k. The spreading factor may thus range from 512 down to 4. The exact number of bits of the different downlink DPCH fields (Npilot, NTPC, NTFCI, Ndata1 and Ndata2) is given in Table 1. What slot format to use is configured by higher layers and can also be reconfigured by higher layers.







TABLE 1







DPDCH and DPCCH fields in DPCH slot
















Channel




Transmitted


Slot
Channel
Symbol


DPDCH
DPCCH
slots per


Format
Bit Rate
Rate

Bits/
Bits/Slot
Bits/Slot
radio frame

















#i
(kbps)
(ksps)
SF
Slot
NData1
NData2
NTPC
NTFCI
NPilot
NTr




















 0
15
7.5
512
10
0
4
2
0
4
15


 0A
15
7.5
512
10
0
4
2
0
4
8-14


 0B
30
15
256
20
0
8
4
0
8
8-14


 1
15
7.5
512
10
0
2
2
2
4
15


 1B
30
15
256
20
0
4
4
4
8
8-14


 2
30
15
256
20
2
14
2
0
2
15


 2A
30
15
256
20
2
14
2
0
2
8-14


 2B
60
30
128
40
4
28
4
0
4
8-14


 3
30
15
256
20
2
12
2
2
2
15


 3A
30
15
256
20
2
10
2
4
2
8-14


 3B
60
30
128
40
4
24
4
4
4
8-14


 4
30
15
256
20
2
12
2
0
4
15


 4A
30
15
256
20
2
12
2
0
4
8-14


 4B
60
30
128
40
4
24
4
0
8
8-14


 5
30
15
256
20
2
10
2
2
4
15


 5A
30
15
256
20
2
8
2
4
4
8-14


 5B
60
30
128
40
4
20
4
4
8
8-14


 6
30
15
256
20
2
8
2
0
8
15


 6A
30
15
256
20
2
8
2
0
8
8-14


 6B
60
30
128
40
4
16
4
0
16
8-14


 7
30
15
256
20
2
6
2
2
8
15


 7A
30
15
256
20
2
4
2
4
8
8-14


 7B
60
30
128
40
4
12
4
4
16
8-14


 8
60
30
128
40
6
28
2
0
4
15


 8A
60
30
128
40
6
28
2
0
4
8-14


 8B
120
60
64
80
12
56
4
0
8
8-14


 9
60
30
128
40
6
26
2
2
4
15


 9A
60
30
128
40
6
24
2
4
4
8-14


 9B
120
60
64
80
12
52
4
4
8
8-14


10
60
30
128
40
6
24
2
0
8
15


10A
60
30
128
40
6
24
2
0
8
8-14


10B
120
60
64
80
12
48
4
0
16
8-14


11
60
30
128
40
6
22
2
2
8
15


11A
60
30
128
40
6
20
2
4
8
8-14


11B
120
60
64
80
12
44
4
4
16
8-14


12
120
60
64
80
12
48
4
 8*
8
15


12A
120
60
64
80
12
40
4
16*
8
8-14


12B
240
120
32
160
24
96
8
16*
16
8-14


13
240
120
32
160
28
112
4
 8*
8
15


13A
240
120
32
160
28
104
4
16*
8
8-14


13B
480
240
16
320
56
224
8
16*
16
8-14


14
480
240
16
320
56
232
8
 8*
16
15


14A
480
240
16
320
56
224
8
16*
16
8-14


14B
960
480
8
640
112
464
16
16*
32
8-14


15
960
480
8
640
120
488
8
 8*
16
15


15A
960
480
8
640
120
480
8
16*
16
8-14


15B
1920
960
4
1280
240
976
16
16*
32
8-14


16
1920
960
4
1280
248
1000
8
 8*
16
15


16A
1920
960
4
1280
248
992
8
16*
16
8-14









Embodiments of the present invention provide that each finger of the rake receiver may be set to its own transmit diversity mode. The output of each finger is combined in the combiner regardless of the transmit diversity mode. Then only one common SNR estimation method is applied in the combiner regardless of each finger's transmit diversity mode.
FIG. 2 is a system diagram illustrating a portion of a cellular wireless communication system 100 that supports wireless terminals operating according to the present invention. The cellular wireless communication system 100 includes a user equipment (ULEs) 102, 104, 106, 108 and 110, a 3GPP capable Node B 112, and a Node B of a Universal Mobile Telecommunications System (UMTS) third-generation (3G) mobile phone systems may couple to the Internet 116 via a GPRS Gateway Support Node (GWSN) 114. MSC 118 couples Node B 112 to the Public Switched Telephone Network (PSTN) 120.
Each Node B services a cell/set of sectors within which it supports wireless communications. Wireless links that include both forward link components and reverse link components support wireless communications between the base stations and their serviced wireless terminals. These wireless links support digital voice, video, multimedia, and data communications. The cellular wireless communication system 100 may also be backward compatible in supporting analog operations as well. The cellular wireless communication system 100 supports the GSM standard which has evolved into the 3rd Generation Partnership Agreement (3GPP). 3GPP provides Technical Specifications and Technical Reports for a 3rd Generation Mobile System based on evolved GSM core networks and the radio access technologies that they support (i.e., Universal Terrestrial Radio Access (UTRA) both Frequency Division Duplex (FDD) and Time Division Duplex (TDD) modes). The scope also includes the maintenance and development of the Global System for Mobile communication (GSM) Technical Specifications and Technical Reports including evolved radio access technologies (e.g. General Packet Radio Service (GPRS) and Enhanced Data rates for GSM Evolution (EDGE)). The cellular wireless communication system 100 may also support the GSM General Packet Radio Service (GPRS) extension to GSM. However, the present invention is also applicable to other standards as well, e.g., TDMA standards, CDMA standards, etc.
Third generation (3G) cellular networks have been specifically designed to fulfill these future demands of the mobile Internet. In this regard, networks based on wideband CDMA (WCDMA) technology can make the delivery of data to end users a more feasible option for today's wireless carriers. WCDMA has evolved continuously towards higher data rates and towards packet-switched IP-based services.
UMTS technology with theoretical data rates as high as 2 Mbps, is a 3G evolution of GSM, using wideband CDMA technology. UMTS may achieve higher data rates than GSM/EDGE due to many enhancements, including higher transmission bandwidth, adaptive higher order modulation and interference averaging due to a unity frequency reuse factor.
High-Speed Downlink Packet Access (HSDPA) technology is an Internet protocol (IP) based service, oriented towards data communications, which adapts WCDMA to support data transfer rates in the order of 14 megabits per second (Mbit/s). Developed by the 3G Partnership Project (3GPP) group, the HSDPA technology achieves higher data rates through a plurality of methods. HSDPA technology maintains a constant transmission power but may change the coding and modulation rate to adapt to changing channel conditions. Other methods that may be used to improve the data throughput are fast packet scheduling and a fast retransmission of lost packets by using Hybrid Automatic Repeat Request techniques. The decision to request a retransmission is reduced in HSDPA where the TTI (transmission time interval) has been shortened to 2 ms in order to allow faster retransmitting of erroneous data blocks compared to the previous minimum TTI of 10 ms. This allows Node B to adapt literally every data block to fast changing radio conditions by the means of AMC. Thus it is possible to counteract the fading on the air-interface by adjusting modulation and coding almost every 2 ms depending on Node B's processing delay and packet scheduling algorithm.
UEs 102-110 support HSDPA and HSUPA communications. UEs 102-110 communicate with Node B via the MAC-hs for packet transmission and retransmission. Several new physical channels and a transport channel.
FIG. 3 is a block diagram functionally illustrating the peripherals of a WCDMA processing block implemented as part of the WCDMA receiver 200. The top-level block diagram of the WCDMA receiver 200 shows the data path leading to the WCDMA processing block. The WCDMA block is configured by and later on interacts with the firmware block 228 to exchange data and control information. WCDMA receiver 200 uses either the Δ-Σ modulator 204 or the 3G DigiRF 206 to convert the RF signal to baseband. In one embodiment as shown, the output of the Δ-Σ modulator 204 is an N-level (i.e., N-level I and N-level Q, e.g., N=5) CxM (122.88 MHz, if M=32) sampled complex signal, while the 3G DigiRF output is a K-bit (i.e., K-bit I and K-bit Q, e.g. K=8) CxP (7.68 MHz, if P=2) sampled complex signal. These signals are the inputs to the baseband receiver block 208 of the WCDMA processor.
Inside one embodiment of baseband receiver block 208, the input from the Δ-Σ modulator 204 is down-sampled to Cx4 (15.36 MHz) K-bit complex signal via a reconstruction/decimation FIR filter 210. Similarly, the CxP output from the 3G DigiRF block 206 is up-sampled via an interpolation FIR filter 212 to reach the same format of Cx4, K-bit. Only one source is used (Δ-Σ modulator 204 or 3G DigiRF 206), based on a firmware configuration as implemented by Multiplexer 214. If 3G DigiRF output is used, then the chip-matched filter (CMF) 216 inside the baseband receiver block 208 can be bypassed if the chip-matched filter inside the 3G DigiRF block is used. The Cx4 sampled signal is then up-sampled by a factor of 4 via an interpolation FIR filter 220 to reach Cx16. A DC-offset detection and correction block 222 then removes the residue DC component from the signal. This signal is then down-sampled to the desired clock rate CxL (e.g., L=16, or 8 or 4) by decimator 230 and passed to the WCDMA processing block 202.
The Cx16 sampled data, on a separate path, is down-sampled to Cx4 in processing block 224 and then used to measure the received signal strength indicator (RSSI) of the received signal to assist the AGC function of the firmware in processing block 226 to adjust the variable gain amplifier inside the RF front-end 204 or the 3G DigiRF block 206.
FIGS. 4A and 4B provide top-level block diagrams of the ‘WCDMA Processing’ block 202 of FIG. 3. in accordance with embodiments of the present invention. FIG. 4 shows the data/control path between major processing functions inside the WCDMA processing block 202. As indicated in FIG. 4A, each Finger x, (x=0, 1, 2, . . . 5) processing block produces a single output which is then directed to two separate modules combiner 302 and combiner 304, labeled here by DPCCH/F-DPCH TPC combiner and DPCCH DP combiner. That is to say, the combiner handles the transmit power control (TPC) bits and DP bits (which are two types of control bits within the DPCCH channel) in two separate modules.
In the structure depicted in FIG. 4B, the processing of TPC bits and DP bits may be handled separately within each finger. Therefore, each finger has now 2 outputs, one for TPC and one for DP. The TPC output is wired to the DPCCH/F-DPCH TPC combiner module 302 and the DP output is wired to the DPCCH DP combiner module 304 for their respective processing.
A lower level block diagram of the WCDMA DPCCH downlink processing block in FIGS. 4A and 4B is depicted in FIG. 5, where the interface signals of the DPCCH processing block 202 to the peripheral hardware blocks and the firmware block is shown. FIG. 5 also shows the interconnections among processing blocks within the DPCCH processing module 202. Table 2 describe the interface signals of the DPCCH processing block, while the following discussion details the operations of the processing blocks within DPCCH processing.
The interface specifications between the DPCCH processing block and other hardware and firmware blocks in accordance with one embodiment are given in the Table 2 below.













Signal name
I/O
Rate
Description















Other HW blocks










Descrambled
Input from
Cx1
Descrambled data, per


Cx1 input data
de-

finger.



scrambler



block


Channel Estimate
Input from
256-chip
Channel estimate that is


for Tx Ant1
channel

read every 256 chips,



estimation

per-finger



block


Channel Estimate
Input from
256-chip
Channel estimate that is


for Tx Ant2
channel

read every 256 chips,



estimation

per-finger, diversity



block

antenna if TxD is on.







FW










DPCH OVSF
Input
At
index for the OVSF


code index

configuration
code




or




reconfiguration


Tx Diversity
Input
At
This is the indicator of


Mode Enable

configuration
open or closed loop




or
diversity.




reconfiguration


STTD Enable
Input
At
This is the indicator of




configuration
Normal mode or




or
diversity mode.




reconfiguration


CL mode gain
Input
slot
This is the closed-loop





mode gain (weight0 and





weight1).


STTD selection
Input
At
Indicates what STTD




configuration
decoding block should




or
be used. The value




reconfiguration
depends on the slot





format


FDPCH enable
Input
At
This is the indicator of




configuration
Fractional DPCH




or




reconfiguration









FIG. 6 provides a block diagram of a finger DPCH processing block in accordance with an embodiment of the present invention, following the structure shown in FIG. 4A, i.e., the finger processing block produces only a single output. Starting from the input of the DPCH processing from the left-most side, the finger processing block 500 takes the chip-level descrambled input 502 from the sampling circuit and despreads the data based on the orthogonal variable spreading factor (OVSF) code in block 504. To complete this function block 504 needs the OVSF index and the OVSF code phase, which is aligned with the slot boundary. The OVSF index can be used to look-up the actual OVSF code. The output of the DPCH despreading block 504 is SF-chip rate or “C/SF.” The despread DPCH symbol is quantized and then passed through the channel compensation block 508. The channel estimates are read in at the same SF-chip rate. The output of the channel compensation block 508 is directed to 3 paths:

    
    
        a) normal mode path: STTD enable=0 and Tx_div_mode=0, the signal is passed directly to the combiner by multiplexers 512 and 514.
        b) STTD mode: STTD enable=1 and Tx_div_mode=0, the signal is passed through the STTD decoding block 516 and then to the combiner by multiplexers 512 and 514.
        c) CL mode: STTD enable=0 or 1 and Tx_div_mode=1, the signal is multiplied by the CL gains w0* and w1* in the CLM1 decoding block 520 and then summed, and finally passed to the combiner by multiplexer 514.
    
    


FIG. 7 provides a block diagram of a finger DPCH processing block in accordance with an embodiment of the present invention. The combination FIG. 7A/7B follows the structure shown in FIG. 4B, i.e., the finger processing block produces two outputs, a TPC output and a DP output, each directed towards its respective combiner block. The combination FIG. 7A/7C follows the structure shown in FIG. 4A, i.e., the finger processing block produces only a single output which is processed by the combiner. Starting from the input of the DPCH processing from the left-most side, the finger processing block takes the chip-level descrambled input from the sampling circuit and despread the data based on the OVSF code. This processing is similar to that done by block 504 as discussed in FIG. 6. To complete this function the block needs the OVSF index and the OVSF code phase, which is aligned with the slot boundary. The OVSF index can be used to look-up the actual OVSF code. The output of the DPCH despreading block is SF-chip rate or “C/SF.”
The despread DPCH symbol is quantized and then passed through the channel compensation module 602. The channel estimates are read in at the same SF-chip rate. The output of the channel compensation block is directed to 2 paths:

    
    
        Normal/STTD mode path: Tx_div_mode=0, the signal is passed directly through Multiplexer 604 for further processing.
        CL mode: Tx_div_mode=1, the signal is passed, multiplied by the CL gains w0* and w1*, and then through multiplexer 604 for further processing.

The output of multiplexer 604 labeled complex output 0 and complex output 1 corresponding to Tx antennas 1 and 2 (Both output signals are active if either STTD or CL1 is ON; In normal mode, only complex output 0 is active) is then directed into two main branches, the TPC branch and DP branch. As continued in FIG. 7B and in FIG. 7C

    
    


This TPC branch and DP branch allow parallel or serial processing of TPC and DP bits. TPC bits, unlike DP bits, are not known a priori. However, it is known that all bits belonging to the TPC field are of the same sign (either all 1 or all −1). The TPC bits may be used to also estimate a SNR to quantify the quality of the downlink channel (specifically for purposes of declaring an In-Sync or Out-of-sync status from the UE).
In TxDiv mode, the TPC are not encoded according to the exact same rules as the DP bits. Therefore the TPC bits need to be treated in an independent manner. There are two possible structures within the Rake finger to handle the two types of bits. First, the TPC bits may be processed in parallel as represented by the combination FIGS. 7A and 7B or in series as represented by the combination FIGS. 7A and 7C. When treated in parallel, then 2 outputs out of each finger go out to the combiner as represented by FIG. 4B. When treated in series, only 1 output out of each finger is given to combiner, which extracts TPC bits and DP bits and treat these bits independently.
As shown in FIGS. 7A and 7B, the finger is split into 2 parts: 1 branch processes the TPC bits, the other branch processes the DP bits. Both branches function in parallel, independently. When treated in series, as shown in FIGS. 7A and 7C, the finger uses a common branch for both and receives control information such that it switches to the appropriate processing method at the correct time. The start time of TPC bits and DP bits may be known as a function of slot format. The different delays between different processing method also needs to be taken into account. The parallel processing method potentially requires additional hardware to execute the parallel processing functions. The series method reduces hardware requirements but adds complexity because of the timing control needed.
Referring to FIG. 7B, in the TPC branch 611, the signal may be processed in 3 ways: Normal mode, STTD-mode-regular-DPCH, and STTD-mode-Fractional-DPCH-or-CL1 -mode-regular-DPCH. In the normal mode, STTD enable=0.
In the STTD-mode-regular-DPCH: STTD enable=1 and FDPCH enable=0. The 2 input signals (corresponding to Tx antennas 1 and 2) are passed through the STTD decoding block 610. The output of the STTD decoding block 610 is a complex number.
In the STTD-mode-Fractional-DPCH-or-CL1-mode-regular-DPCH: STTD enable =1 and FDPCH enable=1, the 2 input signals (corresponding to Tx antennas 1 and 2) are passed through the FDPCH STTD decoding block 612, in which the 2 input signals are simply added to become a complex number. In all cases, the output of is sent to DPCCH/F-DPCH TPC combiner, committed to the TPC processing.
In the DP branch 614, the 2 input signals may be processed in 5 ways. These are the Normal mode, STTD decode, Pair STTD decode, Pair STTD decode compressed mode, and Quartet STTD decode compressed mode. In the normal mode, STTD enable=0: This mode may be applied to all slot formats, and in this mode, the signal is passed directly to the DPCCH DP combiner.
The STTD or CL1 mode has 4 cases and is selected with multiplexer 618. The four inputs to multiplexer 618 include STTD decode block 610, Pair STTD decode block 620, Pair STTD decode compressed mode block 622, and Quartet STTD decode compressed mode block 624. A 2-bit unsigned register STTD_selection allows for the selection of one of these 4 cases depending on the slot format. This is indicated by Table 3.







TABLE 1







Value of register STTD_selection when STTD or CL1 is ON for all different


slot formats













STTD




Slot format
STTD_selection
enable
comment
Slot formats (cf. Table 1)





Non
00
1
STTD decode
2, 3, 4, 5, 8, 9, 2A, 3A, 4A,


compressed



5A, 8A, 9A


Npilot bits = 2, 4


Non
01
1
Pair STTD
6, 7, 10, 11, 12, 13, 14, 15, 16,


compressed


decode
6A, 7A, 10A, 11A, 12A, 13A,


Npilot bits = 8,



14A, 15A, 16A


16


Compressed
00
1
STTD decode
2B, 3B


Npilot bits = 4


Compressed
10
1
Pair STTD
4B, 5B, 8B, 9B


Npilot bits = 8


decode





compressed





mode


Compressed
11
1
Quartet STTD
6B, 7B, 10B, 11B, 12B, 13B,


Npilot bits = 16,


decode
14B, 15B


32


compressed





mode









The STTD decode mode is applied to slot formats: Non compressed Npilot bits=2, 4, and Compressed Npilot bits=4. In this case, the 2 input signals (corresponding to Tx antennas 1 and 2) are passed through the STTD decoding block 610. The output of the STTD decoding block 610 is a complex number.
The Pair STTD decode mode is applied to slot formats: Non compressed Npilot bits=8 and 16. In this case, the 2 input signals (corresponding to Tx antennas 1 and 2) are passed through the pair STTD decoding block 620. The output of the pair STTD decoding block is a complex number.
The Pair STTD decode compressed mode is applied to slot formats: Compressed mode, Npilot bits=8. In this case, the 2 input signals (corresponding to Tx antennas 1 and 2) are passed through the pair STTD decoding compressed mode block 622. The output of the pair STTD decoding compressed mode block is a complex number
The Quartet STTD decode compressed mode is applied to slot formats: Compressed Npilot bits=16 and 32. In this case, the 2 input signals (corresponding to Tx antennas 1 and 2) are passed through the quartet STTD decoding compressed mode block 624. The output of the quartet STTD decoding compressed mode block is a complex number.
FIG. 7C provides a block diagram of the TPC and DP processing branches, when treated in series, in accordance with an embodiment of the present invention. The 2 input signals (corresponding to Tx antennas 1 and 2) are input into a common processing module, which processes both DP and TPC bits, using one of a set of possible processing modes for each type of bits. The common processing module receives control information such that it switches to the appropriate processing method at the correct time. The start time of TPC bits and DP bits may be known as a function of slot format. The different delays between different processing methods also need to be taken into account. Similarly to FIG. 7B, the TPC bits may be processed in 3 ways: Normal mode, STTD-mode-regular-DPCH, and STTD-mode-Fractional-DPCH-or-CL1-mode-regular-DPCH. In the normal mode, STTD enable=0.
In the STTD-mode-regular-DPCH: STTD enable=1 and the 3-bit register input to Mux 724, labeled as select_mode, =001. The 2 input signals (corresponding to Tx antennas 1 and 2) are passed through the STTD decoding block 610. The output of the STTD decoding block 610 is a complex number.
In the STTD-mode-Fractional-DPCH-or-CL1-mode-regular-DPCH: STTD enable=1 and the 3-bit register input to Mux 724, labeled as select_mode,=000. The 2 input signals (corresponding to Tx antennas 1 and 2) are simply added to become a complex number. In all cases, the output of is sent to DPCCH/F-DPCH combiner, which extracts the TPC bits from the output signal and processed them accordingly.
Similarly to FIG. 7B, the DP bits may be processed in 5 ways. These are the Normal mode, STTD decode, Pair STTD decode, Pair STTD decode compressed mode, and Quartet STTD decode compressed mode. In the normal mode, STTD enable=0: This mode may be applied to all slot formats, and in this mode, the signal is passed directly to DPCCH/F-DPCH combiner, which extracts the DP bits from the output signal and processed them accordingly.
The STTD or CL1 mode has 4 cases and is selected with multiplexer 724. The four inputs to multiplexer 724 include STTD decode block 610, Pair STTD decode block 620, Pair STTD decode compressed mode block 622, and Quartet STTD decode compressed mode block 624. A 3-bit register select_mode allows for the selection of one of these 4 cases depending on the slot format. This is indicated by Table 4







TABLE 4







Value of register select_mode when STTD or CL1 is ON for all different slot


formats













STTD




Slot format
Select_mode
enable
comment
Slot formats (cf. Table 1)





Non
001
1
STTD decode
2, 3, 4, 5, 8, 9, 2A, 3A, 4A,


compressed



5A, 8A, 9A


Npilot bits = 2, 4


Non
010
1
Pair STTD
6, 7, 10, 11, 12, 13, 14, 15, 16,


compressed


decode
6A, 7A, 10A, 11A, 12A, 13A,


Npilot bits = 8,



14A, 15A, 16A


16


Compressed
001
1
STTD decode
2B, 3B


Npilot bits = 4


Compressed
011
1
Pair STTD
4B, 5B, 8B, 9B


Npilot bits = 8


decode





compressed





mode


Compressed
100
1
Quartet STTD
6B, 7B, 10B, 11B, 12B, 13B,


Npilot bits = 16,


decode
14B, 15B


32


compressed





mode









The STTD decode mode, the Pair STTD decode mode, the Pair STTD decode compressed mode and the Quartet STTD decode compressed mode function in the same way as described in the description of FIG. 7B.
Delay modules 718 and 716 and Multiplexers 720 and 722 are used to serially process the TPC and DP bit and implement the greater complexity involved in controlling timing issues. In the case where the 3-bit register select_mode=010, or 011, or 100, the first part of the slot (all symbols up to the start of the dedicated pilot field, cf. FIG. 1) needs to go through the STTD decoding block 610 and the rest of the slot (i.e., the dedicated pilot symbols) needs to go through a different processing block, namely,

    
    
        1. if select_mode=010: first part of the slot goes through STTD decoding block 610, DP symbols go through pair STTD decoding block 620.
        2. if select_mode=011: first part of the slot goes through STTD decoding block 610, DP symbols go through pair STTD decoding compressed mode block 622.
        3. if select_mode=100: first part of the slot goes through STTD decoding block 610, DP symbols go through quartet STTD decoding compressed mode block 624.
    
    


The switching is made possible by multiplexers 720 and 722, which receive an input labeled as X. X is an indicator of the switching time within the slot, i.e., it indicates the starting time of the DP field. Over the period of a time slot (cf. FIG. 1), X=0 between the start of the slot and the beginning of the DP field. In this case, multiplexers 720 and 722 select their input corresponding to X=0, i.e., select the output of the STTD decoding block 610, conveniently delayed by delay blocks 716 and 718, Over the duration of the DP field, X=1, and multiplexers 720 and 722 select their input corresponding to X=1, i.e., select the output of blocks 620, 622 and 624, respectively.
The output of the STTD decoding block 610 is delayed by delay module 718 before entering multiplexer 722 because there is a known delay between the output of STTD decoding block 610 and that of the pair STTD decoding block 620. Module 718 is used to time-align the two outputs. The same delay exists between the output of blocks 620 and 622, similarly, the output of the STTD decoding block 610 is delayed by delay module 716 before entering multiplexer 720 because there is a known delay between the output of STTD decoding block 610 and that of the quartet STTD decoding block 624. Module 716 is used to time-align the two outputs.
FIG. 8 provides a detailed block diagram of the STTD decoding block 610 in accordance with embodiments of the present invention. Multiplexer 802 (which refers to multiplexer 604 of FIG. 7A) outputs two branches, branch 804 and branch 806. Block 808 conjugates all symbols incoming in branch 806. Blocks 810 and 812 register even symbols incoming in branch 804 and branch 806. The even symbols of branch 804 are summed with odd symbols of branch 806 in summing module 814. The even symbols of branch 806 are subtracted from odd symbols of branch 804 with summing module 816. The output of the decoding block is a complex number that is processed as described with respect to FIG. 7.
FIG. 9 provides a detailed block diagram of the pair STTD decoding block 620, respectively in accordance with embodiments of the present invention. Pair STTD decoding block 620 is structured in the same way as the STTD decoding block 610. Multiplexer 802 (which refers to multiplexer 604 of FIG. 7A) outputs two branches, branch 804 and branch 806. Pair STTD decoding block 620 performs several steps. First, Pair STTD decoding block 620 take the conjugate of odd symbols incoming in branch 806 with block 808. Next, even pair of symbols incoming in branch 804 and branch 806 is registered with blocks 810 and 812 respectively. Summing module 814 sums the even symbol of odd pairs with even symbol of even pair in branch 804. Summing module 816 sums odd symbol of odd pair of branch 806 with odd symbol of even pair of branch 804. Summing module 818 subtract odd symbols of even pair of branch 806 from odd symbol of odd pair of branch 804. Summing module 820 subtract even symbol of odd pair from even symbol of even pair in branch 806. The output of the decoding block is a complex number that is processed as described with respect to FIG. 7.
FIG. 10 provides a detailed block diagram of the pair STTD decoding compressed mode block 622 in accordance with embodiments of the present invention. The pair STTD decoding compressed mode block is used in the case of compressed mode and 8 DP bits is structured in the same way as the STTD decoding block 610. Multiplexer 902 (which refers to multiplexer 604 of FIG. 7A) outputs two branches, branch 904 and branch 904. The pair STTD decoding compressed mode block performs several steps. First, block 908 take the conjugate of all symbols incoming in branch 906. Blocks 910 and 912 register even pair of symbols incoming in branch 904 and branch 906. Summing module 914 sums even symbol of odd pair of branch 906 with even symbol of even pair of branch 904. Summing module 914 sums odd symbols of odd pair of branch 906 with odd symbol of even pair of branch 904. Summing module 916 subtract even symbol of even pair of branch 906 from even symbol of odd pair of branch 904. Summing module 916 subtracts odd symbol of even pair of branch 906 from odd symbol of odd pair of branch 904. The output of the decoding block is a complex number that is processed as described with respect to FIG. 7.
FIG. 11 provides a detailed block diagram of the quartet STTD decoding compressed mode block 624, respectively in accordance with embodiments of the present invention. The quartet STTD decoding compressed mode block 924, used in the case of compressed mode with 16 and 32 DP bits, is structured in the same way as the STTD decoding block 610. Multiplexer 1002 (which refers to multiplexer 604 of FIG. 7A) outputs two branches, branch 1004 and branch 1006. There are several steps preformed by quartet STTD decoding compressed mode block 624. First, block 1008 takes the conjugate of the last 2 symbols of each quartet of symbols incoming in branch 1006. One way to recognize the last 2 symbols of each quartet is to use the slot-based symbol counter. Register even quartet of symbols incoming in branch 1004 and branch 1006 with blocks 1010 and 1012.
Summing modules 1014 and 1016 sum the first symbol of odd quartet with first symbol of even quartet in branch 1004, the second symbol of odd quartet with second symbol of even quartet in branch 1004, the third symbol of odd quartet of branch 1006 with third symbol of even quartet of branch 1004; the fourth symbol of odd quartet of branch 1006 with fourth symbol of even quartet of branch 1004.
Summing modules 1018 and 1020 subtract third symbol of even quartet of branch 1006 from third symbol of odd quartet of branch 1004, the fourth symbol of even quartet of branch 1006 from fourth symbol of odd quartet of branch 1004, the first symbol of odd quartet from first symbol of even quartet in branch 1006, and subtract second symbol of odd quartet from second symbol of even quartet in branch 1006. The output of the decoding block is a complex number that is processed as described with respect to FIG. 7.
FIG. 14 provides a logic flow diagram in accordance with embodiments of the present invention that describes a method to process DP bits for multiple fingers within a WCDMA rake receiver. Operations 1500 begin in Step 1502, where DPCH pilot symbols are received. In Step 1504 these are quantized and channel compensation is performed in Step 1506. Then processing operations for individual fingers for the channel compensated quantized despread DPCH pilot symbols are chosen based on the DPCH slot format and on the transmit diversity mode used at the transmitter in Step 1508. The DPCH pilot symbols are processed based on the DPCH slot format in order to produce processed DPCH pilot symbols in a common format in Step 1510. These may then be combined in Step 1512. Other embodiments may further allow for the computation of an SNR estimate based on the combined DPCH pilot symbols in Step 1512
As illustrated in FIG. 4, the DPCH combiner handles TPC and DP bits separately. In the design of FIG. 4B, each finger processing block has 2 outputs, one for TPC and one for DP. The TPC output is wired to the DPCCH/F-DPCH TPC combiner module and the DP output is wired to the DPCCH DP combiner module for their respective processing. A new noise estimation method in the DP processing block of the DPCCH DP combiner module is described. This noise power method is shown to produce a more accurate estimate under the scenario of multiple fingers in various normal/TX diversity mode combinations. To highlight the change needed, FIG. 12 shows a prior art combiner block for DP processing and FIG. 13 shows the new combiner block for DP processing.
In FIG. 12, the input to the combiner DP processing block is the DP I and Q post DP extraction after all fingers have been summed. They are denoted by PilotI and PilotQ and represented as 11-bit signed. Three variables are being computed for the purpose of SNR estimation: mean I, meanQ, and meanSquare.
PilotI and PilotQ are multiplied by the pilot sequence (sent from Tx antenna 1). This operation consists of a sign change, therefore the output of the rotation remains an 11-bit signed. Then an accumulation is performed over the number of DP symbols, denoted by n, resulting in a 15-bit signed output. Then the accumulation is normalized by the number of DP symbols n and outputs an 11-bit signed number, denoted as MeanI and MeanQ.
PilotI and PilotQ are multiplied by the pilot sequence (sent from Tx antenna 1). This operation consists of a sign change, therefore the output of the rotation remains an 11-bit signed. Then each signal is squared resulting in a 20-bit unsigned value. Then an accumulation is performed over the number of DP symbols, denoted by n, resulting in a 24-bit unsigned output. The I and Q branch are then summed resulting in a 25-bit unsigned output. Then the accumulation in normalized by the number of DP bits 2n and outputs a 20-bit unsigned number, denoted as meanSquare. The variables meanI, meanQ and meanSquare are passed to FW which proceeds with the SNR computation.
As shown in FIG. 13, one new branch is added for the noise power estimation, of very similar structure as the paths that compute meanI, meanQ and meanSquare.
PilotI and PilotQ are multiplied by the pilot sequence (sent from Tx antenna 1) such that:

yI=PilotQ*ISeq 

yQ=PilotI*QSeq 

where yI and yQ are 11-bit signed values. yI is then subtracted from yQ to obtain a 12-bit signed value denoted as y.

y=YQ−yI, 

then the square of y is taken yielding a 22-bit unsigned value denoted as y_sq:

y—sq=y*y 

y_sq is accumulated over the number of DP symbols, denoted by n, resulting in a 26-bit unsigned output. Then the accumulation in normalized by the number of DP symbols n and outputs a 22-bit unsigned number, denoted as meanNoiseQ. This value is passed on to the FW which may use it as an alternative noise value to the one already currently computed.

In summary, embodiments of the present invention provide a method to process TPC and DP bits from multiple fingers within a WCDMA rake receiver. DPCH symbols are received, quantized and channel compensated. Then processing operations for individual fingers for the channel compensated quantized despread DPCH symbols are chosen based on the DPCH slot format and on the transmit diversity mode used at the transmitter. The DPCH symbols are processed based on the DPCH slot format in order to produce processed DPCH symbols in a common format. These processed symbols may then be combined. Other embodiments may further allow for the computation of an SNR estimate based on the combined DPCH symbols.
As one of average skill in the art will appreciate, the term “substantially” or “approximately”, as may be used herein, provides an industry-accepted tolerance to its corresponding term. Such an industry-accepted tolerance ranges from less than one percent to twenty percent and corresponds to, but is not limited to, component values, integrated circuit process variations, temperature variations, rise and fall times, and/or thermal noise. As one of average skill in the art will further appreciate, the term “operably coupled”, as may be used herein, includes direct coupling and indirect coupling via another component, element, circuit, or module where, for indirect coupling, the intervening component, element, circuit, or module does not modify the information of a signal but may adjust its current level, voltage level, and/or power level. As one of average skill in the art will also appreciate, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two elements in the same manner as “operably coupled”. As one of average skill in the art will further appreciate, the term “compares favorably”, as may be used herein, indicates that a comparison between two or more elements, items, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater magnitude than signal 2, a favorable comparison may be achieved when the magnitude of signal 1 is greater than that of signal 2 or when the magnitude of signal 2 is less than that of signal 1.
The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. The embodiment was chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto, and their equivalents.

## Claims

1. A method for processing downlink Dedicated Pilot (DP) bits and Transmit Power Control (TPC) bits received from a wireless signal by a receiver equipped with a Rake containing multiple fingers, said wireless signal is transmitted by a transmitter, the method comprising:
receiving despread Dedicated Physical Channel (DPCH) symbols;
quantizing the despread DPCH symbols;
selecting one of a set of processing modes for individual fingers for the quantized despread DPCH symbols based on the DPCH slot format associated with the despread DPCH symbols and on the transmit diversity mode used at said transmitter;
processing the DPCH symbols containing DP bits and TPC bits according to the selected mode, wherein the processed DPCH symbols are in a common format; and
combining processed DPCH symbols.

2. The method of claim 1, further comprising performing channel compensation, wherein said channel compensation occurs either on the quantized DPCH symbols predespreading at chip-level or on the quantized despread DPCH symbols at symbol-level.

3. The method of claim 1, wherein:
a TPC processing branch associated with each finger, performs processing of the DPCH symbols containing TPC bits, the TPC processing modes are chosen based on a DPCH slot format associated with DPCH symbols and on the transmit diversity mode used at said transmitter;
a DP processing branch associated with each finger, performs processing of the DPCH symbols containing DP bits, the DP processing modes are chosen based on a DPCH slot format associated with DPCH symbols and on the transmit diversity mode used at said transmitter;
wherein the TPC processing branch and DP processing branch provide processed DPCH symbols in a common format to be combined across fingers.

4. The method of claim 1, wherein TPC bits and DP bits are processed by separate processing branches within the multiple fingers.

5. The method of claim 1, wherein TPC bits and DP bits are processed by common processing modules within the multiple fingers, wherein timing control is applied to the common processing modules to separate TPC bits and DP bits processing.

6. The method of claim 1, wherein the set of TPC processing modes comprises:
a normal mode;
a STTD mode, or
a STTD mode Fractional DPCH mode or CL1 mode.

7. The method of claim 1, wherein the set of DP processing modes comprises:
a Normal mode;
a STTD decoding mode;
a pair STTD decoding mode;
a pair STTD decoding compressed mode; and
a quartet STTD decoding compressed mode.

8. The method of claim 1, wherein the DPCH slot format is defined by the number of bits in multiple downlink DPCH fields.

9. The method of claim 1, wherein said selected mode is selected per-finger and thereby may differ across multiple fingers.

10. A method for processing downlink Dedicated Pilot (DP) bits and Transmit Power Control (TPC) bits received from a wireless signal by a receiver equipped with a Rake containing multiple fingers, said wireless signal is transmitted by a transmitter, the method comprising:
receiving despread Dedicated Physical Channel (DPCH) symbols;
quantizing the despread DPCH symbols;
selecting one of a set of processing modes for individual fingers for the quantized despread DPCH symbols based on the DPCH slot format associated with the despread DPCH symbols and on the transmit diversity mode used at said transmitter;
processing the DPCH symbols containing DP bits and TPC bits according to the selected mode, wherein the processed DPCH symbols are in a common format;
combining processed DPCH symbols; and
processing the combined DPCH symbols to produce an SNR estimate.

11. The method of claim 10, further comprising performing channel compensation, wherein said channel compensation occurs either on the quantized DPCH symbols predespreading at chip-level or on the quantized despread DPCH symbols at symbol-level.

12. The method of claim 10, wherein:
a TPC processing branch associated with each finger, performs processing of the DPCH symbols containing TPC bits, the TPC processing modes are chosen based on a DPCH slot format associated with DPCH symbols and on the transmit diversity mode used at said transmitter;
a DP processing branch associated with each finger, performs processing of the DPCH symbols containing DP bits, the DP processing modes are chosen based on a DPCH slot format associated with DPCH symbols and on the transmit diversity mode used at said transmitter;
wherein the TPC processing branch and DP processing branch provide processed DPCH symbols in a common format to be combined across fingers.

13. The method of claim 10, wherein TPC bits and DP bits are processed by separate processing branches within the multiple fingers.

14. The method of claim 10, wherein TPC bits and DP bits are processed by common processing modules within the multiple fingers, wherein timing control is applied to the common processing modules to separate TPC bits and DP bits processing.

15. The method of claim 10, wherein the set of TPC processing modes comprises:
a normal mode;
a STTD mode, or
a STTD mode Fractional DPCH mode or CL1 mode.

16. The method of claim 10, wherein the set of DP processing modes comprises:
a Normal mode;
a STTD decoding mode;
a pair STTD decoding mode;
a pair STTD decoding compressed mode; and
a quartet STTD decoding compressed mode.

17. The method of claim 10, wherein the DPCH slot format is defined by the number of bits in multiple downlink DPCH fields.

18. The method of claim 10, wherein said selected mode is selected per-finger and thereby may differ across multiple fingers.

19. A WCDMA receiver comprising:
a radio frequency (RF) front end operable to convert a received RF signal to a baseband signal, said RF signal is received from a transmitter;
a baseband receiver block coupled to the RF front end operable to receive the baseband signal; and
a DPCCH/F-DPCH Processing block have a rake structure, the DPCCH/F-DPCH Processing block operable to process Dedicated Pilot (DP) bits and Transmit Power Control (TPC) bits from multiple fingers within the rake structure, wherein DPCH symbols are:
processed based on the DPCH slot format associated with DPCH symbols and on the transmit diversity mode used at said transmitter;
combined based on the DPCH slot format, wherein the processed DPCH symbols are in a common format;

wherein the TPC bits and DP bits are processed by separate processing branches within the multiple fingers.

20. The WCDMA receiver of claim 19, wherein the DPCCH/F-DPCH Processing block having a rake structure comprises:
a plurality of fingers,
a TPC processing branch associated with each finger, wherein processing operations within the TPC processing branch are chosen based on a DPCH slot format associated with DPCH symbols and on the transmit diversity mode used at said transmitter; and
a DP processing branch associated with each finger, wherein processing operations within the DP processing branch are chosen based on a DPCH slot format associated with DPCH symbols and on the transmit diversity mode used at said transmitter;
a TPC combiner module; and
a DP combiner module wherein the TPC processing branch and DP processing branch provide processed DPCH symbols which are in a common format to the combiner modules.

21. The WCDMA receiver of claim 20, wherein the TPC processing branch functions in:
a normal mode;
a STTD; or
a STTD mode Fractional DPCH mode or CL1 mode.

22. The WCDMA receiver of claim 20, wherein DP processing branch functions in:
a normal mode; or
a STTD or CL1 mode, wherein the STTD of CL1 mode comprises four cases, comprising:
a STTD decode mode;
a Pair STTD decode mode;
a Pair STTD decode compressed mode; or
a Quartet STTD decode compressed mode.

23. The WCDMA receiver of claim 22, wherein the case of the STTD of CL1 mode is selected based on the transmit diversity mode used at said transmitter.

24. The WCDMA receiver of claim 19, wherein TPC bits and DP bits are processed by common processing modules within the multiple fingers, wherein timing control is applied to the common processing modules to separate TPC bits and DP bits processing.