# Patent

## Title
Driving apparatus having an adjustable driving current output

## Abstract

An exemplary driving apparatus capable of generating a driving current, including: an analog input generating circuit, an analog input driving circuit, and an output circuit. The analog input generating circuit is electrically connected between a first voltage source and the ground and configured (i.e., structured and arranged) for supplying an adjustable analog signal. The analog input driving circuit is electrically connected between a second voltage source and the ground and configured for converting the analog signal into a pulsed signal. The output circuit is configured for converting the pulsed signal into a driving current as an output. The frequency of the pulsed signal can be adjusted via adjusting the analog signal and thereby varying the driving current. Thus the driving current can be adapted for the different target loads.

## Background
BACKGROUND
1. Technical Field
The present invention generally relates to a driving apparatus, and more particularly to a driving apparatus that could achieve an adjustable driving current output.
2. Description of Related Art
Electronic loads have two types of driving modes, one is current driving mode and the other one is voltage driving mode. For different electronic loads, such as electrical motors, light emitting diodes (LEDs), liquid crystal displays (LCDs), etc., stable and adjustable driving voltages/currents circuits are needed.
Referring to FIG. 8, a driving apparatus 100 configured for supplying a driving current to a target load 101 is provided. The driving apparatus 100 includes a rectifier 110, a micro-programmed control unit (MCU) 120, a digital input driving circuit 130, and an output circuit 140. The rectifier 110 converts a high voltage alternating current (AC) voltage Vac to a high voltage direct current (DC) voltage Vdc. The high voltage DC voltage Vdc can be used as power supply to the digital input driving circuit 130 and the target load 101. A DC voltage Vdc1 as a power source to the MCU 120. The MCU 120 generates/produces a pulse width modulation (PWM) signal. The digital input driving circuit 130 modulates the PWM signal to generate an output signal Vg. The output circuit 140 receives the output signal Vg and then generates a driving current Ic with a level in conjunction with that of the output signal Vg. Finally, the driving current Ic generated by the output circuit 140 can be inputted into the target load 101 for driving the target load 101. Even further, the digital input driving circuit 130 could also generate a stable and constant driving voltage Vout used to drive other loads.
However, because the PWM signal is controlled by embedded software or firmware and is generally preprogrammed by the manufacturer, the PWM signal is non-adjustable, so the output signal Vg cannot be varied correspondingly, which results in electrical parameters of the driving current Ic generated by the driving apparatus 100 could not be adjusted. As such, the above-mentioned driving apparatus 100 is difficult to meet the different driving currents requirements for different target loads.
What is needed, therefore, is a driving apparatus could achieve an adjustable driving current output.
SUMMARY
A driving apparatus capable of generating an adjustable driving current, including: an analog input generating circuit, an analog input driving circuit, and an output circuit. The analog input generating circuit is electrically connected between a first voltage source and the ground and configured (i.e., structured and arranged) for providing/supplying an adjustable analog signal. The analog input driving circuit is electrically connected between a second voltage source and the ground and configured for converting the analog signal into a pulsed signal. The output circuit is configured for converting the pulsed signal into a driving current as an output. The frequency of the pulsed signal can be adjusted via adjusting the analog signal, and thereby varying the driving current.
Other advantages and novel features will become more apparent from the following detailed description of the present driving apparatus, when taken in conjunction with the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
Many aspects of the present driving apparatus can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present driving apparatus.
FIG. 1 is a schematic view of a driving apparatus in accordance with a preferred embodiment;
FIG. 2 is a diagram showing a circuit configuration for the rectifier of FIG. 1;
FIG. 3 is a more detailed schematic view of the driving apparatus of FIG. 1;
FIG. 4 is a schematic view of the analog input driving circuit of FIG. 1;
FIG. 5 is a diagram showing a circuit configuration for the voltage regulator of FIG. 4;
FIG. 6 is a schematic view of the signal converter of FIG. 4;
FIG. 7 is a diagram showing the relationship between time vs. amplitude for five signals in the signal converter of FIG. 6; and
FIG. 8 is a schematic view of a conventional driving apparatus.



Corresponding reference characters indicate corresponding parts throughout the drawings. The exemplifications set out herein illustrate at least one preferred embodiment of the present driving apparatus, in one form, and such exemplifications are not to be construed as limiting the scope of the driving apparatus in any manner.
DETAILED DESCRIPTION OF THE INVENTION
Reference will now be made to the drawings to describe at least one preferred embodiment of the present driving apparatus.
Referring to FIG. 1, a driving apparatus 200, in accordance with a preferred embodiment, is shown. The driving apparatus 200 includes: a rectifier 210, an analog input generating circuit 220, an analog input driving circuit 230, and an output circuit 240.
Referring to FIG. 1 and FIG. 2, the rectifier 210 is configured for converting a AC voltage Vac into a DC voltage Vdc. The DC voltage Vdc can be connected with a power input terminal of the analog input driving circuit 230 and also can be voltage source for the target load 201. In the illustrated embodiment, the rectifier 210 is a full-wave rectifier, and this full-wave rectifier includes four diodes D1, D2, D3, D4 electrically connected together in a well-known manner.
Referring to FIG. 1 with FIG. 3 together, the analog input generating circuit 220 is configured for providing/supplying an adjustable analog signal Vain to the analog input driving circuit 230. In the illustrated embodiment, the analog input generating circuit 220 includes a resistor R1 and a variable resistor Re1 together connected between a DC voltage Vdc1 and the ground. In particular, the resistor R1 is electrically connected with the variable resistor Re1 together, in series, at a node; and an input end/terminal for the analog signal Vain of the analog input driving circuit 230 is connected to the node. As such, the analog signal Vain can be varied via adjusting the value of the variable resistor Re1.
The analog input driving circuit 230 is configured for converting the analog signal Vain into a pulsed signal Vg. The pulsed signal Vg will be supplied to the output circuit 240. The frequency of the pulsed signal Vg varies in conjunction with the analog signal Vain.
The output circuit 240 is configured for converting the pulsed signal Vg into a driving current Ic as an output. The driving current Ic can be outputted into a target load 201 for driving the target load 201. A pulse generation frequency of the pulsed signal Vg can be varied via adjusting the analog signal Vain and thereby indirectly adjusting the driving current Ic. Thus the driving current Ic can be adapted for the target load 201. In the illustrated embodiment, the output circuit 240 includes a metal oxide semiconductor field effect transistor (MOSFET) MOS1 and a current-limiting resistor R2. The MOS1 gate is configured for receiving the pulsed signal Vg, the current-limiting resistor R2 is provided between the MOS1 source and the ground, the MOS1 drain acts as an output terminal of the driving current Ic. Accordingly, the MOS1 gate receives the pulsed signal Vg with an adjustable pulse generation frequency, and the driving current Ic being generated at the MOS1 drain can be adjusted by the variation of the pulse generation frequency of the pulsed signal Vg to meet the requirements of the target load 201.
Referring to FIG. 4, the analog input driving circuit 230 includes a voltage regulator 231, a sawtooth wave generating circuit 232, a clock signal generating circuit 233, and a signal converter 234. The sawtooth wave generating circuit 232 is used to generate a sawtooth wave signal Vsaw. The clock signal generating circuit 233 is used to generate a clock signal Vclk.
In particular, the voltage regulator 231 receives the DC voltage Vdc generated from the rectifier 210 and a reference voltage Vbg can be generated from a band gap circuit (not shown), and the voltage regulator 231 is configured to transform the DC voltage Vdc to another DC voltage Vout with a predetermined level and then provide the DC voltage Vout into the sawtooth wave generating circuit 232, the clock signal generating circuit 233, and the signal converter 234. In addition, the DC voltage Vout also can be provided to other loads as DC voltage supply thereof.
The signal converter 234 is configured for receiving the sawtooth wave signal Vsaw from the sawtooth wave generating circuit 232, the analog signal Vain from the analog input generating circuit 220 and the clock signal Vclk from the clock signal generating circuit 233, and thereby processing the sawtooth wave signal Vsaw, the analog signal Vain and the clock signal Vclk into be the pulsed signal Vg as an output.
Referring to FIG. 5, the voltage regulator 231 includes a relative high voltage MOSFET MOS2, a relative low voltage MOSFET MOS3, a first voltage-dividing resistor R3, a second voltage-dividing resistor R4, a feedback resistor R5, a comparator CMP1, a buffer BUF1, and an adjustable resistor Re2.
The MOSFETs MOS2 and the MOS3 are provided between the DC voltage Vdc and the ground. The first voltage-dividing resistor R3 and the second voltage-dividing resistor R4 are electrically connected, in series, to a node formed between the MOSFET MOS2 source and the MOSFET MOS3 drain. The MOSFET MOS2 drain is configured to receive the DC voltage Vdc, the node formed between the MOSFET MOS2 source and the MOSFET MOS3 drain acts as the output terminal of the DC voltage Vout, the MOSFET MOS3 source is connected to the ground, and the MOSFET MOS3 gate is connected to an output terminal of the buffer BUF1.
The comparator CMP1 includes a negative input terminal, a positive input terminal, and an output terminal. The positive input terminal of the comparator CMP1 is configured to receive the reference voltage Vbg; the output terminal is connected to an input terminal of the buffer BUF1.
One terminal of the feedback resistor R5 is connected to the negative input terminal of the comparator CMP1, the other terminal of the feedback resistor R5 is connected to a node formed between the first voltage-dividing resistor R3 and the second voltage-dividing resistor R4.
One terminal of the adjustable resistor Re2 is connected to the node formed between the first voltage-dividing resistor R3 and the second voltage-dividing resistor R4; the other terminal of the adjustable resistor Re2 is connected to the ground. As such, the DC voltage Vout is controllable due to the adjustable resistor Re2.
Referring to FIG. 6, the signal converter 234 includes a first level converter 2341 and a second level converter 2342. The first level converter 2341 is configured to receive the analog signal Vain and the sawtooth wave signal Vsaw, and then process the analog signal Vain and the sawtooth wave signal Vsaw into a pulse width modulation (PWM) wave signal. The PWM wave signal will be provided into the second level converter 2342. The second level converter 2342 is configured to receive the PWM wave signal and the clock signal Vclk, and then process the PWM wave signal and the clock signal Vclk into a pulsed signal Vg. As an illustrated purpose, the first level converter 2341 is a comparison circuit, and the second level converter 2342 is a NAND gate.
FIG. 7 shows the relationship between time vs. amplitude for five signals in the signal converter 234. A duty-cycle of the PWM wave signal is varied with the variation of the amplitude of the analog signal Vain, and thereby the pulse generation frequency of the pulsed signal Vg is varied correspondingly. As shown in FIG. 7, if a high level of analog signal Vain is higher than a high level of the sawtooth wave signal Vsaw, the PWM wave will not be influenced by the sawtooth wave signal Vsaw. Correspondingly, the driving current Ic generated from the driving apparatus 200 will not be influenced by the sawtooth wave Vsaw at the time when the high level of analog signal Vain is higher than the high level of the sawtooth wave signal Vsaw.
Therefore, the driving current Ic can be adjusted by modulating the pulse generation frequency of the pulsed signal Vg, and the pulse generation frequency of the pulsed signal Vg can be varied by adjusting the analog signal Vain based upon the change of the value of the variable resistor Re1, so the driving apparatus 200 can output an adjustable driving current Ic to meet the different driving currents requirements for different target loads.
It is to be understood that the above-described embodiment is intended to illustrate rather than limit the invention. Variations may be made to the embodiment without departing from the spirit of the invention as claimed. The above-described embodiments are intended to illustrate the scope of the invention and not restrict the scope of the invention.

## Claims

1. A driving apparatus configured for generating an adjustable driving current, comprising:
an analog input generating circuit;
an analog input driving circuit; and
an output circuit;
wherein the analog input generating circuit is electrically connected between a first voltage source and ground, and configured for providing an adjustable analog signal;
the analog input driving circuit is electrically connected between a second voltage source and ground, and configured for converting the analog signal into a pulsed signal;
the output circuit is configured for converting the pulsed signal into a driving current as an output, and the frequency of the pulsed signal can be adjusted via adjusting the analog signal and thereby varying the driving current;
the second voltage source comprises a rectifier, the rectifier being configured for converting an alternating current (AC) voltage into a direct current (DC) voltage; and
wherein the analog input generating circuit comprises a resistor R1 and a variable resistor Re1 together connected between the first voltage source and ground, the resistor R1 is electrically connected to the variable resistor Re1 together, in series, at a node, and the adjustable analog signal is supplied to the analog input driving circuit from the node.

2. The driving apparatus of claim 1, wherein the rectifier is a full-wave rectifier.

3. The driving apparatus of claim 1, wherein the analog input driving circuit comprises a voltage regulator, a sawtooth wave generating circuit, a clock signal generating circuit, and a signal converter; the sawtooth wave generating circuit being configured for generating a sawtooth wave signal; the clock signal generating circuit being configured for generating a clock signal; the voltage regulator being configured for converting the DC voltage provided by the second voltage source into another DC voltage with a predetermined level and then providing the another DC voltage to the sawtooth wave generating circuit, the clock signal generating circuit and the signal converter; the signal converter being configured for processing the sawtooth wave signal, the adjustable analog signal and the clock signal into the pulsed signal as an output.

4. The driving apparatus of claim 3, wherein the voltage regulator comprises a first metal oxide semiconductor field effect transistor (MOSFET), a second MOSFET, a first voltage-dividing resistor, a second voltage-dividing resistor, a feedback resistor, a comparator, a buffer, and an adjustable resistor; the first MOSFET and the second MOSFET being provided between the second voltage source and ground; the first voltage-dividing resistor and the second voltage-dividing resistor being electrically connected, in series, to a node formed between the first MOSFET source and the second MOSFET drain, and the node acting as an output terminal of the another DC voltage; the first MOSFET drain being configured to receive the DC voltage provided by the second voltage source; the second MOSFET source being connected to ground, and the second MOSFET gate being connected to an output terminal of the buffer; the comparator comprising a negative input terminal, a positive input terminal and an output terminal, the positive input terminal being configured to receive a reference voltage, the output terminal being connected to an input terminal of the buffer; one terminal of the feedback resistor being connected to the negative input terminal of the comparator, and the other terminal of the feedback resistor being connected to a node formed between the first voltage-dividing resistor and the second voltage-dividing resistor; and one terminal of the adjusting resistor being connected to the node formed between the first voltage-dividing resistor and the second voltage-dividing resistor, and the other terminal of the adjustable resistor being connected to ground.

5. The driving apparatus of claim 3, wherein the signal converter comprises a first level converter and a second level converter; the first level converter being configured to receive the adjustable analog signal and the sawtooth wave signal, and process the adjustable analog signal and the sawtooth wave signal into a pulse width modulation (PWM) wave signal; and the second level converter being configured to receive the PWM wave signal and the clock signal, and then process the PWM wave signal and the clock signal into the pulsed signal.

6. The driving apparatus of claim 5, wherein the first level converter is a comparison circuit, and the second level converter is a NAND gate.

7. The driving apparatus of claim 1, wherein the output circuit comprises a first MOSFET and a current-limiting resistor, the first MOSFET gate is configured for receiving the pulsed signal, the current-limiting resistor is provided between the first MOSFET source and ground, and the first MOSFET drain acts as an output terminal of the driving current.

8. A method for generating an adjustable driving current, comprising:
providing an adjustable analog signal by an analog input generating circuit, the analog input generating circuit being electrically connected between a first voltage source and ground;
converting the analog signal into a pulsed signal by an analog input driving circuit, the analog input driving circuit being electrically connected between a second voltage source and ground, wherein a pulse generation frequency of the pulsed signal can be adjusted via adjusting the analog signal, and the second voltage source comprises a rectifier, the rectifier being configured for converting an alternating current (AC) voltage into a direct current (DC) voltage, wherein the analog input generating circuit comprises a resistor R1 and a variable resistor Re1 together connected between the first voltage source and ground, the resistor R1 is electrically connected to the variable resistor Re1 together, in series, at a node, and the adjustable analog signal is supplied to the analog input driving circuit from the node; and
converting the pulsed signal into a driving current as an output by an output circuit, wherein the driving current can be adjusted corresponding to the variation of frequency of the pulsed signal.

9. A driving apparatus configured for generating an adjustable driving current, comprising:
an analog input generating circuit;
an analog input driving circuit; and
an output circuit;
wherein the analog input generating circuit is electrically connected between a first voltage source and ground, and is configured for providing an adjustable analog signal;
the analog input driving circuit is electrically connected between a second voltage source and ground, and is configured for converting the analog signal into a pulsed signal, and comprises a voltage regulator, a sawtooth wave generating circuit, a clock signal generating circuit, and a signal converter; the sawtooth wave generating circuit is configured for generating a sawtooth wave signal; the clock signal generating circuit is configured for generating a clock signal; the voltage regulator is configured for converting a direct current (DC) voltage provided by the second voltage source into another DC voltage with a predetermined level and then providing the another DC voltage to the sawtooth wave generating circuit, the clock signal generating circuit and the signal converter; and the signal converter is configured for processing the sawtooth wave signal, the adjustable analog signal and the clock signal into the pulsed signal as an output; and
the output circuit is configured for converting the pulsed signal into a driving current as an output, wherein the frequency of the pulsed signal can be adjusted via adjusting the analog signal and thereby varying the driving current.

10. The driving apparatus of claim 9, wherein the second voltage source comprises a rectifier, the rectifier being configured for converting an alternating current (AC) voltage into the DC voltage.

11. The driving apparatus of claim 10, wherein the rectifier is a full-wave rectifier.

12. The driving apparatus of claim 9, wherein the analog input generating circuit comprises a resistor R1 and a variable resistor Re1 together connected between the first voltage source and ground, the resistor R1 is electrically connected with the variable resistor Re1together, in series, at a node, and the adjustable analog signal is supplied to the analog input driving circuit from the node.

13. The driving apparatus of claim 9, wherein the voltage regulator comprises a first metal oxide semiconductor field effect transistor (MOSFET), a second MOSFET, a first voltage-dividing resistor, a second voltage-dividing resistor, a feedback resistor, a comparator, a buffer, and an adjustable resistor; the first MOSFET and the second MOSFET being provided between the second voltage source and ground; the first voltage-dividing resistor and the second voltage-dividing resistor being electrically connected, in series, to a node formed between the first MOSFET source and the second MOSFET drain, and the node acting as an output terminal of the another DC voltage; the first MOSFET drain being configured to receive a DC voltage provided by the second voltage source; the second MOSFET source being connected to ground, and the second MOSFET gate being connected to an output terminal of the buffer; the comparator comprising a negative input terminal, a positive input terminal, and an output terminal, the positive input terminal being configured to receive a reference voltage, and the output terminal being connected to an input terminal of the buffer; one terminal of the feedback resistor being connected to the negative input terminal of the comparator, and the other terminal of the feedback resistor being connected to a node formed between the first voltage-dividing resistor and the second voltage-dividing resistor; and one terminal of the adjusting resistor being connected to the node formed between the first voltage-dividing resistor and the second voltage-dividing resistor, and the other terminal of the adjustable resistor being connected to ground.

14. The driving apparatus of claim 9, wherein the signal converter comprises a first level converter and a second level converter; the first level converter being configured to receive the adjustable analog signal and the sawtooth wave signal, and process the adjustable analog signal and the sawtooth wave signal into a pulse width modulation (PWM) wave signal; and the second level converter being configured to receive the PWM wave signal and the clock signal, and then process the PWM wave signal and the clock signal into the pulsed signal.

15. The driving apparatus of claim 14, wherein the first level converter is a comparison circuit, and the second level converter is a NAND gate.

16. The driving apparatus of claim 9, wherein the output circuit comprises a first MOSFET and a current-limiting resistor, the first MOSFET gate is configured for receiving the pulsed signal, the current-limiting resistor is provided between the first MOSFET source and ground, and the first MOSFET drain acts as an output terminal of the driving current.