# Patent

## Title
Four-stage circuit architecture for detecting pulsed signals

## Abstract

An electrical circuit includes a photodiode that receives a light signal from a light source and generates a photocurrent signal, a trans-impedance amplifier that amplifies the photocurrent signal and generates a low noise signal, and a high pass filter that converts the low noise signal into an alternating current (AC) signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive amplitude and the negative amplitude. The electrical circuit also includes a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period. The electrical circuit further includes at least one analog-to-digital converter that receives the positive and negative integrated values.

## Background
FIELD OF THE DISCLOSURE
This disclosure relates in general to the field of electronic devices and, more particularly, to a circuit architecture for photodiodes.
BACKGROUND
A photodiode is a type of photo-detector capable of converting light into current or voltage. Generally, the photodiode is a semiconductor device with a PIN or PN connection structure. When a photon of sufficient energy strikes the photodiode, it excites electrons, creating free electrons and positively charged electron holes. The holes move toward the anode, and electrons toward the cathode, and a photocurrent is produced proportional to the amount of incident light on the photodiode.
SUMMARY OF THE DISCLOSURE
An example electrical circuit is provided and includes a photodiode that receives a light signal from a light source and generates a photocurrent signal, a trans-impedance amplifier that amplifies the photocurrent signal and generates a low noise signal, and a high pass filter that converts the low noise signal into an alternating current (AC) signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive amplitude and the negative amplitude. The electrical circuit also includes a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period. The electrical circuit further includes at least one analog-to-digital converter that receives the positive and negative integrated values.
In a specific embodiment, the electrical circuit is coupled to a photoplethysmography system. Light from the light source reflects off, or transmits through an organ before reaching the photodiode, such that the photocurrent signal from the photodiode can provide an indication of a measurement of the organ. The photoplethysmography system does not have to include a light blocking enclosure to keep out ambient light for accurate measurements.
A system is also provided that includes a plurality of photodiodes that receive a light signal from a light source, with each one of the photodiodes generates a photocurrent signal, a plurality of trans-impedance amplifiers, in which each trans-impedance amplifier amplifies the photocurrent signal from one of the photodiodes and generates a low noise signal, a plurality of high pass filters, in which each high pass filter converts the low noise signal from each trans-impedance amplifier into an AC signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive amplitude and the negative amplitude and a plurality of integrators. Each integrator includes a positive integrating amplifier that receives the positive amplitude of the AC signal from each high pass filter and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal from each high pass filter and generates a negative integrated value over the integration period. The system further includes an ADC that receives the positive and negative integrated values from the plurality of integrators.



BRIEF DESCRIPTION OF THE DRAWINGS
To provide a more complete understanding of the present disclosure and features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying figures, wherein like reference numerals represent like parts, in which:
FIG. 1 is a simplified circuit diagram of a circuit architecture for photodiodes in accordance with one embodiment;
FIG. 2 is a simplified diagram illustrating example details of measurements associated with the circuit architecture according to an embodiment;
FIG. 3 is a simplified diagram of other example details of measurements associated with the circuit architecture according to an embodiment;
FIG. 4 is a simplified diagram of yet other example details of measurements associated with the circuit architecture according to an embodiment;
FIG. 5 is a simplified diagram of an example detail of an application associated with the circuit architecture according to an embodiment;
FIG. 6 is a simplified block diagram of another embodiment of the circuit architecture;
FIG. 7 is a simplified block diagram of example details of an application of an embodiment of the circuit architecture; and
FIG. 8 is a simplified circuit diagram of another embodiment of the circuit architecture.



DETAILED DESCRIPTION
The present disclosure provides for measurement of photocurrent signal from a light source, which may be synchronized (e.g., specifically modulated). Common photodiode circuits (e.g., photodiode amplifiers) are typically configured for one of low noise, wide bandwidth, and high dynamic range. Such circuits do not generally provide all three characteristics (low noise, wide bandwidth, and high dynamic range) simultaneously. Even if some circuits do provide all three characteristics, such circuits may require high power, or may not provide for high signal extraction of a target light source (especially in the presence of a high amount of ambient light, which is considered an interference and acts like noise), or may not be flexible to accommodate different sampling modes or multiple channels.
For example, Burr Brown's OPT201 integrated photodiode and amplifier provides low noise operation, and rejects ambient light (when combined with a direct current (DC) restoration circuit). However, it does not provide high GBW, and operates at high power. In another example, New Focus Inc.'s 1601 and 1611 high-speed photo-receivers have large gain bandwidth (GBW), low noise, high drive capability and large dynamic range to enable wide bandwidth low-noise detection of signals distributed over fiber-optic cables, or found in applications such as high resolution spectroscopy, fiber-optic sensors, and optical metrology. The photo-receivers consist of a silicon or InGaAs PIN photodiode followed by a low-noise amplifier, coupled to alternating current (AC). However, these photo-receives are not capable of sampling multiple channels, and require high DC power supply.
Turning to FIG. 1, FIG. 1 is a simplified block diagram of electrical circuit 10 that implements circuit architecture for photodiodes. Electrical circuit 10 is configured to simultaneously provide low-noise and low-power consumption (among other features) while avoiding interference from uncorrelated light sources (e.g., sunlight, background light, ambient light) in the environment. Furthermore, the circuit architecture is configured to have high dynamic range that is suitable for use in the presence of a strong light source such as sunlight. The circuit architecture can be extended to multiple channels, for example, in applications that involve reading multiple photodiode signals concurrently.
According to various embodiments, electrical circuit 10 can provide the following features substantially simultaneously: low noise; high dynamic range; high rejection of uncorrelated light sources or ambient light; high signal extraction of a locked or target light source; low power operation; simultaneous sampling of multiple channels for analog-to-digital conversion, which can improve ambient light rejection (ALR) in many cases and allow the use of relatively slower and more precise analog-to-digital converters (ADCs); and flexibility for different sampling modes.
According to a specific embodiment, electrical circuit 10 may comprise a photodiode 12 that receives light from a light source 14. Light source 14 may or may not be synchronized to facilitate the operations described herein. In a specific embodiment, light source 14 may be a synchronized light source, modulated to a suitable frequency with an appropriate microprocessor or similar electrical component. The photocurrent signal from photodiode 12 can include a single pulse of low duty cycle or a multiple pulse train of low duty cycle (e.g., depending on the duty cycle of light source 14). In some embodiments, light source 14 may be modulated by an integrated circuit (not shown) coupled to electrical circuit 10.
According to various embodiments, electrical circuit 10 can comprise four stages 16, 18, 20, and 22. Stage 16 can include a trans-impedance amplifier, which may amplify the photocurrent signal from photodiode 12 and generate a low noise signal. The trans-impedance amplifier can also convert the photocurrent signal to a voltage at the output. Stage 16 includes a feedback capacitance 24 (Cf) in parallel with a feedback resistor 26 (Rf) connected to an operational amplifier (op-amp) 28 in an R-C feedback loop, for example, to reduce noise and stabilize the circuit.
Any light source 14 (including DC light) whose bandwidth is within the amplifier bandwidth may be amplified by amplifier 28. Generally, capacitance of photodiodes can affect noise gain based on the relative value of the capacitance to resistance value Rf of feedback resistor 26 and capacitance value Cf of feedback capacitor 24. Configuring stage 16 as a first stage can provide increased flexibility to minimize excess noise gain. In a general sense, two dominant noise sources in electrical circuit 10 include Johnson noise of feedback resistor 26 and amplifier 28's input voltage noise. To reduce Johnson noise, resistance value Rf of feedback resistor 26 can be chosen to be as large as possible consistent with the largest DC photocurrent that is expected for a given arrangement of photodiode 12 and other components. Such a configuration may provide minimum amplifier noise consistent with the total DC photocurrent. Capacitance value Cf of feedback capacitor 24 can be chosen to change the bandwidth of the photocurrent signal (which may be of the order of approximately 1/τ, where τ is the input pulse duration) as desired. Stage 16 can also include a low pass filter (LPF) 30 that additionally filters out high frequency noise in the photocurrent signal. LPF 30 can also increase the duration of pulses of the photocurrent signal (which may coincide with the pulse duration of the (synchronized) light source 14). The frequency threshold of LPF 30 can be configured as desired based on particular needs depending on the expected (or measured) noise characteristics.
Stage 18 may comprise a high pass filter (active or passive) including an AC power source 32 (with frequency fac) and a capacitor that provides AC coupling. Stage 18 can eliminate low frequencies (e.g., remove DC) and allow high gain to be provided in subsequent stages. AC input 32 that can change the DC component of the photocurrent signal to AC, thereby providing a zero cross-over point where the amplitude of the photocurrent signal changes from positive to negative. Stage 18 can eliminate some of the noise components from stage 16 and high frequency noise and lower frequency photocurrents from ambient light (or uncorrelated light sources).
In some embodiments, a square pulse shaped signal from light source 14 may be modified by the filtering action of LPF 30 and stage 18 to eliminate low frequencies. The corner frequencies (e.g., boundary in the frequency response at which energy flowing through begins to reduce (attenuate or reflect)) of stages 16 and 18 may be chosen to maximize signal measurement and provide ALR. For example, the corner frequency of the high pass filter of stage 18 can be set as large as 0.5/τ. The choice can also be influenced by the integration time chosen in next stage 20.
Stage 20 may comprise integration and demodulation. A single pole changeover switch 34 may switch the incoming signal based on a clock from timer 36. The clock cycle of timer 36 may be configured to match the zero cross-over point of the photocurrent signal from stage 18. When the zero cross-over point occurs, switch 34 may switch from integrating amplifier 38(1) to integrating amplifier 38(2). Two integrating amplifiers 38(1) and 38(2) may be used to integrate in succession on the positive portion of the signal from stage 18 when switch 34 is connected to the positive integrating amplifier 38(1) and on the negative portion of the signal from stage 18 when switch 34 is connected to the negative integrating amplifier 38(2). Each of positive integrating amplifier 38(1) and negative integrating amplifier 38(2) may include a capacitor Cint configured to enable the operational amplifier therein to operate as an integrator. In some embodiments, switches SW2 may be used to reset positive integrating amplifier 38(1) and negative integrating amplifier 38(2), for example, after every conversion cycle or after multiple integration phases.
Each of positive integrating amplifier 38(1) and negative integrating amplifier 38(2) (generally referred to individually as integrator 38) acts like a storage element that produces an output voltage output proportional to the integral of its input current (converted from voltage output of the previous stage) over time. In other words, the magnitude of the output voltage is determined by the length of time (integration period tint) during which an input voltage is present as the current through the feedback loop (comprising Cint) charges or discharges capacitor Cint. The circuit operates by passing a current that charges capacitor Cint over time from the input current of stage 18. When the input current of stage 18 is firstly applied to the integrator, the feedback capacitor Cint begins to charge and the output voltage is determined by the total charge (which is the integral of the input current over time).
Positive integrating amplifier 38(1) may generate a positive integrated value 40 (Q+), which is the integral over time of the positive amplitude of the alternating current signal from stage 18, and negative integrating amplifier 38(2) may generate a negative integrated value 42 (Q−), which is the integral over time of the negative amplitude of the alternating current signal from stage 18. The integration period tint can be configured over a wide range based on particular needs. The start of the integration cycle may be controlled by timer 36 in a microcomputer, a simple programmable circuit, or other suitable component. The gain of the amplifier can be chosen to optimize conversion by an analog-to-digital convertor (ADC) 44 (as DC and low frequency components of ambient light are largely removed after stage 18) at stage 22. At the end of the positive and negative integration cycle, substantially all photocurrents in the integration period tint may be integrated and the voltage may be held at the outputs of stage 20. The voltages may be subtracted either before conversion by a difference amplifier or converted by ADC 44 and then subtracted digitally.
Mathematically, the integration and subtraction are similar to a low pass filter and a “lock-in” filter to further remove noise artifacts of the ambient light while amplifying the photocurrent signal. For example, the phase of switch 34 can be adjusted to provide “lock-in” functionality to a signal originating from a distant system. Assume, merely for illustrative purposes, and not as a limitation, that a distant light source produces a train of N pulses repeating at a rate R. Timer 36 can be configured to lock to the phase of the clock that generates the N pulses. Thus a phase lock loop can be constructed to measure the light intensity of the distant light source. Positive integrating amplifier 38(1) and negative integrating amplifier 38(2) can together provide increased ALR. Outputs 40 and 42 may be fed to ADC (or ADC integrated with a micro-controller) 44 at stage 22 to perform further operations.
ADC 44 can read the output voltage of stage 20 and a controller therein can reset integrators 38(1) and 38(2), for example, by momentarily closing SW2, to start a new integration cycle. The reset can occur at the end of each pulse or at the end of a group of pulses. The voltage at stage 20 may represent a signal charge deposited at photodiode 12 in addition to charge from substantially all ambient interference. In an example embodiment, the pulses may be added together thereby increasing signal strength and reducing noise and interference digitally after ADC 44. In another example embodiment, the pulses may be added in an analog domain until SW2 resets integrating capacitors Cint. Embodiments of electrical circuit 10 can permit extension of the circuit architecture to ultra short pulses, for example in nanosecond and picosecond domain, without substantially increasing the speed of ADC 44. High dynamic range may be facilitated as digital additions of pulses can be carried out over many more pulses, almost without limit, than any analog addition on the integrating capacitors Cint would permit.
According to various embodiments, input photocurrent may be converted to voltage at stage 16. Any frequency content of the voltage signal may be shaped by the band pass filtering functions at state 18. The output voltage of stage 18 may be converted back to current, for example, using a suitable resistor, and integrated with capacitor Cint over time tint over positive and negative cycles. At least a portion of the behavior of electrical circuit 10 may be indicated by the following equations:



  
    
      V
      TIA
    
    =
    
      
        i
        p
      
      ×
      
        R
        f
      
    
  




  
    
      V
      ac
    
    =
    
      
        BPF
        ⁡
        
          (
          
            f
            filt
          
          )
        
      
      ×
      
        V
        TIA
      
    
  




  
    
      V
      int
    
    =
    
      
        (
        
          
            V
            ac
          
          
            R
            in
          
        
        )
      
      ×
      
        (
        
          
            C
            int
          
          ×
          
            t
            int
          
        
        )
      
    
  



where VTIA is the output voltage at stage 16; ip is the photovoltaic current; Rf is the resistance of feedback resistor 26; Vac is the output voltage at stage 18; BPF(ffilt) is a bandpass filter shaping function of stage 18; Vint is the output voltage at stage 20; Rin is the resistance of a resistor (not shown) at stage 20; Cint is the capacitance at stage 20; and tint is the integration time.

For example, Rf may be chosen to prevent saturation at stage 16 with a high amount of low frequency light, such as sunlight. The corner frequencies can be chosen to minimize interference while transmitting most of the signal pulse at stage 18. Moreover, the choice of Rin and Cint can allow signal gain at stage 20 to match ADC input range at stage 22. Further, multiple cycles of analog integration over many pulses with digital integration at ADC 44 can allow a large dynamic range.
In some embodiments, an intense short light pulse may perform better for low power operation as the system of amplifiers and ADC can be powered down between the pulses. Also, for the same net power consumed by synchronous light source 14, signal-to-noise-ratio (SNR) can be maximized by using the shortest possible pulse that can be produced by a driver circuit. (The shortest possible pulse may be limited by the peak current output available.) Electrical circuit 10 may be dynamically or programmatically configured in some embodiments, for example, by changing the Cf, Rf, Cint, and other passive component values and corner frequency values as desired.
In some embodiments, the low frequency (e.g., DC) component of the photocurrent signal may be measured by directly connecting stage 16 to the input of ADC 44. Alternatively, the low frequency component may be measured by connecting stage 16 to either positive integrating amplifier 38(1) or negative integrating amplifier 38(2) of stage 20. In embodiments with low levels of ambient light, one of positive and negative integrating amplifiers 38(1) and 38(2). respectively, may be connected directly to photodiode 12, bypassing stages 16 and 18.
According to various embodiments, at least some components of stages 16, 18, and 20 are programmable (e.g., component values adjustable according to user specifications) after electrical circuit has been implemented in a physical form. The component values may be programmable manually, or by a suitable computing device or controller. For example, capacitance Cf of feedback capacitor 24, resistance Rf of feedback resistor 26; bandpass filter shaping function BPF(ffilt), resistance Rin, capacitance Cint etc. can be programmed according to the application in which electrical circuit 10 is to be used. Thus, the same physical representation of electrical circuit 10 may have a first set of component values in one application (e.g., photoplethysmography system used in controlled ambient light) and a different, second set of component values in a different application (e.g., wireless sensor used in uncontrolled ambient light).
Turning to FIG. 2, FIG. 2 is a simplified diagram illustrating an example signal chart 50 according to an embodiment of electrical circuit 10. Merely for example purposes, and not as a limitation, the pulse duration τ was set at 1 μs, and the high pass filter corner frequency (of stage 18) was set at 300 kHz or 0.3/τ. The output of the stages was referred to the input to allow for easy comparison. Input photocurrent pulse 52 from synchronized light source may result in a photocurrent signal 54, illustrated after stages 16 and 18. Signal 54 indicates an AC signal, with a zero cross-over point. The zero cross-over point may set the integrating cycle duration tint. Positive and negative integration cycles may be denoted by a line 56, which also has a zero cross-over point coinciding with the zero cross-over point of signal 54.
Turning to FIG. 3, FIG. 3 is a simplified diagram illustrating an example signal chart 60 according to an embodiment of electrical circuit 10. Input photocurrent pulse 62 from synchronized light source may result in a photocurrent signal 64, illustrated after stages 16 and 18. Signal 64 is an AC signal, with a zero cross-over point. The zero cross-over point may set the integrating cycle duration tint. Positive and negative integration cycles may be denoted by the line 66, which also has a zero cross-over point coinciding with the zero cross-over point of signal 64. Input photocurrent signal 62 may be generated as pulses (e.g., with a short 1 μs pulse). Each pulse of signal 64 may be shaped by the action of stages 16 and 18. Positive and negative integration cycles are applied to each pulse in the train of pulses. The separation ts between pulses may be configured based on the settling time or to minimize any effect of particularly dominant frequency components (if any) from ambient light.
Turning to FIG. 4, FIG. 4 is a simplified diagram illustrating a graph 80 showing input charge over frequency of interfering ambient light. Graph 80 illustrates the suppression of ambient light according to electrical circuit 10. Assume, merely for illustrative purposes, and not as a limitation, that a light source in the environment has a frequency f. Further assume that the phase of the ambient light is somehow synchronized to produce worst case interference at each possible frequency of the ambient light (indicated along the x-axis). The measured amplitude of the photocurrent signal produced at that frequency can be reduced by the action of all four stages 16, 18, 20 and 22. In the case of a train of multiple pulses, suppression may be increased even further.
Graph 80 was generated using 16 pulses, and the input referred integrated current (after stage 22) was calculated as charge on the Y-axis. According to embodiments of electrical circuit 10, ALR of almost a factor of 100 at frequencies below 50 kHz may be observed. Many ambient light sources such as fluorescent lamps and light emitting diode (LED) lights have components at low frequencies. Very low frequencies such as 120 Hz may be suppressed by factors exceeding 1000 and DC light may be completely blocked.
It may be noted that embodiments of electrical circuit 10 may reject electrical noise injected at photodiode 12 similar to rejection of photocurrents generated by ambient light. Indeed, components of electrical circuit 10 may not distinguish between photocurrents or electromagnetic interference (EMI) or any other electrical noise injected into the circuit, facilitating robustness in the presence of both electrical and optical interference.
Turning to FIG. 5, FIG. 5 is a simplified diagram illustrating an example application 90 of electrical circuit 10 as used in a photoplethysmography system 92. A photoplethysmograph is a device used to optically measure changes in the effective light transmission or reflectance of an organ. Examples of photoplethysmography systems include pulse oximeters, cardiovascular monitors, and respiration detectors. Application 90 illustrated in the FIGURE can include a pulse oximeter, although electrical circuit 10 may be implemented in any other type of photoplethysmography systems as well, within the broad scope of the embodiments.
The pulse oximeter of application 90 may include photodiode 12 and synchronous light source (e.g., red and infrared light emitting LED) connected to photoplethysmography system 92, which can include electrical circuit 10 and other components, based on the particular application need. The pulse oximeter may be attached to, or otherwise placed in proximity with an organ (e.g., fingertip) 94 (e.g., of the patient whose pulse is being monitored). Light emitted by synchronous light source 14 may be partially reflected, transmitted, absorbed, and/or scattered by the organ (e.g., skin, surrounding tissues, and the blood at the fingertip) before it reaches photodiode 12. The photocurrent signal from photodiode 12 can provide a measurement of the organ, for example, indicative of pulse rate, or oxygen content, etc.
Currently available pulse oximeters and other photoplethysmography systems use caps, light proof enclosures, and other such devices to prevent ambient/background light from generating noise in the photoplethysmography systems. With electrical circuit 10, such light blocking enclosures (e.g., caps, boxes, etc.) need not be used, as electrical circuit 10 includes noise reduction capabilities sufficient to overcome ambient and other background light noise. Moreover, because of the noise reduction characteristics of electrical circuit 10, and its consequent reduced sensitivity to ambient and DC light, the distance between synchronous light source 14 and photodiode 12 may be configured based on convenience factors, rather than noise reduction.
Turning to FIG. 6, FIG. 6 is a simplified block diagram illustrating another embodiment of electrical circuit 10. Multiple (e.g., four) photodiodes 12 may be connected to ADC 44, for example, to measure light intensity from four different spatial orientations. Each photodiode 12 may be connected to separate stages 16, 18 and 20, with all photodiodes 12 sharing common ADC 44. Each of stages 20 may provide a positive integrated value and a negative integrated value to ADC 44. ADC 44 may sample the outputs from a specific stage 20 before proceeding to the next stage 20, and so on, until it samples the outputs from substantially all stage 20 within a certain time interval. The time interval may be configured according to the power cycle of light source 14, such that ADC 44 completes sampling the outputs from all stage 20 before light source 14 powers down.
Moreover, the output from stage 20 can remain constant after the integration phase until reset, ADC 44 can be multiplexed to sample each of the outputs without compromising performance. Thus embodiments of electrical circuit 10 can allow a relatively lower cost low speed ADC with low frequency switching between channels can be used without compromising performance. Such circuit architecture can be used in specialized photodiode applications, for example, that use lateral photodiodes, quad detectors, or optical angle sensors. With the circuit architecture of embodiments of electrical circuit 19, pulse width of the input light and substantially all components of stages 16, 18, and 20 can be configured with nanosecond pulses without substantially affecting ADC 44's sample rate.
Turning to FIG. 7, FIG. 7 is a simplified diagram illustrating an example application 100 of electrical circuit 10. Smartphone 102 may be configured to detect gestures of a user 104 based on optical signals (rather than touch). Multiple photodiodes 12 may be configured on Smartphone 102 (e.g., on its display screen). Synchronous light source 14 may be provided on Smartphone 102 in some embodiments. Light from light source 14 may be reflected off user 104, and may be measured by photodiodes 12. The amount of light arriving at each photodiode 12 may depend on the particular gesture (hand, finger or body position) of user 104. When user 104 changes the gesture, the amount of light on photodiodes 12 may also change. This change may be calculated by a suitably calibrated microcontroller to detect the gesture and derive a suitable meaning thereof. With electrical circuit 10 implemented in such application 100, the sensitivity of the system to the background light and other extraneous light may be reduced without compromising the performance.
Turning to FIG. 8, FIG. 8 is a simplified circuit diagram illustrating another example configuration of an embodiment of electrical circuit 10. Instead of ADC 44, a differential amplifier 110 may be used in stage 22. Differential amplifier 110 may compute a difference between outputs 40 and 42 and send the difference to ADC 44 or other suitable component (e.g., microprocessor, digital signal processor, etc.). Differential amplifier 110 may also amplify the difference in outputs 40 and 42, and thereby increase accuracy of measurement based on particular needs.
Note that in this Specification, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment”, “example embodiment”, “an embodiment”, “another embodiment”, “some embodiments”, “various embodiments”, “other embodiments”, “alternative embodiment”, and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments.
In one example embodiment, electrical circuit 10 of the FIGURES may be implemented on a motherboard of an associated electronic device. The motherboard can be a general circuit board that can hold various components of the internal electronic system of the electronic device and, further, provide connectors for other peripherals. More specifically, the motherboard can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processors (inclusive of digital signal processors, microprocessors, supporting chipsets, etc.), memory elements, etc. can be suitably coupled to the motherboard based on particular configuration needs, processing demands, computer designs, etc. Other components such as external storage, additional sensors, controllers for audio/video display, and peripheral devices may be attached to the motherboard as plug-in cards, via cables, or integrated into the motherboard itself.
In another example embodiment, electrical circuit 10 of the FIGURES may be implemented as stand-alone modules (e.g., a device with associated components and circuitry configured to perform a specific application or function) or implemented as plug-in modules into application specific hardware of electronic devices. Note that particular embodiments of the present disclosure may be readily included in a system on chip (SOC) package, either in part, or in whole. An SOC represents an IC that integrates components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio frequency functions: all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip-module (MCM), with a plurality of separate ICs located within a single electronic package and configured to interact closely with each other through the electronic package. In various other embodiments, the amplification functionalities may be implemented in one or more silicon cores in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and other semiconductor chips.
It is also imperative to note that all of the specifications, dimensions, and relationships outlined herein (e.g., the number of processors and memory elements, logic operations, etc.) have only been offered for purposes of example and teaching only. Such information may be varied considerably without departing from the spirit of the present disclosure, or the scope of the appended claims. The specifications apply only to one non-limiting example and, accordingly, they should be construed as such. In the foregoing description, example embodiments have been described with reference to particular processor and/or component arrangements. Various modifications and changes may be made to such embodiments without departing from the scope of the appended claims. The description and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.
Note that with the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electrical components. However, this has been done for purposes of clarity and example only. It should be appreciated that the system can be consolidated in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, and elements of the FIGURES may be combined in various possible configurations, all of which are clearly within the broad scope of this Specification. In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows by only referencing a limited number of electrical elements. It should be appreciated that electrical circuit 10 of the FIGURES and its teachings are readily scalable and can accommodate a large number of components, as well as more complicated/sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of electrical circuit 10 as potentially applied to a myriad of other architectures.
Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the appended claims. In order to assist the United States Patent and Trademark Office (USPTO) and, additionally, any readers of any patent issued on this application in interpreting the claims appended hereto, Applicant wishes to note that the Applicant: (a) does not intend any of the appended claims to invoke paragraph six (6) of 35 U.S.C. section 112 as it exists on the date of the filing hereof unless the words “means for” or “step for” are specifically used in the particular claims; and (b) does not intend, by any statement in the specification, to limit this disclosure in any way that is not otherwise reflected in the appended claims.

## Claims

1. An electrical circuit, comprising:
a photodiode that receives a light signal from a light source and generates a photocurrent signal;
a first stage comprising a trans-impedance amplifier that amplifies the photocurrent signal and generates a low noise signal;
a second stage comprising a high pass filter that converts the low noise signal into an alternating current (AC) signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive amplitude and the negative amplitude;
a third stage comprising:
a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period; and
a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period; and

a fourth stage comprising at least an analog-to-digital converter (ADC) that receives the positive and negative integrated values.

2. The electrical circuit of claim 1, wherein the trans-impedance amplifier includes an operational amplifier with a feedback loop comprising a feedback capacitor and a feedback resistor and a low pass filter.

3. The electrical circuit of claim 2, where at least some components of the first stage, the second stage, and the third stage are programmable.

4. The electrical circuit of claim 1, wherein the light source is a synchronous light source.

5. The electrical circuit of claim 4, wherein a pulse of the synchronized light source has a duration of τ, a bandwidth of the second stage is of the order of approximately 1/τ, and a corner frequency of the high pass filter is set as high as 0.5/τ.

6. The electrical circuit of claim 1, wherein the second stage includes an AC source and a capacitor that provides AC coupling.

7. The electrical circuit of claim 1, wherein the third stage includes a switch configured to change from the positive integrating amplifier to the negative integrating amplifier at the occurrence of the zero cross-over point.

8. The electrical circuit of claim 7, wherein the switching action of the switch is configured by a timer.

9. The electrical circuit of claim 8, wherein the timer is configured to provide a clock synchronized with a frequency of the light source.

10. The electrical circuit of claim 1, wherein the negative integrated value is subtracted from the positive integrated value by the ADC.

11. The electrical circuit of claim 1, wherein the fourth stage includes a differential amplifier that subtracts the negative integrated value from the positive integrated value.

12. The electrical circuit of claim 1, wherein the electrical circuit can substantially simultaneously provide: low-noise, high dynamic range, high ambient light rejection, high signal extraction of the light source, low-power operation, and different sampling modes.

13. The electrical circuit of claim 12, wherein the electrical circuit can further substantially simultaneously provide sampling of multiple channels for analog-to-digital conversion.

14. The electrical circuit of claim 1, further comprising a photoplethysmography system connected thereto.

15. The electrical circuit of claim 14, wherein light from the light source reflects off, or transmits through an organ before reaching the photodiode, such that the photocurrent signal from the photodiode can provide an indication of a measurement of the organ.

16. The electrical circuit of claim 14, wherein the photoplethysmography system does not have to include a light blocking enclosure to keep out ambient light for accurate measurements.

17. A system comprising:
a plurality of photodiodes that receive a light signal from a light source, wherein each one of the photodiodes generates a photocurrent signal;
a plurality of trans-impedance amplifiers, wherein each trans-impedance amplifier amplifies the photocurrent signal from one of the photodiodes and generates a low noise signal;
a plurality of high pass filters, wherein each high pass filter converts the low noise signal from each trans-impedance amplifier into an AC signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive amplitude and the negative amplitude;
a plurality of integrators, wherein each integrator comprises:
a positive integrating amplifier that receives the positive amplitude of the AC signal from each high pass filter and generates a positive integrated value over an integration period; and
a negative integrating amplifier that receives the negative amplitude of the AC signal from each high pass filter and generates a negative integrated value over the integration period; and

an ADC that receives the positive and negative integrated values from the plurality of integrators.

18. The system of claim 17, wherein the ADC is a low speed ADC having a total sampling time consistent with a power cycle of the light source.

19. The system of claim 17, wherein the ADC is a high speed ADC that samples the outputs from each integrator at high frequency.

20. The system of claim 17, wherein the system is coupled to a Smartphone configured to detect gestures of a user based on optical signals.