# Patent

## Title
Array-reader based magnetic recording systems with quadrature amplitude modulation

## Abstract

A magnetic recording system includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, a quadrature amplitude modulator operable to combine the analog signals to yield a quadrature amplitude modulated signal, a quadrature amplitude demodulator operable to yield a plurality of demodulated signals from the quadrature amplitude modulated signal corresponding to each channel of the array, and a joint equalizer operable to filter the plurality of demodulated signals to yield an equalized output.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
The present application claims priority to (is a non-provisional of) U.S. Pat. App. No. 61/872,161, entitled “Array-Reader Based Magnetic Recording Systems With Quadrature Amplitude Modulation”, and filed Aug. 30, 2013 by Mathew et al, the entirety of which is incorporated herein by reference for all purposes.


FIELD OF THE INVENTION
Various embodiments of the present invention provide systems and methods for processing data, and more particularly to systems and methods for multiplexing signals from an array-reader in a magnetic recording system.
BACKGROUND
In a typical magnetic storage system, digital data is stored in a series of concentric circular tracks along a storage medium. Data is written to the medium by positioning a read/write head assembly over the medium at a selected location as the storage medium is rotated, and subsequently passing a modulated electric current through the head assembly such that a corresponding magnetic flux pattern is induced in the storage medium. To retrieve the stored data, the head assembly is positioned anew over the track as the storage medium is rotated. In this position, the previously stored magnetic flux pattern induces a current in the head assembly that can be converted to the previously recorded digital data.
BRIEF SUMMARY
Some embodiments of the present invention provide a magnetic recording system having an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, a quadrature amplitude modulator operable to combine the analog signals to yield a quadrature amplitude modulated signal, a quadrature amplitude demodulator operable to yield a plurality of demodulated signals from the quadrature amplitude modulated signal corresponding to each channel of the array, and a joint equalizer operable to filter the plurality of demodulated signals to yield an equalized output.
This summary provides only a general outline of some embodiments according to the present invention. Many other embodiments of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several figures to refer to similar components. In some instances, a sub-label consisting of a lower case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components.
FIG. 1 depicts a magnetic storage system including an array-reader with quadrature amplitude modulation and demodulation in accordance with some embodiments of the present invention;
FIG. 2 depicts an array reader magnetic recording system with quadrature amplitude modulation and digital demodulator in accordance with some embodiments of the present invention;
FIG. 3 depicts an array reader magnetic recording system with quadrature amplitude modulation and analog demodulator in accordance with some embodiments of the present invention;
FIG. 4A depicts a preamplifier with quadrature amplitude modulation in accordance with some embodiments of the present invention;
FIG. 4B depicts a frequency domain chart of multiple reader channels multiplexed by the quadrature amplitude modulation in accordance with some embodiments of the present invention;
FIG. 5 depicts a read channel with quadrature amplitude demodulator in accordance with some embodiments of the present invention;
FIG. 6 depicts a carrier synchronizer in accordance with some embodiments of the present invention;
FIG. 7 depicts a quadrature amplitude demodulator in accordance with some embodiments of the present invention; and
FIG. 8 depicts a flow diagram of an operation to transmit data from an array-reader in a magnetic recording system in accordance with some embodiments of the present invention.



DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention are related to systems and methods for multiplexing signals from an array-reader in a magnetic recording system using quadrature amplitude modulation (QAM). In an array-reader, an array of read heads are provided, yielding multiple data streams. The multiple data streams can be used in some embodiments to improve noise compensation, for example reducing inter-track interference by reading a data track at a number of offsets from the track center, or to increase throughput by reading data bits written on multiple tracks. In some embodiments, the array-reader simultaneously reads a particular data track with multiple read heads at different locations. The data is processed first by a preamplifier connected to a read/write head, then by a read channel including circuits such as, but not limited to, analog front end, analog to digital converter, equalizer, and data detector circuits. Because the read heads are moved over a storage medium in the magnetic recording system, the preamplifier is connected to the read channel by a flexible cable or flex cable. Each channel of the array-reader output is processed by a separate analog front-end circuit in the read channel, performing functions such as, but not limited to, amplification, biasing, and filtering. The data is recovered by applying a data detection algorithm to a jointly equalized version of the outputs of the array-reader, where the joint equalizer is a multi-input single output filter or multi-input multi-output filter. With two read heads in the array, the read channel includes two analog front-end circuits in the read channel, which would require two pairs of flex cables to deliver the signals from the preamplifier to the read channel without the combination of array-reader signals using quadrature amplitude modulation disclosed herein.
In some embodiments, the array-reader based magnetic storage system with quadrature amplitude modulation combines the two channels of signals into one channel with two times the bandwidth inside the preamplifier, thereby saving flex cables and analog circuitry. The storage system uses one pair of flex cables to deliver the signals from the preamplifier to the read channel. In some embodiments, the read channel includes one high bandwidth analog front end and one high speed analog to digital converter. In some embodiments, demodulation is performed in the analog domain, and the read channel includes two normal speed analog to digital converters. In some embodiments, quadrature amplitude modulation is used to reduce the number of flex cables, while still including more than one pair of flex cables.
Turning to FIG. 1, an array-reader based magnetic storage system 100 with quadrature amplitude modulation and demodulation is depicted in accordance with some embodiments of the present invention. The storage system 100 includes a read channel circuit 102 with quadrature amplitude demodulation. Storage system 100 may be, for example, a hard disk drive. Storage system 100 also includes a preamplifier 104, an interface controller 106, a hard disk controller 110, a motor controller 112, a spindle motor 114, a disk platter 116, and a read/write head assembly 120 with an array-reader. Interface controller 106 controls addressing and timing of data to/from disk platter 116. The data on disk platter 116 consists of groups of magnetic signals that may be detected by read/write head assembly 120 when the assembly is properly positioned over disk platter 116. In one embodiment, disk platter 116 includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.
In a typical read operation, read/write head assembly 120 is accurately positioned by motor controller 112 over a desired data track on disk platter 116. Motor controller 112 both positions read/write head assembly 120 in relation to disk platter 116 and drives spindle motor 114 by moving read/write head assembly 120 to the proper data track on disk platter 116 under the direction of hard disk controller 110. Spindle motor 114 spins disk platter 116 at a determined spin rate (RPMs). Once read/write head assembly 120 is positioned adjacent the proper data track, magnetic signals representing data on disk platter 116 are sensed by an array-reader in read/write head assembly 120 as disk platter 116 is rotated by spindle motor 114. The sensed magnetic signals are provided as continuous, minute analog signals representative of the magnetic data on disk platter 116. These minute analog signals are processed by preamplifiers 104 in the read/write head assembly and combined using quadrature amplitude modulation, then transferred from read/write head assembly 120 to read channel circuit 102 via flex cables. Preamplifier 104 is operable to amplify the minute analog signals accessed from disk platter 116 for each of the two channels. In turn, read channel circuit 102 demodulates, digitizes and decodes the received analog signal to recreate the information originally written to disk platter 116. This data is provided as read data 122 to a receiving circuit. The signal combining using quadrature amplitude modulation can be implemented consistent with the disclosure below in relation to FIGS. 2-7. In some embodiments, the data processing is performed consistent with the flow diagram disclosed below in relation to FIG. 8.
Turning to FIG. 2, an array reader magnetic recording system with quadrature amplitude modulator 200 and digital quadrature amplitude demodulator 202 is depicted in accordance with some embodiments of the present invention. A pair of analog inputs 204, 206 from an array-reader with two read heads are provided to preamplifiers 214, 216 in an array-reader preamplifier 226, yielding amplified analog signals 230, 232. In some embodiments, each of the preamplifiers 214, 216 are adapted to the characteristics of its associated analog input 204, 206 and the reader in the array-reader from which the analog input is obtained. Each of the two channels has a bandwidth of B Hz each, and each of the preamplifiers 214, 216 has a bandwidth of at least B Hz. The preamplifiers 214, 216 may be any circuit known in the art or that may be developed in the future that is capable of amplifying analog signals. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of amplifier circuits that may be used in relation to different embodiments of the present invention.
Amplified analog signals 230, 232 from preamplifiers 214, 216 are provided to the quadrature amplitude modulator 200 in the array-reader preamplifier 226. In some embodiments, the quadrature amplitude modulator 200 combines the two channels into one channel by quadrature amplitude modulation of a carrier signal by the two channels. In some embodiments, a sinusoidal carrier signal is amplitude modulated by the signal from one reader, a 90 degree phase-shifted version of the carrier signal is amplitude modulated by the signal from the other reader, and the modulated output is combined in a quadrature amplitude modulated signal 240. In some embodiments, the carrier signal is also combined in the quadrature amplitude modulated signal, providing the demodulator with carrier phase information.
The resulting quadrature amplitude modulated signal 240 has a bandwidth of 2B Hz, where B is the bandwidth of a single channel from the array-reader. The quadrature amplitude modulated signal 240 is transmitted to a read channel 242 on flex cables (or any other suitable connection). The quadrature amplitude modulated signal 240 is processed in an analog front end circuit 244, an analog circuit with a bandwidth of at least 2B Hz. The analog front end circuit 244 performs functions such as, but not limited to, amplification, biasing, and filtering of the analog signal 240, yielding processed analog signal 246. The analog front end circuit 244 may be any circuit known in the art for processing an analog signal prior to sampling and further processing such as equalization and value detection. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog front end circuits that may be used in relation to different embodiments of the present invention.
The processed analog signal 246 is provided to an analog to digital converter (ADC) 248 which samples the processed analog signal 246 to yield a stream of digital data samples 250. The analog to digital converter 248 has a bandwidth of at least about 2B Hz with a sampling rate at least twice that required for one channel. For example, in some embodiments, the sampling rate for a single channel would be 2B samples/sec, and the analog to digital converter 248 has a sampling rate of 4B samples/sec to support the two combined channels. Analog to digital converter 248 may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. The analog circuits 252 in read channel 242 thus are high speed, high bandwidth analog circuits adapted to process the 2-channel quadrature amplitude modulated signal 240.
The data samples 250 are provided to a digital quadrature amplitude demodulator 202 which operates to separate the signal for data samples 250 into two individual data channels 254, 256, each with a rate of 2B samples/sec, each corresponding with one of the analog inputs 204, 206. The two data channels 254, 256 are provided to a joint equalizer 264, which equalizes or filters the two data channels 254, 256. In some embodiments, the joint equalizer 264 applies digital finite impulse response filtering to the two data channels 254, 256 to yield equalized data samples 266 for the data track based on the two data channels 254, 256. The joint equalizer 264 thus increases the signal to noise ratio for the data track based on the information in the multiple channels from the array-reader. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of equalizer circuits that may be used in relation to different embodiments of the present invention. The equalized data samples 266 may be subsequently processed in any suitable manner, such as in a Viterbi algorithm detector or a maximum a posteriori detector to identify the values in the equalized data samples 266. If the array-reader is configured such that the signals 204, 206 are coming from the readback of two tracks on the medium 116, the joint equalizer 264 can be configured to result in two output signal streams to facilitate detection of data bits from two tracks on the medium 116.
Turning to FIG. 3, an array reader magnetic recording system with quadrature amplitude modulator 300 and analog quadrature amplitude demodulator 370 in accordance with some embodiments of the present invention. In this embodiment, the analog quadrature amplitude demodulator 370 performs the demodulation in the analog circuits 368 of the read channel 398, and two analog to digital converters 382, 384 are provided, each with a sampling rate of 2B and a bandwidth at least high enough to support the demodulated signals.
The two analog inputs 304, 306 from an array-reader are provided to preamplifiers 314, 316 in an array-reader preamplifier 326, yielding amplified analog signals 330, 332. In some embodiments, each of the preamplifiers 314, 316 are adapted to the characteristics of its associated analog input 304, 306 and the reader in the array-reader from which the analog input is obtained. Each of the two channels has a bandwidth of B Hz each, and each of the preamplifiers 314, 316 has a bandwidth of at least B Hz. The preamplifiers 314, 316 may be any circuit known in the art or that may be developed in the future that is capable of amplifying analog signals. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of amplifier circuits that may be used in relation to different embodiments of the present invention.
Amplified analog signals 330, 332 from preamplifiers 314, 316 are provided to the quadrature amplitude modulator 300 in the array-reader preamplifier 326. In some embodiments, the quadrature amplitude modulator 300 combines the two channels into one channel by quadrature amplitude modulation of a carrier signal by the two channels. In some embodiments, a sinusoidal carrier signal is amplitude modulated by the signal from one reader, a 90 degree phase-shifted version of the carrier signal is amplitude modulated by the signal from the other reader, and the modulated output is combined in a quadrature amplitude modulated signal 340. In some embodiments, the carrier signal is also combined in the quadrature amplitude modulated signal, providing the demodulator with carrier phase information.
The analog signal 340 is processed in an analog front end circuit 344, an analog circuit with a bandwidth of at least 2B Hz. The analog front end circuit 344 performs functions such as, but not limited to, amplification, biasing, and filtering of the analog signal 340, yielding processed analog signal 346. The analog front end circuit 344 may be any circuit known in the art for processing an analog signal prior to sampling and further processing such as equalization and value detection. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog front end circuits that may be used in relation to different embodiments of the present invention.
The processed analog signal 346 is provided to an analog quadrature amplitude demodulator 370 which operates to separate the signal for processed analog signal 346 into two individual analog signals 372, 374, each with a bandwidth of B Hz, each corresponding with one of the analog inputs 304, 306. The two analog signals 372, 374 are each provided to an analog to digital converter (ADC) 382, 384 which sample the two analog signals 372, 374 to yield two streams of digital data samples 391, 392. The analog to digital converters 382, 384 each have a bandwidth of at least about B Hz with a sampling rate of 2B samples/sec. Analog to digital converters 382, 384 may be any circuits known in the art that are capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. The analog front end 344 in read channel 398 is thus a high bandwidth circuit adapted to process the 2-channel analog signal 340, while the analog to digital converters 382, 384 are lower bandwidth circuits.
The two streams of digital data samples 391, 392 are provided to a joint equalizer 396, which equalizes or filters the two streams of digital data samples 391, 392. In some embodiments, the joint equalizer 396 applies digital finite impulse response filtering to the two streams of digital data samples 391, 392 to recover equalized data samples 397 for the data track. The joint equalizer 396 thus increases the signal to noise ratio for the data track based on the information in the multiple channels from the array-reader. The equalized data samples 397 may be subsequently processed in any suitable manner, such as in a Viterbi algorithm or maximum a posteriori detector to identify the values in the equalized data samples 397. In some embodiments, the joint equalizer 396 output consists of two streams of digital samples to facilitate detection of data bits from two tracks on the storage medium.
Turning to FIG. 4A, a quadrature amplitude modulator 400 is depicted, integrated in an array-reader preamplifier 438 with two channel preamplifiers 404, 424, in accordance with some embodiments of the present invention. The quadrature amplitude modulator 400 can be used in place of the quadrature amplitude modulator 200 of FIG. 2 in some embodiments.
Two analog inputs 402, 422 from an array-reader are provided to preamplifiers 404, 424 in an array-reader preamplifier 438, yielding amplified analog signals 406, 426. In some embodiments, each of the preamplifiers 404, 424 are adapted to the characteristics of its associated analog input 402, 422 and the reader in the array-reader from which the analog input is obtained. Each of the two channels has a bandwidth of B Hz each, and each of the preamplifiers 404, 424 has a bandwidth of at least B Hz. The preamplifiers 404, 424 may be any circuit known in the art or that may be developed in the future that is capable of amplifying analog signals. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of amplifier circuits that may be used in relation to different embodiments of the present invention.
Amplified analog signals 406, 426 from preamplifiers 404, 424 are provided to the quadrature amplitude modulator 400 in the array-reader preamplifier 438. Each amplified analog signals 406, 426 are used to amplitude modulate a carrier signal 408, 428. Carrier signal 408, represented in some embodiments as 2 cos [2πBt], and carrier signal 428, or 2 sin [2πBt], are analog carrier signals of the same frequency B but with a 90 degree phase difference. Amplified analog signal 406 is multiplied by carrier signal 408 in multiplier 410, yielding a modulated signal or modulated channel one 412. Amplified analog signal 426 is multiplied by carrier signal 428 in multiplier 430, yielding modulated channel two 432. Carrier signals 408, 428 can be generated in any suitable manner, such as, but not limited to, a frequency synthesizer, and the multipliers 410, 430 can be any suitable circuits known in the art that are capable of multiplying time-varying analog signals. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of signal generator and multiplier circuits that may be used in relation to different embodiments of the present invention.
The modulated channels 412, 432 are combined with each other and with the carrier signal 408 in a summer 434 to yield a combined analog signal 436. Again, the carrier signal 408 is added to the combined analog signal 436 to provide phase information about the carrier to facilitate coherent demodulation at the receiver. The amplitude of the carrier signal 408 is set at a point that yields the desired performance balance for the particular system, with a smaller amplitude not degrading as much the signal to noise ratio in the analog front end circuit and a larger amplitude reducing the latency of extracting a coherent carrier signal in the receiver. The bandwidth of combined analog signal 436 is about 2B Hz, where B is the bandwidth of a single channel. The summer 434 can be any circuit known in the art that is capable of combining analog signals to produce a single analog output containing information from all the inputs. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of summer circuits that may be used in relation to different embodiments of the present invention.
The combined analog signal 436 can be transmitted to any suitable receiver, such as, but not limited to, an analog front end in a read channel, using any suitable conductor or transmission medium, such as, but not limited to, flex cables or flexible printed circuits.
In some embodiments in which multiple analog signals are combined into one analog front end, the combined analog signal may be need to be attenuated. Given that multiple analog signals are being combined into one analog front end with a fixed allowable signal range, the total signal energy of multiple analog signals might exceed the allowable signal range of the analog front end. Accordingly, in some embodiments, the combined signal is attenuated before applying the combined signal to the analog front end, or attenuated within early stages of the analog front end, as long as the combined signal still stays within the limits of allowable signal range before it is attenuated. Attenuating the signal, however, tends to degrade signal to noise range (SNR) due to the relative contribution of noise present downstream in the signal path after attenuation; therefore the amount of attenuation should be set to the minimum required value. Moreover, attenuation should be placed as late as possible in the signal path. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of attenuation techniques that may be used in relation to different embodiments of the present invention.
The operation of the quadrature amplitude modulator 400 is described in the following equations, in which a capitalized symbol for a signal denotes the Fourier transform of the signal represented by a lower case symbol, that is, Rk(f) is the Fourier transform of rk(t). The signal combining performed by some embodiments of the quadrature amplitude modulator 400 can be described as:

Z(f)=R1(f+B)+R1(f−B)+jR2(f+B)−jR2(f−B)+δ(f+B)−δ(f−B)  (Eq 1)

where Z(f) is the Fourier transform of combined analog signal 436, B is the bandwidth of a single channel, or 1/T where T is the baud rate for a single channel, R1(f+B) and R1(f−B) are the Fourier transforms of amplified analog signal 406 r1(t), shifted down and up by B Hz, R2(f+B) and R2(f−B) are the Fourier transforms of amplified analog signal 426 r2(t), shifted down and up by B Hz, and δ(f+B) and δ(f−B) are the Fourier transforms of the carrier signal.
Turning to FIG. 4B, a frequency domain spectrum chart shows the two array-reader channels combined by an embodiment of the quadrature amplitude modulator 400 of FIG. 4A. The Fourier transforms of the amplified analog signals 406, 426 for two channels X1(f) 450 and X2(f) 452 are depicted prior to quadrature amplitude modulation. (The shapes of the envelopes 450 and 452 are selected only for clarity in distinguishing them in FIG. 4B and are not indicative of the content or frequency response.) Each of the two channels X1(f) 450 and X2(f) 452 are centered at a center frequency zero prior to modulation. The Fourier transform Z(f) 454 of the combined analog signal 454 combines both channels, frequency shifted and duplicated as shown in FIG. 4B. The quadrature amplitude modulation combines the two amplified analog signals 406, 426 into a single combined analog signal 436 with bandwidth from −2B to 2B that can be transmitted on a single flex cable. (Depending on the manner of transmission, the “single flex cable” can contain a single conductor or, in some embodiments, multiple conductors, such as in a differential signal.) The quadrature amplitude modulated analog signal 436 has overlapping bands, with the components differentiated by their different phase. This phase information used to separate the components is provided to the receiver by including the carrier signal 408 in the combined analog signal 436.
Turning to FIG. 5, a read channel 500 with quadrature amplitude demodulator 516 is depicted in accordance with some embodiments of the present invention. The read channel 500 receives and processes quadrature amplitude modulated analog signal 502 z(t), which can be represented as:

z(t)=A1r1(t)cos(ω0t+θ0)+A2r2(t)sin(ω0t+θ0)+A0 cos(ω0t+θ0)  (Eq 2)

where r1(t) and r2(t) are the signals to be modulated from the array-reader, A1 and A2 are amplitude factors for the signals to be modulated, cos(ω0t+θ0) and sin(ω0t+θ0) are the carrier signals at the same frequency with a 90 degree phase offset, and A0 cos(ω0t+θ0) is the carrier signal component added to the quadrature amplitude modulated analog signal 502 z(t), where A0 is the amplitude factor for the carrier signal and θ0 is the phase of the carrier signal. Amplitude factors A0, A1 and A2 are gain changes in the signal as it is transmitted and are not known a priori. The relationship between the frequency ω0, channel bandwidth B and baudrate T is as follows:




  
    
      
        
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A quadrature amplitude modulated analog signal 502 z(t) is processed by analog front end circuit 504, an analog circuit with a bandwidth of at least 2B Hz. The analog front end circuit 504 performs functions such as, but not limited to, amplification, biasing, and filtering of the quadrature amplitude modulated analog signal 502, yielding processed analog signal 506. In some embodiments, the analog front end circuit 504 also performs analog equalization of quadrature amplitude modulated analog signal 502 z(t), equalizing or filtering the signal 502 in the analog domain to compensate for limited bandwidth in the signal path between the preamplifier (e.g., FIG. 1, 104) and the read channel (e.g., FIG. 1, 102, FIG. 5, 500). The analog equalizer in the analog front end circuit 504 can be any suitable equalizer that improves data detection of the resulting signal, based on the effect of limited bandwidth on quadrature amplitude modulated analog signal 502 z(t). In some embodiments, the analog equalizer is a linear equalizer, with filter tap coefficients configured based on the expected signal and the bandwidth of the signal. In some embodiments, the analog equalizer is implemented as a system of real and/or complex poles and/or zeros such that certain frequencies are emphasized while other frequencies are de-emphasized to make use of the dynamic range of the analog-to-digital converter. In some embodiments, the analog equalizer is an adaptive decision feedback equalizer, adapting the filter tap coefficients based on detected data (e.g., 528). The analog front end circuit 504 may be any circuit known in the art for processing an analog signal prior to sampling. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog front end circuits that may be used in relation to different embodiments of the present invention.
The processed analog signal 506 is provided to an analog to digital converter 508 which samples the processed analog signal 506 to yield a stream of digital data samples 510 z[m]. The analog to digital converter 508 has a bandwidth of at least about 2B Hz with a sampling rate at least twice that required for one channel. For example, in some embodiments, the sampling rate for a single channel would be 2B samples/sec, and the analog to digital converter 508 has a sampling rate of 4B samples/sec. Analog to digital converter 508 can be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. The digital data samples 510 z[m] can be represented as:




  
    
      
        
          
        
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Alternative methods of timing and/or carrier recovery do not require the insertion of an actual carrier signal into the signal transferred to the analog front end. For example, applying the analog signal to a circuit block with sufficient nonlinearity, and then subsequently filtering (e.g., bandpass filtering) the signal output of the nonlinear block will yield a signal with carrier component from which a timing clock can be derived via known techniques. Signal gain might be required for the signal at the output of the filter to increase signal amplitude as required. Similarly, phase adjustments might also be required with the appropriate circuitry. Alternatively, the above functions (nonlinearity, filtering, gain, carrier/timing recovery, phase adjust) can also be accomplished in the digital domain (after the analog to digital converter)—with the proviso that the analog to digital converter is appropriately clocked. These techniques may also be applied in some embodiments in the digital domain, after the analog to digital converter. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of techniques for timing and/or carrier recovery that may be used in relation to different embodiments of the present invention.
In some embodiments, the analog to digital converter 508 is not synchronized to the quadrature amplitude modulated analog signal 502, and the phase θ0 of the carrier signal may not be known at the receiver. The digital data samples 510 z[m] are therefore processed by a carrier synchronizer 512, which extracts the carrier signal and its phase from digital data samples 510 z[m], and which phase shifts the digital data samples 510 z[m] to synchronize them to the carrier, yielding synchronized digital data samples 514 p[m]. The carrier synchronizer 512 extracts the embedded carrier in the received signal by averaging the received signal over blocks of four samples since the carrier signal cos(mπ/2+θ0) in the sampled signal z[m] 510 is periodic with period 4 samples. Phase shifting the modulated channel portion of the received signal by the estimated carrier phase makes it suitable for coherent demodulation by a locally generated carrier reference. In some embodiments in which the carrier signal is not inserted into the quadrature amplitude modulated analog signal 502, the carrier synchronizer 512 or other circuit element is operable to perform timing and/or carrier recovery as disclosed above.
The two channels in synchronized digital data samples 514 p[m] are separated by quadrature amplitude demodulator 516, yielding two individual data channels 518 x1[n], 520 x2[n], each containing digital samples corresponding with one of the array-reader outputs. Quadrature amplitude demodulation involves down-sampling the odd and even streams of phase-compensated received signal by the respective carrier at the baseband. Notably, the term “quadrature amplitude demodulator” is sometimes used herein to refer to a circuit or device that incorporates the functions of both the carrier synchronizer 512 and demodulator 516. The two data channels 518 x1[n], 520 x2[n] are provided to a joint equalizer 522, which equalizes or filters the two data channels 518 x1[n], 520 x[n]. In some embodiments, the joint equalizer 522 applies digital finite impulse response filtering to the two data channels 518 x1[n], 520 x2[n] to yield equalized data samples 524 y[n] for the data track based on the two data channels 518 x1[n], 520 x2[n]. The joint equalizer 522 thus increases the signal to noise ratio for the data track based on the information in the multiple channels from the array-reader. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of equalizer circuits that may be used in relation to different embodiments of the present invention. The equalized data samples 524 y[n] may be subsequently processed in any suitable manner, such as in a Viterbi algorithm detector or a maximum a posteriori detector to generate bit decisions for the equalized data samples 524 y[n]. In some embodiments, the joint equalizer 522 output consists of two streams of digital samples to facilitate detection of data bits from two tracks on the storage medium.
In some embodiments, equalized data samples 524 y[n] are provided to data detector circuit 526 which produces a detected output 528 by applying a data detection algorithm to the data input. In some embodiments, the data detection algorithm can be but is not limited to, a Viterbi algorithm detection algorithm or a maximum a posteriori detection algorithm as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detection algorithms that may be used in relation to different embodiments of the present invention.
Detected output 528 is provided to a central queue memory circuit 530 that operates to buffer data passed between data detector circuit 526 and data decoder circuit 534. When data decoder circuit 534 is available, data decoder circuit 534 receives detected output 528 from central queue memory 530 as a decoder input 532. Data decoder circuit 534 applies a data decoding algorithm to decoder input 532 in an attempt to recover originally written data. The result of the data decoding algorithm is provided as a decoded output 538. Data decoder circuit 534 can be any data decoder circuit known in the art that is capable of applying a decoding algorithm to a received input. Data decoder circuit 534 can be, but is not limited to, a low density parity check decoder circuit or a Reed Solomon decoder circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data decoder circuits that may be used in relation to different embodiments of the present invention. Where the original data is recovered (i.e., the data decoding algorithm converges) or a timeout condition occurs, data decoder circuit 534 provides the result of the data decoding algorithm as a decoded output 542. Decoded output 542 is provided to a hard decision output circuit 544 where the data is reordered before providing a series of ordered data sets as a data output 546.
One or more iterations through the combination of data detector circuit 526 and data decoder circuit 534 can be made in an effort to converge on the originally written data set. Processing through both the data detector circuit 526 and data decoder circuit 534 is referred to as a “global iteration”. For the first global iteration, data detector circuit 526 applies the data detection algorithm without guidance from a decoded output. For subsequent global iterations, data detector circuit 526 applies the data detection algorithm to equalized data samples 524 y[n] as guided by decoded output 538. Decoded output 538 is received from central queue memory 530 as a detector input 540.
During each global iteration it is possible for data decoder circuit 534 to make one or more local iterations including application of the data decoding algorithm to decoder input 532. For the first local iteration, data decoder circuit 534 applies the data decoder algorithm without guidance from a decoded output 536. For subsequent local iterations, data decoder circuit 534 applies the data decoding algorithm to decoder input 532 as guided by a previous decoded output 536.
Turning to FIG. 6, a carrier synchronizer 600 is depicted which can be used in place of carrier synchronizer 512 in accordance with some embodiments of the present invention. Digital data samples 602 z[m] are stored in buffer 604, from which delayed digital data samples 606 z[m−d] are later retrieved. Digital data samples 602 z[m] are also processed by carrier extractor 608, extracting the carrier signal and yielding the estimated carrier signal 610 c[m]. In some embodiments, carrier extractor 608 calculates the carrier signal, a repeating signal with four samples per period for the array-reader with two readers, by averaging the samples for each of the four sample phases over the block of modulated data, such as a data sector. The carrier extractor 608 can be any circuit known in the art that is capable of extracting a carrier signal from a quadrature amplitude modulated signal that contains the carrier signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of carrier extraction circuits that may be used in relation to different embodiments of the present invention. In some embodiments, the carrier signal frequency is known in advance by carrier extractor 608. The estimated carrier signal 610 c[m] is an estimate of A0 cos(mλ/2+θ0) and can be calculated as:




  
    
      
        
          c
          ⁡
          
            [
            m
            ]
          
        
        =
        
          
            1
            K
          
          ⁢
          
            
              ∑
              
                i
                =
                1
              
              K
            
            ⁢
            
              z
              ⁡
              
                [
                
                  m
                  +
                  
                    i
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                
                ]
              
            
          
        
      
    
    
      
        (
        
          Eq
          ⁢
          
            
          
          ⁢
          6
        
        )
      
    
  




where K is the number of cycles of 4 samples in the transmitted data block or sector, and where c[m] repeats every four samples. Thus, c[m]=c[m+4]=c[m+8], etc.
Subtraction circuit 612 subtracts the carrier signal 610 c[m] from the delayed digital data samples 606 z[m−d], which are delayed in buffer 604 based on the delay in carrier extractor 608, yielding quadrature amplitude modulated signal 614 q[m] without the carrier component. The quadrature amplitude modulated signal 614 q[m] corresponds to the combination of modulated channel one 412 and modulated channel two 432, although possibly with some phase offset since the analog to digital converter 508 does not sample synchronously with the carrier signal. Subtraction circuit 612 calculates quadrature amplitude modulated signal 614 q[m] in some embodiments as:

q[m]=z[m−d]−c[m]  (Eq 7)

A phase estimator 616 determines the phase offset 618 τ0 that occurs in the carrier component in the digital data samples 510 z[m] during transmission between the output of the preamplifier (e.g., 438) and the output of the analog to digital converter 508, which causes the digital data samples 510 z[m] to be out of phase with the original combined analog signal 436 when sampled. The phase estimator 616 can be any circuit known in the art that is capable of determining a phase offset in digital samples based on an extracted carrier signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of phase estimator circuits that may be used in relation to different embodiments of the present invention. In some embodiments, phase estimator 616 estimates the delay incurred by the carrier during transmission according to Equation 9 below, which is derived from Equation 8:




  
    
      
        
          
            
              
                c
                ⁡
                
                  [
                  m
                  ]
                
              
              =
              
              ⁢
              
                
                  A
                  0
                
                ⁢
                
                  cos
                  ⁡
                  
                    (
                    
                      
                        m
                        ⁢
                        
                          
                        
                        ⁢
                        
                          π
                          /
                          2
                        
                      
                      +
                      
                        θ
                        0
                      
                    
                    )
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    
                      (
                      
                        -
                        1
                      
                      )
                    
                    
                      m
                      /
                      2
                    
                  
                  ⁢
                  
                    A
                    0
                  
                  ⁢
                  
                    cos
                    ⁡
                    
                      (
                      
                        θ
                        0
                      
                      )
                    
                  
                  ⁢
                  
                    
                  
                  ⁢
                  for
                  ⁢
                  
                    
                  
                  ⁢
                  m
                
                =
                even
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    
                      (
                      
                        -
                        1
                      
                      )
                    
                    
                      
                        (
                        
                          m
                          +
                          1
                        
                        )
                      
                      /
                      2
                    
                  
                  ⁢
                  
                    A
                    0
                  
                  ⁢
                  
                    sin
                    ⁡
                    
                      (
                      
                        θ
                        0
                      
                      )
                    
                  
                  ⁢
                  
                    
                  
                  ⁢
                  for
                  ⁢
                  
                    
                  
                  ⁢
                  m
                
                =
                odd
              
            
          
        
      
    
    
      
        (
        
          Eq
          ⁢
          
            
          
          ⁢
          8
        
        )
      
    
  
  
    
      
        
          τ
          0
        
        =
        
          
            1
            
              ω
              0
            
          
          ⁢
          
            
              tan
              
                -
                1
              
            
            ⁡
            
              (
              
                
                  ∑
                  
                    
                      
                        (
                        
                          -
                          1
                        
                        )
                      
                      n
                    
                    ⁢
                    
                      c
                      ⁡
                      
                        [
                        
                          
                            2
                            ⁢
                            n
                          
                          -
                          1
                        
                        ]
                      
                    
                  
                
                
                  ∑
                  
                    
                      
                        (
                        
                          -
                          1
                        
                        )
                      
                      n
                    
                    ⁢
                    
                      c
                      ⁡
                      
                        [
                        
                          2
                          ⁢
                          n
                        
                        ]
                      
                    
                  
                
              
              )
            
          
        
      
    
    
      
        (
        
          Eq
          ⁢
          
            
          
          ⁢
          9
        
        )
      
    
  




A phase shifter 620 applies a phase offset to quadrature amplitude modulated signal 614 q[m] to cancel the phase offset 618 τ0, yielding synchronized digital data samples 622 p[m]. The phase shifter 620 can be any circuit known in the art that is capable of shifting the phase of a digital signal that comprises samples from an analog signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of phase shifter circuits that may be used in relation to different embodiments of the present invention. The resulting synchronized digital data samples 622 p[m] correspond to the original combined modulated channel one 412 and modulated channel two 432, with no carrier signal and no phase change. In some embodiments, phase shifter 620 synchronizes the received signal to the local carrier, removing the phase change of transmission, according to the following:




  
    
      
        
          
            
              
                p
                ⁡
                
                  [
                  m
                  ]
                
              
              =
              
              ⁢
              
                q
                ⁡
                
                  [
                  
                    m
                    -
                    
                      τ
                      0
                    
                  
                  ]
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    A
                    1
                  
                  ⁢
                  
                    
                      r
                      1
                    
                    ⁡
                    
                      [
                      m
                      ]
                    
                  
                  ⁢
                  
                    cos
                    ⁡
                    
                      (
                      
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          π
                        
                        2
                      
                      )
                    
                  
                
                +
                
                  
                    A
                    2
                  
                  ⁢
                  
                    
                      r
                      2
                    
                    ⁡
                    
                      [
                      m
                      ]
                    
                  
                  ⁢
                  
                    sin
                    ⁡
                    
                      (
                      
                        
                          m
                          ⁢
                          
                            
                          
                          ⁢
                          π
                        
                        2
                      
                      )
                    
                  
                
              
            
          
        
      
    
    
      
        (
        
          Eq
          ⁢
          
            
          
          ⁢
          10
        
        )
      
    
  




where cos(mπ/2)={1,0,−1,0,1,0,−1,0, . . . } and sin(mπ/2)={0,1,0,−1,0,1,0,−1, . . . }.
Turning to FIG. 7, a quadrature amplitude demodulator is depicted that can be used in place of quadrature amplitude demodulator 516 in accordance with some embodiments of the present invention. The synchronized digital data samples 702 p[m] are multiplied by digital forms 704, 718 of the phase compensated carrier signal, frequency shifting the channels. One digital carrier signal 704 corresponds to carrier signal 408 in the quadrature amplitude modulator 400 and can be represented in some embodiments as cos [mπ/2]. The other digital carrier signal 718 is at the same frequency with a 90 degree phase offset, corresponds to carrier signal 428, and can be represented in some embodiments as sin [mπ/2]. This produces demodulated signals v1[m] 708, v2[m] 722 representing channels one and two from the array-reader, but with bandwidth 2B Hz at 4B samples per second. The demodulated signals v1[m]708 and v2[m] 722 are given by:

v1[m]=2p[m]2 cos(mπ/2)=A1r1[m]*(1+cos(mπ))  (Eq 11)

v2[m]=2p[m]2 sin(mπ/2)=A2r2[m]*(1+cos(mπ))  (Eq 12)

Low pass filters 710, 724 are low pass filters of bandwidth B Hz which filter the demodulated signals v1[m] 708 and v2[m] 722 to reject the frequency components beyond the band [−B, +B]. The low-pass filtered signals 712 p1[m] and 726 p2[m] are still with 4B samples per second but bandwidth B Hz. Low pass filters 710, 724 can be any circuit known in the art that are capable of low pass filtering digital signals. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of low pass filters that may be used in relation to different embodiments of the present invention. The filtered signals 712 p1[m] and 726 p2[m] can be represented as follows:

p1[m]=LPF{v1[m]}=A1r1[m]  (Eq 13)

p2[m]=LPF{v2[m]}=A2r2[m]  (Eq 14)

The filtered signals 712 p1[m] and 726 p2[m] are down-sampled in down-samplers 714, 728, which decimate or down-sample the filtered signals 712 p1[m] and 726 p2[m], yielding band-limited digital signals 716 x1[n], 730 x2[n], each containing digital samples at a rate of 2B samples per second and each corresponding with one of the array-reader outputs. The down-samplers 714, 728 can be any circuit known in the art that is capable of sampling a signal or otherwise reducing the data rate of a digital signal, for example by discarding every other sample. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of down-sampling circuits that may be used in relation to different embodiments of the present invention. In some embodiments, the down-sampling of filtered signals 712 p1[m] and 726 p2[m] in down-samplers 714, 728 can be represented as follows:

x1[n]=p1[2n]=A1r1[2n]  (Eq 15)

x2[n]=p2[2n]=A2r2[2n]  (Eq 16)

In some embodiments, the read channel includes an analog quadrature amplitude demodulator as in FIG. 3. In these embodiments, the analog to digital conversion is performed after demodulation as shown in FIG. 3. The analog quadrature amplitude demodulation is performed in any suitable manner, such as, but not limited to, in the same manner as disclosed in FIGS. 6-7 and Equations 2-14, although in the analog domain, and without the need for down-samplers 714 and 728.
Turning to FIG. 8, a flow diagram 800 depicts an operation to transmit data from an array-reader in a magnetic recording system in accordance with some embodiments of the present invention. Following flow diagram 800, multiple analog signals are received from an array-reader (block 802). The multiple analog signals and a carrier signal are combined using quadrature amplitude modulation to yield a modulated analog signal (block 804). In some embodiments, two analog signals are combined by modulating each using in-phase and quadrature carriers and adding the result. In some embodiments, the carrier signal that is combined with the multiple analog signals is the in-phase carrier, thereby facilitating coherent demodulation in the receiver. The modulated analog signal is transmitted on flex cables to a read channel (block 806).
The carrier embedded in the received modulated signal is extracted or recovered (block 810). In some digital demodulation embodiments, in which the received modulated signal is sampled before demodulation, this is accomplished by averaging like-phase samples over the transmitted block of data. For example, given four samples per period for the array-reader having 2 readers, the first of the four samples in each period in the transmitted block of data is averaged to yield the averaged first sample, the second of the four samples in each period in the transmitted block of data is averaged to yield the averaged second sample, and so on. The like-phase samples are thus samples captured at repetitive, regular intervals. The extracted carrier component is removed from the received modulated signal, yielding a modulated data signal (block 812). In some digital demodulation embodiments, this is accomplished by subtracting the extracted carrier from the modulated signal samples. The phase of the extracted carrier is estimated to yield a phase offset (block 814). The phase offset is cancelled in the modulated data signal (block 816), yielding phase compensated modulated data. The phase compensated modulated data is frequency shifted by locally generated versions of in-phase and quadrature carrier signals, yielding high bandwidth channel signals representing demodulated versions of the outputs of the array-reader (block 820). The high bandwidth channel signals are low-pass filtered (block 822). In some digital demodulation embodiments, the outputs of the low-pass filters are down-sampled to obtain demodulated versions of the outputs of the array-reader.
It should be noted that the various blocks discussed in the above application may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.
In conclusion, embodiments of the present invention provide novel systems, devices, methods and arrangements for an array-reader based magnetic recording system with quadrature amplitude modulation. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of embodiments of the invention which are encompassed by the appended claims.

## Claims

1. A magnetic recording system comprising:
an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium;
a quadrature amplitude modulator operable to combine the analog signals to yield a quadrature amplitude modulated signal;
a quadrature amplitude demodulator operable to yield a plurality of demodulated signals from the quadrature amplitude modulated signal corresponding to each channel of the array; and
a joint equalizer operable to filter the plurality of demodulated signals to yield an equalized output.

2. The system of claim 1, wherein the quadrature amplitude modulator is operable to include a carrier signal with the analog signals in the quadrature amplitude modulated signal.

3. The system of claim 1, further comprising a carrier synchronizer operable to extract the carrier signal and to synchronize the quadrature amplitude modulated signal to the extracted carrier signal.

4. The system of claim 3, wherein the carrier synchronizer comprises a carrier extractor operable to recover the carrier signal from the quadrature amplitude modulated signal by averaging like-phase samples of the quadrature amplitude modulated signal, a subtractor circuit operable to subtract the carrier signal from the quadrature amplitude modulated signal, a phase estimator operable to estimate a phase offset of the carrier signal, and a phase shifter operable to cancel the phase offset of the carrier signal from the quadrature amplitude modulated signal.

5. The system of claim 1, further comprising a flexible cable operable to transmit the quadrature amplitude modulated signal.

6. The system of claim 1, wherein the quadrature amplitude modulator comprises:
a first multiplier operable to multiply a first of the analog inputs by an in-phase carrier signal to yield a first modulated signal;
a second multiplier operable to multiply a second of the analog inputs by a quadrature carrier signal to yield a second modulated signal, wherein the in-phase carrier signal and quadrature carrier signal comprise a same analog signal with a 90 degree phase offset; and
a summer circuit operable to combine the first modulated signal and second modulated signal to yield the quadrature amplitude modulated signal.

7. The system of claim 6, wherein the summer circuit is further operable to combine the in-phase carrier signal in the quadrature amplitude modulated signal.

8. The system of claim 1, wherein the quadrature amplitude demodulator comprises:
a first multiplier operable to multiply the quadrature amplitude modulated signal by an in-phase carrier signal to yield a first demodulated signal;
a first low-pass filter operable to filter the first demodulated signal to yield a first filtered signal;
a second multiplier operable to multiply the quadrature amplitude modulated signal by a quadrature carrier signal to yield a second demodulated signal, wherein the in-phase carrier signal and quadrature carrier signal comprise a same signal with a 90 degree phase offset; and
a second low-pass filter operable to filter the second demodulated signal to yield a second filtered signal.

9. The system of claim 8, wherein the quadrature amplitude demodulator comprises a digital demodulator, wherein the in-phase carrier signal and the quadrature carrier signal comprise digital signals, the system further comprising an analog to digital converter operable to sample the quadrature amplitude modulated signal to yield a digital quadrature amplitude modulated signal, and wherein the quadrature amplitude demodulator operates on the digital quadrature amplitude modulated signal.

10. The system of claim 9, wherein the quadrature amplitude demodulator further comprises a first down-sampler operable to down-sample the first filtered signal, and a second down-sampler operable to down-sample the second filtered signal.

11. The system of claim 8, wherein the quadrature amplitude demodulator comprises an analog demodulator, wherein the in-phase carrier signal and the quadrature carrier signal comprise analog signals, the system further comprising a plurality of analog to digital converters operable to sample the first filtered signal and the second filtered signal.

12. The system of claim 1, further comprising a signal attenuator operable to attenuate a signal derived from the analog signals.

13. The system of claim 1, further comprising a carrier synchronizer operable to recover timing information for a carrier signal used to generate the quadrature amplitude modulated signal, wherein the carrier signal is not included in the quadrature amplitude modulated signal by the quadrature amplitude modulator.

14. A method of connecting an array-reader head assembly in a magnetic storage system to a read channel in the magnetic storage system, comprising:
providing a quadrature amplitude modulator in the array-reader head assembly operable to yield a quadrature amplitude modulated signal containing an array of analog signals from the array-reader head assembly;
connecting the quadrature amplitude modulator in the array-reader head assembly to the read channel by a flexible cable pair;
providing a quadrature amplitude demodulator in the read channel operable to yield a plurality of demodulated signals from the quadrature amplitude modulated signal corresponding to each element of the array; and
providing a joint equalizer in the read channel operable to filter the plurality of demodulated signals to yield an equalized output.

15. The method of claim 14, wherein the quadrature amplitude modulator is operable to modulate the array of analog signals with different phase offset versions of a carrier signal to yield modulated signals, and to combine the modulated signals and one of the versions of the carrier signal in the quadrature amplitude modulated signal.

16. The method of claim 15, further comprising providing a carrier synchronizer operable to recover the carrier signal from the quadrature amplitude modulated signal, to subtract the carrier signal from the quadrature amplitude modulated signal, to estimate a phase offset of the carrier signal, and to cancel the phase offset of the carrier signal from the quadrature amplitude modulated signal.

17. The method of claim 16, wherein the carrier synchronizer is operable to recover the carrier signal by averaging like-phase samples of the quadrature amplitude modulated signal captured at regular intervals.

18. The method of claim 14, further comprising providing an analog to digital converter operable to sample the quadrature amplitude modulated signal to yield a sampled quadrature amplitude modulated signal, wherein the quadrature amplitude demodulator is operable to demodulate a signal derived from the sampled quadrature amplitude modulated signal.

19. The method of claim 14, wherein the quadrature amplitude demodulator comprises a digital demodulator, further operable to low-pass filter and down-sample the plurality of demodulated signals.

20. A storage system comprising:
a storage medium;
an array-reader head assembly disposed in relation to the storage medium and operable to provide an array of analog signals corresponding to information on the storage medium;
a preamplifier operable to amplify the array of analog signals;
a quadrature amplitude modulator operable to combine the analog signals to yield a quadrature amplitude modulated signal; and
a flexible cable operable to carry the quadrature amplitude modulated signal from the array-reader head assembly to a read channel circuit, the read channel circuit comprising:
an analog front end circuit operable to perform analog equalization of the quadrature amplitude modulated signal to reduce effects of limited bandwidth;

a quadrature amplitude demodulator operable to yield a plurality of demodulated signals from the quadrature amplitude modulated signal corresponding to each channel of the array; and
a joint equalizer operable to filter the plurality of demodulated signals to yield an equalized output.