# Patent

## Title
Electronic parts mounting method

## Abstract

This is a division of application Ser. No. 605,883, filed Oct. 29, 1990, now U.S. Pat. No. 5,117,282, issued May 26, 1992.

## Background
The present invention relates in general to integrated circuit packaging assemblies and is particularly directed to the stacking of a plurality of integrated circuit devices by multiple folding of a flexible interconnect web upon which the devices are mounted.

Integrated circuits are typically packaged in a single chip or `monolithic` configuration which, in turn, is soldered or plugged into a printed circuit board, or other type of interconnect support substrate. In a multi-chip `hybrid` package, several devices are assembled into a single package. Such a packaging scheme has the advantages of reduced weight, size and, occasionally, circuit performance. In an effort to further enhance packaging density, edge-wise or vertically stacked multi-chip packaging assemblies have been proposed. In such configurations, rather than array a plurality of devices in what is essentially a single dimensional, or planar, layout, the devices are arranged on top of one another in a `stack` or `layered` assembly.

The present invention is directed to method of forming such a stacked packaging assembly and is particularly directed to the stacking of a plurality of integrated circuit devices by employing a web of flexible interconnect material that is readily folded into a `layered` arrangement of parallel web fingers onto which a plurality of integrated circuit devices may be mounted. The flexible interconnect circuit web has a first web portion, from one side of which a first plurality of spaced apart web fingers extend parallel to one another, and from another side of which a second plurality of spaced apart web fingers extend parallel to one another and parallel to the first plurality of web fingers. The second web fingers are longer than the first web fingers and are folded across the first web portion, so as to be interleaved with the first web fingers along the on side of the first web portion. The interleaved first and second web fingers are then folded so as to form a stack of parallel flexible interconnect web fingers `vertically` separated from one another by the displacement imparted by folds therebetween.

The web fingers have integrated circuit devices surface-mounted to device receiving regions such that leads of the integrated circuit devices are attached to interconnect links of the flexible interconnect web. A plurality of heat sinks in the form of thin thermally conductive plates (heat sink plates) are interleaved with the folded web fingers of the stack, so as to engage the integrated circuit devices mounted on the web fingers. The heat sink plates are retained by thermally conductive spacer members in the form of spacer blocks along edge regions of the plates. The spacer blocks are clamped together in a compact laminate structure, so as to form a rigid support which relieves mechanical stresses in the folds of the web fingers.

The folded web fingers and the heat sink plates also contain mutually engageable alignment elements such that an alignment element (tab) of a respective heat sink plate engages an alignment element (tab-receiving slot) of a respective web finger. In addition, the web fingers have chip capacitor-mounting regions adjacent to the mounting locations of the integrated circuit devices for receiving chip capacitors. Chip capacitors are surface mounted at the chip capacitor mounting regions of the web fingers such that leads of the chip capacitors are connected to interconnect links of the flexible interconnect web. The heat sink plates also contain chip capacitor mounting regions have juxtaposed chip capacitor openings for accommodating chip capacitors that are surface mounted on adjacent folded web fingers.

FIGS. 1-4 are respective views, taken in perspective, of the sequential folding of a flexible circuit web to form a stack of integrated circuit device supporting web fingers;

FIG. 5 is a partially exploded view of an individual layer of a stacked packaging assembly in accordance with the present invention; and

FIGS. 6, 7 and 8 are respective top, side and end views of a stacked packaging assembly of the present invention.

Referring now to FIGS. 1-4, the respective steps of the sequential folding of a flexible interconnect circuit web to form a stack of integrated circuit device-supporting web fingers in accordance with the present invention will be described. For purposes of clarity, respective integrated circuit devices and chip capacitors that have been surface-mounted to associated apertures in the web fingers (to be described more fully below with reference to FIG. 5) are omitted from FIGS. 1-4.

As shown in FIG. 1, the flexible interconnect circuit web 10 itself is configured in a comb-like arrangement of first and second pluralities 11 and 12 of web fingers 21 and 22, respectively extending from opposite sides 23 and 24 of a central web portion 25. Flexible interconnect web 10 may comprise Flex Film, manufactured under the name R-Flex by Rogers Corporation, or other commercially available flexible interconnect. In the illustrated embodiment, first plurality 11 contains four web fingers 21-1 . . . 21-4 and second plurality 12 contains four web fingers 22-1 . . . 22-4. Each web finger is shown as having an aperture 18 sized to receive an integrated circuit device and an adjacent aperture 19 sized to receive a chip capacitor. (It should be observed that the invention is not limited to the specific parameters of the illustrated embodiment but may vary to meet specific requirements.)

Each web finger is spaced apart from an adjacent web finger by a distance S corresponding to the width W of the finger, plus an additional separation sufficient to accommodate a fold on either side or edge of the finger, whereby, when folded on top of one another as shown in FIGS. 3 and 4, the web fingers are mutually aligned in a stack. In addition, the lengths L22 of web fingers 22 are greater than the lengths L21 of web fingers 21 by the width 27 of central web portion 25 plus an additional fold-accommodating distance.

As shown in FIG. 1, the longer web fingers 22 are initially folded in the direction of arrows 31 across of the central web portion 25, so as to be horizontally interleaved with web fingers 21 such that web fingers 21 and 22 are mutually horizontally aligned with one another, as shown in FIG. 2. Following this initial fold, the mutually horizontally aligned web fingers are folded, accordion style, along the lengthwise direction of central web portion 25, as shown by arrow 41 in FIG. 2 and arrows 42 and 43 in FIG. 3, such that the web fingers overlie one another in the form of a vertically aligned stack 50, as shown in FIG. 4. As will be described below with reference to FIGS. 5-8, respective pairs of spacer blocks (not shown in FIG. 4) are engaged with the side edges of each web finger, so as to provide a fold stress-relieving support structure to which the folded arrangement of FIG. 4 is mechanically secured.

Referring now to FIG. 5, a partially exploded view of an individual layer of a stacked packaging assembly in accordance with the present invention is shown as comprising a respective flexible interconnect circuit web finger 61 having a first aperture 63 sized to accommodate an integrated circuit device 65 and a second aperture 67 sized to accommodate a chip capacitor 69. Device 65 is shown as having two sets of leads 71, 73 extending along side edges 75, 77, respectively. It should be observed however, that what is shown is an exemplary embodiment. Leads could extend along all four sides of body 65. Leads 71, 73 are arranged in alignment with conductor tracks (or interconnect links) 81, 83 of web finger 61, so that when device 65 is captured within aperture 63, leads 71, 73 may be bonded to tracks 81, 83. Similarly, chip capacitor 69 has leads 91, 93 extending along side edges 95, 97, respectively. Leads 91, 93 are arranged in alignment with tabs 101, 103 of web finger 61, so that when chip capacitor 67 is captured within aperture 67, leads 91, 93 may be bonded to tabs 101, 103. Web finger 61 also has an alignment element in the form of a slot 111 which is sized to capture an alignment tab 113 of an adjacent heat sink plate 115.

In addition to alignment tab 113, heat sink plate 115 has an aperture 117, aligned with aperture 67 in web finger 61 and sized to accommodate that portion of a chip capacitor that extends through aperture 67 in web finger 61. The heat sink plate is retained at its edges 121, 123 in grooves 125, 127, respectively, of a pair of generally rectangular solid metallic spacer blocks 131, 133. With web finger 61 placed against heat sink plate 115, such that tab 113 fits into slot 111, the bottom surface 76 of device 65, captured in aperture 63 of web finger 61, is in flush contact with heat sink plate 115, so as to provide a thermal flow path from the device through the heat sink plate to the spacer blocks.

Each spacer block has a pair of bores 141 at its opposite ends, to accommodate a retention fitting (e.g. threaded pin) for clamping a plurality of spacer blocks together in a rigid stacked configuration, as diagrammatically illustrated in FIGS. 6-8. With the spacer blocks of plural ones of the finger layer of FIG. 5 clamped together as shown in FIGS. 6-8, there results a compact laminate structure, which both relieves mechanical stresses at the folds of the web fingers and facilitates attachment of the stacked assembly to an associated housing or motherboard. Since the spacer blocks are mutually contiguous, there is a heat sink path for each circuit device all the way to an underlying support substrate.

A particular advantage of the layered assembly of the present invention is ease of repairability. If one of the circuits fail, its layer can be easily removed, the defective device replaced, tested, and the arrangement reassembled. It should be noted that the manner in which the multilayer structure is attached to an attendant support member is not limited to any particular orientation. For the example, the multilayer arrangement may be attached in a vertical configuration or mounted on edge; it also may be folded into an irregular shape to accommodate different housing/support configurations. The interface feed of the flexible interconnect web allows circuit connections to be made in essentially any orientation.

While I have shown and described an embodiment in accordance with the present invention, it is to be understood that the same is not limited thereto but is susceptible to numerous changes and modifications as known to a person skilled in the art, and I therefore do not wish to be limited to the details shown and described herein but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.

## Claims

1. A method of manufacturing a multilayer integrated circuit packaging assembly comprising the steps of: interconnect circuit web having plurality of finger portions, a respective finger portion having interconnect links on a first surface thereof and an aperture therethrough sized to accommodate an integrated circuit device; said plurality of finger portions such that said respective integrated circuit devices pass through and are thereby captured within apertures of said respective ones of said plurality of finger portions, and connecting leads extending from said respective integrated circuit devices to interconnect links on first surfaces of respective ones of said finger portions; step (c) such that respective heat sinks engage and are in thermal contact with second surfaces of respective captured integrated circuit devices adjacent to second surfaces of respective ones of said folded finger portions.

2. A method according to claim 1, wherein step (d) comprises securing said heat sinks together to form a support structure which relieves mechanical stresses in said folded finger portions.

3. A method according to claim 2, wherein step (d) comprises attaching said heat sinks to spacer members and securing said spacer members together as a stacked structure.

4. A method according to claim 3, wherein said finger portions and said heat sinks contain mutually engageable alignment elements and wherein step (d) comprises engaging an alignment element of a respective heat sink with an alignment element of a respective finger portion.

5. A method according to claim 1, wherein said flexible interconnect circuit web has plurality of spaced apart finger portions arranged parallel to one another and wherein step (c) comprises folding said finger portions such that said finger portions overlie one another as parallel flexible interconnect web finger portions spaced apart from one another by folds in said flexible interconnect web.

6. A method according to claim 1, wherein said flexible interconnect circuit web has a first web portion, from one side of which a first plurality of spaced apart finger portions extend parallel to one another, and from another side of which a second plurality of spaced apart finger portions extend parallel to one another and to said first plurality of finger portions, said second finger portions being longer than said first finger portions, and wherein step (c) comprises folding said second finger portions across said first web portion of said flexible interconnect web, such that said second finger portions are interleaved with said first finger portions along said one side of said flexible interconnect web, and said first and second finger portions being folded in the form of a stack of parallel flexible interconnect web fingers spaced apart from one another by folds therebetween.

7. A method according to claim 1, wherein said first and second pluralities of spaced apart finger portions include chip capacitor mounting regions for receiving chip capacitors, and wherein chip capacitors are surface mounted at the chip capacitor mounting regions thereof such that leads of said chip capacitors are connected to interconnect links of said finger portions.

8. A method according to claim 7, wherein those heat sinks that engage chip capacitors mounted at said chip capacitor mounting regions have corresponding chip capacitor openings for accommodating said mounted chip capacitors.